IC PACKAGE AND PROCEDURE

Abstract

Procedure, comprehensive: Bonding a rear side of a first storage device (10A) to a front side of a second storage device (10B, 10C, 10D) using dielectric-dielectric bonds and metal-metal bonds; after bonding, forming first conductive bumps (22A) through a first dielectric layer (24A) on a front face of the first storage device (10A), wherein the first conductive bumps (22A) are raised from a main surface of the first dielectric layer (24A); Testing the first storage device (10A) and the second storage device (10B, 10C, 10D) using the first conductive hump (22A); and After testing, attaching a logic device (10L) to the first conductive protrusions (22A) by means of solder joints with fusible connectors (108) as solder material, and Forming a first underfill (110) between the logic device (10L) and the first storage device (10A), wherein the first underfill (110) surrounds each of the meltable connectors (108).

Description

BACKGROUND

[0001] In the development of integrated circuits (ICs), the semiconductor industry has experienced sustained rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). These improvements in integration density are largely attributable to periodic reductions in the minimum feature size, allowing more components to be integrated into a given area.

[0002] These improvements in integration are essentially two-dimensional, as the area occupied by the integrated components is primarily located on the surface of the semiconductor wafer. The increased density and corresponding reduction in the area of ​​the integrated circuit have generally surpassed the ability to directly bond an IC chip to a substrate. Interposers have been used to redistribute areas of spherical contacts from the chip to a larger area of ​​the interposer. Furthermore, interposers have enabled three-dimensional packages containing multiple chips. Additional packages have also been developed to address three-dimensional aspects.

[0003] German patent DE 10 2018 116 729 B3 discloses a semiconductor device package and a method for its fabrication, in which several dies are stacked on top of each other and tested using test pads. US patent 2012 / 0 135 565 A1 proposes filling gaps between stacked substrates with a casting resin. US patent 2014 / 0 203 429 A1 describes a fan-out package and a method for its fabrication. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. Fig. Figure 1 is a cross-sectional view of an integrated circuit device according to some embodiments. The Fig. Figures 2A to 2F are cross-sectional views of intermediate steps in a process for forming a storage cube according to some embodiments. The Fig. Figures 3A to 3F are cross-sectional views of intermediate steps in a process for forming an HBM device according to some embodiments. The Fig. Figures 4A to 4D are cross-sectional views of intermediate steps in a process for forming an HBM device according to some further embodiments. The Fig. Figures 5A to 5C are cross-sectional views of intermediate steps in a process for forming an HBM device according to some further embodiments. The Fig. Figures 6A to 6F are cross-sectional views of intermediate steps in a process for forming a storage cube according to some further embodiments. The Fig. 7, Fig. 8 to Fig. Figure 9 shows cross-sectional views of HBM devices according to some further embodiments. The Fig. Figures 10A to 10E are cross-sectional views of intermediate steps in a process for forming a storage cube according to some embodiments. The Fig. 11, Fig. 12 and Fig. Figure 13 shows cross-sectional views of HBM devices according to some further embodiments. The Fig. 14A and Fig. Figure 14B shows cross-sectional views of intermediate steps in a process for forming integrated circuit packages according to some embodiments. The Fig. Figures 15A to 15C are cross-sectional views of intermediate steps in a process for forming integrated circuit packages according to some further embodiments. The Fig. Figures 16A to 16F are cross-sectional views of intermediate steps in a process for forming integrated circuit packages according to some further embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not, in itself, imply any relationship between the various described embodiments and / or configurations.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0007] According to some embodiments, a memory cube is formed by stacking several memory devices via hybrid bonding. Die connectors, such as conductive protrusions, are formed in the uppermost memory device of the cube after hybrid bonding. The memory cube is tested using the die connectors, ensuring that only known good memory cubes are used for further processing. The die connectors can then be used to attach the memory cube to a logic device with fusible connectors. This avoids the processing of known defective memory cubes, thereby reducing the manufacturing costs of the devices.

[0008] Fig. Figure 1 is a cross-sectional view of an integrated circuit device 10 according to some embodiments. The integrated circuit device 10 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, etc.), a memory die (e.g., a DRAM die (dynamic random-access memory die), an SRAM die (static random-access memory die), etc.), a power control die (e.g., a PMIC die (integrated power control circuit die)), a radio frequency die (RF die), a sensor die, a microsystems die (MEMS die), a signal processing die (e.g., a digital signal processing die (DSP die)), a front-end die (e.g., an analog front-end die (AFE)), the like, or a combination thereof. The integrated circuit device 10 is formed in a wafer (not shown) which has various device areas.In some embodiments, several wafers are stacked to form a wafer stack, which is then singulated during subsequent processing to form several die stacks. In other embodiments, a single wafer is singulated to form several integrated circuit devices 10, which are then stacked during subsequent processing to form several die stacks. The integrated circuit device 10 can be processed according to suitable manufacturing methods to form integrated circuits. For example, the integrated circuit device 10 can comprise a semiconductor substrate 12, an interconnect structure 14, conductive vias 16, die connectors 22, and a dielectric layer 24.

[0009] The semiconductor substrate 12 can be silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can include other semiconductor materials such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The semiconductor substrate 12 has an active surface (e.g., the one in Fig. 1 upward-facing surface), sometimes referred to as the front face, and an inactive surface (e.g., the one in Fig. 1 downward-facing surface), which is sometimes referred to as the back.

[0010] Devices can be formed on the active surface of the semiconductor substrate 12. The devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface can be free of devices. An interlayer dielectric (ILD) is located above the active surface of the semiconductor substrate 12. The ILD surrounds the devices and can cover them. The ILD can have one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0011] The interconnect structure 14 is located above the active surface of the semiconductor substrate 12. The interconnect structure 14 connects the devices on the active surface of the semiconductor substrate 12 to each other, thus forming an integrated circuit. The interconnect structure 14 can be formed, for example, by metallization structures in dielectric layers. The metallization structures have metal conductors and vias formed in one or more dielectric layers. The metallization structures of the interconnect structure 14 are electrically connected to the devices on the active surface of the semiconductor substrate 12.

[0012] The conductive vias 16 are configured to extend into the interconnect structure 14 and / or the semiconductor substrate 12. The conductive vias 16 are electrically connected to metallization structures of the interconnect structure 14. For example, cavities in the interconnect structure 14 and / or the semiconductor substrate 12 can be formed by etching, milling, laser techniques, a combination thereof, and / or the like. A thin dielectric can be formed in the cavities, for example, using an oxidation technique. A barrier layer 18 can be conformally deposited in the cavities, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and / or the like.The barrier layer 18 can be formed from an oxide, a nitride, or an oxynitride, for example, titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and / or the like. A conductive material 20 can be deposited over the barrier layer 18 and in the openings. The conductive material 20 can be formed by an electrochemical plating process, CVD, PVD, a combination thereof, and / or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like. Excesses of the conductive material 20 and the barrier layer 18 are removed from the surface of the interconnect structure 14 and / or the semiconductor substrate 12, for example, by chemical-mechanical polishing (CMP). Remaining portions of the barrier layer 18 and the conductive material 20 form the conductive vias 16.

[0013] In the illustrated embodiment, the conductive vias 16 on the back side of the integrated circuit device 10 are not yet exposed. Rather, the conductive vias 16 are embedded in the semiconductor substrate 12. As described in more detail below, the conductive vias 16 are exposed during subsequent processing on the back side of the integrated circuit device 10. After exposure, the conductive vias 16 can be referred to as silicon vias or substrate vias (TSVs).

[0014] The die connectors 22 are located on a front face of the integrated circuit device 10. The die connectors 22 can be conductive pillars, pads, or the like, to which external connections are made. The die connectors 22 are located in and / or on the interconnect structure 14. The die connectors 22 can be made of a metal such as copper, aluminum, or the like, and can be formed, for example, by plating or the like.

[0015] The dielectric layer 24 is located on the front face of the integrated circuit device 10. The dielectric layer 24 is located in and / or on the interconnect structure 14. The dielectric layer 24 encapsulates the die connectors 22 laterally, and the dielectric layer 24 is laterally flush (within process variations) with the side walls of the integrated circuit device 10. The dielectric layer 24 can be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene-based (BCB-based) polymer, or the like; or a combination thereof. The dielectric layer 24 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like.In some embodiments, the dielectric layer 24 is formed downstream of the die connectors 22 and may bury the die connectors 22, such that the top surface of the dielectric layer 24 lies above the top surfaces of the die connectors 22. In some embodiments, the die connectors 22 are formed downstream of the dielectric layer 24, for example, by a damascene process, such as single-damascene, dual-damascene, or the like. After formation, the die connectors 22 and the dielectric layer 24 may be planarized using, for example, a CMP process, a back-etching process, or the like. After planarization, the top surfaces of the die connectors 22 and the dielectric layer 24 are coplanar (within process variations) and are exposed on the front face of the integrated circuit device 10.In another embodiment, the die connectors 22 are formed after the dielectric layer 24, for example by a plating process, and are raised connectors (e.g. microbumps) so that the upper surfaces of the die connectors 22 extend over the upper surface of the dielectric layer 24.

[0016] The Fig. Figures 2A to 2F are cross-sectional views of intermediate steps in a process for forming a storage cube 50 according to some embodiments. As described in more detail below, the Fig. 2A to 2F describe a process in which a storage cube 50 is formed by stacking several wafers, each having first integrated circuit devices, on a support substrate 52. The first integrated circuit devices can each have a structure similar to the integrated circuit device 10 described above with reference to Fig. The wafers described in Figure 1 can, in one embodiment, be storage devices. Stacking wafers to form a storage cube 50 in a device area 52A of the support substrate 52 is shown; however, it should be noted that the support substrate 52 can have any number of device areas, and a storage cube 50 can be formed in each device area. The storage cube 50 is formed from top to bottom (or vice versa) by wafer-wafer stacking (WoW stacking), wherein a wafer is provided for the top layer of the storage cube 50, and wafers for underlying layers of the storage cube 50 are subsequently stacked onto the top wafer. The wafer stack is singulated so that multiple storage cubes 50 are formed. The storage cubes 50 are inspected after formation to reduce or prevent subsequent processing of known defective storage cubes 50.

[0017] The memory cube 50 can then be used to form a high-bandwidth memory device (HBM device). As described in more detail below, the memory cube 50 can also be stacked on top of a second integrated circuit device to form an HBM device. The second integrated circuit device can have a structure similar to that described above with reference to Fig. 1 described integrated circuit device 10 resembles, and in one embodiment can be a logic device.

[0018] In Fig. In step 2A, a support substrate 52 is provided, and a separating layer 54 is formed on the support substrate 52. The support substrate 52 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 52 can be a wafer, so that several storage cubes 50 can be formed simultaneously on the support substrate 52.

[0019] The release layer 54 can be made of a polymer-based material that, together with the support substrate 52, can be removed from the overlying structures formed in subsequent steps. In some embodiments, the release layer 54 is an epoxy-based thermal release material that loses its adhesive properties when heated, for example, a light-heat conversion release coating (LTHC release coating). In other embodiments, the release layer 54 can be an ultraviolet adhesive (UV adhesive) that loses its adhesive properties when exposed to UV light. The release layer 54 can be dispensed as a liquid and cured, can be a laminate film that is laminated onto the support substrate 52, or the like. The top surface of the release layer 54 can be flattened and exhibit a high degree of planarity.

[0020] A wafer 56A is stacked on the support substrate 52. The wafer 56A has several integrated circuit devices, for example, a storage device 10A in the device area 52A. The storage device 10A is subsequently singulated so that it is incorporated into the storage cube 50. The storage device 10A has a semiconductor substrate 12A, an interconnect structure 14A, conductive vias 16A, and a dielectric layer 24A, but in this processing step, it does not have any die connectors in the dielectric layer 24A. The wafer 56A is stacked upside down on the support substrate 52 so that a major surface of the dielectric layer 24A faces / contacts the support substrate 52. As described in more detail below, the storage cube 50 is attached to another integrated circuit device after singulation.Fusible connectors are used to attach the memory cube 50 to the further integrated circuit device. In some embodiments, die connectors suitable for use with fusible connectors such as microbumps can be formed in the dielectric layer 24A. The microbumps are formed after the wafer stacking is complete to prevent damage to the microbumps during the stacking process.

[0021] In Fig. In step 2B, wafer 56A is thinned. Thinning can be performed by a CMP process, a grinding process, an etching process, or the like, or combinations thereof, and is carried out on the inactive surface of the semiconductor substrate 12A. Thinning exposes the conductive vias 16A. After thinning, the surfaces of the conductive vias 16A and the inactive surface of the semiconductor substrate 12A are coplanar (within process variations). As such, the conductive vias 16A are exposed on the back side of the memory device 10A.

[0022] In Fig. In step 2C, a wafer 56B is stacked on the support substrate 52. In particular, the front side of wafer 56B is attached to the back side of wafer 56A. Wafer 56B has several integrated circuit devices, for example, a memory device 10B in the device area 52A. The memory device 10B is subsequently singulated so that it is included in the memory cube 50. The memory device 10B has a semiconductor substrate 12B, an interconnect structure 14B, conductive vias 16B, die connectors 22B, and a dielectric layer 24B.

[0023] Wafer 56A and wafer 56B are bonded back-to-front, e.g., by hybrid bonding such that the back side of wafer 56A is bonded to the front side of wafer 56B. In particular, dielectric-dielectric bonds and metal-metal bonds are formed between wafer 56A and wafer 56B. In the illustrated embodiment, a dielectric layer 58 and die connectors 60 are formed on the back side of wafer 56A and are used for hybrid bonding.

[0024] The dielectric layer 58 is formed on the back side of the wafer 56A, for example, on the semiconductor substrate 12A. The dielectric layer 58 is laterally flush (within process variations) with the sidewalls of the integrated circuit device 10. The dielectric layer 58 can be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene-based (BCB-based) polymer, or the like; or a combination thereof. The dielectric layer 58 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments (described in more detail below), the semiconductor substrate 12A is recessed before the dielectric layer 58 is formed, so that the dielectric layer 58 surrounds the conductive vias 16A.

[0025] The die connectors 60 are formed on the back side of the wafer 56A and are in physical contact with the conductive vias 16A. The die connectors 60 can be conductive pillars, pads, or the like, to which external connections are made. The die connectors 60 can be made of a metal such as copper, aluminum, or the like, and can be formed, for example, by plating or the like. The die connectors 60 are electrically connected to integrated circuits of the storage device 10A via the conductive vias 16A. After formation, the dielectric layer 58 and the die connectors 60 are planarized using, for example, a CMP process, a back-etch process, or the like. After planarization, the top surfaces of the die connectors 60 and the dielectric layer 58 are coplanar (within process variations) and are exposed on the back side of the wafer 56A.

[0026] The dielectric layer 58 is bonded to the dielectric layer 24B by dielectric-dielectric bonding without the use of an adhesive material (e.g., a die-fixing film), and the die connectors 60 are bonded to the die connectors 22B by metal-metal bonding without the use of a eutectic material (e.g., solder). The bonding process may include pre-bonding and annealing. During pre-bonding, a small compressive force is applied to press the wafer 56B against the wafer 56A. Pre-bonding is performed at a low temperature, for example, room temperature, such as a temperature in the range of approximately 15°C to approximately 30°C, and after pre-bonding, the dielectric layer 24B and the dielectric layer 58 are bonded together.The bond strength is then improved in a subsequent annealing step, in which dielectric layer 24B and dielectric layer 58 are annealed at a high temperature, for example, in the range of approximately 140°C to approximately 280°C. After annealing, bonds such as fusion bonds are formed, connecting dielectric layer 24B and dielectric layer 58. For example, the bonds can be covalent bonds between the material of dielectric layer 58 and the material of dielectric layer 24B. The die connectors 22B and 60 are connected in a one-to-one mapping. The die connectors 22B and 60 may be in physical contact after pre-bonding or may expand during annealing to the point of physical contact. Furthermore, during tempering, the material of the die connectors 22B and the die connectors 60 mixes (e.g.copper), so that metal-metal bonds are also formed. Therefore, the resulting bonds between wafer 56A and wafer 56B are hybrid bonds, exhibiting both dielectric-dielectric and metal-metal bonds.

[0027] In a further embodiment, the die connectors 60 are omitted. The dielectric layer 58 is bonded to the dielectric layer 24B by dielectric-dielectric bonding without the use of an adhesive material (e.g., a die mounting film), and the conductive vias 16A are bonded to the die connectors 22B by metal-metal bonding without the use of a eutectic material (e.g., solder).

[0028] In another embodiment, the dielectric layer 58 and the die connectors 60 are omitted. The semiconductor substrate 12A can be bonded to the dielectric layer 24B by dielectric-dielectric bonding without the use of an adhesive material (e.g., a die mounting film), and the conductive vias 16A can be bonded to the die connectors 22B by metal-metal bonding without the use of a eutectic material (e.g., solder). For example, an oxide such as a native oxide, a thermal oxide, or the like can be formed on the inactive surface of the semiconductor substrate 12A and can be used for the dielectric-dielectric bonding.

[0029] In Fig. In step 2D, the steps described above are repeated so that wafers 56C, 56D, 56E, 56F, 56G, 56H are stacked on the support substrate 52. Each wafer 56C, 56D, 56E, 56F, 56G, 56H has several integrated circuit devices in the device area 52A, for example, memory devices 10C, 10D, 10E, 10F, 10G, 10H. In the subsequent processing, the memory devices 10C, 10D, 10E, 10F, 10G, 10H are singulated so that they are incorporated into the memory cube 50. Each of the wafers 56C, 56D, 56E, 56F, 56G, 56H is bonded directly to wafers 56B, 56C, 56D, 56E, 56F, 56G by back-front hybrid bonding. The last stacked wafer, e.g., wafer 56H, does not need to be thinned, so the conductive vias 16H of wafer 56H remain electrically isolated.

[0030] In Fig. 2E, a support substrate debonding process is performed to separate (or "debond") the support substrate 52 from the wafer stack, e.g., wafer 56A. According to some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separator layer 104, causing the separator layer 104 to decompose under the heat of the light and allowing the support substrate 52 to be removed. Removing the support substrate 52 exposes the main surface of the upper storage device (e.g., storage device 10A) of the storage cube 50. The wafer stack is then turned over and placed on a conveyor belt (not shown).

[0031] The die connectors 22A are then formed for the top layer of the storage cube 50, e.g., on a front face of the wafer 56A. The die connectors 22A can be conductive pillars, pads, or the like, to which external connections are made. In some embodiments, the die connectors 22A are conductive bumps, for example, microbumps. The die connectors 22A can (within process variations) have substantially vertical sidewalls. In the embodiment shown, the die connectors 22A are formed through the dielectric layer 24A such that they are connected to the metallization structure of the interconnect structure 14A. As an example of forming the die connectors 22A, openings are formed in the dielectric layer 24A, and a nucleation layer is formed above the dielectric layer 24A and in the openings.In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The structure of the photoresist corresponds to the die connectors 22A. The patterning creates openings through the photoresist, exposing the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer.The conductive material can be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material can contain a metal such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, the photoresist and sections of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed sections of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching. The remaining sections of the seed layer and the conductive material form the die connectors 22A.

[0032] The die connectors 22A differ from the die connectors 22B, 22C, 22D, 22E, 22F, 22G, and 22H. Specifically, the die connectors 22A are bumps (e.g., microbumps) that are raised from the main surface of the dielectric layer 24A. Conversely, the die connectors 22B, 22C, 22D, 22E, 22F, 22G, and 22H are bond pads with upper surfaces that are coplanar with the main surface of the dielectric layers 24B, 24C, 24D, 24E, 24F, 24G, and 24H, respectively (e.g., not raised from them). In other words, the upper storage device 10A of the storage cube 50 has conductive bumps on the front of the storage device, and the lower storage devices 10B, 10C, 10D, 10E, 10F, 10G, 10H of the storage cube 50 have bond pads on their respective fronts.

[0033] In Fig. 2F, a singulation process is performed along the scoring line areas, e.g., between the fixture area 52A and adjacent fixture areas. Singulation can be carried out by sawing, laser cutting, or the like. The singulation process can be performed before or after the formation of the die connectors 22A. Singulation separates the fixture area 52A from adjacent fixture areas. The resulting singulated storage cube 50 originates from the fixture area 52A. After singulation, the storage devices of the storage cube 50 are laterally flush (within process variations).

[0034] It is understood that the storage cube 50 can have any number of layers. In the embodiment shown, the storage cube 50 has eight layers. In another embodiment, the storage cube 50 has more or fewer than eight layers, for example, two layers, four layers, sixteen layers, thirty-two layers, or the like.

[0035] After the formation of the storage cube 50 is complete (e.g., after forming the die connectors 22A and singulating the storage cube 50), the resulting storage cube 50 is inspected using a probe 62. The probe 62 is physically and electrically connected to the die connectors 22A. The die connectors 22A are used to inspect the storage cube 50 so that only known good storage cubes are used for further processing. The inspection may include checking the functionality of the storage devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, or it may include checking for known open circuits or short circuits that can be expected based on the design of the storage devices. During the inspection, all storage devices of the storage cube 50 can be inspected sequentially.

[0036] The Fig. Figures 3A to 3D are cross-sectional views of intermediate steps in a process for forming an HBM device 100 according to some embodiments. As described in more detail below, the Fig. 3A to 3D a process in which an HBM device 100 is created by stacking a memory cube 50 on a second integrated circuit device (e.g. a logic device 10L, see Fig. 3A). The second integrated circuit device is a bare die that can be formed in a wafer 102. Forming an HBM device 100 in a device area 102A of the wafer 102 is shown; however, it should be noted that the wafer 102 can have any number of device areas and an HBM device 100 can be formed in any device area.

[0037] The HBM device 100 can subsequently be used in the formation of an integrated circuit package. In particular, as described in more detail below, the HBM device 100 can be packaged in a three-dimensional integrated circuit package (3DIC package), for example, a system-in-package (SiP). Examples of a 3DIC package include a chip-on-wafer package (CoW package), a chip-on-wafer-on-substrate package (CoWoS package), an integrated fan-out package (InFO package), and the like, although it should be clear that embodiments can be applied to other 3DIC packages.

[0038] In Fig. Wafer 102 is obtained at step 3A. Wafer 102 has a logic device 10L in device area 102A. The logic device 10L is singulated in subsequent processing so that it can be incorporated into the HBM device 100. The logic device 10L can be an interface device or connection device, a buffer device, a control device, or the like for the storage devices of the storage cube 50. In some embodiments, the logic device 10L provides the input / output interface (I / O interface) for the HBM device 100. The logic device 10L has a semiconductor substrate 12L, an interconnect structure 14L, conductive vias 16L, die connectors 22L, and a dielectric layer 24L.The 22L die connectors are used for connections to other devices, for example, devices in an integrated circuit package in which the HBM device 100 can be implemented. The 22L die connectors can be made from a similar material and by a similar process as those mentioned above. Fig. The die connectors 22A described in section 2E can be formed. For example, the die connectors 22L can be connectors suitable for use with fusible connectors such as microbumps and which extend through the dielectric layer 24L.

[0039] In Fig. In step 3B, wafer 102 is thinned. Thinning can be performed by a CMP process, a grinding process, an etching process, or the like, or combinations thereof, and is carried out on the inactive surface of the semiconductor substrate 12L. Thinning exposes the conductive vias 16L. After thinning, the surfaces of the conductive vias 16L and the inactive surface of the semiconductor substrate 12L are coplanar (within process variations). As such, the conductive vias 16L are exposed on the back side of the logic device 10L.

[0040] A dielectric layer 104 is then formed over the wafer 102, e.g., on the back side of the logic device 10L. The dielectric layer 104 can be made of a similar material and by a similar process as that described in relation to Fig. The dielectric layer 58 described in section 2C is formed. Then, die connectors 106 are formed that extend through the dielectric layer 104. The die connectors 106 can be made of a similar material and by a similar process as those described in section 2C. Fig. The die connectors 22A described in section 2E can be configured. For example, the die connectors 106 can be connectors suitable for use with fusible connectors such as micro-bumps. The die connectors 106 are physically connected to the conductive vias 16L and are electrically connected to the integrated circuits of the logic device 10L via the conductive vias 16L.

[0041] In Fig. In 3C, a memory cube 50 is attached to the wafer 102, for example, to the back of the logic device 10L. The memory cube 50 is connected to the wafer 102 by fusible connectors 108. The fusible connectors 108 can be formed on the die connectors 106 and / or the die connectors 22A. The fusible connectors 108 can be made of a solder material such as tin, tin-lead, gold, silver, tin-silver, tin-bismuth, copper, copper-tin, copper-tin-silver, copper-nickel-tin-silver, palladium, indium, nickel, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof. In some embodiments, the fusible connectors 108 are formed by initially forming a layer of solder material by evaporation, electroplating, printing, solder transfer, ball placement, or the like.After a layer of solder material has formed on the structure, it can be melted to shape the material into the desired bump shape. In some embodiments, the fusible connectors 108 are formed on the die connectors 106. In such embodiments, the storage cube 50 is connected to the wafer 102 by bringing the die connectors 22A into contact with the fusible connectors 108 and then melting the fusible connectors 108, thereby soldering the storage cube 50 to the wafer 102. Thus, solder joints are formed between the die connectors 22A and the die connectors 106, connecting the storage cube 50 to the wafer 102.

[0042] In some embodiments, an underfill 110 is formed between the storage cube 50 and the wafer 102, surrounding the fusible connectors 108. The underfill 110 can reduce stresses and protect the connections resulting from the melting of the fusible connectors 108. The underfill 110 can be formed by a capillary flow process after the storage cube 50 is attached or by a suitable deposition process before the storage cube 50 is attached.

[0043] In Fig. In 3D, an encapsulation 112 is formed on and around the various components. After formation, the encapsulation 112 encapsulates the storage cube 50 and contacts the sidewalls of the underfill 110 and each storage device of the storage cube 50. The encapsulation 112 can be a molding compound, an epoxy resin, or the like. The encapsulation 112 can be applied by compression molding, injection molding, or the like, and can be formed over the wafer 102 such that the storage cube 50 is buried or covered. The encapsulation 112 can be applied in liquid or semi-liquid form and subsequently cured. Optionally, a planarization process is performed on the encapsulation 112 to expose the storage cube 50. After the planarization process, the top surfaces of the storage cube 50 and the encapsulation 112 are coplanar (within process variations).The planarization process can be, for example, a chemical-mechanical polishing (CMP) process, a grinding process, or the like. In some embodiments, planarization can be omitted, for example, if the storage cube 50 is already exposed.

[0044] A singulation process is then carried out along scoring line areas, for example, around device area 102A. Singulation can be performed by sawing, laser cutting, or the like. The singulation process separates device area 102A (which contains logic device 10L) from adjacent device areas, so that an HBM device 100 is formed that contains logic device 10L. The singulated logic device 10L has a greater width than any of the storage devices of the storage cube 50. After singulation, logic device 10L and the encapsulation 112 are laterally flush (within process variations).

[0045] Conductive connectors 114 are formed on the die connectors 22L. The conductive connectors 114 can be ball grid array (BGA) connectors, solder balls, metal columns, flip-chip interconnect bumps (C4 bumps), bumps formed by ENEPIG (electroless nickel-electroless palladium-gold immersion) technology, or the like. The conductive connectors 114 can contain a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 114 are formed by initially forming a solder layer by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder has formed on the structure, melting can be performed to shape the material into the desired bump shape.In another embodiment, the conductive connectors 114 have metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer can contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or a combination thereof, and can be formed by a plating process. The conductive connectors 114 can be formed before or after the singulation process. The conductive connectors 114 are used for external connections (described below).

[0046] Fig. 3E is a detailed view of area 102R of the Fig. 3D according to some embodiments. In this embodiment, the dielectric layer 58 is formed around the conductive vias 16A, and the die connectors 60 are formed in the dielectric layer 58 such that they contact the conductive vias 16A. The die connectors 22B contact the die connectors 60. Furthermore, it shows Fig. 3E also makes it clearer that the die connectors 106 and the die connectors 22A are bumps (e.g. microbumps) that are raised from the main surfaces of the dielectric layer 104 and the dielectric layer 24A, respectively.

[0047] Fig. 3F is a detailed view of area 102R of the Fig. 3D according to some further embodiments. In this embodiment, the dielectric layer 58 is formed around the conductive vias 16A, but the die connectors 60 are omitted. Instead, the die connectors 22B contact the conductive vias 16A. Furthermore, it shows Fig. 3F also makes it clearer that the die connectors 106 and the die connectors 22A are bumps (e.g. microbumps) that are raised from the main surfaces of the dielectric layer 104 and the dielectric layer 24A, respectively.

[0048] The Fig. Figures 4A to 4D are cross-sectional views of intermediate steps in a process for forming an HBM device 100 according to some further embodiments. As described in more detail below, the Fig. 4A to 4D a process in which an HBM device 100 is formed by placing a memory cube 50 onto a package component 200 (see Fig. 4D) instead of being stacked on a bare die. The package component 200 is formed on a carrier substrate 202 and includes a second integrated circuit device (e.g., a logic device 10L, see Fig. 4A). It is shown that an HBM device 100 is formed in a device area 202A of the support substrate 202; however, it should be noted that the support substrate 202 can have any number of device areas and an HBM device 100 can be formed in any device area.

[0049] In Fig. 4A A support substrate 202 is provided, and a separation layer 204 is formed on the support substrate 202. The support substrate 202 can be made of a similar material and by a similar process as that described in Fig. The support substrate 52 described in 2A is formed. The separating layer 204 can be made of a similar material and by a similar process as described in Fig. The separating layer 54 described in 2A is formed.

[0050] A single logic device 10L is arranged on the separating layer 204. The logic device 10L can be made of a similar material and by a similar method as the one described above. Fig. The logic device 10L described in 3A is designed, with the exception that the die connectors 22L do not have to be bumps and the conductive vias 16L are exposed on a rear side of the logic device 10L.

[0051] An encapsulation 206 is formed on and around the logic device 10L. The encapsulation 206 can be made of a similar material and by a similar method as that described in relation to Fig. The encapsulation 112 described in 3D can be formed. If necessary, a planarization process can be carried out on the encapsulation 206 so that the die connectors 22L are exposed.

[0052] A dielectric layer 208 is formed on the encapsulation 206 and the front face of the logic device 10L. The dielectric layer 208 can be an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene-based (BCB-based) polymer, or the like; or a combination thereof. The dielectric layer 208 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like.

[0053] Under-bump metallurgies (UBMs) 210 are formed and connected to the logic device 10L. The UBMs 210 have bump sections on and along the main surface of the dielectric layer 208 and have via sections extending through the dielectric layer 208 such that they are physically and electrically connected to the die connectors 22L. As a result, the UBMs 210 are electrically connected to the logic device 10L. As an example of forming the UBMs 210, openings are formed through the dielectric layer 208, and a nucleation layer is formed above the dielectric layer 208 and in the openings extending through the dielectric layer 208. In some embodiments, the nucleation layer is a metal layer, which may be a single layer or a composite layer having a plurality of sublayers formed from different materials.In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and exposed to light for patterning. The structure of the photoresist corresponds to UBMs 210. The patterning creates openings through the photoresist, exposing the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, for example, electroplating or electroless plating or the like. The conductive material can contain a metal such as copper, titanium, tungsten, aluminum, or the like.The combination of the conductive material and the underlying sections of the nucleation layer forms the UBMs 210. The photoresist and the sections of the nucleation layer where the conductive material is not formed are removed. The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed sections of the nucleation layer are removed, for example, using a suitable etching process, such as wet or dry etching.

[0054] In Fig. 4B, a substrate debonding process is performed to separate (or debond) the substrate 202 from the logic device 10L. According to some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separating layer 204, causing the separating layer 204 to decompose under the heat of the light and allowing the substrate 202 to be removed. The structure can then be turned over and, for example, placed on a tape.

[0055] A dielectric layer 212 is then formed on the encapsulation 206 and the back side of the logic device 10L. The dielectric layer 212 can be formed from a similar material and by a similar process as the dielectric layer 208.

[0056] UBMs 214 are then formed and connected to the logic device 10L. The UBMs 214 have bump sections on and extending along the main surface of the dielectric layer 212 and have via sections extending through the dielectric layer 212 in such a way that they are physically and electrically connected to the conductive vias 16L. The UBMs 214 can be formed from a similar material and by a similar process as the UBMs 210.

[0057] In Fig. 4C, a memory cube 50 is attached to the package component 200, e.g., to the UBMs 214. The memory cube 50 is a known good memory cube that has been tested. The die connectors 22A of the memory cube 50 are connected to the UBMs 214 of the package component 200 with fusible connectors 108 in a similar manner to that described above. Fig. 3C described connected. In some embodiments, an underfill 110 is connected between the storage cube 50 and the package component 200 in a similar manner to that described above. Fig. 3C described and trained.

[0058] In Fig. 4D will encapsulate 112 on and around the various components in a similar way to how it is applied to Fig. The device is described in 3D. A singulation process is then carried out along scoring lines, for example, around the fixture area 202A. Singulation can be performed by sawing, laser cutting, or the like. The singulation process separates the fixture area 202A (which contains the package component 200) from adjacent fixture areas, so that an HBM fixture 100 is formed that contains the package component 200. After singulation, the packaging component 200 and the encapsulation 112 are laterally flush (within process variations).

[0059] Conductive connectors 114 are formed on the UBMs 210. The conductive connectors 114 can be made from a similar material and by a similar process as those described in relation to Fig. The conductive connectors 114 described in 3D can be formed. The conductive connectors 114 can be formed before or after the singulation process. The conductive connectors 114 are used for an external connection (described below).

[0060] Attaching the memory cube 50 to the package component 200 instead of a bare die advantageously allows the logic device 10L to be of any desired size. If the HBM device 100 is attached by directly attaching the memory cube 50 to a bare die (as in the diagram relating to...) Fig. In the embodiment described in 3C), the bare die has a greater width than any of the storage devices of the memory cube 50. However, if the HBM device 100 is formed by attaching the memory cube 50 to a package component, the package component has a greater width than any of the storage devices of the memory cube 50, but the packaged logic device 10L can have a width that is greater than, less than, or similar to any of the storage devices of the memory cube 50.

[0061] The Fig. Figures 5A to 5C are cross-sectional views of intermediate steps in a process for forming an HBM device 100 according to some further embodiments. As described in more detail below, the Fig. 5A to 5C a process in which an HBM device 100 is formed by a second integrated circuit device (e.g. a logic device 10L, see Fig. 5A) is stacked onto a storage cube 50 before the storage cube 50 is singulated. It is a processing of a structure (e.g., an unsingulated wafer stack) similar to that described in relation to Fig. The embodiment described in Figure 2E is shown. It shows the formation of an HBM device 100 in a device area 52A of the wafer stack; however, it should be noted that the wafer stack can have any number of device areas, and an HBM device 100 can be formed in any device area. In this embodiment, the storage cubes 50 are inspected before singulation, and only known good storage cubes 50 (e.g., known good device areas of the unsingulated wafer stack) can be selected using the device described in the Fig. The processes shown in 5A to 5C are processed.

[0062] In Fig. In step 5A, a single logic device 10L is bonded to the wafer stack, for example, the memory cube 50. The logic device 10L can be made of a similar material and by a similar process as those described in relation to Fig. The logic device 10L described in Section 3A is formed, except that the die connectors 22L need not be protrusions and the conductive vias 16L are exposed on a rear side of the logic device 10L. A dielectric layer 104 is formed on the rear side of the logic device 10L. The dielectric layer 104 is formed from a similar material and by a similar process as described in Section 3A. Fig. The dielectric layer 58 described in Section 2C is formed. The die connectors 106 are formed such that they extend through the dielectric layer 104. The die connectors 106 can be made of a similar material and by a similar process as those described in Section 2C. Fig. The die connectors 22A described in section 2E can be configured. For example, the die connectors 106 can be connectors suitable for use with fusible connectors such as micro-humps. The die connectors 106 of the logic device 10L are connected to the die connectors 22A of the memory cube 50 with fusible connectors 108 in a similar manner to how described in section 2E. Fig. 3C described connected. In some embodiments, an underfill 110 is connected between the logic device 10L and the storage cube 50 in a similar manner to that described in relation to Fig. 3C described and trained.

[0063] In Fig. 5B, an encapsulation 124 is formed on and around the logic device 10L. The encapsulation 124 can be made of a similar material and by a similar method as that described in relation to Fig. The encapsulation 112 described in 3D can be formed. If necessary, a planarization process can be carried out on the encapsulation 124 so that the die connectors 22L are exposed.

[0064] A dielectric layer 126 is formed on the encapsulation 124 and the front face of the logic device 10L. The dielectric layer 126 can be made of a similar material and by a similar method as that described in relation to Fig. The dielectric layer 208 described in 4A is formed.

[0065] Then, UBMs 128 are formed, which are connected to the logic device 10L. The UBMs 128 have bump sections on the main surface of the dielectric layer 126 and extend along it, and have via sections that extend through the dielectric layer 126 in such a way that they are physically and electrically connected to the die connectors 22L. The UBMs 128 can be made from a similar material and by a similar process as those described in relation to Fig. 4A described UBMs 210 will be trained.

[0066] In Fig. 5C, a singulation process is performed along scoring line areas, e.g., around the fixture area 52A. Singulation can be carried out by sawing, laser cutting, or the like. The singulation process separates the fixture area 52A (which contains the storage cube 50) from adjacent fixture areas, so that an HBM fixture 100 is formed that contains the storage cube 50. After singulation, the storage cube 50 and the encapsulation 124 are laterally flush (within process variations).

[0067] Conductive connectors 114 are formed on the UBMs 128. The conductive connectors 114 can be made of a similar material and by a similar process as those described in relation to Fig. The conductive connectors 114 described in 3D can be formed. The conductive connectors 114 can be formed before or after the singulation process. The conductive connectors 114 are used for an external connection (described below).

[0068] Attaching the logic device 10L to the storage cube 50 before singulation advantageously allows the use of smaller logic devices. When the HBM device 100 is formed by attaching a logic device 10L to the storage cube 50, the logic device 10L has a smaller width than the storage cubes 50. The horizontal footprint of the HBM device 100 can thus be reduced.

[0069] The Fig. Figures 2A to 5C show embodiments in which memory cubes 50 are formed by wafer-wafer stacking (WoW stacking), where, for example, a wafer stack is formed and then singulated to form multiple memory cubes 50. As described in more detail below, in some embodiments the memory cubes 50 can be formed by chip-chip stacking (CoC stacking), where, for example, a wafer is singulated to form multiple integrated circuit devices, and the integrated circuit devices are stacked to form a memory cube 50. Such memory cubes 50 can also be used in forming HBM devices, as described in relation to the Fig. 3A to 5C are described.

[0070] The Fig. Figures 6A to 6F are cross-sectional views of intermediate steps in a process for forming a storage cube 50 according to some further embodiments. As described in more detail below, the Fig. 6A to 6F describe a process in which a storage cube 50 is formed by stacking several first integrated circuit devices onto a support substrate 52. The first integrated circuit devices can each have a structure similar to the integrated circuit device 10 described above with reference to Fig. As described in Figure 1, the integrated circuit devices can, in one embodiment, be storage devices. Stacking the first integrated circuit devices to form a storage cube 50 in a device area 52A of the support substrate 52 is shown; however, it should be noted that the support substrate 52 can have any number of device areas, and a storage cube 50 can be formed in any of the device areas. The storage cube 50 is formed from top to bottom (or vice versa) by chip-chip stacking (CoC stacking), wherein a single integrated circuit device is provided for the top layer of the storage cube 50, and single integrated circuit devices for underlying layers of the storage cube 50 are subsequently stacked on top of the upper integrated circuit device. Each layer of the storage cube 50 is encapsulated.The memory cubes 50 are checked after training in order to reduce or avoid subsequent processing of known defective memory cubes 50.

[0071] In Fig. 6A a support substrate 52 is provided, and a separation layer 54 is formed on the support substrate 52. The support substrate '2 can be adapted to the Fig. 2A. The separating layer 54 can be similar to the one described in relation to Fig. resemble those described in 2A.

[0072] A single storage device 10A is then stacked onto the support substrate 52. The storage device 10A has a semiconductor substrate 12A, an interconnect structure 14A, conductive vias 16A, and a dielectric layer 24A, but in this processing step, it does not have any die connectors in the dielectric layer 24A. Die connectors suitable for use with meltable connectors such as microbumps can be formed in the dielectric layer 24A during subsequent processing steps.

[0073] In Fig. In step 6B, the isolated memory device 10A is thinned. The thinning can be performed by a CMP process, a grinding process, an etching process, or the like, or combinations thereof, and is carried out on the inactive surface of the semiconductor substrate 12A. The thinning exposes the conductive vias 16A. After thinning, the surfaces of the conductive vias 16A and the inactive surface of the semiconductor substrate 12A are coplanar (within process variations). As such, the conductive vias 16A are exposed on the back side of the memory device 10A.

[0074] In Fig. In step 6C, a single storage device 10B is stacked on top of the storage device 10A. Specifically, the front side of the storage device 10B is attached to the back side of the storage device 10A. The storage device 10B comprises a semiconductor substrate 12B, an interconnect structure 14B, conductive vias 16B, die connectors 22B, and a dielectric layer 24B. The storage device 10A and the storage device 10B are bonded by back-to-front direct hybrid bonding, such that the back side of the storage device 10A is bonded to the front side of the storage device 10B. The hybrid bonding can be performed in a similar manner to that described in step 1. Fig. 2C can be carried out as described. For example, die connectors 60 and a dielectric layer 58 can be formed on the back side of the storage device 10B. The dielectric layer 58 is bonded to the dielectric layer 24B by dielectric-dielectric bonding without the use of an adhesive material (e.g., a die mounting film), and the die connectors 60 are bonded to the die connectors 22B by metal-metal bonding without the use of a eutectic material (e.g., solder).

[0075] In Fig. In step 6D, the steps described above are repeated so that individual storage devices 10C, 10D, 10E, 10F, 10G, 10H are stacked over the support substrate 52. Each of the storage devices 10C, 10D, 10E, 10F, 10G, 10H is bonded directly to the storage devices 10B, 10C, 10D, 10E, 10F, and 10G, respectively, by back-to-front hybrid bonding. The last stacked storage device, e.g., storage device 10H, does not need to be thinned, so that the conductive vias 16H of storage device 10H remain electrically insulated.

[0076] In some embodiments, a dielectric layer 64 is formed that surrounds the storage devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H. The dielectric layer 64 fills gaps between the storage devices in device area 52A and storage devices in adjacent device areas, thereby protecting the storage devices. The dielectric layer 64 can be an oxide such as silicon dioxide, PSG, BSG, BPSG, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene-based (BCB-based) polymer, or the like; an encapsulation material such as a molding compound, an epoxy, or the like; or a combination thereof. In some embodiments, the dielectric layer 64 is an oxide such as silicon dioxide.

[0077] In Fig. 6E, a support substrate debonding process is performed to separate (or "debond") the support substrate 52 from the stack of integrated circuit devices, e.g., the storage device 10A. According to some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separator layer 54, causing the separator layer 54 to decompose under the heat of the light and allowing the support substrate 52 to be removed. The wafer stack is then turned over and placed on a conveyor belt (not shown).

[0078] The die connectors 22A are then formed on a front face of the storage device 10A. The die connectors 22A can be made from a similar material and by a similar process as those in Fig. 2E described training will be provided.

[0079] In Fig. 6F performs a singulation process along the scoring lines, e.g., between the fixture area 52A and adjacent fixture areas. Singulation can be carried out by sawing, laser cutting, or the like. The singulation process can be performed before or after the formation of the die connectors 22A. Singulation separates the fixture area 52A from adjacent fixture areas. The resulting singulated storage cube 50 originates from the fixture area 52A. After singulation, the dielectric layer 64 encapsulates the storage devices laterally, and the dielectric layer 64 is laterally flush with the side walls of the storage cube 50 (within process variations).

[0080] It is understood that the storage cube 50 can have any number of layers. In the embodiment shown, the storage cube 50 has eight layers. In another embodiment, the storage cube 50 has more or fewer than eight layers, for example, two layers, four layers, sixteen layers, thirty-two layers, or the like.

[0081] After the formation of the storage cube 50 is complete (e.g., after forming the die connectors 22A and singulating the storage cube 50), the resulting storage cube 50 is inspected using a probe 62. The probe 62 is physically and electrically connected to the die connectors 22A. The die connectors 22A are used to inspect the storage cube 50 so that only known good storage cubes are used for further processing. The inspection may include checking the functionality of the storage devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, or it may include checking for known open circuits or short circuits that can be expected based on the design of the storage devices. During the inspection, all storage devices of the storage cube 50 can be inspected sequentially.

[0082] The 50-unit storage cube can then be used to form a high-bandwidth memory device (HBM device). Fig. 7, Fig. 8 to Fig. Figure 9 shows cross-sectional views of HBM devices 100 implementing the storage cube 50 according to some embodiments.

[0083] Fig. Figure 7 shows an embodiment in which an HBM device 100 is formed by stacking a memory cube 50 onto a second integrated circuit device (e.g., a logic device 10L), for example, a bare die. The HBM device 100 of Fig. 7 can be achieved through a similar process to the one described in the Fig. 3A to 3D described, except that it has a storage cube 50 formed by CoC stacking, for example a storage cube formed by the one described in relation to the Fig. The process described in sections 6A to 6F is being trained.

[0084] Fig. Figure 8 shows an embodiment in which an HBM device 100 is formed by stacking a storage cube 50 onto a package component 200, which includes a second integrated circuit device (e.g., a logic device 10L). The HBM device 100 of Fig. 8 can be achieved through a similar process to the one described in the Fig. 4A to 4D are formed, except that it has a storage cube 50 formed by CoC stacking, for example a storage cube formed by the one described in relation to the Fig. The process described in sections 6A to 6F is being trained.

[0085] Fig. Figure 9 shows an embodiment in which an HBM device 100 is formed by stacking a second integrated circuit device (e.g., a logic device 10L) onto a storage cube 50 before the storage cube 50 is separated. The HBM device 100 of Fig. 9 can be achieved through a similar process to the one described in the Fig. described in 5A to 5C, except that it has a storage cube 50 formed by stacking CoCs, for example a storage cube formed by the one described in relation to the Fig. The process described in sections 6A to 6F is being trained.

[0086] The Fig. Figures 2A to 9 show embodiments in which storage cubes 50 are configured to contain only storage devices. As described in more detail below, in some embodiments the storage cubes 50 can be configured to include other devices, such as passive devices, which are used by the storage devices of the storage cubes.

[0087] The Fig. Figures 10A to 10E are cross-sectional views of intermediate steps in a process for forming a storage cube 50 according to some embodiments. As described in more detail below, the Fig. 10A to 10E describe a process in which a storage cube 50 is formed by stacking several wafers, each having first integrated circuit devices, onto a support substrate 52. The first integrated circuit devices can each have a structure similar to the integrated circuit device 10 described above with reference to Fig. The wafers described in Figure 1 can, in one embodiment, be storage devices. In this embodiment, a passive device is provided in the wafer stack, for example, on a middle level of the wafer stack. The wafer stack is singulated so that several storage cubes 50 are formed. Stacking wafers to form a storage cube 50 in a device area 52A of the support substrate 52 is shown; however, it should be noted that the support substrate 52 can have any number of device areas, and a storage cube 50 can be formed in each device area. The storage cube 50 is formed from top to bottom (or vice versa) by wafer-wafer stacking (WoW stacking), wherein a wafer is provided for the top layer of the storage cube 50, and wafers for underlying layers of the storage cube 50 are subsequently stacked onto the top wafer.In this embodiment, the passive device is located on a middle level of the stack. The storage cubes 50 are inspected after forming to reduce or prevent subsequent processing of known defective storage cubes 50.

[0088] In Fig. In step 10A, a support substrate 52 is provided, and a separation layer 54 is formed on the support substrate 52. The support substrate 52 can be adapted to the Fig. 2A. The separating layer 54 can be similar to the one described in relation to Fig. resemble those described in 2A.

[0089] The wafers 56A, 56B, 56C, 56D are then stacked over the support substrate 52 by aligning them with respect to the Fig. The steps described in sections 2A to 2C are performed / repeated. Wafers 56A, 56B, 56C, and 56D each have several integrated circuit devices, for example, memory devices 10A, 10B, 10C, and 10D, respectively, in device area 52A. In the subsequent processing, the memory devices 10A, 10B, 10C, and 10D are separated so that they are included in the memory cube 50. Wafer 56A is stacked onto the support substrate 52. Each of the wafers 56B, 56C, and 56D is directly bonded to wafers 56A, 56B, and 56C by back-front hybrid bonding.

[0090] A dielectric layer 66 and die connectors 68 are formed on the back side of the wafer 56D. The dielectric layer 66 can be made of a similar material and by a similar process as those described in relation to Fig. The dielectric layer 58 described in section 2C can be formed. The die connectors 68 can be made of a similar material and by a similar process as those described in section 2C. Fig. The die connectors 60 described in section 2C are formed. The die connectors 68 are physically connected to the conductive vias 16D and are electrically connected to integrated circuits of the storage device 10D via the conductive vias 16D.

[0091] In Fig. In 10B, a passive device 70 is bonded to the storage device 10D, e.g., to the wafer 56D. The passive device 70 can be an integrated passive device (IPD), an integrated power management circuit (PMIC), an integrated voltage regulator (IVR), or the like. In some embodiments, the passive device 70 is an IVR for the storage devices in the storage cube 50. The passive device 70 has a substrate 72 that corresponds to the one described above. Fig. The passive device 70 may resemble the semiconductor substrate 12 described in Section 1, but further comprises passive devices (e.g., resistors, capacitors, inductors, etc.) and may be free of active devices (e.g., transistors, diodes, etc.). The passive device 70 also has conductive vias 74, die connectors 76, and a dielectric layer 78 on the front side of the passive device 70, and die connectors 80 and a dielectric layer 82 on the back side of the passive device 70. The conductive vias 74 connect the die connectors 76 to the die connectors 80. The passive device 70 is a single device that is bonded to the storage device 10D by hybrid bonding such that the back side of the storage device 10D is bonded to the front side of the passive device 70. For example, the dielectric layer 66 is bonded by dielectric-dielectric bonding without the use of an adhesive material (e.g.a die mounting film) is bonded to the dielectric layer 78, and a first subset 68A of the die connectors is bonded to the die connectors 76 by metal-to-metal bonds without the use of a eutectic material (e.g. solder).

[0092] A dielectric layer 84 is then formed, surrounding the passive device 70. The dielectric layer 84 can be formed after the passive device 70 has been arranged but before annealing to complete the hybrid bond, or it can be formed after annealing. The dielectric layer 84 fills gaps between the passive device 70 in device area 52A and passive devices in adjacent device areas, thereby protecting the passive devices. The dielectric layer 84 can be formed from a similar material and by a similar process as described in relation to Fig. The dielectric layer 64 described in 6D is formed. In some embodiments, the dielectric layer 84 is an oxide such as silicon oxide.

[0093] Conductive vias 86 are then formed such that they extend through the dielectric layer 84. As an example of forming the conductive vias 86, openings in the dielectric layer 84 are patterned. The patterning can be carried out by a suitable method, for example, by exposing the dielectric layer 84 to light if the dielectric layer 84 is a photosensitive material, or by etching the dielectric layer 84, for example, using anisotropic etching. The openings expose a second subset 68B of the die connectors. A seed layer is formed on the dielectric layer 84 and on portions 68B of the die connectors exposed by the openings.In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In one particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A conductive material is formed on the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like. Excess portions of the seed layer and the conductive material are then removed, the excess portions being those that lie above the dielectric layer 84.Removal can be achieved through a planarization process. This process is performed on the seed layer, the conductive material, the dielectric layer 84, and the passive device 70. The removal simultaneously eliminates excess portions of the seed layer and conductive material, exposing the die connectors 80 and the dielectric layer 82. The planarization process can be, for example, a CMP process, a grinding process, a re-etching process, or a combination thereof. The remaining portions of the seed layer and conductive material in the openings form the conductive vias 86. After the planarization process, the top surfaces of the conductive vias 86, the dielectric layer 84, the dielectric layer 82, and the die connectors 80 are coplanar (within process variations).

[0094] In Fig. 10C wafers 56E, 56F, 56G, 56H are stacked over the support substrate 52 by aligning them with respect to the Fig. The steps described in sections 2A to 2C are performed / repeated. Wafers 56E, 56F, 56G, and 56H each have several integrated circuit devices, for example, storage devices 10E, 10F, 10G, and 10H, respectively, in device area 52A. In the subsequent processing, the storage devices 10E, 10F, 10G, and 10H are singulated so that they are included in the storage cube 50. Wafer 56E is bonded to the passive device 70, with some sections of the dielectric layer 84 and the conductive vias 86 participating in the hybrid bonding. For example, dielectric layer 24E is bonded to dielectric layer 82 and dielectric layer 84 by dielectric-dielectric bonding without the use of any adhesive material (e.g., epoxy).a die mounting film is used, and the die connectors 22E are bonded to the die connectors 80 and the conductive vias 86 by metal-to-metal bonds without the use of a eutectic material (e.g., solder). Each of the wafers 56F, 56G, 56H is directly bonded to the wafers 56E, 56F, 56G by back-front hybrid bonding. The last stacked wafer, e.g., wafer 56H, does not need to be thinned, so the conductive vias 16H of wafer 56H remain electrically insulated.

[0095] In Fig. In 10D, a support substrate debonding process is performed to separate (or "debond") the support substrate 52 from the stack of integrated circuit devices, e.g., the storage device 10A. According to some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separator layer 54, causing the separator layer 54 to decompose under the heat of the light and allowing the support substrate 52 to be removed. The wafer stack is then turned over and placed on a conveyor belt (not shown).

[0096] The die connectors 22A are then formed on a front face of the storage device 10A. The die connectors 22A can be made from a similar material and by a similar process as those in Fig. 2E described training will be provided.

[0097] In Fig. A singulation process is performed along the scoring line areas, e.g., between the fixture area 52A and adjacent fixture areas. Singulation can be carried out by sawing, laser cutting, or the like. The singulation process can be performed before or after the formation of the die connectors 22A. Singulation separates the fixture area 52A from adjacent fixture areas. The resulting singulated storage cube 50 originates from the fixture area 52A.

[0098] It is understood that the storage cube 50 can have any number of layers. In the embodiment shown, the storage cube 50 has eight layers of storage devices and one layer of a passive device. In another embodiment, the storage cube 50 has more or fewer than eight layers of storage devices, for example, two layers, four layers, sixteen layers, thirty-two layers, or the like. The storage cube 50 can also have more than one layer of passive devices.

[0099] After the formation of the storage cube 50 is complete (e.g., after forming the die connectors 22A and singulating the storage cube 50), the resulting storage cube 50 is inspected using a probe 62. The probe 62 is physically and electrically connected to the die connectors 22A. The die connectors 22A are used to inspect the storage cube 50 so that only known good storage cubes are used for further processing. The inspection may include checking the functionality of the storage devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H and the passive device 70, or it may include checking for known open circuits or short circuits that can be expected based on the design of the storage devices. During the inspection, all devices of the storage cube 50 can be inspected sequentially.

[0100] The 50-unit storage cube can then be used to form a high-bandwidth memory device (HBM device). Fig. Figure 11 is a cross-sectional view of an HBM device 100 implementing the storage cube 50 according to some further embodiments. Fig. Figure 11 shows an embodiment in which an HBM device 100 is formed by stacking a memory cube 50 onto a second integrated circuit device (e.g., a logic device 10L), for example, a bare die. The HBM device 100 of Fig. 11 can be achieved through a similar process to the one relating to the Fig. 3A to 3D are designed, except that a storage cube 50 is designed which has a passive device 70, for example a storage cube which is designed by the in relation to the Fig. The process described in sections 10A to 10E is being trained.

[0101] Although the Fig. Figures 10A to 10E show an embodiment in which a storage cube 50 with a passive device 70 is formed by wafer-wafer stacking (WoW stacking). It should be noted that a storage cube 50 with a passive device 70 can also be formed by chip-chip stacking (CoC stacking), for example by the one shown in the Fig. Process shown in 6A to 6F. Fig. Figure 12 is a cross-sectional view of an HBM device 100 implementing such a storage cube 50 according to some embodiments. Fig. Figure 12 shows an embodiment in which an HBM device 100 is formed by stacking a storage cube 50 onto a second integrated circuit device (e.g. a logic device 10L), for example a bare die.

[0102] The HBM devices 100 of the Fig. 11 and Fig. 12 will be processed through a similar process to the one used for the Fig. 3A to 3D described, except that a storage cube 50 is formed which has a passive device 70. It is further understood that HBM devices can also be formed by similar processes to those described in relation to the Fig. 4A to 4D and 5A to 5C can be designed, except that a storage cube 50 is designed which has a passive device 70.

[0103] Fig. Figure 13 shows an HBM device 100 according to some further embodiments. As described in more detail below, it shows Fig. 13 A device in which several memory cubes, such as a 50A memory cube and a 50B memory cube, are stacked on a second integrated circuit device (e.g., a logic device 10L). The encapsulation 112 thus surrounds both 50A and 50B memory cubes. The 50A and 50B memory cubes are known to be good memory cubes that have been tested. The 50A memory cube can be used in a similar way to how described above. Fig. 3C described on the wafer 102. In the embodiment shown, die connectors 116 and a dielectric layer 118 are formed on the rear side of the lower device of the storage cube 50A. The die connectors 116 can be made of a similar material and by a similar method as those described in relation to Fig. The die connectors 22A described in section 2E are formed. The dielectric layer 118 can be made of a similar material and by a similar process as those described in relation to Fig. The dielectric layer 58 described in 2C is formed.

[0104] The storage cube 50B can be attached to the storage cube 50A using fusible connectors 120. The fusible connectors 120 can be made of a similar material and by a similar process as those mentioned in relation to... Fig. The fusible connectors 108 described in section 3C are designed to connect the die connectors 116 of storage cube 50A to the die connectors 22A of storage cube 50B.

[0105] In some embodiments, an underfill 122 is formed between storage cube 50A and storage cube 50B, surrounding the fusible connectors 120. The underfill 122 can reduce stresses and protect the connections resulting from the melting of the fusible connectors 120. The underfill 122 can be formed by a capillary flow process after the storage cubes 50A and 50B have been attached, or it can be formed by a suitable deposition process before the storage cubes 50A and 50B are attached.

[0106] The HBM device 100 of the Fig. 13 is determined by a similar procedure to that used in the Fig. 3A to 3D are configured, except that multiple storage cubes 50A, 50B are configured. It is further understood that HBM devices can also be configured by similar methods to those described in relation to the Fig. 4A to 4D and the Fig. 5A to 5C can be configured, except that multiple storage cubes 50A, 50B are configured.

[0107] The storage cube 50 in Fig. 13 is similar to the one in Fig. 2F described. It is further understood that an HBM device similar to that described by Fig. 13 can be trained using the storage cubes 50, which in relation to the Fig. 6F, Fig. 11 and Fig. 12 are described.

[0108] The Fig. 14A and Fig. Figure 14B shows cross-sectional views of intermediate steps in a process for forming integrated circuit packages according to some embodiments. As described in more detail below, the Fig. 14A and Fig. 14B a process in which an HBM device 100 is integrated into an integrated circuit package 300 (see Fig. 14A) such as a CoW package. The integrated circuit package 300 is then placed on a package substrate 400 (see Fig. 14B) is assembled to form another package, for example, a CoWoS package. The integrated circuit package 300 is formed by stacking the HBM device 100 and a third integrated circuit device onto a wafer 302. The third integrated circuit device may have a structure similar to that described above with reference to Fig. The integrated circuit device 10 described in Figure 1 is similar and, in one embodiment, can be a processor device. The formation of integrated circuit packages in a package area 302A of the wafer 302 is shown; however, it should be noted that the wafer 302 can have any number of device areas and an HBM device 100 can be stacked in each device area.

[0109] In Fig. Wafer 302 will be received in step 14A. Wafer 302 has an interposer 304 in package area 302A. In subsequent processing, the interposer 304 is singulated so that it is included in the integrated circuit package 300. The interposer 304 has a semiconductor substrate 306, an interconnect structure 308, conductive vias 310, and die connectors 312, which may resemble the semiconductor substrate 12, the interconnect structure 14, the conductive vias 16, and the die connectors 22 of the integrated circuit device 10, which were described above with reference to Fig. as described in Figure 1, except that the semiconductor substrate 306 may be free of active / passive devices and the die connectors 312 may be connectors suitable for use with remeltable connectors such as microbumps. The interposer 304 further comprises external connectors 314, which may resemble the die connectors 312 and are connected to the conductive vias 310.

[0110] An HBM device 100 and a processor device 10P are attached to the wafer 302, for example, to the interconnect structure 308 of the interposer 304. The processor device 10P can be a processing unit, such as a CPU, a GPU, a SoC, or the like. The processor device 10P comprises a semiconductor substrate 12P, an interconnect structure 14P, die connectors 22P, a dielectric layer 24P, and conductive connectors 26P. The processor device 10P is free of TSVs, and the die connectors 22P can be connectors suitable for use with remeltable connectors such as microbumps. The conductive connectors 26P can be made of a similar material and by a similar process as those described in relation to Fig. The conductive connectors 114 described in 3D are formed. The HBM device 100 can be attached to the die connectors 312 of the wafer 302 by melting the conductive connectors 114, and the processor device 10P can be attached to the die connectors 312 of the wafer 302 by melting the conductive connectors 26P.

[0111] In some embodiments, an underfill 316 is formed between the wafer 302 and each of the HBM devices 100 and the processor device 10P, surrounding the conductive connectors 26P and the conductive connectors 114. The underfill 316 can be made of a similar material and by a similar method as that described in relation to Fig. The underfill described in 3C will be formed at 110.

[0112] An encapsulation 318 is then formed on and around the various components. After formation, the encapsulation 318 encapsulates the HBM device 100 and the processor device 10P and contacts the underfill 316. The encapsulation 318 can be made from a similar material and by a similar process as that described in relation to Fig. The encapsulation 112 described in 3D is formed. A planarization process is optionally carried out on the encapsulation 318 so that the HBM device 100 and / or the processor device 10P are exposed.

[0113] Conductive connectors 320 are formed on the external connectors 314. The conductive connectors 320 can be made of a similar material and by a similar process as those described in relation to Fig. 3D described conductive connector 114 are formed.

[0114] In Fig. In step 14B, a singulation process is performed by sawing along scribed line areas, e.g., between package area 302A and adjacent package areas. The sawing singulates package area 302A. The resulting singulated integrated circuit package 300 originates from package area 302A.

[0115] The integrated circuit package 300 can then be mounted on a package substrate 400 using the conductive connectors 320. The package substrate 400 has a substrate core 402 and bond pads 404 over the substrate core 402. The substrate core 402 can be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, bonding materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can be used. Additionally, the substrate core 402 can be an SOI substrate. In general, an SOI substrate has a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof.In an alternative embodiment, the substrate core 402 is based on an insulating core, such as a core made of glass fiber reinforced resin. An example of a core material is a glass fiber resin like FR4. Alternative core materials include bismaleimide triazine BT resin or, alternatively, other PCB materials or films. Build-up films such as ABF or other laminates can be used for the substrate core 402.

[0116] The substrate core 402 can incorporate active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the device stack. The devices can be fabricated using any suitable method.

[0117] The substrate core 402 can also include metallization layers and vias (not shown), wherein the bond pads 404 are spatially and / or electrically connected to the metallization layers and vias. The metallization layers can be formed over the active and passive devices and configured to connect the various devices, thus forming functional circuits. The metallization layers can be formed from alternating layers of a dielectric (e.g., a low-k dielectric) and conductive material (e.g., copper), with vias connecting the conductive material layers, and can be formed by any suitable process (e.g., deposition, damascene, dual-damascene, or the like). In some embodiments, the substrate core 402 is essentially free of active and passive devices.

[0118] In some embodiments, the conductive connectors 320 are melted to attach the external connectors 314 to the bond pads 404. The conductive connectors 320 electrically and / or physically connect the package substrate 400, for example, the metallization layers in the substrate core 402, to the integrated circuit package 300. In some embodiments, a solder mask is formed on the substrate core 402. The conductive connectors 320 can be positioned in openings in the solder mask so that they are electrically and mechanically connected to the bond pads 404. The solder mask can be used to protect areas of the substrate core 402 from external damage.

[0119] In some embodiments, an underfill 406 can be formed between the integrated circuit package 300 and the package substrate 400, surrounding the conductive connectors 320 to reduce stresses resulting from the melting of the conductive connectors 320 and to protect the connections. The underfill 406 can be formed by a capillary flow process after the integrated circuit package 300 has been attached, or it can be formed by a suitable deposition process before the integrated circuit package 300 is attached. The conductive connectors 320 can have an epoxy flow (not shown) formed on them before they are melted, with at least a portion of the epoxy content of the epoxy flow remaining after the integrated circuit package 300 has been attached to the package substrate 400. This remaining epoxy content can serve as the underfill 406.

[0120] In some embodiments, passive devices (e.g., surface-mount devices (SMDs), not shown) can also be attached to the integrated circuit package 300 (e.g., to the external connectors 314) or to the package substrate 400 (e.g., to the bond pads 404). For example, the passive devices can be bonded to the same surface of the integrated circuit package 300 or the package substrate 400 as the conductive connectors 320. The passive devices can be attached to the integrated circuit package 300 before the integrated circuit package 300 is mounted on the package substrate 400, or they can be attached to the package substrate 400 before or after the integrated circuit package 300 is mounted on the package substrate 400.

[0121] The Fig. Figures 15A to 15C are cross-sectional views of intermediate steps in a process for forming integrated circuit packages according to some embodiments. As described in more detail below, the Fig. 15A to 15C a process in which an HBM device 100 is integrated into a 500 integrated circuit package (see Fig. 15B). The integrated circuit package 500 is then packaged on a package substrate 400 (see Fig. 15C) is mounted, forming another package. The integrated circuit package 500 is mounted on a carrier substrate 502 (see Fig. 15A). It is shown that an integrated circuit package 500 is formed in a package area 502A of the carrier substrate 502; however, it should be noted that the carrier substrate 502 can have any number of package areas and an integrated circuit package can be formed in any package area.

[0122] In Fig. In step 15A, a support substrate 502 is provided, and a separation layer 504 is formed on the support substrate 502. The support substrate 502 can be adapted to the Fig. The carrier substrate 52 described in 2A is similar to the separating layer 504 described in relation to Fig. 2A resembles the separating layer 54 described.

[0123] A redistribution structure 506 is formed on the interface layer 504. The redistribution structure 506 has dielectric layers 508 and metallization structures 510 (sometimes referred to as redistribution layers or redistribution lines) in addition to the dielectric layers 508. The redistribution structure 506 can, for example, have several metallization structures 510 separated from each other by respective dielectric layers 508.

[0124] In some embodiments, the dielectric layers 508 are formed from a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layers 508 are formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layers 508 can be formed by spin coating, lamination, CVD, or the like, or a combination thereof. After each dielectric layer 508 is formed, it is patterned to expose underlying conductive features, such as portions of the underlying metallization structures 510.The structuring can be achieved through a suitable process, for example, by exposing the dielectric layers to light if the dielectric layers 508 are a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layers 508 are photosensitive materials, they can be developed after exposure.

[0125] The metallization structures 510 each feature conductive vias and / or conductor tracks. The conductive vias extend through the dielectric layers 508, and the conductor tracks extend along the dielectric layers 508. As an example of forming a metallization structure, a seed layer (not shown) is formed over the underlying conductive features. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using a deposition process such as PVD or the like. A photoresist is then formed and patterned on the seed layer.The photoresist can be formed by rotoplating or similar processes and exposed to light for patterning. The photoresist's structure corresponds to the metallization structure. Patterning creates openings through the photoresist, exposing the nucleation layer. A conductive material is formed in these openings and on the exposed portions of the nucleation layer. This conductive material can be formed by plating, for example, electroplating or electroless plating. The conductive material can be a metal or metal alloy such as copper, titanium, tungsten, aluminum, or similar materials, or combinations thereof. The photoresist and the portions of the nucleation layer where the conductive material is not present are then removed.The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the nucleation layer are removed, for example, using a suitable etching process, such as wet or dry etching. The remaining portions of the nucleation layer and the conductive material form the metallization structure 506 for one level of the redistribution structure.

[0126] In the redistribution structure 506, more or fewer dielectric layers 508 and metallization structures 510 can be formed than shown. In some embodiments, the redistribution structure 506 is a wafer-level redistribution structure comprising a first section 506A and a second section 506B, wherein the first section 506A comprises thin dielectric layers 508 and thin metallization structures 510, and wherein the second section 506B comprises thick dielectric layers 508 and thick metallization structures 510.

[0127] Conductive connectors 512 are formed and connected to the metallization structures 510 of the redistribution structure 506. The upper dielectric layer 508 of the redistribution structure 506 can be structured such that sections of the underlying metallization structures 510 are exposed. In some embodiments, under-bump metallurgies (UBMs) can be formed in the openings. The conductive connectors 512 are formed on the UBMs. The conductive connectors 512 can be made from a similar material and by a similar process as those described in relation to Fig. 3D described conductive connector 114 are formed.

[0128] In Fig. In 15B, a support substrate debonding process is performed to separate (or debond) the support substrate 502 from the redistribution structure 506, e.g., the lower dielectric layer 508. According to some embodiments, the debonding process includes projecting light, such as laser light or UV light, onto the separating layer 504, so that the separating layer 504 decomposes under the heat of the light and the support substrate 502 can be removed. The structure can then be turned over and, for example, placed on a belt.

[0129] An HBM device 100 and a processor device 10P are mounted on the redistribution structure 506. The processor device 10P can be a processing unit, such as a CPU, a GPU, a SoC, or the like. The processor device 10P can be the one that is related to Fig. resemble those described in 14A.

[0130] In the illustrated embodiment, the HBM device 100 is attached to the redistribution structure 506 using the conductive connectors 114, and the processor device 10P is attached to the redistribution structure 506 using the conductive connectors 26P. For example, UBMs can be formed that extend through the lower dielectric layer 508 of the redistribution structure 506 such that they are connected to the metallization structures 510 of the redistribution structure 506. The conductive connectors 26P, 114 can be brought into contact with the UBMs and melted to attach the HBM device 100 and the processor device 10P to the redistribution structure 506.

[0131] In some embodiments, an underfill 514 is formed between the redistribution structure 506 and each of the HBM devices 100 and the processor device 10P, surrounding the conductive connectors 26P and the conductive connectors 114. The underfill 514 can be made of a similar material and by a similar method as that described in relation to Fig. The underfill described in 3C will be formed at 110.

[0132] An encapsulation 516 is then formed on and around the various components. After formation, the encapsulation 516 encapsulates the HBM device 100 and the processor device 10P and contacts the underfill 514. The encapsulation 516 can be made from a similar material and by a similar process as that described in relation to Fig. The encapsulation 112 described in 3D is formed. Optionally, a planarization process is carried out on the encapsulation 516 so that the HBM device 100 and the processor device 10P are exposed.

[0133] In Fig. In step 15C, a singulation process is performed by sawing along scoring lines, for example, between package area 502A and adjacent package areas. The sawing singulates package area 502A. The resulting singulated integrated circuit package 500 originates from package area 502A. After singulation, the redistribution structure 506 and the encapsulation 516 are laterally flush (within process variations).

[0134] The integrated circuit package 500 is then attached to a package substrate 400 using the conductive connectors 512. The package substrate 400 can be adapted to the Fig. similar to those described in 14B. For example, the package substrate 400 can have bond pads 404 which are connected to the conductive connectors 512. In some embodiments, an underfill 406 can be formed between the integrated circuit package 500 and the package substrate 400 and surround the conductive connectors 512.

[0135] The Fig. Figures 16A to 16F are cross-sectional views of intermediate steps in a process for forming integrated circuit packages according to some embodiments. As described in more detail below, the Fig. 16A to 16F a process in which an HBM device 100 is integrated into a 600 integrated circuit package (see Fig. 16E). The integrated circuit package 500 is then packaged on a package substrate 400 (see Fig. 16F) is mounted, forming another package. The integrated circuit package 600 is mounted on a carrier substrate 602 (see Fig. 16A). It is shown that an integrated circuit package 600 is formed in a package area 602A of the carrier substrate 602; however, it should be noted that the carrier substrate 602 can have any number of package areas and an integrated circuit package can be formed in any package area.

[0136] In Fig. In step 16A, a support substrate 602 is provided, and a separation layer 604 is formed on the support substrate 602. The support substrate 602 can be adapted to the Fig. The carrier substrate 52 described in 2A is similar. The separation layer 604 can be similar to the one described in relation to Fig. 2A resembles the separating layer 54 described.

[0137] A redistribution structure 606 is then formed on the separating layer 604. The redistribution structure 606 can be formed in a similar manner and from similar materials as those described in relation to Fig. The redistribution structure 506 described in Section 15A is formed. The redistribution structure 606 has dielectric layers 608 and metallization structures 610 (sometimes referred to as redistribution layers or redistribution lines) in addition to the dielectric layers 608.

[0138] In Fig. In 16B, conductive vias 612 are formed, which are connected to the metallization structures 610 of the redistribution structure 606. As an example for forming the conductive vias 612, openings can be formed in the upper dielectric layer 608 of the redistribution structure 606. A seed layer is then formed over the redistribution structure 606, e.g., on the upper dielectric layer 608 and sections of the metallization structure 610 that are exposed through the openings in the upper dielectric layer 608. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer having a plurality of sublayers formed from different materials. In one particular embodiment, the seed layer has a titanium layer and a copper layer over the titanium layer.The seed layer can be formed, for example, using PVD or similar processes. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by rotational plating or similar processes and exposed to light for patterning. The pattern of the photoresist corresponds to the conductive vias. The patterning creates openings through the photoresist, exposing the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, for example, electroplating or electroless plating, or similar processes. The conductive material can contain a metal such as copper, titanium, tungsten, aluminum, or similar materials. The photoresist and the portions of the seed layer where the conductive material is not formed are then removed.The photoresist can be removed by a suitable ashing or peeling process, for example using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the conductive vias 612.

[0139] A bridge die 614 is then arranged on the redistribution structure 506 (e.g., the upper dielectric layer 508). The bridge die 614 can be an interposer, a TSV die, or the like. In some embodiments, the bridge die 614 has a semiconductor substrate 616 and TSVs 618 extending through the semiconductor substrate 616. The semiconductor substrate 616 can be a bulk substrate or a substrate having active and / or passive devices.

[0140] In Fig. In process 16C, an encapsulation 620 is formed on and around the conductive vias 612 and the bridge die 614. After formation, the encapsulation 620 encapsulates the conductive vias 612 and the bridge die 614. The encapsulation 620 can be a molding compound, an epoxy resin, or the like. The encapsulation 620 can be applied by compression molding, injection molding, or the like and can be formed over the support substrate 602 such that the bridge die 614 and / or the conductive vias 612 are buried or covered. The encapsulation 620 can be applied in liquid or semi-liquid form and subsequently cured. A planarization process can then be carried out on the encapsulation 620 to expose the conductive vias 612 and the bridge die 614.The planarization process can remove material from the encapsulation 620 until the conductive vias 612 and the TSVs 618 are exposed. The top surfaces of the planarized components are coplanar after the planarization process (within process variations). The planarization process can be, for example, chemical-mechanical polishing (CMP), grinding, etching, or the like. In some embodiments, planarization can be omitted, for example, if the conductive vias 612 and the TSVs 618 are already exposed.

[0141] In Fig. In 16D, a redistribution structure 622 is formed on the encapsulation 620, the bridge die 614, and the conductive vias 612. The redistribution structure 622 can be fabricated in a similar manner and from similar materials as those described in relation to Fig. The redistribution structure 506 described in Section 15A is formed. The redistribution structure 622 has dielectric layers 624 and metallization structures 626 (sometimes referred to as redistribution layers or redistribution lines) in addition to the dielectric layers 624.

[0142] Conductive connectors 628 are formed and connected to the metallization structures 626 of the redistribution structure 622. The upper dielectric layer 624 of the redistribution structure 622 can be structured such that sections of the underlying metallization structures 626 are exposed. In some embodiments, under-bump metallurgies (UBMs) can be formed in the openings. The conductive connectors 628 are formed on the UBMs. The conductive connectors 628 can be formed in a similar manner and from similar materials as those described in relation to Fig. 3D described conductive connector 114 are formed.

[0143] In Fig. In 16E, a support substrate debonding process is performed to separate (or debond) the support substrate 602 from the redistribution structure 606, e.g., the lower dielectric layer 608. According to some embodiments, the debonding process includes projecting light, such as laser light or UV light, onto the separating layer 604, so that the separating layer 604 decomposes under the heat of the light and the support substrate 602 can be removed. The structure can then be turned over and, for example, placed on a belt.

[0144] An HBM device 100 and a processor device 10P are mounted on the redistribution structure 606. The processor device 10P can be a processing unit, such as a CPU, a GPU, a SoC, or the like. The processor device 10P can be the one that is related to Fig. resemble those described in 14A.

[0145] In the illustrated embodiment, the HBM device 100 is attached to the redistribution structure 606 using the conductive connectors 114, and the processor device 10P is attached to the redistribution structure 606 using the conductive connectors 26P. For example, UBMs can be formed that extend through the lower dielectric layer 608 of the redistribution structure 606 such that they are connected to the metallization structures 610 of the redistribution structure 606. The conductive connectors 26P, 114 can be brought into contact with the UBMs and melted to attach the HBM device 100 and the processor device 10P to the redistribution structure 606.

[0146] In some embodiments, an underfill 630 is formed between the redistribution structure 606 and both the HBM devices 100 and the processor device 10P, surrounding the conductive connectors 26P and the conductive connectors 114. The underfill 630 can be made of a similar material and by a similar method as that described in relation to Fig. The underfill described in 3C will be formed at 110.

[0147] An encapsulation 632 is then formed on and around the various components. After formation, the encapsulation 632 encapsulates the HBM device 100 and the processor device 10P and contacts the underfill 630. The encapsulation 632 can be made from a similar material and by a similar process as that described in relation to Fig. The encapsulation 112 described in 3D is formed. Optionally, a planarization process is carried out on the encapsulation 632 such that the HBM device 100 and the processor device 10P are exposed.

[0148] In Fig. In 16F, a singulation process is performed by sawing along scribed line areas, e.g., between package area 602A and adjacent package areas. The sawing singulates package area 602A. The resulting singulated integrated circuit package 600 originates from package area 602A. After singulation, the redistribution structure 606, the encapsulation 620, the redistribution structure 622, and the encapsulation 632 are (see Fig. 16E) flush laterally (within process variations).

[0149] The integrated circuit package 600 is then attached to a package substrate 400 using the conductive connectors 628. The package substrate 400 can be adapted to the Fig. similar to those described in 14B. For example, the package substrate 400 can have bond pads 404 which are connected to the conductive connectors 628. In some embodiments, an underfill 406 can be formed between the integrated circuit package 600 and the package substrate 400 and surround the conductive connectors 628.

[0150] Certain embodiments can offer specific advantages. Forming the memory cubes by stacking memory devices with hybrid bonds allows for improved electrical and thermal performance compared to bonding the memory devices using other methods, such as solder bonds. Testing the memory cubes after formation avoids the processing of defective cubes, thereby reducing manufacturing costs. Furthermore, forming die connectors, such as conductive protrusions, in the upper memory device of the memory cube allows the memory cube to be attached to a logic device more cost-effectively using fusible connectors.

[0151] In one embodiment, a method comprises: bonding a rear side of a first storage device to a front side of a second storage device with dielectric-dielectric bonds and with metal-metal bonds; after bonding, forming first conductive bumps through a first dielectric layer on a front side of the first storage device, wherein the first conductive bumps are raised from a major surface of the first dielectric layer; testing the first storage device and the second storage device using the first conductive bumps; and after testing, attaching a logic device to the first conductive bumps with fusible connectors.

[0152] In some embodiments of the method, bonding the back side of the first storage device to the front side of the second storage device comprises bonding a back side of a first wafer to a front side of a second wafer with dielectric-dielectric bonds and with metal-metal bonds, wherein the first wafer comprises the first storage device, wherein the second wafer comprises the second storage device, and wherein the method further comprises: after bonding, singulating the first storage device and the second storage device.In some embodiments of the method, bonding the back side of the first storage device to the front side of the second storage device comprises bonding the back side of a first integrated circuit die to the front side of a second integrated circuit die using dielectric-dielectric bonds and metal-metal bonds, the method further comprising: after bonding, forming a second dielectric layer around the first integrated circuit die and the second integrated circuit die. In some embodiments of the method, bonding the back side of the first storage device to the front side of the second storage device comprises: pressing the second storage device against the first storage device; and annealing the first storage device and the second storage device.In some embodiments, the method further comprises: bonding a front face of a passive device to a rear face of the second storage device with dielectric-dielectric bonds and with metal-metal bonds; forming a second dielectric layer around the passive device; forming conductive vias extending through the second dielectric layer; and bonding a front face of a third storage device to the conductive vias and a rear face of the passive device with metal-metal bonds and to the second dielectric layer and the rear face of the passive device with dielectric-dielectric bonds.In some embodiments of the method, attaching the logic device to the first conductive protrusions with the fusible connectors comprises: obtaining a wafer having the logic device and second conductive protrusions, wherein the second conductive protrusions are arranged on a back side of the wafer; and soldering the first conductive protrusions to the second conductive protrusions with the fusible connectors. In some embodiments of the method, attaching the logic device to the first conductive protrusions with the fusible connectors comprises: forming a package component having the logic device, an encapsulation, and second conductive protrusions, wherein the encapsulation surrounds the logic device and the second conductive protrusions are connected to the logic device; and soldering the first conductive protrusions to the second conductive protrusions with the fusible connectors.In some embodiments of the method, attaching the logic device to the first conductive protrusions with the fusible connectors comprises: obtaining an integrated circuit die, wherein the integrated circuit die has a second conductive protrusion on a back side of the integrated circuit die; and soldering the first conductive protrusions to the second conductive protrusions with the fusible connectors. In some embodiments of the method, the logic device is an interface device for the first storage device and the second storage device, wherein the method further comprises: attaching the interface device and a processor device to an interposer; and attaching the interposer to a substrate.In some embodiments of the method, the logic device is an interface device for the first storage device and the second storage device, the method further comprising: attaching the interface device and a processor device to a wafer-level redistribution structure; and attaching the wafer-level redistribution structure to a support substrate.In some embodiments of the method, the logic device is an interface device for the first storage device and the second storage device, the method further comprising: forming a first redistribution structure; forming a conductive via extending from the first redistribution structure; arranging a bridge die adjacent to the conductive via; encapsulating the bridge die and the conductive via with an encapsulation; forming a second redistribution structure on the encapsulation, the bridge die, and the conductive via; attaching the interface device and a processor device to the first redistribution structure; and attaching the second redistribution structure to a support substrate.

[0153] In one embodiment, a method comprises: stacking several storage devices over a support substrate; removing the support substrate so that a major surface of a dielectric layer is exposed at a front face of an upper storage device of the storage devices; after removal, forming conductive bumps through the dielectric layer, the conductive bumps being raised from the major surface of the dielectric layer; testing each of the storage devices using the conductive bumps; and after testing, attaching a logic device to the conductive bumps with fusible connectors.

[0154] In one embodiment, a structure comprises: a first storage cube having multiple first storage devices bonded back-to-front by dielectric-dielectric bonds and metal-to-metal bonds, wherein an upper storage device of the first storage cube has first conductive bumps on a front face of the upper storage device, and each respective lower storage device of the first storage cube has bond pads on a front face of the respective lower storage device; a logic device having second conductive bumps; first fusible connectors physically and electrically connecting the first conductive bumps to the second conductive bumps; and a first underfill between the logic device and the first storage cube, the first underfill surrounding each of the first fusible connectors.

[0155] In some embodiments, the structure further comprises: an encapsulation that contacts the first subfill and each of the first storage devices. In some embodiments, the structure further comprises: a dielectric layer that surrounds each of the first storage devices; and an encapsulation that contacts the first subfill and the dielectric layer. In some embodiments of the structure, the first storage cube further comprises a passive device on a middle plane of the first storage cube. In some embodiments of the structure, a width of the logic device is greater than a width of the first storage cube. In some embodiments of the structure, a width of the logic device is less than a width of the first storage cube. In some embodiments of the structure, the logic device is part of a package component.In some embodiments, the structure further comprises: a second storage cube comprising several second storage devices bonded back-to-front with dielectric-dielectric bonds and metal-metal bonds; second fusible connectors physically and electrically connecting the second storage cube to the first storage cube; and a second underfill between the first storage cube and the second storage cube, the second underfill surrounding each of the second fusible connectors.

Claims

[1] Procedure, encompassing: Bonding a rear side of a first storage device (10A) to a front side of a second storage device (10B, 10C, 10D) using dielectric-dielectric bonds and metal-metal bonds; after bonding, forming first conductive bumps (22A) through a first dielectric layer (24A) on a front face of the first storage device (10A), wherein the first conductive bumps (22A) are raised from a main surface of the first dielectric layer (24A); Testing the first storage device (10A) and the second storage device (10B, 10C, 10D) using the first conductive hump (22A); and After testing, attaching a logic device (10L) to the first conductive protrusions (22A) by means of solder joints with fusible connectors (108) as solder material, and Forming a first underfill (110) between the logic device (10L) and the first storage device (10A), wherein the first underfill (110) surrounds each of the meltable connectors (108). [2] The method of claim 1, wherein bonding the back side of the first storage device (10A) to the front side of the second storage device (10B, 10C, 10D) comprises bonding a back side of a first wafer (56A) to a front side of a second wafer (56B) with dielectric-dielectric bonds and with metal-metal bonds, wherein the first wafer (56A) comprises the first storage device (10A), wherein the second wafer (56B) comprises the second storage device (10B, 10C, 10D), wherein the method further comprises: after bonding, singulation of the first storage device (10A) and the second storage device (10B, 10C, 10D). [3] Method according to claim 1, wherein the bonding of the back side of the first storage device (10A) to the front side of the second storage device (10B, 10C, 10D) comprises bonding a back side of a first integrated circuit die to a front side of a second integrated circuit die with dielectric-dielectric bonds and with metal-metal bonds, wherein the method further comprises: After bonding, a second dielectric layer (64) is formed around the first integrated circuit die and the second integrated circuit die. [4] Method according to any of the preceding claims, comprising bonding the rear side of the first storage device (10A) to the front side of the second storage device (10B, 10C, 10D): Pressing the second storage device (10B, 10C, 10D) against the first storage device (10A); and annealing the first storage device (10A) and the second storage device (10B, 10C, 10D). [5] The method of claim 1, further comprising: Bonding of a front side of a passive device (70) to a rear side of the second storage device (10B, 10C, 10D) with dielectric-dielectric bonds and with metal-metal bonds; Forming a second dielectric layer (84) around the passive device (70); Forming conductive vias (86) extending through the second dielectric layer (84); and Bonding of a front side of a third storage device (10E) with the conductive vias (86) and a rear side of the passive device (70) with metal-metal bonds and with the second dielectric layer (84) and the rear side of the passive device (70) with dielectric-dielectric bonds. [6] Method according to one of the preceding claims, comprising attaching the logic device (10L, 102) to the first conductive protrusions (24A) by means of solder joints with the fusible connectors (108) as solder material: Obtaining a wafer (102) having the logic device (10L) and second conductive protrusions (106), wherein the second conductive protrusions (106) are arranged on a rear side of the wafer (102); and Soldering the first conductive bumps (24A) to the second conductive bumps (106) with the fusible connectors (108). [7] Method according to any one of claims 1 to 5, wherein the fastening of the logic device (10L) to the first conductive protrusions (24A) by means of solder joints with the fusible connectors (108) as solder material comprises: Forming a package component (200) comprising the logic device (10L), an encapsulation (112) and second conductive protrusions (106), wherein the encapsulation (112) surrounds the logic device (10L), and the second conductive protrusions (106) are connected to the logic device (10L); and Soldering the first conductive bumps (22A) to the second conductive bumps (106) with the fusible connectors (108). [8] Method according to any one of claims 1 to 5, wherein the fastening of the logic device (10L) to the first conductive protrusions (22A) by means of solder joints with the fusible connectors (108) as solder material comprises: Obtaining an integrated circuit die, wherein the integrated circuit die has a second conductive bump (106) on a back side of the integrated circuit die; and Soldering the first conductive bumps (22A) to the second conductive bumps (106) with the fusible connectors (108). [9] Method according to any of the preceding claims, wherein the logic device (10L) is an interface device for the first storage device (10A) and the second storage device (10B), the method further comprising: Attaching the interface device and a processor device (10P) to an interposer (304); and Attaching the interposer (304) to a support substrate (400). [10] Method according to any one of claims 1 to 8, wherein the logic device (10L) is an interface device for the first storage device (10A) and the second storage device (10B), the method further comprising: Attaching the interface device and a processor device (10P) to a redistribution structure (506) at the wafer level; and Attaching the redistribution structure (506) at wafer level to a support substrate (400). [11] Method according to any one of claims 1 to 8, wherein the logic device (10L) is an interface device for the first storage device (10A) and the second storage device (10B), the method further comprising: Forming an initial redistribution structure (606); Forming a conductive through-hole (612) extending from the first redistribution structure (606); Arranging a bridge die (614) next to the conductive via (612); encapsulating the bridge die (614) and the conductive via (612) with an encapsulation (620); Forming a second redistribution structure (622) on the encapsulation (620), the bridge die (614) and the conductive via (612); Attaching the interface device and a processor device (10P) to the first redistribution structure (606); and Attaching the second redistribution structure (622) to a support substrate (400). [12] Procedures, including: Stacking multiple storage devices (10A, 10B) over a support substrate (52); Removal of the support substrate (52) so that a main surface of a dielectric layer (24A) is exposed on a front face of an upper storage device (10A) of the storage devices (10A, 10B); after removal, forming conductive bumps (22A) through the dielectric layer (24A), wherein the conductive bumps (22A) are raised from the main surface of the dielectric layer (24A); Test each of the storage devices (10A, 10B) using the conductive humps (22A); and After testing, attaching a logic device (10L) to the conductive protrusions (22A) by means of solder joints with fusible connectors (108) as solder material, and forming a first underfill (110) between the logic device (10L) and the upper storage device (10A), wherein the first underfill (110) surrounds each of the fusible connectors (108). [13] Structure, exhibiting: a first storage cube (50, 50A) comprising several first storage devices (10A, 10B) bonded back-to-front by dielectric-dielectric bonds and metal-metal bonds, wherein an upper storage device (10A) of the first storage cube (50, 50A) has first conductive bumps (22A) on a front face of the upper storage device (10A), wherein each respective lower storage device (10B) of the first storage cube (50) has bond pads on a front face of the respective lower storage device (10B); a logic device (10L) having a second conductive protrusion (106); first fusible connectors (108) as solder material, which physically and electrically connect the first conductive protrusions (22A) to the second conductive protrusions (106) by means of solder joints; and a first underfill (110) between the logic device (10L) and the first storage cube (50, 50A), wherein the first underfill (110) surrounds each of the first meltable connectors (108). [14] Structure according to claim 13, further comprising: an encapsulation (112) that touches the first subfill (110) and each of the first storage devices (10A, 10B). [15] Structure according to claim 13, further comprising: a dielectric layer (64) surrounding each of the first storage devices (10A, 10B); and an encapsulation (112) that contacts the first subfill (110) and the dielectric layer (64), wherein the dielectric layer (64) is arranged between the encapsulation (112) and each of the first storage devices (10A, 10B). [16] Structure according to one of claims 13 to 15, wherein the first storage cube (50, 50A) further comprises a passive device (70) on a middle plane of the first storage cube (50, 50A). [17] Structure according to one of claims 13 to 16, wherein a width of the logic device (10L) is greater than a width of the first storage cube (50, 50A). [18] Structure according to one of claims 13 to 16, wherein a width of the logic device (10L) is smaller than a width of the first storage cube (50, 50A). [19] Structure according to one of claims 13 to 18, wherein the logic device (10L) is part of a package component (200). [20] Structure according to any one of claims 13 to 19, further comprising: a second storage cube (50, 5\0B) comprising several second storage devices bonded back-front with dielectric-dielectric bonds and metal-metal bonds; second fusible connectors that physically and electrically connect the second storage cube (50, 50B) to the first storage cube (50, 50A); and a second underfill between the first storage cube (50, 50A) and the second storage cube (50, 50B), wherein the second underfill surrounds each of the second fusible connectors.

Images