Semiconductor circuit structure with interconnected, various functional blocks

Abstract

Semiconductor circuit structure, featuring: a semiconductor substrate (102) with a first circuit region (120) and a second circuit region (122); active fin regions (106) that protrude from the semiconductor substrate (102) and are surrounded by insulating features; first transistors having first gate stacks (112A) formed on the active fin regions (106) and arranged in the first circuit region (120), wherein the first gate stacks (112A) have a first gate spacing that is smaller than a reference spacing (100); second transistors having second gate stacks (112B) formed on the active fin regions (106) and arranged in the second circuit region (122), wherein the second gate stacks (112B) have a second gate spacing that is larger than the reference spacing (100), wherein the second transistors are high-frequency transistors and the first transistors are logic transistors, and a first dummy region surrounding the first transistors, and a second dummy region surrounding the second transistors, wherein the first dummy region has several first dummy gates configured with a gate spacing equal to the first gate spacing; and the second dummy region has several second dummy gates (114B) configured with a gate spacing that is smaller than the second gate spacing.

Description

BACKGROUND

[0001] Integrated circuits have evolved to advanced technologies with smaller feature sizes, such as 7 nm, 5 nm, and 3 nm. In these advanced technologies, the gate pitch is constantly shrinking, leading to various performance and reliability issues, such as overlay shift, contact-to-gate bridging problems, increased parasitic capacitance, and circuit timing problems. Furthermore, three-dimensional transistors, such as those formed on active fin regions, are often desirable to improve device performance. These three-dimensional field-effect transistors (FETs) formed on active fin regions are also called FinFETs. Other three-dimensional field-effect transistors include gate-all-around FETs. These FETs require a narrow fin width for short-channel control, resulting in smaller source / drain regions than those of planar FETs.This further reduces alignment margins and leads to various problems for further shrinking device pitches and increasing packaging density. Along with the reduction in component sizes, existing circuit structures face various challenges, including short circuits, leakage, routing resistance, alignment margins, layout flexibility, and packaging density. Therefore, there is a need for a transistor structure and process to address concerns regarding improved circuit performance and reliability.

[0002] US 2019 / 0 311 969 A1 discloses a method comprising doping a substrate with a dopant to form a first well region of a first core circuit and a second well region of a second core circuit; forming first and second semiconductor fins respectively over the first and second well regions and extending along one direction; forming a first gate stack over the first semiconductor fin and a second gate stack over the second semiconductor fin; forming a first source / drain adjacent to the first semiconductor fin and a second source / drain adjacent to the second semiconductor fin;and forming a first contact over the first source / drain and having a first width measured along the direction, and a second contact over the second source / drain and having a second width measured along the direction, wherein the second width of the second contact is greater than the first width of the first contact. Further prior art is disclosed in US 2016 / 0 111 421 A1, US 2005 / 0 044 522 A1, and US 2003 / 0 020 098 A1.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this invention can best be understood from the following detailed description taken in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the sake of clarity of illustration. Fig. Figure 1A is a top view of an integrated circuit (IC) structure. Fig. 1B, Fig. 1C, Fig. 1D and Fig. 1E are cross-sectional views of the IC structure of Fig. 1A. Fig. 2A and Fig. 2B are cross-sectional views of the IC structure. Fig. 3, Fig. 4A and Fig. 4B are top views of an IC structure. Fig. 5, Fig. 6 and Fig. 7 are cross-sectional views of the IC structure. Fig. 8, Fig. 9 and Fig. 10 are cross-sectional views of a gate in an IC structure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. For example, in the following description, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact.

[0006] Furthermore, this disclosure may repeat reference numbers and / or letters from the various examples. This repetition is for simplicity and clarity and does not, in and of itself, dictate a relationship between the various embodiments and / or configurations discussed. Furthermore, the formation of a feature on, connected to, and / or coupled to another feature in this following disclosure may include embodiments where the features are formed in direct contact, and may also include embodiments where additional features may be formed between the features such that the features need not be in direct contact. In addition, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "over," "on," "below," "downward," "top," "bottom," etc., as well as derivatives thereof (e.g., "horizontal," "downward," "upward," etc.), are used.) is used for simplicity of this disclosure of the relationship of one of the features to another feature. The spatially relative terms are intended to cover various orientations of the device incorporating the features. Still further, when a number or range of numbers is referred to as "about," "approximately," and the like, the term is intended to include numbers that are within a suitable range encompassing the referred number, such as within + / - 10% of the described number, or at other values ​​as will be understood by those skilled in the art. For example, the term "about 5 nm" encompasses the dimensional range of 4.5 nm to 5.5 nm.

[0007] This application relates to a semiconductor circuit structure with field-effect transistors (FETs) and their manufacturing process, in particular to a multi-pitch gate. An integrated circuit includes various devices and various functional blocks integrated with each other. The various functional blocks or devices have different designs and performance requirements but are fabricated on the same chip. Manufacturing is difficult to tailor to different functional blocks and therefore affects circuit performance. The general purpose of this disclosure includes the design of a gate layout with different pitches tailored to the respective functional blocks or various types of devices, such as logic devices and radio-frequency devices. A general configuration of a semiconductor circuit structure includes field-effect transistors with gates configured with different pitches.In an exemplary structure, the gate layout includes a first set of gates arranged at a smaller pitch P. s configured for logic devices, and a second set of gates configured with a larger pitch P l configured for high-frequency devices, such as radio frequency devices. The smaller distance P s is smaller than a reference distance and the larger distance P lis larger than the reference pitch, which can be determined based on various factors such as circuit specification, device characteristics, and manufacturing technologies. In some embodiments, the reference pitch is determined according to the manufacturing technology and the characteristics of the first and second transistors. In various embodiments, the gate layout in the semiconductor circuit structure includes different pitches, different dimensions (such as length and width), different spacings, a different number of grouped gates, different compositions, different designs in the surrounding regions, a different configuration, or a combination thereof. According to the invention, dummy gates are configured around a functional block with a different configuration and different functions, such as, in some examples, dummy gates configured around a radio frequency device block to act as a guard ring.

[0008] In addition, the different gate designs for different functional blocks, combined with the manufacturing stress effect, produce different gate structures in different blocks. These differences include the geometry, dimensions, material profile, and structure of the gates, which can be tuned to improve the respective device performance. Further details of the semiconductor circuit structure and the manufacturing process are shown in the attached drawings.

[0009] This present invention provides various embodiments of an integrated circuit (IC) formed on a semiconductor substrate. The integrated circuit has a design layout that can be incorporated using various standard cells. The standard cells are predesigned IC structures that are repeatedly used in individual IC designs. Effective IC design layouts include various predesigned standard cells and predefined rules for the placement of these standard cells to improve circuit performance and reduce circuit areas.

[0010] Fig. 1A is a top view and a cross-sectional view of an integrated circuit (IC) structure (or semiconductor structure) 100 and Fig. 1B, Fig. 1C and Fig. 1D are sectional views of the IC structure 100 along the dashed lines AA', BB' and CC' of Fig. 1A, each constructed according to various aspects in one embodiment. In some embodiments, the IC structure 100 is formed on shallow active regions and includes field effect transistors (FETs). In some embodiments, the IC structure 100 is formed on fin active regions and includes fin-field effect transistors (FETs). In some embodiments, the IC structure 100 includes FETs formed on vertically stacked channels (also referred to as gate-all-around transistors). Using the IC structure 100 as an illustrative example, an IC structure and a method of fabricating the same are described together.

[0011] In various embodiments, the IC structure 100 comprises various circuit modules integrated on a common substrate. These circuit modules (or simply circuits) can have different functions or different circuit properties. These circuit modules are placed on different circuit regions of the substrate, either adjacent to each other or remote from each other, or with different surroundings. According to the invention, they are surrounded by dummy regions. The IC structure 100 comprises, for example, a first circuit region 120 and a second circuit region 122 arranged on a substrate 102. The IC structure 100 can comprise additional circuit regions that are similar to or different from the first and second circuit regions.For example, the IC structure 100 includes other logic circuit regions, other RF circuit regions, other circuit regions such as memory regions, image sensor regions, analog circuit regions, or a combination thereof. In some embodiments, the first circuit formed in the first circuit region 120 is a logic circuit, and the second circuit formed in the second circuit region 122 is a radio frequency (RF) circuit. RF circuitry typically requires high frequency and high speed and, accordingly, less parasitic capacitance. In some embodiments, the IC structure further includes a third circuit formed in a third circuit region, wherein the third circuit is a memory circuit comprising various memory devices, such as static random access memory (SRAM) cells, configured in an array.

[0012] These circuit regions can comprise one or more standard cells, which are placed on the IC layout according to predefined rules. These standard cells are reused in integrated circuit designs and are therefore prefabricated according to the manufacturing technologies and stored in a standard cell library. IC designers can retrieve these standard cells, incorporate them into their IC designs, and place them in the IC layout according to the predefined placement rules. A standard logic cell can, for example, comprise various basic circuit devices such as inverters, AND, NAND, OR, XOR, and NOR, flip-flops, latches, or a combination thereof, which are popular in digital circuit design for applications such as central processing units (CPUs), graphics processing units (GPUs), and system-on-chip (SOC) designs.

[0013] The IC structure 100 includes a semiconductor substrate 102. The semiconductor substrate 102 includes silicon. Alternatively, the substrate 102 may include an elemental semiconductor, such as silicon or germanium in a crystalline structure, a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, or combinations thereof. Possible substrates 102 also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated by separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods.

[0014] The substrate 102 also includes various isolation features 104, such as isolation features formed on the substrate 102, thereby defining various active regions 106 on the substrate 102. The isolation features 104 utilize isolation technology, such as shallow trench isolation (STI), to define and electrically isolate the various active regions. Each active region 106 is surrounded by a continuous isolation feature, separating it from other adjacent active regions. The isolation features 104 include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectrics, or combinations thereof. The isolation features 104 are formed by any suitable process.An example of forming STI features includes a lithography process to expose a portion of the substrate, etching a trench into the exposed portion of the substrate (e.g., by dry etching and / or wet etching), filling the trench (e.g., by a chemical vapor deposition process) with one or more dielectrics, and planarizing the substrate and removing excess portions of the dielectric(s) through a polishing process, such as a chemical mechanical polishing (CMP) process. In some examples, the filled trench may include a multi-layer structure, such as a thermal oxide liner layer and fill layer(s) of silicon nitride or silicon oxide.

[0015] The active region 106 is a region having a semiconductor surface in which various doped features are formed and configured into one or more devices, such as a diode, a transistor, and / or other suitable devices. The active region may include a semiconductor material similar to the bulk semiconductor material of the substrate 102 (such as silicon), or a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (such as alternative silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth to improve performance, such as through the strain effect to increase charge carrier mobility.

[0016] In some embodiments, the active region 106 is three-dimensional, such as an active fin region that extends above the isolation feature. The active fin region 106 is extruded from the substrate 102 above the isolation features 104 and has a three-dimensional profile for more effective coupling between the channel and the gate electrode of a FET. In particular, the substrate 102 has a top surface, and the active fin region 106 has a top surface 106A that overlies the top surface of the substrate 102. The active fin region 106 may be formed by selective etching to excise the isolation features, by selective epitaxial growth to build active regions with a semiconductor the same as or different from that of the substrate 102, or by a combination thereof.

[0017] The semiconductor substrate 102 further includes various doped features, such as n-doped wells, p-doped wells, source and drain features, other doped features, or a combination thereof, configured to form various devices or components of the devices, such as source and drain features of a field-effect transistor. In the Fig. In the example illustrated in Figure 1A, the IC structure 100 includes a negatively doped well (also referred to as an N-well) 108 and a positively doped well (also referred to as a P-well) 110. The N-well 108 includes a negative dopant, such as phosphorus. And the P-well 110 includes a positive dopant, such as boron. The N-well 108 and the P-well 110 are formed by suitable technologies, such as ion implantation, diffusion, or a combination thereof. In this embodiment, an active region 106 is formed in the N-well 108 and another active region 106 is formed in the P-well 110.

[0018] Fig. 1C further illustrates the isolation features 104 and an interlayer dielectric (ILD) layer 140 in a cross-sectional view. Specifically, the top surface of the substrate 102 is defined as a surface level with the top surface of the isolation features 104 and is denoted as 102A, while the top surface of the active fin regions 106 is denoted as 106A.

[0019] Various IC devices formed on the semiconductor substrate 102. The IC devices include fin-field-effect transistors (FinFETs) and may further include diodes, bipolar transistors, image sensors, resistors, capacitors, inductors, memory cells, or a combination thereof. Fig. 1A shows exemplary FETs for illustrative purposes only.

[0020] The IC structure 100 further includes various gates (or gate stacks) 112 having an elongated shape and aligned in a first direction (X direction). In this embodiment, the X and Y directions are orthogonal and define a top surface of the semiconductor substrate 102. A gate stack includes a gate dielectric layer and a gate electrode. The gate stack is a feature of an FET and interacts with other features, such as source / drain (S / D) features and a channel, where the channel is a portion of the active region directly underlying the gate stack; and the S / D features are located in the active region and arranged on two sides of the gate stack. In these embodiments, the gate stacks in the first circuit region 120 and the second circuit region 122 are referred to as gate stacks (or simply gates) 112A and 112B, respectively.It is noted that a gate stack (or a gate) should not be confused with a logic gate, such as a NOR logic gate.

[0021] According to the invention, the IC structure 100 also includes several dummy gate stacks arranged on the semiconductor substrate 102. A dummy gate is not a gate and does not function as a gate. Instead, the dummy gate is arranged for other purposes, such as tuning the feature density and isolation. The dummy gate may have a similar structure to a functional gate 112. Alternatively, the dummy gate may have a different structure or even be a dielectric feature (also referred to as a dielectric gate), which includes one or more dielectrics and, in some cases, acts as an isolation feature.

[0022] The dummy gates are similar in formation to gates 112. In some embodiments, gates 112 and the dummy gates are formed together by a process such as a gate-last process. In other embodiments, the initial dummy gates are first formed by deposition and patterning, wherein the patterning further includes a lithography process and etching. Thereafter, a subset of the initial dummy gates are replaced to form gates 112 by depositing a gate dielectric layer and a gate electrode, while the remainder of the initial dummy gates are replaced to form dielectric gates by depositing one or more dielectrics. In addition, the dummy gate is arranged and configured differently and therefore has a different appearance.In the illustrated embodiment, some dielectric gates are placed at the boundary regions between circuit modules or at the edges of the standard cells to act as insulation to separate one standard cell from a neighboring standard cell. Some dielectric gates are placed within the standard cells or within a circuit module in a circuit region for one or more reasons, such as isolation between neighboring FETs and for adjusting feature density. Thus, the dummy gates provide an isolation function between neighboring IC devices and additionally enable adjustment of feature density for improved manufacturing, such as etching, deposition, and CMP.

[0023] In this embodiment, the IC structure 100 includes a first circuit region 120 for a logic circuit and a second circuit region 122 for an RF circuit. The two circuit regions 120 and 122 can be arranged side by side or at a certain distance from each other, separated by a dummy region comprising a plurality of dummy gates.

[0024] In the illustrated embodiment, the IC structure 100 includes the first active region 106 in the N-well 108 and the second active region 106 in the P-well 110. The gate 112A in the first circuit region 120 may extend continuously in the X-direction from the first active region 106 (in the N-well 108) to the second active region 106 (in the P-well 110). Similarly, the gate 112A in the second circuit region 122 may extend continuously in the X-direction from the first active region 106 (in the N-well 108) to the second active region 106 (in the P-well 110).

[0025] With a source 126, a drain 128, and a channel 130 formed for each transistor associated with a respective gate, a respective active region, and a respective circuit region, the first circuit region 120 includes a p-FET (pFET) 132 in the N-well 108 and an n-FET (nFET) 134 in the P-well 110; and the second circuit region 122 includes a pFET 136 in the N-well 108 and an nFET 138 in the P-well 110. In this embodiment, the pFET 132, the nFET 134, and other FETs in the first circuit region 120 are integrated to form a functional circuit block, such as a logic circuit; and the pFET 136, the nFET 138, and other FETs in the second circuit region 122 are integrated to form another functional circuit block, such as an RF circuit.

[0026] Fig. 1A to 1D illustrate an exemplary IC structure 100 with the first circuit region 120 and the second circuit region 122. However, it is understood that the IC structure 100 may include additional circuit regions and some dummy regions (or fill regions) provided according to the invention, which are added in a different configuration. In embodiments according to the invention, various circuit regions are surrounded by corresponding dummy regions. For example, depending on the individual design, additional circuit regions and dummy regions may be provided at the left edge, the right edge, the top edge, and / or the bottom edge of Fig. 1A in a similar configuration. The IC structures in other figures, such as those discussed below, are to be understood similarly. As shown in Fig. As illustrated in Figure 1B, two or more circuit regions are configured in a cascade mode.

[0027] In particular, according to the invention, the gates 112A in the first circuit region 120 and the gates 112B in the second circuit region 122 have different pitches. A pitch is defined as the periodic pitch of an array of gates, such as the center-to-center distance between two adjacent gates in the array of gates. In this embodiment, the gates 112A have a first pitch P1 and the gates 112B have a second pitch P2 that is greater than the first pitch P1. For example, the first pitch P1 is smaller than a reference pitch, and the second pitch P2 is larger than the reference pitch. The reference pitch is determined according to the manufacturing technology and the properties of the first and second transistors. In the illustrated embodiment, the reference pitch is 100 nm. For example, the first pitch P1 is smaller than 100 nm, and the second pitch P2 is greater than 100 nm.In some embodiments, the ratio P2 / P1 is large enough, such as greater than 1.5, to achieve the expected performance improvement of the circuit with corresponding gate profiles, which are described in more detail later. In some embodiments, the ratio P2 / P1 is between 1.2 and 2. The first pitch P1 and the second pitch P2 can each be tuned to the corresponding circuit performance. For example, the RF circuitry in the second circuit region 122 can have a larger pitch, less parasitic capacitance, and higher frequency performance, while the logic circuitry in the first circuit region 120 can have a smaller pitch and higher packing density without compromising the overall circuit performance.

[0028] Additionally, gates 112A and 112B may differ in gate pitch, gate dimensions, gate structure, gate profile, gate alignment, gate configuration, gate composition, gate environment, dummy gate design, or a combination thereof. IC structure 100 may have a three-dimensional structure to achieve improved gate coupling and improved circuit performance. In some embodiments, IC structure 100 includes fin active regions, where the active regions are extruded over substrate 102, such as extruded over the top surface of isolation features 104. In some embodiments, IC structure 100 includes vertically stacked multiple channels, such as a gate-all-around (GAA) structure. In some embodiments, IC structure 100 includes a third circuit region, a fourth circuit region, etc.with different gate pitches for different circuits, such as memory cells, input / output devices (I / O devices), etc.

[0029] In the example above, only two circuit regions (120 and 122) are illustrated. However, the IC structure 100 may include multiple circuit regions, each designed for a corresponding function, such as a first circuit region for a logic circuit with a first gate pitch, a second circuit region for an RF circuit with a second gate pitch, a third circuit region for a memory circuit with a third gate pitch, a fourth circuit region for I / O devices with a fourth gate pitch, etc. These gate pitches are different from each other and individually tuned to the respective circuit characteristics and performance improvement. Furthermore, each circuit region includes dummy gates surrounding the functional gates.The dummy gates are further tuned with various designs (such as gate pitch, gate dimensions, and gate groups) to compensate for the structure density so that the process defects are eliminated while improving the circuit performance. The areas for the dummy gates are referred to as dummy regions, and the areas for the functional gates are referred to as active device regions (or active circuit regions). Since the dummy gates in the dummy regions are not sections of the circuits and are designed to improve manufacturing and circuit performance, they have more freedom in tuning, such as in the gate materials, gate pitch, gate dimensions, gate orientations, and gate structure density. In addition, the placement and size of the dummy regions are also factors used in the tuning process. For example, a dummy region shouldbe placed next to an edge of a circuit region where the gate structure density is relatively far from the average.

[0030] Fig. 1E is a sectional view of the IC structure 100 along the dashed line AA' of Fig. 1A constructed according to various aspects of this invention in one embodiment. Fig. 1E is similar to Fig. 1B, but additionally illustrated with the contacts 146. The contacts 146 are configured to land on the respective sources 126 and drains 128. Due to the different gate pitches and other different gate dimensions, the contacts 146 to the sources 126 and drains 128 in the first circuit region 120 and in the second circuit region 122 have different dimensions. For example, the contacts 146 to the sources 126 and drains 128 for the logic circuitry in the first circuit region 120 have a first dimension D1 that is smaller than a reference dimension (such as 45 nm in some examples), and the contacts 146 to the sources 126 and drains 128 for the RF circuitry in the second circuit region 122 have a second dimension D2 that is larger than a reference dimension. In some embodiments, the ratio D2 / D1 is greater than 2. In some embodiments, the ratio D2 / D1 is between 1.5 and 3.The contacts 146 are formed by any suitable method. In some embodiments, the contacts 146 are formed by a method including a lithography process and an etch to form contact holes in the ILD layer 140; a deposition to fill the contact holes with one or more conductive materials (such as tungsten, nickel, cobalt, ruthenium, another suitable conductive material, or a combination thereof); and a CMP process to remove the excess conductive materials. In the illustrated embodiment, the contacts 146 are self-aligned with the gaps between the gates 112.

[0031] Fig. 2A and Fig. 2B are cross-sectional views of an IC structure 100 in a section constructed according to some embodiments. In Fig. 2A, only the gates (or gate stacks) 112A and 112B in the first and second circuit regions 120 and 122, respectively, are illustrated. In Fig. For clarity, only the ILD layer 140 is illustrated in Figure 2B. The gates 112 (112A and 112B) are formed by deposition and patterning. The gate materials are, for example, deposited on the substrate 102 and patterned into gate stacks by a lithography process and etching. In some embodiments, initial dummy gates, such as polysilicon gates, are formed by deposition and patterning. Then, the initial dummy gates are replaced with high-k metal and dielectric gates 112 in a process such as a gate-loading process. The gate-loading process may further include etching to remove the initial dummy gates, resulting in gate trenches; filling the gate trenches with gate materials (such as high-k dielectric and metal); and performing a CMP process.

[0032] The gates 112A and 112B are designed and formed to have different pitches, as described above. In the illustrated embodiment, the first pitch P1 of the gate stacks 112A in the first circuit region 120 is smaller than the second pitch P2 of the gate stacks 112B in the second circuit region 122. In the illustrated embodiment, the gates 112A and 112B have a constant gate width along the Y-direction. Due to the different gate pitches in the first circuit region 120 and in the second circuit region 122, the etch loading effect causes a stronger etching effect on the gate materials in the second circuit region 122 and results in different gate profiles in these two circuit regions. In particular, the gate 112A has a first height H1 and the gate 112B has a second height H2 that is less than H1, such as when the gate height ratio H1 / H2 is greater than 1.1.In some embodiments, the gate height ratio H1 / H2 is between 1.1 and 1.5. Furthermore, the etch loading effect causes the gate stacks 112B in the second circuit region 122 to have a rounded corner 142, as shown in FIG. Fig. 2A. Conversely, this also causes the ILD layer 140 in the second circuit region 122 with constriction profile 144, as in Fig. 2B. The ILD layer 140 is formed in the gaps between the adjacent gates 112 by deposition and additional polishing (such as CMP). The profile of the ILD layer 140 is complementary to the profile of the gates 112. The necking profile 144 is associated with the rounded corner 142.

[0033] Our experimental data demonstrate that the characteristics and performance of the IC structure 100 are improved and enhanced by using the disclosed structure and method of fabricating the same. The experiments confirm that the transition frequency ("fT") can be effectively improved by increasing the gate pitch. This is because the increased gate pitch can reduce the parasitic capacitance. However, as the gate pitch is further increased, the contribution to the parasitic capacitance is dominated by the dielectric constant of the insulating material, such as the ILD layer 140, between the gaps of the adjacent gates 112. Thus, beyond a certain point, further increasing the gate pitch increases the parasitic capacitance under the competing factors of dielectric constant and gate pitch. This point is referred to as the fT peak.The gate pitch of the RF circuit is increased to be close to the fT peak to optimize the performance of the RF circuit. Overall, RF circuit performance is improved when the gate pitch is increased, particularly when it reaches the fT peak. Therefore, this disclosure provides an IC structure with logic and RF circuits with different gate pitches and a method for fabricating them, particularly the second gate pitch associated with the fT peak.

[0034] Fig. Figure 3 is a top view of the IC structure 100 constructed according to some embodiments of the invention. The IC structure 100 includes the first circuit region 120 for a logic circuit and the second circuit region 122 for an RF circuit. The IC structure 100 in Fig. 3 has a gate layout optimized for improved circuit performance for both the logic circuitry in the first circuit region 120 and the RF circuitry in the second circuit region 122. The first circuit region 120 includes an active device region 120A with FETs and corresponding first gates 112A having the first pitch P1, and the second circuit region 122 includes an active device region 122A with FETs and corresponding second gates 112B having the second pitch P2, where P2 is greater than P1. For example, P1<100 nm and P2>100 nm. In particular, the first circuit region 120 further comprises a dummy area 120D having various dummy gates 114A surrounding the functional gates 112A in the active device area 120A, and the second circuit region 122 comprises a dummy area 122D having various dummy gates 114B surrounding the functional gates 112B in the active device area 122A.As described above, the dummy gates in the dummy regions provide greater freedom in tuning circuit performance and manufacturing window. For example, increasing the gate pitch of the second gates 112B, such as near the fT peak, reduces parasitic capacitance and improves the high-frequency performance of the device for the RF circuit. However, the increased gate pitch reduces the gate density, leading to more process defects (such as CMP variations at different feature densities). Accordingly, the gate pitch for the dummy gates 114B in the dummy region 122D surrounding the functional gates 112B in the active device region 122A is tuned to compensate for the variation in gate feature density in the second circuit region 122 to improve manufacturing.According to the invention, the gate pitch of the dummy gates 114B is designed to be smaller than P2, so that, for example, the average gate structure density in the second circuit region 122 is increased or is substantially the same or similar to that in the first circuit region 120. The high-frequency parasitic capacitance effect is not relevant for the logic circuit. The corresponding dummy gates 114A are designed according to the invention to have the same gate pitch P1 as the functional gate stacks 112A.

[0035] In the illustrated embodiment, the dummy gates 114A have a shape, size pitch, orientation, and configuration similar to those of the functional gates 112A, while the dummy gates 114B have a shape, size pitch, orientation, and configuration different from those of the functional gates 112B. Furthermore, the dummy gates 114B may have various subsets, each tuned to provide greater tuning freedom and tuning effect. For example, the dummy gates 114B include a first subset S1 and a second subset S2. The dummy gates 114B in the first subset S1 have a similar shape, size pitch, orientation, and configuration as the functional gates 112B, while the dummy gates 114B in the second subset S2 have a shape, size pitch, orientation, configuration, or a combination thereof that differs from those of the functional gates 112B.In the illustrated embodiment, the dummy gates 114B in the second subset S2 are designed to have a different length in the X direction, a different pitch in the Y direction, or both a different length and a different pitch. According to a further embodiment, the dummy gate stacks 114B in the second subset S2 are designed with a reduced gate pitch ( <P2) designt, um die Strukturdichte zu erhöhen, sodass die durchschnittliche Strukturdichte der Dummygates 114B und der Funktionsgates 112B in der zweiten Schaltungsregion 122 zusammengenommen erhöht wird oder nahe an der der ersten Schaltungsregion 120 liegt. In einigen Ausführungsformen, die in . Fig. 3, the dummy gates 114B in the second subset S2 are designed to have a shorter length in the X direction and a smaller pitch in the Y direction than the gates of the gate function gates 122A.

[0036] In some embodiments, the IC structure 100 further includes guard rings arranged and configured to pre-bias the substrate to shield interference, reduce noise, and improve circuit performance. A guard ring may be a conductive feature, such as a metal line, configured to connect to the substrate via a contact feature. The guard ring is further connected to a power line, such as a ground line, to pre-bias the substrate. In some embodiments, a guard ring 152 is interposed between the active device region 122A and the dummy region 122D, specifically, between the functional gates 112B of the active device region 122A and the dummy gates 114B of the dummy region 122D.In another embodiment, another guard ring 150 may be displaced between the functional gates 112A of the active device area 120A and the dummy gates 114A of the dummy region 120D.

[0037] In some embodiments, some dummy gates 114B are configured to be pre-biased or connected to pre-bias the substrate 102, such as through underlying doped wells (an N-well, a P-well, or both) to act as a guard ring. In further embodiments, the dummy gates 114B of the dummy region 122D are configured to be pre-biased or connected to pre-bias the substrate 102, while the dummy gates 114A of the dummy region 120D are not pre-biased (such as floating). In an illustrated embodiment, the dummy gates 114B of the dummy region 122D are free of a gate dielectric layer and connected to a power line (such as a ground line) to pre-charge the substrate 102, while the dummy gates 114A of the dummy region 120D include a gate dielectric layer and are not connected to a power line, such as floating.

[0038] Fig. 4A is a top view of the IC structure 100 in a portion (particularly guard rings) constructed according to some embodiments. In the illustrated embodiments, the gates are designed to act as guard rings. Specifically, these gates are configured to surround the active device regions and are oriented to be parallel to the adjacent edges of the respective active device regions. The guard rings may comprise multiple layers to increase the protection effect, such as in the Fig. 4A, three layers. The multiple layers of guard rings may be further designed with different spacings to accommodate protection effectiveness and circuit area. In some embodiments, the guard rings may have graduated spacings. For example, there is a first spacing between the inner guard ring and the middle guard ring C1, and a second spacing between the middle guard ring and the outer guard ring C2. C2 is greater than C1. The ratio C2 / C1 is greater than 1.5 in some examples. In the illustrated embodiment, the guard rings 152 in the second circuit region 122 are configured to be connected to a bias current line, such as ground, while the guard rings 150 in the first circuit region 120 are configured to be floating, which is similar to the dummy gates 114 in the dummy regions.Specifically, the guard rings are not aligned in only one direction, such as the X direction, but include portions aligned in the X direction and portions aligned in the Y direction, so that they are configured to enclose the circuit region (such as 122A). Alternatively, the guard rings 152 are configured around the RF circuitry in the active circuit area 122A, while the guard rings 150 are absent.

[0039] Fig. 4B is a top view of the IC structure 100 constructed in section according to some embodiments. The IC 100 has a gate layout optimized for improved circuit performance for both the logic circuitry in the first circuit region 120 and the RF circuitry in the second circuit region 122 (in Fig. 4B, only the second circuit region 122 is shown. The IC structure 100 includes active fin regions 106 and gates (such as functional gates 112B and dummy gates 114B) aligned in the Y and X directions, respectively. The second circuit region 122 includes an active device area 122A for an RF circuit 154 and a dummy region 122D surrounding the active device area 122A. Specifically, the IC structure 100 includes various blocks with different gate configurations. In the illustrated embodiments, the RF circuit 154 includes functional gates 112B configured in an array and surrounded by dummy gates 114B in the dummy region. The RF circuit 154 further includes active fin regions 106, sources, drains, contacts, vias, and metal lines configured to form various transistors.In particular, the functional gates 112B of the RF circuit 154 have an increased gate pitch (larger than that of the logic circuit) for improved high-frequency performance of the RF circuit 154. The dummy gates 114B are designed to have different gate pitches than the functional gates 112B to compensate for the feature density and reduce process errors. More specifically, the dummy gates 114B in different blocks (or sub-dummy regions) are configured differently (different in gate pitch, gate dimensions, gate orientations, gate grouping, or a combination thereof) to provide more freedom in tuning the feature density and eliminate (or reduce) process errors. In the illustrated embodiment, the dummy gates 114B surrounding the functional gates 112B include various subsets of dummy gates 114B in respective sub-dummy regions 156, 158, 160, 162, and 164.

[0040] The first subset of dummy gates 114B in the first sub-dummy region 156 is arranged on two sides (spaced along the X-direction) of the functional gates 112B with a gate pitch similar to that of the functional gates 112B; the second subset of dummy gates 114B in the second sub-dummy region 158 is arranged on two sides (spaced along the Y-direction) of the functional gates 112B with a gate pitch and gate dimension that are different from those of the functional gates 112B (e.g.,greater than this); the third subset of dummy gates 114B in the third sub-dummy region 160 are arranged on the outermost side of the RF circuit region 154 of the functional gates 112B with a gate pitch that is smaller than that of the functional gates 112B; the fourth subset of dummy gates 114B in the fourth sub-dummy region 162 is arranged on the outermost side of the RF circuit region 154 and configured on two edges (spaced along the X direction) of the functional gates 112B with a gate pitch that is smaller than that of the functional gates 112B (or the same as the gate pitch of the dummy gates 114B in the third sub-dummy region 160); and the fifth subset of dummy gates 114B in the fifth sub-dummy region 164 on the outermost side of the RF circuit 154 of the functional gates 112B is arranged with a gate pitch smaller than that of the functional gates 112B (or equal to the gate pitch of the dummy gates 114B in the third sub-dummy region 160).

[0041] Specifically, the third subset of dummy gates 114B in the third sub-dummy region 160 is grouped into an array, each row having a first number N1 of dummy gates 114B; and the fifth subset of dummy gates in the fifth sub-dummy region 164 is grouped into an array, each row having a second number N2 of dummy gates 114B, where N2 is greater than N1. For example, N1=8 and N2=15. The dummy gates 114B in the third sub-dummy region 160 and in the fifth sub-dummy region 164 have a first gate length L1, while the dummy gates 114B in the fourth sub-region 162 have a second gate length L2 that is greater than L1. All functional gates 112B and dummy gates 114B are aligned in the X direction. By tuning the dummy gates 114B with respect to gate pitch, gate dimensions and distribution of the dummy gates in different subregions.The structure density is improved and the process errors are eliminated or reduced while the RF circuit performance is improved.

[0042] The IC structure 100 also includes guard rings 166 configured around the active device area 122A and connected to the substrate's pre-load, such as ground. The guard rings 166 are attached and connected to shield the RF circuitry 154 from noise during high-frequency operation. The guard rings 166 may have different configurations, for example, they may surround the RF circuitry 154 with multiple layers (such as three layers in the illustrated example of Fig. 4). In some examples, guard rings 152 are metal lines connected to the substrate via the contact features. In some embodiments, guard rings 152 are configured between functional gates 112B in active device region 122A and dummy gates 114B in dummy region 122D.

[0043] Fig. 5 is a cross-sectional view of the IC structure 100 constructed in section according to some embodiments. Fig. 5 is similar to Fig. 2A, however, shows more detail. The gate 112 (such as gate 112A or gate 112B) includes a gate dielectric layer 202, a gate electrode 204, and a gate spacer 206. The gate dielectric layer 202 may further include an interface layer and a high-k dielectric layer. The gate electrode 204 may further include a work function metal 204A and a fill metal 204B. The gate 112 may further include other materials, such as a cap layer between the gate dielectric layer 202 and the gate electrode 204. The gate spacer 206 may include one or more dielectrics, such as silicon oxide, silicon nitride, or a combination thereof, disposed on the sidewalls of the gate electrode 204. In the illustrated embodiment, the gate spacer 206 includes an inner spacer 206A and an outer spacer 206B having different dielectric compositions.The gates 112 are embedded in an ILD layer 140.

[0044] Fig. 7 is similar to Fig. 5 and is constructed in more detail according to some embodiments. The gate 112B includes the gate dielectric layer 202 disposed on the channel, the gate electrode 204 disposed on the gate dielectric layer, and the gate spacer 206 disposed on the sidewalls of the gate electrode. The gate dielectric layer 202 may include an interface layer 202A and a high-k dielectric layer 202B. In some examples, the gate dielectric layer 202 may include two or more oxide layers with different dielectric constants, such as silicon oxide with different oxygen concentration or silicon oxide / silicon nitride, or a combination thereof. In the illustrated embodiment, the gate electrode 204 includes a work function metal layer 204A and a fill metal layer 204B.The workfunction metal layer 204A may comprise multiple films, where one film has a higher work function than others, is thicker than other films, or both. The workfunction metal layer 204A may comprise Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, Sn, or a combination thereof, and a film of the workfunction metal layer 204A may be an oxide or nitride of the aforementioned metal(s). The workfunction metal layer 204A may have a thickness ranging between 1 nm and 4 nm (10 angstroms and 40 angstroms). The fill metal layer 204B may comprise W, Al, Cu, or a combination thereof. The gate spacer 206 may comprise multiple dielectric layers, such as a silicon oxide layer and a silicon nitride layer. In the illustrated embodiment, the gate spacer 206 includes a first silicon nitride layer 206A and a silicon nitride layer 206B having a different composition, a different thickness, or both.In one example, the first silicon nitride layer 206A has a higher nitrogen concentration than that of the second silicon nitride layer 206B. In another example, the first silicon nitride layer 206A has a greater nitrogen concentration than that of the second silicon nitride layer 206B. In another example, the first silicon nitride layer 206A has a higher nitrogen concentration and a greater thickness than that of the second silicon nitride layer 206B. In another example, the first silicon nitride layer 206A has a lower nitrogen concentration and a smaller thickness than that of the second silicon nitride layer 206B. The structure, composition, and formation of the gate 112 are described with reference to FIG. Fig. 8, Fig. 9 and Fig. 10. In particular, the profiles of the gates 112 depend on the compositions and thicknesses of the various materials in the gate 112, as described above. The gate dielectric layer 202 has the same composition(s) and thickness(es) for the gate 112A for the logic circuit as for the gate 112B for the RF circuit.

[0045] Fig. 6 is a cross-sectional view of the IC structure 100 constructed in section according to some embodiments. Fig. Figure 6 provides further details on the profiles of gates 112A and 112B. The first gates 112A include a top portion with a trapezoidal shape; and the second gates 112B include a top portion with rounded corners.

[0046] The gate 112 (112A or 112B) includes a lower portion G1 below the upper surface 106A of the active fin region 106 and an upper portion G uabove the upper surface 106A of the active fin region 106. In the sectional view through the active fin region, the lower section is not visible. However, it is Fig. 6 to better illustrate the vertical positions and profiles of the gates 112. Only the lower section is connected to the channel 130 for the capacitive coupling between the respective gate 112 (such as 112A or 112B) and the channel 130 and therefore contributes significantly to the gate performance. The lower sections of the gates 112A and 112B have different profiles. Since the functional gate 112B in the RF circuit has a larger gate pitch, the lower section G l of the functional gate 112B is subjected to an additional etching due to the etching charge effect, whereby the horizontal dimension of the gate 112B in the lower section G lis further reduced. The lower portion of the gate 112B has a minimum dimension (or neckdown) in the middle. Specifically, the lower portion of the gate 112B spans a first dimension W1 at the bottom surface, a second dimension W2 at the middle, and a third dimension W3 at the top surface (which is flush with the top surface 106A of the active fin region 106). W1 and W3 are each greater than W2; and W3 is greater than W1. In the illustrated example, the ratio W3 / W2 is between 1.2 and 1.3; and the ratio W1 / W2 is between 1.05 and 1.13. The upper portion of the functional gate 112B also has an uneven profile. Specifically, the upper portion of the gate 112B spans the third dimension W3 at the bottom surface (flush with the top surface 106A of the active fin region 106); a fourth dimension W4 in the center; and a fifth dimension W5 on the upper surface. W3 and W5 are each larger than W4.In the example shown, the ratio W5 / W4 or W3 / W4 is between 1.06 and 1.14. This non-uniform profile of the functional gate 112B further reduces the parasitic capacitance to the components (such as FETs) of the RF circuit, thereby achieving improved high-frequency characteristics and performance of the RF circuit.

[0047] In various embodiments described above, the gates 112 are described with reference to Fig. 8 to 10 in cross-sectional views according to various embodiments. The gate 112 includes a gate dielectric layer 202 (e.g., silicon oxide) and a gate electrode 204 (e.g., doped polysilicon) disposed on the gate dielectric layer, as shown in Fig. 8 is illustrated.

[0048] In some embodiments, the gate 112 alternatively or additionally comprises other suitable materials for circuit performance and manufacturing integration. For example, the gate dielectric layer 202 comprises an interface layer 202A (e.g., silicon oxide) and a high-k dielectric layer 202B, as shown in Fig. 9. The high-k dielectric may comprise metal oxide, metal nitride, or metal oxynitride. In various examples, the high-k dielectric layer comprises metal oxide: ZrO2, Al2O3, and HfO2, formed by a suitable process, such as metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). In some examples, the interfacial layer comprises silicon oxide formed by ALD, thermal oxidation, or ultraviolet oxidation. The gate electrode 204 comprises metal, such as aluminum, copper, tungsten, metal silicide, doped polysilicon, another suitable conductive material, or a combination thereof. The gate electrode may comprise a plurality of conductive films designed as a cap layer, a work function metal layer, a barrier layer, and a fill metal layer (e.g., aluminum or tungsten).The multiple conductive films are designed to match the work function of the n-FET (nFET) or p-FET (pFET). In some embodiments, the gate electrode for the nFET comprises a work function metal with a composition designed with a work function of 4.2 eV or less, and the gate electrode for the pFET comprises a work function metal with a composition designed with a work function of 5.2 eV or greater. For example, the work function metal layer for the nFET comprises tantalum, titanium aluminum, titanium aluminum nitride, or a combination thereof. In other examples, the work function metal layer for the pFET comprises titanium nitride, tantalum nitride, or a combination thereof.

[0049] In some embodiments described in Fig. 10, the gate 112 is formed by a different process with a different structure. The gate may be formed by various deposition techniques and a suitable process, such as the gate-last process, in which a dummy gate is first formed, which is then replaced by a metal gate after the formation of the source and drain features. Alternatively, the gate is formed by a high-k load process, in which both the gate dielectric layer and the gate electrode are replaced by high-k dielectric and metal, respectively, after the formation of the source and drain features. In a high-k load process, a dummy gate is first formed by deposition and patterning; then, source / drain features are formed on the gate sides and an interlayer dielectric layer is formed on the substrate; the dummy gate is removed by etching to obtain a gate trench; and then the gate material layers are deposited in the gate trench.In this example, the gate electrode 204 includes a work function metal layer 204A and a fill metal 204B, such as aluminum or copper. A gate 112 formed in this way includes various gate material layers in a U-shape.

[0050] In some embodiments, the method for tuning the IC circuit structure is described in more detail below according to some embodiments. The method includes receiving a circuit layout of an IC circuit; and classifying circuit regions according to the respective circuit functions, such as logic circuitry, RF circuitry, memory circuitry, I / O circuitry, and so on. The method further includes modifying the gate pitches of the respective circuits, such as increasing the gate pitch of the RF circuitry to improve high-frequency performance and decreasing the gate pitch of the logic circuitry to increase the packaging density of the circuitry. In particular, the gate pitch of the RF circuitry is adjusted so that the crossover frequency is equal to or close to the fT peak.The method further includes modifying the gate width and gate length to further improve circuit performance according to the circuit characteristics of the respective circuits, such as the parasitic capacitance of the RF circuit. The method also includes adding a dummy region surrounding a circuit, such as a dummy region surrounding the RF circuit. The shape and size of the dummy region are determined depending on one or more factors, such as the feature density and the shape and size of the RF circuit. The method further includes determining the dummy gates arranged in the dummy region, including the gate pitch, gate width, gate length, gate structure (such as with or without a gate dielectric layer), gate composition (such as polysilicon, metal, or metal alloy), and gate configuration (such as connected to the power line or floating).In some examples, the dummy gates include subsets with different grouping, gate pitch, gate length, and gate width, as in . Fig. 4B. The method also includes adding guard rings surrounding the respective circuitry, such as guard rings surrounding the RF circuitry. In some examples, the guard rings are arranged between the respective circuitry (such as RF circuitry) and the surrounding dummy gates in the dummy region. In some embodiments, the guard rings are made of gates, but differ in configuration, composition, and orientation from the dummy gates in the dummy region. For example, the guard rings are connected to power lines (such as ground), while the dummy gates are unconnected and floating. In some examples, the guard rings include X-direction oriented portions and Y-direction oriented portions arranged to enclose the respective circuitry (e.g., the RF circuitry), as shown in Fig. 4A or Fig. 4B is illustrated.

[0051] This disclosure provides various embodiments of an IC structure with multiple circuit regions with different functions, such as logic circuitry and RF circuitry. These circuits can be designed as standard cells configured according to predefined rules. In various embodiments described above, circuits or standard cells are designed and placed according to the disclosed rules. Each circuit is surrounded by dummy regions with dummy gates formed thereon. In particular, the functional gates in an RF circuit are designed to have a larger gate pitch to reduce parasitic capacitance and improve high-frequency performance.The dummy gates surrounding the RF circuitry are designed to have a reduced gate pitch to compensate for the variation in pattern density caused by the larger-pitch functional gates in the RF circuitry, thereby eliminating or reducing process errors and allowing the overall IC structure to exhibit improved circuit performance without degrading manufacturing quality.

[0052] In one exemplary aspect, this invention provides a semiconductor structure according to some embodiments. The semiconductor structure comprises a semiconductor substrate having a first circuit region and a second circuit region; active regions extending from the semiconductor substrate and surrounded by isolation features; first transistors comprising first gate stacks formed on the active regions and arranged in the first circuit region, the first gate stacks having a first gate pitch that is smaller than a reference pitch; and second transistors comprising second gate stacks formed on the active regions and arranged in the second circuit region, the second gate stacks having a second pitch that is larger than the reference pitch. The second transistors are radio frequency transistors and the first transistors are logic transistors.A first dummy region surrounds the first transistors, and a second dummy region surrounds the second transistors. The first dummy region has a plurality of first dummy gates configured with a gate pitch equal to the first gate pitch. The second dummy region has a plurality of second dummy gates configured with a gate pitch smaller than the second gate pitch.

[0053] In another exemplary aspect, this invention provides a semiconductor circuit structure. The semiconductor circuit structure comprises a semiconductor substrate having a first circuit region and a second circuit region; logic transistors comprising first gate stacks arranged in the first circuit region, the first gate stacks having a first gate pitch; high-frequency transistors comprising second gate stacks arranged in the second circuit region, the second gate stacks having a second gate pitch greater than the first gate pitch; a first dummy region surrounding the logic transistors and a second dummy region surrounding the high-frequency transistors; and a guard ring arranged between the second circuit region and the second dummy region.The first dummy region includes first dummy gates configured with a third gate pitch equal to the first gate pitch; and the second dummy region includes second dummy gates configured with a fourth gate pitch smaller than the second gate pitch.

[0054] In yet another exemplary aspect, this invention provides a semiconductor structure. The semiconductor structure comprises a semiconductor substrate having a first circuit region and a second circuit region; logic transistors comprising first gate stacks arranged in the first circuit region, the first gate stacks having a first gate pitch and a first gate height; radio-frequency transistors comprising second gate stacks arranged in the second circuit region, the second gate stacks having a second gate pitch greater than the first gate pitch and a second gate height smaller than the first gate height; a first dummy region surrounding the logic transistors and a second dummy region surrounding the radio-frequency transistors; and a guard ring arranged between the second circuit region and the second dummy region.The first dummy region includes first dummy gates configured with a third gate pitch equal to the first gate pitch, and the second dummy region includes second dummy gates configured with a fourth gate pitch smaller than the second gate pitch.

Claims

[1] Semiconductor circuit structure, comprising: a semiconductor substrate (102) having a first circuit region (120) and a second circuit region (122); active fin regions (106) protruding from the semiconductor substrate (102) and surrounded by insulation features; first transistors having first gate stacks (112A) formed on the active fin regions (106) and arranged in the first circuit region (120), the first gate stacks (112A) having a first gate pitch that is smaller than a reference pitch (100); second transistors having second gate stacks (112B) formed on the active fin regions (106) and arranged in the second circuit region (122), the second gate stacks (112B) having a second gate pitch that is greater than the reference pitch (100), the second transistors being radio frequency transistors and the first transistors being logic transistors, and a first dummy region surrounding the first transistors and a second dummy region surrounding the second transistors, wherein the first dummy region has a plurality of first dummy gates configured with a gate pitch equal to the first gate pitch; and the second dummy region has a plurality of second dummy gates (114B) configured with a gate pitch smaller than the second gate pitch. [2] The semiconductor circuit structure of claim 1, further comprising third transistors having third gate stacks formed on the active fin regions (106) and arranged in a third circuit region of the semiconductor substrate (102), the third gate stacks having a third gate pitch different from the first and second gate pitches. [3] Semiconductor circuit structure according to one of the preceding claims, wherein the first gate stacks (112A) have a first gate height; and the second gate stacks (112B) have a second gate height that is less than the first gate height. [4] Semiconductor circuit structure according to one of the preceding claims, wherein the first gate stacks (112A) have an upper portion with a trapezoidal shape; and the second gate stacks (112B) have an upper section with rounded corners. [5] A semiconductor circuit structure according to claim 4, wherein the second gate stacks (112B) each further comprise an upper portion above an upper surface (106A) of the active fin regions (106) and a lower portion below the upper surface (106A) of the active fin regions (106); and the lower section has an uneven profile in a sectional view. [6] A semiconductor circuit structure according to claim 5, wherein the lower portion of each of the second gate stacks (112B) spans a first width W1 at a lower surface, a second width W2 at a middle location, and a third width W3 at an upper surface (106A) flush with the upper surface (106A) of the active fin region (106); each of W1 and W3 is greater than W2; and W3 is greater than W1. [7] A semiconductor circuit structure according to claim 6, wherein a first ratio W1 / W2 is between 1.05 and 1.13; and a second ratio W3 / W2 is between 1.2 and 1.

3. [8] A semiconductor circuit structure according to claim 6 or 7, wherein the upper portion of each of the second gate stacks (112B) spans a fourth width W4 at a central location and a fifth width W5 at an upper surface (106A); and W3 and W5 are each larger than W4. [9] A semiconductor circuit structure according to any one of claims 6 to 8, wherein a third ratio W5 / W4 is between 1.06 and 1.

14. [10] The semiconductor circuit structure according to any one of claims 1 to 9, wherein the second dummy gates (114B) comprise a first subset and a second subset designed to differ in gate pitch, gate dimensions, and gate grouping, thereby tuning a structure density. [11] A semiconductor circuit structure according to any one of claims 1 to 10, comprising multi-layer guard rings (150, 152, 166) arranged between the second transistors and the second dummy region. [12] The semiconductor circuit structure of claim 11, wherein the multilayer guard rings (152) include conductive features connected to a ground line to pre-charge the semiconductor substrate (102). [13] A semiconductor circuit structure according to any preceding claim, wherein the first and second transistors are vertically stacked multiple channel field effect transistors. [14] Semiconductor circuit structure, comprising: a semiconductor substrate (102) having a first circuit region (120) and a second circuit region (122); Logic transistors having first gate stacks (112A) arranged in the first circuit region (120), the first gate stacks (112A) having a first gate pitch; High frequency transistors having second gate stacks (112B) arranged in the second circuit region (122), the second gate stacks (112B) having a second gate pitch that is greater than the first gate pitch; a first dummy region surrounding the logic transistors and a second dummy region surrounding the high-frequency transistors; and a guard ring (152) disposed between the second circuit region (122) and the second dummy region, wherein the first dummy region has first dummy gates configured with a third gate pitch equal to the first gate pitch; and the second dummy region has second dummy gates (114B) configured with a fourth gate pitch smaller than the second gate pitch. [15] A semiconductor circuit structure according to claim 14, wherein the first gate stacks (112A) have a first gate height; and the second gate stacks (112B) have a second gate height that is less than the first gate height. [16] A semiconductor circuit structure according to claim 14 or 15, wherein the second gate stacks (112B) each further comprise an upper portion above an upper surface (106A) of active fin regions (106) and a lower portion below the upper surface (106A) of the active fin regions (106); the lower portion of each of the second gate stacks (112B) spans a first width W1 at a lower surface, a second width W2 at a middle location, and a third width W3 at an upper surface (106A) flush with the upper surface (106A) of the active fin region (106); each of W1 and W3 is greater than W2; and W3 is greater than W1. [17] A semiconductor circuit structure according to any preceding claim, wherein the first and second transistors are field effect transistors each having vertically stacked multiple channels.

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