Cascaded measuring circuits for detecting and monitoring cracks in an integrated circuit

Abstract

System (100) for detecting and monitoring cracks (130), which includes: a plurality of electrically conductive structures (604, 606, 608) extending around a protective barrier (110) formed in an inactive region (108) of an integrated circuit (102), wherein an active region (106) of the integrated circuit (102) is enclosed within the protective barrier (110); and a plurality of stages of measuring circuits (610, 612, 614) connected in series and measuring a change in an electrical characteristic (RPL0, RPL1, RPL2) of each of the plurality of structures (604, 606, 608) and receiving an activation signal (ENN; CRACKN_S0, CRACKN_S1, CRACKN_S2), wherein each measuring circuit (610, 612, 614) is coupled to a respective structure (604, 606, 608) of the plurality of structures (604, 606, 608) and the change in the electrical characteristic (RPL0, RPL1, RPL2) indicates damage to the respective structure (604, 606, 608), wherein each measuring circuit (610, 612, 614) includes a circuit for selectively generating the activation signal (CRACKN_S0, CRACKN_S1) for a next measuring circuit (612, 614) of the plurality of stages of measuring circuits (610, 612, 614).

Description

background

[0001] The present disclosure relates to integrated circuits and in particular to cascaded measuring circuits for detecting and monitoring cracks in an integrated circuit (IC).

[0002] Processes such as wafer dicing can lead to the formation and propagation of cracks in an integrated circuit. These cracks often form at the interfaces between dielectric materials and metal traces / contacts within the integrated circuit.

[0003] Integrated circuits are frequently exposed to harsh, aggressive, and stressful environmental conditions (e.g., in automotive, aerospace, military applications, etc.). Fluctuations in these environmental conditions (e.g., temperature, humidity, and barometric fluctuations) can exacerbate or trigger slow crack propagation mechanisms in both incipient and dormant cracks (e.g., cracks that originate during wafer dicing) within the integrated circuits. Continuous fluctuations in environmental conditions can promote the growth of incipient and dormant cracks over time and potentially lead to integrated circuit failure.

[0004] So-called crackstops (e.g., a continuous structure of metal traces and contact holes) have been manufactured and used to prevent crack propagation into the active region of an integrated circuit. Such crackstops are typically located at the outer edge of the integrated circuit and surround the inner core (active region) of the integrated circuit.

[0005] Although effective, crack stoppers are not always able to prevent a crack from propagating into the active area of ​​an integrated circuit. Therefore, crack detection structures have been developed that are positioned within the active area of ​​the integrated circuit, inside the crack stopper, to detect the presence of a crack that has propagated past the crack stopper into the active area of ​​the IC chip. However, such crack detection structures are inherently flawed because they are designed to detect a crack when it is too late and the crack has already reached the active area of ​​the IC chip.

[0006] Document EP 3 425 664 A1 relates to a device comprising: a substrate; an integrated circuit area formed in the substrate; a sealing ring arranged in the substrate, which forms a ring around the integrated circuit area, wherein the sealing ring is configured to provide protection against the ingress of moisture and / or ions into the integrated circuit area and against the propagation of cracks through the substrate;and a defect sensor comprising a conductive track formed from at least one conductive layer in the substrate, wherein the conductive track is arranged outside the sealing ring and is arranged to at least partially surround the integrated circuit area and the sealing ring, wherein the conductive track has a first end terminal and a second end terminal to receive a detection signal passing through the conductive track in order to detect a break in the conductive track and thus a defect in the substrate.

[0007] Document US 2018 / 0138098A1 relates to a detector for determining a defective semiconductor device comprising a semiconductor device, a contact via chain arranged laterally spaced from the semiconductor device and partially enclosing the semiconductor device, a guard ring arranged laterally spaced from the semiconductor device, and an evaluation unit arranged on the semiconductor device, characterized in that the evaluation unit is configured to apply an electrical voltage to the contact via chain, in particular a continuous electrical voltage, to detect a resistance value of the contact via chain, and to generate an output signal when the resistance value of the contact via chain exceeds a threshold value.

[0008] Document US 2020 / 0150174A1 concerns an integrated circuit chip comprising a circumferential edge and a sealing ring extending along the circumferential edge and surrounding a functional integrated circuit region. A test logic circuit located within the functional integrated circuit region generates a serial input data signal applied to the first end of a conductive sensor lead extending around the sealing ring between the sealing ring and the circumferential edge of the integrated circuit chip. Propagation of the serial input data signal along the conductive sensor lead generates a serial output data signal at a second end of the conductive sensor lead. The test logic circuit compares data patterns of the serial input data signal and the serial output data signal to detect damage to the circumferential edge of the integrated circuit. Summary

[0009] One aspect of the disclosure relates to a system for detecting and monitoring a crack in an integrated circuit, comprising: a plurality of electrically conductive structures extending around a protective barrier formed in an inactive region of an integrated circuit, wherein an active region of the integrated circuit is enclosed within the protective barrier; and a plurality of stages of measuring circuits connected in series, measuring a change in an electrical characteristic of each of the plurality of structures and receiving an activation signal, wherein each measuring circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, and each measuring circuit including a circuit for selectively generating the activation signal for the next measuring circuit of the plurality of stages of measuring circuits.

[0010] Another aspect concerns a method for detecting and monitoring a crack in an integrated circuit, which includes: providing a plurality of electrically conductive structures in an inactive region of the integrated circuit, wherein the plurality of electrically conductive structures extends around a protective barrier formed in the inactive region of the integrated circuit, and an active region of the integrated circuit is enclosed within the protective barrier; coupling a plurality of stages of measuring circuits connected in series with the plurality of electrically conductive structures, wherein each measuring circuit is coupled to a respective structure of the plurality of structures; activating the measuring circuit at a stage N of the plurality of stages of measuring circuits; monitoring an electrical characteristic of the respective structure coupled to the activated measuring circuit by the activated measuring circuit;and outputting an activation signal to activate the measuring circuit in a downstream stage N+1 of the plurality of stages of measuring circuits by the activated measuring circuit in response to detection of a change in the electrical characteristic of the respective structure coupled to the activated measuring circuit.

[0011] Another aspect concerns a procedure that includes: Coupling a plurality of stages of measuring circuits connected in series with a plurality of electrically conductive structures on an integrated circuit, wherein each measuring circuit is coupled to a respective structure of the plurality of structures; activating the measuring circuit in a stage N of the plurality of stages of measuring circuits; monitoring an electrical characteristic of the respective structure coupled to the activated measuring circuit by the activated measuring circuit; and outputting an activation signal to activate the measuring circuit in a downstream stage N+1 of the plurality of stages of measuring circuits by the activated measuring circuit in response to detection of a change in the electrical characteristic of the respective structure coupled to the activated measuring circuit.

[0012] The features listed above and others of the disclosure will become apparent from the following more detailed description of embodiments of the disclosure. Brief description of the drawings

[0013] The embodiments of the present disclosure are described in detail with reference to the following figures, in which identical designations denote identical elements. Fig. Figure 1 shows a top view of an integrated circuit that includes a system for detecting and monitoring crack growth according to embodiments. Fig. Figure 2 shows a sectional view of the integrated circuit in Fig. 1 along line A - A according to embodiments. Fig. Figure 3 shows a top view of an integrated circuit incorporating a crack detection and monitoring system according to embodiments, wherein the crack detection and monitoring system includes boundary lines (PLINEs) and bridging connections. Fig. Figure 4 shows an enlarged partial top view of the integrated circuit in Fig. 3 according to embodiments. Fig. Figure 5 shows a partial sectional view of a boundary line of the integrated circuit in Fig. 3 according to embodiments. Fig. Figure 6 shows a top view of an integrated circuit incorporating a system for detecting and monitoring crack growth according to embodiments, wherein the crack detection and monitoring system includes boundary lines and tunnel connections. Fig. Figure 7 shows an enlarged, partial top view of the integrated circuit in Fig. 6 according to embodiments. Fig. Figure 8 shows a partial sectional view of a boundary line (PLINE) of the integrated circuit in Fig. 6 according to embodiments. Fig. Figure 9 shows a partial sectional view of the integrated circuit in Fig. 6 along line BB according to embodiments. Fig. Figure 10 shows a sectional view of a boundary line for guiding and fixing a propagating crack according to embodiments. Fig. 11A, Fig. 11B and Fig. Figure 11C shows an example of the function for guiding and fixing cracks of the boundary line in Fig. 10 according to embodiments. Fig. Figure 12 shows a flowchart of a method for detecting and monitoring cracks in an integrated circuit according to embodiments. Fig. Figure 13 shows a top view of an integrated circuit incorporating a system for detecting and monitoring cracks according to other embodiments. Fig. Figure 14 shows a top view of an integrated circuit that includes a system for detecting and monitoring the growth of cracks according to embodiments. Fig. Figure 15 shows a circuit diagram of a detection and monitoring circuit which includes a cascade arrangement of measuring circuits according to embodiments. Fig. Figure 16 shows a circuit diagram of a detection and monitoring circuit which includes a cascade arrangement of measuring circuits according to embodiments.

[0014] It should be noted that the drawings in the revelation are not necessarily to scale. The drawings are intended to illustrate typical aspects of the revelation and should therefore not be considered as limiting the scope of protection afforded by the revelation. In the drawings, the same numbering represents the same elements in the different drawings. Detailed description

[0015] The following description refers to the accompanying drawings, which form part thereof and illustrate specific exemplary embodiments in which the present teaching can be practically implemented. These embodiments are described in sufficient detail to enable the person skilled in the art to practically implement the present teaching, and it is understood that other embodiments can be used and modifications made without deviating from the scope of protection of the present teaching. The following description therefore serves only for illustration.

[0016] Fig. Figure 1 shows a top view of an integrated circuit incorporating a crack detection and monitoring system 100, according to embodiments, which detects and monitors crack growth. The integrated circuit 102 is formed on a semiconductor substrate 104 (e.g., a silicon wafer) and includes an inner core (hereinafter referred to as the active region 106) surrounded by a guard ring 110 and insulated from an inactive region 108, as well as at least one crack stopper 112, 114. The active region 106 typically includes a variety of active and passive components (e.g., transistors, resistors, etc.). The guard ring 110 and the crack stoppers 112, 114 protect against environmental influences and provide electrical protection (e.g., the guard ring represents an electrical ground) and / or mechanical protection for the active region 106 of the integrated circuit 102.The crack stoppers 112, 114 can, for example, be used to prevent crack propagation from the inactive region 108 of the integrated circuit 102 into the active region 106 of the integrated circuit 102. The protective ring 110 and the crack stoppers 112, 114 can be of conventional design and can be created using any currently known or future methods / technologies.

[0017] According to embodiments, the crack detection and monitoring system 100 is designed to detect and monitor the growth of one or more cracks in the inactive region 108 of the integrated circuit 102 – before cracks propagate into the active region 106 of the integrated circuit 102. In general, as described in Fig. As shown in Figure 1, the system 100 for detecting and monitoring cracks includes at least one electrically conductive boundary line (PLINE) formed in the inactive region 108 of the integrated circuit 102. For example, a first boundary line 120, a second boundary line 122, and a third boundary line 124 can be formed in the inactive region 108 of the integrated circuit 102. In the present example, as shown in Figure 1, the system 100 for detecting and monitoring cracks includes at least one electrically conductive boundary line (PLINE) formed in the inactive region 108 of the integrated circuit 102. Fig. As shown in Figure 1, the first boundary line 120 is formed around an outer circumference of the protective ring 110 between the protective ring 110 and the crack stop 112. The second boundary line 122 can be formed around an outer circumference of the crack stop 112 between the crack stop 112 and the crack stop 114. The third boundary line 124 can be formed around an outer circumference of the crack stop 114. Although three boundary lines 120, 122, 124 are used in the present embodiment, it should be clear that the system 100 for detecting and monitoring cracks can contain a larger or smaller number of boundary lines (e.g., one or more). Furthermore, boundary lines can be formed at other positions in the inactive region 108 of the integrated circuit 102, and / or a plurality of boundary lines can be formed adjacent to each other in the inactive region 108 of the integrated circuit 102.

[0018] Several other embodiments illustrating such positioning of boundary lines are described below.

[0019] Each boundary line 120, 122, 124 is independently coupled to a detection and monitoring circuit 126. The functionality of the detection and monitoring circuit 126 can be provided, in the present embodiment and in other embodiments as shown, by the integrated circuit 102 or via an external circuit (not shown). According to embodiments, connections above and / or below the protective ring 110, crack stop 112, and / or crack stop 114 can be provided to couple the boundary lines 120, 122, 124 to the detection and monitoring circuit 126. Therefore, depending on the embodiment, the integrity of the protective ring 110, the crack stopper 112 and the crack stopper 114 is not affected or only minimally affected by the connections (e.g., no holes are formed in or through the protective ring 110, the crack stopper 112 or the crack stopper 114).

[0020] The detection and monitoring circuit 126 is configured to measure a change in an electrical parameter (e.g., resistance value) of each independent boundary line 120, 122, 124, wherein the change in the electrical parameter indicates the presence of a crack at boundary line 120, 122, 124. The detection and monitoring circuit 126 can also be configured to monitor the propagation of a detected crack through the inactive area 108 of the integrated circuit 102 and warn an end user of the status and / or hazard potential of the detected crack (e.g., impending breakthrough of the crack into the active area 106 of the integrated circuit 102). For example, if a crack 130 (e.g.,If a crack (formed during the dicing of the silicon wafer containing the integrated circuit 102) propagates up to boundary line 124 and creates a break in / through it, the detection and monitoring circuit 126 can detect an increase (e.g., by orders of magnitude) in the resistance value of boundary line 124 (e.g., due to the presence of an open circuit in boundary line 124). Therefore, the detection and monitoring circuit 126 can inform an end user that a crack has occurred in / through boundary line 124 and alert them.If the crack 130 propagates beyond the crack stop 114 through the inactive area 108 of the integrated circuit 102 and creates a break in / through boundary line 122, the detection and monitoring circuit 126 can detect an increase in the resistance value of boundary line 122 and inform an end user that crack 130 is propagating. Furthermore, the detection and monitoring circuit 126 can inform the end user that the integrated circuit 102 should be replaced within an approximate time period (e.g., 12 months) to prevent failure of the integrated circuit 102.If the crack 130 propagates through and beyond the crack stop 112 and into / through boundary line 120, the detection and monitoring circuit 126 can detect an increase in the resistance value of boundary line 120 and inform the end user that a failure of the integrated circuit 102 is imminent and that the integrated circuit 102 should be replaced immediately.

[0021] As described above and in Fig. As shown in Figure 1, the crack detection and monitoring system 100 can be configured to issue early, intermediate, and final warnings of an impending crack breakthrough into the active area 106 of the integrated circuit 102. In other embodiments, the crack detection and monitoring system can be configured to provide aging information. For example, the crack detection and monitoring system 100 can be calibrated to determine an approximate time until the failure of an integrated circuit 102. For example, in a stable operating environment, the growth rate of a crack in a test IC 102 can be determined / estimated (e.g., x micrometers per year).Based on the growth rate, boundary lines 120, 122, 124 can be positioned at specific distances from the active area 106 of the integrated circuit 102, with the distances corresponding to different remaining lifetimes of the integrated circuit 102. If a crack propagates into / through a specific boundary line, the detection and monitoring circuit 126 can warn an end user that a crack has reached this boundary line and that, if conditions remain stable, the crack may reach another position on the integrated circuit 102 (e.g., the active area 106 of the integrated circuit 102) within a certain time period. Such a warning message might read, for example: "A crack has reached boundary line A, which is B micrometers away from the active area of ​​the chip. If conditions remain stable, the crack may reach another position on the integrated circuit 102 (e.g., the active area 106 of the integrated circuit 102) within approximately 100 micrometers."The active area of ​​the integrated circuit can be reached within 16 months. To avoid failure, replace the integrated circuit within 12 months.

[0022] Fig. Figure 2 shows a partial sectional view of the integrated circuit 102 in Fig. 1 along line A - A according to embodiments. The crack stoppers 112, 114 can be formed, as shown, using a plurality of layers of metal segments 140 connected to one another via a plurality of intermediate connections 142 made of metal (e.g., contact holes, contact bars, etc.) and embedded in a dielectric material 144. The metal segments 140 can be formed in metallization layers M1, M2, ..., Mn of the integrated circuit 102 (e.g., BEOL metallization layers). The crack stoppers 112, 114 can be formed similarly to those shown in Fig. 2 shown may be constructed or may include other constructions made of metal segments 140 and / or intermediate connections 142 made of metal (e.g., the number, shapes, spacings, dimensions, etc. of the metal segments 140 and intermediate connections 142 made of metal between the crack stoppers 112, 114 may vary)

[0023] Each boundary line 120, 122, 124 can enclose a plurality of layers of electrically conductive metal segments 150, which are interconnected by a plurality of electrically conductive intermediate connections 152 made of metal (e.g., contact holes, contact rods, etc.) and embedded in the dielectric material 144. The boundary lines 120, 122, 124 (and other boundary lines disclosed herein) can be formed in the same processing steps as the crack stoppers 112, 114 and can consist of any suitable metal, including, for example, copper, tungsten, aluminum, silver, gold, other metals, or their alloys. The metal segments 150 can also be formed in metallization layers M1, M2, M3, ..., Mn of the integrated circuit 102. As with the crack stoppers 112, 114, the boundary lines 120, 122, 124 may have similar or other constructions made of metal segments 150 and / or intermediate connections 152 made of metal (e.g.B. the number, shapes, spacing, dimensions, etc. of the metal segments 150 and intermediate connections 152 made of metal between the boundary lines 120, 122, 124 can vary).

[0024] According to embodiments, the boundary lines can be coupled to the detection and monitoring circuit 126 via connections that extend above (e.g., bridging connections) or below (e.g., tunnel connections) the protective ring 110, crack stop 112, and / or crack stop 114. For example, in Fig. Figures 3-5, to which reference is made, show an integrated circuit 102 which includes a system 200 for detecting and monitoring cracks with electrically conductive boundary lines 220, 222, 224 and electrically conductive bridging connections 230, 232, 234 made of metal according to embodiments. Fig. Figure 3 shows a top view of the integrated circuit 102. Fig. Figure 4 shows an enlarged partial top view of the integrated circuit in Fig. 3. Fig. Figure 5 shows a partial sectional view along the length of a boundary line (e.g., boundary line 220 in Fig. 3) Although three boundary lines 220, 222, 224 are used in this embodiment, it should be clear that the crack detection and monitoring system 200 can contain a larger or smaller number of boundary lines (e.g., one or more). Furthermore, boundary lines can be formed at other positions in the inactive region 108 of the integrated circuit 102, and / or a plurality of boundary lines can be formed adjacent to each other in the inactive region 108 of the integrated circuit 102.

[0025] Similar to the one in Fig. In the system 100 for detecting and monitoring cracks shown in Figure 1, the system 200 for detecting and monitoring cracks is designed to detect and monitor the growth of one or more cracks in the inactive region 108 of the integrated circuit 102 before cracks propagate into the active region 106 of the integrated circuit 102. In general, the system 200 for detecting and monitoring cracks can include at least one boundary line formed in the inactive region 108 of the integrated circuit 102. For example, as shown in Figure 1, the system 200 can include at least one boundary line formed in the inactive region 108 of the integrated circuit 102. Fig. Figure 3 shows that a first boundary line 220, a second boundary line 222 and a third boundary line 224 are formed in the inactive area 108 of the integrated circuit 102 and can be coupled independently to the detection and monitoring circuit via corresponding bridging connections.

[0026] The first boundary line 220 can be formed around the outer circumference of the protective ring 110, between the protective ring 110 and the crack stop 112. The second boundary line 222 can be formed around the outer circumference of the crack stop 112, between the crack stop 112 and the crack stop 114. The third boundary line 224 can be formed around the outer circumference of the crack stop 114. Opposite ends 240 of the first boundary line 220 can be connected to the detection and monitoring circuit 126 via metal bridging connections 230. The metal bridging connections 230 can extend over the protective ring 110 and be electrically insulated from it. Opposite ends 242 of the second boundary line 222 can be coupled to the detection and monitoring circuit 126 via bridging connections 232 made of metal.The metal bridging connections 232 can extend over the crack stop 112, boundary line 220, and the protective ring 110, as shown, and be electrically insulated from them. Opposite ends 244 of the third boundary line 224 can be coupled to the detection and monitoring circuit 126 via metal bridging connections 234. The metal bridging connections 234 can extend over the crack stop 114, the crack stop 112, boundary line 222, boundary line 220, and the protective ring 110, and be electrically insulated from them. Electrical insulation can be achieved, for example, by using one or more layers of a dielectric material 144 and / or the like.

[0027] A sectional view along an end section of boundary line 220 in Fig. 3 according to embodiments is in Fig. Figure 5 illustrates this. Boundary lines 222 and 224 can each be constructed similarly to or differently from boundary line 220. Boundary line 220 can, as shown, contain a plurality of electrically conductive metal sections 250, which can be linked (e.g., tacked) to one another via an alternating sequence of lower and upper electrically conductive metal connectors 252, 254. The metal connectors 252, 254 can have the same or different lengths. The lengths of the metal connectors 252, 254 can affect the crack detection accuracy of boundary line 220. For example, a larger number (e.g., higher density) of metal sections 250 can be linked together if shorter metal connectors 252, 254 are used. In general, the minimum lengths of the metal connectors 252, 254 can be determined by the processing guidelines used in the assembly of the integrated circuit 102.For example, it is possible that with the lithography tools used in the manufacture of the metal connectors 252, 254 in the respective metallization layers of the integrated circuit 102, only metal conductors of a certain minimum length can be produced in a certain dielectric layer.

[0028] According to embodiments, the lower metal connectors 252 can, for example, be formed in a lower BEOL metallization layer of the integrated circuit 102 (e.g., as shown, M1 metallization layer). The upper metal connectors 254 can be formed in an upper metallization layer of the integrated circuit 102. According to embodiments, the lengths of the metal connectors 252, 254 can, for example, be in the range of a few tens of nanometers to a few micrometers (e.g., depending on manufacturing constraints and / or other factors). As shown in Fig. As shown in Figure 5, a crack 130 propagating into / through boundary line 220 can form a fracture in / through one or more of the metal sections 250, which can be measured by the detection and monitoring circuit 126 (e.g. as an increase in the resistance value of boundary line 220).

[0029] The metal sections 250 can enclose a plurality of layers of electrically conductive metal segments 260, which are interconnected by means of a plurality of electrically conductive metal intermediate connections 262 (e.g., contact holes, contact rods, etc.) and embedded in a dielectric material 144. The metal segments 262 can be formed in metallization layers of the integrated circuit 102 (e.g., as shown, metallization layers M2-M5). One or more metal intermediate connections 262 can also be used to couple the metal sections 250 to respective lower and upper metal connectors 252, 254. The upper metal connector 254, located at one end 240 of boundary line 220, can be coupled to a metal bridging connection 230 via a metal intermediate connection 262.

[0030] According to embodiments, as described above, boundary lines can be coupled to the detection and monitoring circuit 126 via connections that extend above (e.g., bridging connections) or below (e.g., tunnel connections) the protective ring 110, crack stop 112, and / or crack stop 114. An integrated circuit 102, which includes a crack detection and monitoring system 300 containing tunnel connections according to embodiments, is shown in Fig. Figures 6-9 are shown, which are also referenced. For example, it shows Fig. 6 a top view of an integrated circuit 102 which includes a plurality of independent and electrically conductive boundary lines 320, 322, 324 and electrically conductive tunnel connections 330, 332, 334. Fig. Figure 7 shows an enlarged partial top view of the integrated circuit 102 in Fig. 6. Fig. Figure 8 shows a partial sectional view along a length of a boundary line (e.g. boundary line 320) in Fig. 6. Fig. Figure 9 shows a partial sectional view of system 300 for detecting and monitoring cracks along line B - B in Fig. 6. Although three boundary lines 320, 322, 324 are used in this embodiment, it should be clear that the crack detection and monitoring system 300 can include a larger or smaller number of boundary lines (e.g., one or more). Furthermore, boundary lines can be formed at other positions in the inactive region 108 of the integrated circuit 102, and / or a plurality of boundary lines can be formed adjacent to each other in the inactive region 108 of the integrated circuit 102.

[0031] Similar to the ones in Fig. 1 and Fig. In the three depicted systems 100 and 200 for detecting and monitoring cracks, system 300 for detecting and monitoring cracks is designed to detect and monitor the growth of cracks in the inactive region 108 of the integrated circuit 102 before cracks propagate into the active region 106 of the integrated circuit 102. In general, system 300 for detecting and monitoring cracks can include at least one boundary line formed in the inactive region 108 of the integrated circuit 102. For example, as shown in Fig. Figure 6 shows that a first boundary line 320, a second boundary line 322 and a third boundary line 324 are formed in the inactive area 108 of the integrated circuit 102.

[0032] Boundary line 320 can be formed around the outer circumference of the protective ring 110 between the protective ring 110 and the crack stop 112. The second boundary line 322 can be formed around the outer circumference of the crack stop 112 between the crack stop 112 and the crack stop 114. The third boundary line 324 can be formed around the outer circumference of the crack stop 114.

[0033] Opposite ends 340 of the first boundary line 320 can be coupled to the detection and monitoring circuit 126 via electrically conductive semiconductor tunnel connections 330. The tunnel connections 330 can extend under the protective ring 110 and be electrically isolated from it. Opposite ends 342 of the second boundary line 322 can be coupled to the detection and monitoring circuit 126 via semiconductor tunnel connections 332. The tunnel connections 332 can extend under the crack stop 112 and the protective ring 110, as shown, and be electrically isolated from them. Opposite ends 344 of the third boundary line 324 can be coupled to the detection and monitoring circuit 126 via semiconductor tunnel connections 334. The tunnel connections 334 can extend under the crack stop 114, the crack stop 112 and the protective ring 110 and be electrically insulated from them.According to embodiments, the tunnel connections 344 can also be electrically isolated from the boundary lines 320, 322, and the tunnel connections 342 can also be electrically isolated from boundary line 320. The tunnel connections 340, 342, 344 can be formed, as described below, using doped regions of the substrate 104 of the integrated circuit 102.

[0034] A sectional view along an end section of boundary line 320 in Fig. 6 according to embodiments is in Fig. Figure 8 illustrates this. Boundary lines 322 and 324 can each be constructed similarly to or differently from boundary line 320. Boundary line 320 can, as shown, contain a plurality of electrically conductive metal sections 350, which can be linked together by an alternating sequence of electrically conductive lower metal connectors 352 (only one shown) and electrically conductive upper metal connectors 354. The metal connectors 352, 354 can have the same or different lengths. The lengths of the metal connectors 352, 354 can affect the crack detection accuracy of boundary line 320. For example, a larger number (e.g., higher density) of metal sections 350 can be linked together if shorter metal connectors 352, 354 are used.In general, the minimum lengths of the metal connectors 352, 354 can be determined by the processing guidelines used in forming the integrated circuit 102. For example, it is possible that the lithography tools used to fabricate the metal connectors 352, 354 in the respective metallization layers of the integrated circuit 102 can only produce metal conductors of a certain minimum length in a specific dielectric layer. According to embodiments, the lower metal connectors 352 can, for example, be formed in a lower BEOL metallization layer of the integrated circuit 102 (e.g., as shown, M1 metallization layer). The upper metal connectors 354 can be formed in an upper metallization layer of the integrated circuit 102.According to embodiments, the lengths of the metal connectors 352, 354 can, for example, be in the range of a few tens of nanometers to a few micrometers (e.g. depending on manufacturing constraints and / or other factors).

[0035] The metal sections 350 can enclose a plurality of layers of electrically conductive metal segments 360, which are interconnected by a plurality of electrically conductive metal intermediate connections 362 (e.g., contact holes, contact rods, etc.) and embedded in a dielectric material 144. The metal segments 362 can be formed in metallization layers of the integrated circuit 102 (e.g., as shown, BEOL metallization layers M1-M5). One or more metal intermediate connections 362 can also be used to couple adjacent metal sections 350 to respective upper metal connectors 352. The lowest metal segment 360 (e.g., M1 metallization layer) of at least one of the metal sections 350 can be coupled to a doped region 356 of the semiconductor substrate 104 via at least one metal intermediate connection 362 and one doped semiconductor intermediate connection 364.

[0036] The doped semiconductor region 356 can, as in Fig. Figure 8 shows a doped section 358 of the semiconductor substrate 104 of the integrated circuit 102. At least one intermediate connection 364 made of doped semiconductor can be formed over the doped semiconductor area 356 to couple a metal section 350, located at one end 340 of boundary line 320, to a tunnel connection 330, which in the present embodiment is formed by a doped semiconductor well formed in the doped section 358 of the semiconductor substrate 104. The metal section 350 can be coupled to the intermediate connection 364 made of doped semiconductor by means of one or more intermediate connections 362 made of metal. The doping of the semiconductor area 356, the intermediate connection 364 made of semiconductor material, and the tunnel connection 330 allows the passage of an electrical signal when measuring the electrical parameter (e.g.,of the resistance value) of boundary line 320. The semiconductor area 356 and the intermediate connection 364 made of semiconductor material can be, as in . Fig. 8 shown, n + -doped, or in other embodiments p + -doped. Doping can be carried out, for example, using ion implantation or any other suitable method.

[0037] When using a n + -doped semiconductor area 356 (with an intermediate 364 made of n + -doped semiconductor) can, as in Fig. 8 shown, the n + A -doped semiconductor region 356 is formed in a p-doped region 358 of the semiconductor substrate 104 of the integrated circuit 102. This doping method, as further explained in Fig. 8 shown, the n +-doped semiconductor area 356, which is located adjacent to an end 340 of boundary line 320, is coupled to the detection and monitoring circuit 126 via a tunnel connection 330, which is formed using an n-doped semiconductor well (n-doped well) formed in the p-doped area 358 of the semiconductor substrate 104 of the integrated circuit 102.

[0038] According to other embodiments, a p + -doped semiconductor region and an intermediate connection made of p + -doped semiconductor instead of the n + -doped semiconductor area 356 and the intermediate 364 made of n + -doped semiconductors are used. The p + -doped semiconductor region can be in an n + -doped region of the semiconductor substrate 104 of the integrated circuit 102 can be formed. In addition, the p +-doped semiconductor area, which is located adjacent to the end 340 of boundary line 320, is coupled to the detection and monitoring circuit 126 via a tunnel connection 330 of a p-doped semiconductor well, which is formed in the n-doped area of ​​the substrate 104 of the integrated circuit 102.

[0039] Fig. Figure 9 shows a partial sectional view of the integrated circuit 102 along line B - B in Fig. 6 according to embodiments. A tunnel connection 332 is formed from an n-doped semiconductor well (hereinafter n-doped tunnel connection 332) in the p-doped region 358 of the substrate 104 of the integrated circuit 102 in order to connect the n + The -doped semiconductor area 356 adjacent to an end 342 of boundary line 322 is to be coupled to the detection and monitoring circuit 126 via an I / O connection 370. Boundary line 322 can be connected via at least one intermediate connection 364 consisting of n +-doped semiconductor with the n + -doped semiconductor area 356 must be coupled. At least one intermediate connection 364 made of n + -doped semiconductor can also be used to couple the n-doped tunnel junction 332 with the I / O junction 370.

[0040] The crack stopper 114 can be positioned above the p-doped region 358 of the semiconductor substrate 104. The crack stopper 114 can be connected via at least one intermediate connection 364 made of n + -doped semiconductor coupled to the p-doped semiconductor region 358. A bias voltage applied to the p-doped region 358 can serve to couple the pn junction(s) that connects the p-doped region 358 to the at least one intermediate connection 364 made of n + -doped semiconductor is / are formed, to be biased in the blocking direction in order to electrically isolate the crack stopper 114 from the p-doped region 358.

[0041] The n-doped tunnel connection 332 runs below the crack stop 112 and the protective ring 110 and is electrically insulated from them. The crack stop 112 can be constructed using at least one intermediate connection 366 made of p + The -doped semiconductor can be coupled to the n-doped tunnel junction 332. Likewise, the guard ring 110 can be coupled using at least one intermediate junction 366 made of p + The -doped semiconductor is coupled to the n-doped tunnel junction 332. The reverse-biased pn junctions between the semiconductor intermediate junction(s) 366 are made of p + The crack stopper 112 and the protective ring 110 electrically isolate the crack stopper 112 and the protective ring 110 from the n-doped tunnel connection 332, formed by the -doped semiconductor and the n-doped tunnel connection 332.

[0042] According to other embodiments, in each of the crack detection and monitoring systems described herein, both types of connection structures can be used to electrically connect boundary lines to the detection and monitoring circuit 126. For example, a first boundary line in a crack detection and monitoring system can be electrically connected to the detection and monitoring circuit 126 using metal bridging connectors, a second boundary line in the same crack detection and monitoring system can be electrically connected to the detection and monitoring circuit 126 using doped semiconductor tunnel connectors, while a third boundary line in the same crack detection and monitoring system can be connected using both bridging and tunnel connectors.

[0043] Each of the boundary lines described here can be designed such that a crack propagating through the inactive region 108 of an integrated circuit 102 is guided and fixed. A sectional view of a boundary line 400 according to embodiments for guiding and fixing a crack is shown, for example, in Fig. Figure 10 shows the boundary line 400 containing, as shown, a first and a second electrically conductive metal section 402, 404, which are connected to each other. The metal sections 404 can include a plurality of layers of electrically conductive metal segments 406, which are connected to each other by means of an arrangement of electrically conductive intermediate connections 408 made of high-density metal (e.g., contact holes, contact rods, etc.) and are embedded in a dielectric material 144. The metal sections 402 can also include a plurality of layers of electrically conductive metal segments 406, which are connected to each other by means of an arrangement of intermediate connections 408 made of high-density metal and are embedded in a dielectric material 144.Furthermore, a plurality (in the present example, 2) of the metal segments 406 in the metal section 402 can be interconnected by means of an arrangement of electrically conductive metal intermediate connections 410 (e.g., contact holes, contact rods, etc.) of low density. The metal intermediate connections 410 form a weakened region 412 in the metal section 402, which effectively attracts a crack propagating towards the boundary line 400. An elongated metal segment 406' in the metal section 402 can also be coupled to an elongated metal segment 406' in the metal section 404 via a metal intermediate connection 410. The metal section 404 can furthermore include a fixation region 414, which has been reinforced to fix / slow down a crack after it has propagated through the weakened region 412 in the metal section 402.The fixing area 414 can be reinforced, for example, by providing a group of larger / stronger metal intermediate connections 416 (e.g. wider / thicker than the metal intermediate connection 408) and / or by embedding the set of metal intermediate connections 416 (or even the entire metal section 404) in a stronger dielectric material 418 that is less prone to cracking (e.g. compared to the dielectric material 144).

[0044] According to embodiments, the arrangement of high-density metal intermediates 408 and the arrangement of low-density metal intermediates 410 can be provided in various ways. For example, the metal intermediates 408 and 410 can be arranged in the same pattern, but the metal intermediates 408 can be thicker than the metal intermediates 410. In another example, the metal intermediates 408 and 410 can have the same thickness, but the metal intermediates 408 can be arranged closer together than the metal intermediates 410.

[0045] Fig. 11A, Fig. 11B and Fig. 11C provides an example of the function for guiding and fixing cracks from boundary line 400 in Fig. 10 according to embodiments. In Fig. 11A A crack 130, propagating through the inactive region 108 of an integrated circuit, is attracted towards the weakened region 412 formed by the metal intermediate connections 410 in the metal section 402. Fig. 11B the crack 130 extends through the arrangement of low-density metal intermediate connections 410 in the metal section 402 towards the fixing area 414. Fig. In 11C, the crack is fixed / slowed down by the metal intermediate connections 416 in the fixing area 414, and its energy is distributed. The fracture in the metal section 402 leads to an increase in the resistance value of boundary line 400, which is measured by the detection and monitoring circuit 126. If no fixing area 414 is used, the crack 130 can be fixed / slowed down by the arrangement of the metal intermediate connections 408 in the metal section 404.

[0046] In Fig. Figure 12 shows a flowchart of a method for detecting and monitoring cracks in an integrated circuit according to embodiments. In process A1, an electrical parameter (e.g., resistance value) of a plurality of boundary lines positioned in an inactive region of an integrated circuit is monitored (continuously or periodically) by a detection and monitoring circuit. If the detection and monitoring circuit measures a change in the electrical parameter of a boundary line that indicates that a crack has propagated into / through the boundary line (YES in process A2), the process proceeds to process A3. Otherwise (NO in process A2), the process returns to process A1.

[0047] In process A3, the detection and monitoring circuit sends a warning message (e.g., email, text message, system message, and / or similar) to an end user indicating that a crack has broken through the boundary line. The type of warning message can depend, for example, on the position of the boundary line within the inactive area of ​​the integrated circuit (e.g., the closer the boundary line is to the active area of ​​the integrated circuit, the more urgent the warning message). The process then returns to process A1.

[0048] Fig. Figure 13 shows a top view of an integrated circuit 102, which includes a crack detection and monitoring system 500 according to other embodiments. Similar to crack detection and monitoring systems 100, 200, and 300, crack detection and monitoring system 500 can include an electrically conductive boundary line 502 formed around an outer circumference of the crack stop 114, and an electrically conductive boundary line 504 formed around an outer circumference of the crack stop 112 between the crack stop 112 and the crack stop 114. Unlike systems 100, 200, and 300 for detecting and monitoring cracks, system 500 for detecting and monitoring cracks can contain a plurality (e.g., > 2) of adjacent, electrically conductive boundary lines formed around an outer circumference of the crack stop 110 between the crack stop 110 and the crack stop 112. For example, as in Fig. As shown in Figure 13, five boundary lines 506, 508, 510, 512, 514 are present between the crack stop 110 and the crack stop 112. Each boundary line 502, 504, 506, 508, 510, 512, 514 can be interrupted (or continuous) as described above and can be coupled to the detection and monitoring circuit 126 via appropriate bridging or tunnel connections.

[0049] The detection and monitoring circuit 126 can be configured to issue a first type of warning message when a crack propagates into / through the boundary lines 502, 504, and a second type of warning message when a crack propagates into / through the boundary lines 506, 508, 510, 512, 514. For example, the detection and monitoring circuit 126 can be configured to issue initial warning messages to an end user when a crack propagates into / through the boundary lines 502, 504. These warning messages could be, for example, "A crack breakthrough has occurred in the integrated circuit" and "A crack is propagating further into the interior of the integrated circuit."

[0050] The crack detection and monitoring system 500 can further be configured to provide aging information regarding the expected remaining lifetime (e.g., approximate operating time until failure) of the integrated circuit 102 when a crack propagates into / through the boundary lines 506, 508, 510, 512, 514. To ensure this functionality, the crack growth rate in a test IC 102 can be determined. Based on the growth rate, the boundary lines 506, 508, 510, 512, 514 can be positioned at specific distances from the active area 106 of an integrated circuit 102, with each distance representing a different remaining lifetime of the integrated circuit 102.If a crack propagates into / through a specific boundary line, the detection and monitoring circuit 126 can warn an end user that a crack has reached this boundary line and that, if conditions remain unchanged, the crack may reach the active area of ​​the integrated circuit 102 in a certain number of days / months / years (e.g., in 18 months). Warning messages might include, for example: "A crack is approaching the active area of ​​the integrated circuit." or "The integrated circuit is expected to fail in approximately 18 months."“If a crack propagates into / through a certain boundary line that is closer to the active area 106 of the integrated circuit 102, the detection and monitoring circuit 126 can warn an end user that a crack has reached this boundary line and that, if conditions remain unchanged, the crack may reach the active area 106 of the integrated circuit 102 in a certain number of days / months / years (e.g., in 12 months).

[0051] According to embodiments, the detection and monitoring circuit can include at least one measuring circuit for detecting and monitoring a resistance value of at least one boundary line. The detection and monitoring circuit can, for example, include a serial (cascade) arrangement of several stages of measuring circuits, each measuring circuit being configured to measure the resistance value of a corresponding boundary line. An activation signal generated by a measuring circuit serves to activate the next measuring circuit in the plurality of stages of measuring circuits when a crack propagates through the integrated circuit.

[0052] Fig. Figure 14 represents a detection and monitoring circuit 602 according to embodiments, which can be used in a system 600 for detecting and monitoring cracks, which includes a plurality of boundary lines (e.g., boundary line 604, boundary line 606, boundary line 608), wherein boundary line 608 is closer to the active area 106 of the integrated circuit 102 than boundary line 606, and boundary line 606 is closer to the active area 106 than boundary line 604. The crack detection and monitoring circuit 602 can be, as shown in Fig. Figure 14 shows a plurality of N (N = 3 in this example) stages of cascaded measuring circuits. For example, the sensing and monitoring circuit 602 can include a first-stage measuring circuit 610 for measuring the resistance value R. PL0 from boundary line 604, a second-stage measuring circuit 612 for measuring the resistance value R PL1from boundary line 606 and a third-stage measuring circuit 614 for measuring the resistance value R PL2 including boundary line 608. The measuring circuits 610, 612, 614 can be arranged in series (e.g., in a cascade) such that measuring circuit 612 is only activated after measuring circuit 610 has detected a crack on boundary line 604. Likewise, measuring circuit 614 is only activated after measuring circuit 612 has detected a crack on boundary line 606. Fig. 15, which coincide with Fig. Reference is made to Figure 14, which shows a circuit diagram 700 of the detection and monitoring circuit 602, which includes a cascade arrangement of measuring circuits 610, 612, 614 according to embodiments.

[0053] Circuit 700 is designed to output a variety of different flags during operation, indicating the presence and growth of a crack 130 towards the active area 106 of the integrated circuit 102. That is, each of the cascaded measuring circuits 610, 612, 614 is designed to set a corresponding flag when the crack 130 propagates closer to the active area 106 of the integrated circuit 102. Based on these flags, appropriate warning messages can be issued to an end user of the integrated circuit 102.

[0054] The measuring circuit 610 of the first stage receives an input voltage VIN0, which is generated by a voltage divider of the first stage 702. Likewise, the measuring circuit 612 of the second stage receives an input voltage VIN1 generated by a voltage divider 704 of the second stage, while the measuring circuit 614 of the third stage receives an input voltage VIN2 generated by a voltage divider 706 of the third stage.

[0055] The voltage divider 702 of the first stage is connected by a reference resistor R0 and a resistor R PL0 formed, which represents the resistance value of boundary line 604. According to embodiments, boundary line 604 in an intact state can have a resistance value R PL0 The resistance is approximately 10 kΩ, and in the case of damage from a crack, it can exceed 1 MΩ. The resistance R0 can have a value much larger than the resistance R. PL0of boundary line 604 in an intact state. Resistor R0 can, for example, have a resistance value of approximately 100 kΩ. VIN0 is the voltage at a node 708 of the voltage divider 702 between resistor R0 and resistor R PL0 .

[0056] The drain of an n-type field-effect transistor (NFET) N0 is coupled to node 708. One source of the n-type field-effect transistor N0 is coupled to a ground voltage VSS (e.g., 0 V). The drain of a p-type field-effect transistor (PFET) P0 is coupled to R0, with one source of the p-type field-effect transistor P0 being coupled to a supply voltage VDD (e.g., 1 V).

[0057] The first-stage measuring circuit 610 can be selectively activated by an activation signal ENN. The activation signal ENN is also applied to the gates of the n-type field-effect transistor N0 and the p-type field-effect transistor P0 of the first-stage voltage divider 702. When the activation signal ENN = 1 V (e.g., VDD), the first-stage measuring circuit 610 is deactivated, and no current (only nA leakage currents) is consumed by it. Furthermore, when the activation signal ENN = 1 V, the p-type field-effect transistor P0 is switched off and the n-type field-effect transistor N0 is switched on, pulling the voltage VIN0 at node 708 to ground (e.g., VIN0 = 0 V). Therefore, if ENN = 1V, no current is consumed by the measuring circuit 610 of the first stage and no direct current flows through the voltage divider 702 of the first stage.

[0058] Each measuring circuit 610, 612, 614 receives a reference voltage VREF. VREF can be provided using a bandgap voltage reference circuit or in any other suitable way by a voltage divider 720, as shown in Fig. Figure 15 shows a circuit consisting of two resistors RR0 and RR1. The voltage divider 720 is designed such that, assuming RR0 = RR1, it outputs a reference voltage VREF = VDD / 2 (e.g., VREF = ~0.5 V).

[0059] When ENN = 0, the first-stage measuring circuit 602 is activated, the n-type field-effect transistor N0 is off, and the p-type field-effect transistor P0 is on. The first-stage measuring circuit 610 is configured to compare the voltages VIN0 and VREF when activated (e.g., ENN = 0 V) ​​and generate an activation signal CRACKN_S0, which is provided to the second-stage voltage divider 704 and the second-stage measuring circuit 612. The first-stage measuring circuit 610 can also generate a flag F0 indicating the state of boundary line 604.

[0060] In its intact state, boundary line 604 can represent an equivalent resistance R. PL0 of 10 kΩ. Therefore, when ENN = 0 V (enables the measuring circuit 610 of the first stage), the voltage divider 702 of the first stage outputs the following voltage VIN0 at node 708: VDD*(RPL0 / (RPL0+R0))=VDD*(10k / (10k+100k))=∼0.009*VDD=∼0V.

[0061] In response, since VIN0 is smaller than the reference voltage VREF, the first-stage measuring circuit 610 sets CRACKN_S0 = 1V, thereby deactivating the second-stage measuring circuit 612, and sets F0 = 0V, thus indicating that boundary line 604 is intact.

[0062] If boundary line 604 has been damaged by a crack, its resistance value R may change. PL0 increase by several orders of magnitude (e.g., from 10 kΩ to > 1 MΩ). In this situation, the voltage divider 702 of the first stage outputs the following voltage VIN0 at node 708: VDD*(RPL0 / (RPL0+R0))=VDD*(1M / (1M+100k))=∼0.9*VDD=∼VDD.

[0063] In response, since VIN0 is now greater than the reference voltage VREF, the first-stage measuring circuit 610 sets CRACKN_S0 = 0V, thereby activating the second-stage measuring circuit 612, and sets F0 = 1V, indicating that boundary line 604 has been damaged. According to embodiments, the flag F0 is the reciprocal of the activation signal CRACKN_S0.

[0064] The voltage divider 704 of the second stage is connected by a reference resistor R1 and a resistor R PL1 formed, which represents the resistance value of boundary line 606. The voltage divider 706 of the third stage connects a reference resistor R2 and a resistor R. PL2 one that represents the resistance value of boundary line 608. Boundary lines 606 and 608, when intact, can have a resistance value R PL1 or R PL2The resistance may be approximately 10 kΩ if damaged by a crack exceeding 1 MΩ. Resistors R1 and R2 can have a resistance value of approximately 100 kΩ. VIN1 is the voltage at node 710 of the second-stage voltage divider 704. VIN2 is the voltage at node 712 of the third-stage voltage divider 706.

[0065] In the voltage divider 704 of the second stage, the drain and source of an n-type field-effect transistor N1 are coupled to node 710 and to ground, respectively. The drain and source of a p-type field-effect transistor P1 are coupled to resistor R1 and VDD, respectively.

[0066] The second-stage measuring circuit 612 can be selectively activated by the activation signal CRACKN_S0 generated by the first-stage measuring circuit 612. The activation signal CRACKN_S0 is also applied to the gates of n-type field-effect transistor N1 and p-type field-effect transistor P1 of the second-stage voltage divider 704. When the activation signal CRACKN_S0 = 1V (indicating that boundary line 604 is intact), the second-stage measuring circuit 612 is deactivated and consumes no current. Furthermore, when the activation signal CRACKN_S0 = 1V, p-type field-effect transistor P1 is switched off and n-type field-effect transistor N1 is switched on, pulling the voltage VIN1 at node 710 to ground (e.g., VIN1 = 0V).

[0067] When the activation signal CRACKN_S0 = 0 V (indicating that boundary line 604 has been damaged), the second-stage measuring circuit 612 is activated, n-type field-effect transistor N1 is switched off, and p-type field-effect transistor P1 is switched on. The second-stage measuring circuit 612 is configured to compare the voltages VIN1 and VREF when activated (e.g., CRACKN_0 = 0 V) ​​and generate an activation signal CRACKN_S1 for the third-stage measuring circuit 614. The second-stage measuring circuit 612 can also generate a flag F1 (e.g., the reciprocal of CRACKN_S1) indicating the state of boundary line 606.

[0068] In its intact state, boundary line 606 can represent an equivalent resistance R. PL1 exhibiting a resistance of 10 kΩ. In this case, when CRACKN_S0 = 0V, the voltage divider 704 of the second stage outputs the following voltage VIN1 at node 710: VDD*(RPL0 / (RPL0+R0))=VDD*(10k / (10k+100k))=∼0.009*VDD=∼0V.

[0069] In response, since VIN1 is smaller than the reference voltage VREF, the second-stage measuring circuit 612 sets CRACKN_S1 = 1V, thereby deactivating the third-stage measuring circuit 614, and sets F1 = 0V, thus indicating that boundary line 606 is intact.

[0070] If boundary line 606 has been damaged by a crack, its resistance value R increases. PL1 by several orders of magnitude (e.g., from 10 kΩ to > 1 MΩ). Therefore, the voltage divider 704 of the second stage outputs the following voltage VIN1 at node 710: VDD*(RPL0 / (RPL0+R0))=VDD*(1M / (1M+100k))=∼0.9*VDD=∼VDD.

[0071] In response, since VIN1 is now greater than the reference voltage VREF, the second-stage measuring circuit 612 sets CRACKN_S1 = 0V, thereby activating the third-stage measuring circuit 614, and sets F1 = 1V, indicating that boundary line 606 has been damaged.

[0072] In the voltage divider 706 of the third stage, the drain and source of an n-type field-effect transistor N2 are coupled to node 712 and to ground, respectively. The drain and source of a p-type field-effect transistor P2 are coupled to resistor R2 and VDD, respectively.

[0073] The third-stage measuring circuit 614 can be selectively activated by the activation signal CRACKN_S1 generated by the second-stage measuring circuit 614. The activation signal CRACKN_S1 can also be applied to the gates of n-type field-effect transistor N2 and p-type field-effect transistor P2 of the third-stage voltage divider 706. When the activation signal CRACKN_S1 = 1V (indicating that boundary line 606 is intact), the third-stage measuring circuit 614 is deactivated and consumes no current, p-type field-effect transistor P2 is switched off, and n-type field-effect transistor N2 is switched on, thereby pulling the voltage VIN2 at node 712 to ground (e.g., VIN2 = 0V).

[0074] When the activation signal CRACKN_S1 = 0 V (indicating that boundary line 606 has been damaged), the third-stage measuring circuit 613 is activated, n-type field-effect transistor N2 is switched off, and p-type field-effect transistor P2 is switched on. The third-stage measuring circuit 614 compares the voltages VIN2 and VREF and generates an activation signal CRACKN_S2 as well as a flag F2 (e.g., the reciprocal of CRACKN_S2) indicating the state of boundary line 608. Since the third-stage measuring circuit 614 is the last of the cascaded measuring circuits in the described embodiment, the activation signal CRACKN_S2 is not used to activate a subsequent measuring circuit.

[0075] In its intact state, boundary line 608 can represent an equivalent resistance R. PL2 of 10 kΩ. In this case, if CRACKN_S1 = 0V, the voltage divider 706 of the third stage outputs the following voltage VIN2 at node 712: VDD*(RPL0 / (RPL0+R0))=VDD*(10k / (10k+100k))=∼0.009*VDD=∼0V.

[0076] Since VIN2 is smaller than the reference voltage VREF, the third-stage measuring circuit 614 sets CRACKN_S2 = 1V and sets F2 = 0V, thus indicating that boundary line 608 is intact.

[0077] If boundary line 608 has been damaged by a crack, its resistance value R increases. PL2 by several orders of magnitude (e.g., from 10 kΩ to > 1 MΩ). Therefore, the voltage divider 706 of the third stage outputs the following voltage VIN2 at node 712: VDD*(RPL0 / (RPL0+R0))=VDD*(1M / (1M+100k))=∼0.9*VDD=∼VDD.

[0078] In response, since VIN2 is now greater than the reference voltage VREF, the third-stage measuring circuit 614 sets CRACKN_S2 = 0V and sets F2 = 1V, indicating that boundary line 608 has been damaged.

[0079] Fig. Figure 16 shows a more detailed circuit diagram 800 of the detection and monitoring circuit 602, which includes a cascade arrangement of measuring circuits 610, 612, 614 according to embodiments. In the measuring circuit 6 of the first stage, as shown in Fig. Figure 16 shows the activation signal ENN coupled to the gate of a p-type field-effect transistor T1. The source of p-type field-effect transistor T1 is coupled to VDD, and the drain of p-type field-effect transistor T1 is coupled to the source terminals of a p-type field-effect transistor T2 and a p-type field-effect transistor T3.

[0080] The input voltage VIN0 at node 708 of the voltage divider 702 of the first stage is coupled to the gate of an n-type field-effect transistor T4. The source of n-type field-effect transistor T4 is coupled to ground, and the drain of n-type field-effect transistor T4 is coupled to the drain of p-type field-effect transistor T2 as well as the gate terminals of p-type field-effect transistors T2 and T3. The drain of p-type field-effect transistor T3 and the drain of n-type field-effect transistor T5 are connected at node 802. The gate of n-type field-effect transistor T5 is coupled to the reference voltage VREF.

[0081] The activation signal ENN activates the measuring circuit 610 when ENN = 0 V, thereby switching on the p-type field-effect transistor T1. When ENN = 1 V (e.g., VDD), the p-type field-effect transistor T1 is switched off and the measuring circuit 610 is deactivated. Additionally, when ENN = 1 V, the reference voltage VREF, which has a value of ~VDD / 2, switches on the n-type field-effect transistor T5 and pulls the voltage OUT0 at node 802 to ground (0 V).

[0082] The voltage OUT0 at node 802 is passed through a first inverter 804 to generate the activation signal CRACKN_S0, which is then passed to the voltage divider 704 of the second stage and the measuring circuit 612 of the second stage. The activation signal CRACKN_S0 is also passed through a second inverter 806 to generate the flag F0. When ENN = 1V, OUT0 = 0V, CRACKN_S0 = 1V, and F0 = 0V.

[0083] An activation signal ENN = 0V activates both the first-stage measuring circuit 610 and the first-stage voltage divider 702, which outputs an input voltage VIN0 at node 708. The n-type field-effect transistor T4 is gate-controlled by the input voltage VIN0, which is either ~0V or VDD depending on the integrity (intact or broken) of boundary line 604. The measuring circuit 610 is configured to compare the current through n-type field-effect transistor T5 due to the reference voltage VREF with the current through n-type field-effect transistor T4 due to the input voltage VIN0. If ENN = 0V and boundary line 604 is completely intact (no damage), then VIN0 = 0V, OUT0 = 0V, CRACKN_S0 = 1V, and F0 = 0V. If ENN = 0V and boundary line 604 is damaged, then VIN0 = ~VDD (1V), CRACKN_S0 = 0V, and F0 = 1V. In this situation, the activation signal CRACKN_S0 = 0V activates the measuring circuit 612 of the next (second) stage.The measuring circuits 612, 614 of the second and third stage operate similarly to the measuring circuit 610 of the first stage, based on the value of their respective activation signals CRACKN_S0, CRACKN_S1.

[0084] The measuring circuit 610 consumes no current when the boundary line 604 is intact (undamaged). In this case, VIN0 = ~0V, which switches off the n-type field-effect transistor T4 and makes the MID0 voltage floating. Since the reference voltage (or, depending on the implementation, another reference voltage) is VREF = VDD / 2, the voltage OUT0 is safely pulled to 0V, providing a known output for subsequent circuits. The measuring circuit 604 only consumes current if the boundary line 604 is damaged (e.g., when ENN = 0V and VIN0 = 1V).

[0085] Embodiments of the disclosure can offer various technical and economic advantages, some of which are explained here by way of example. The crack detection and monitoring systems disclosed herein are designed to detect the presence of a crack in an inactive region of an integrated circuit and to warn an end user of the presence of the crack and its propagation toward the active region of the integrated circuit. Furthermore, the crack detection and monitoring systems disclosed herein are designed to warn an end user of an impending catastrophic failure before an actual catastrophic failure occurs, in which a crack propagates into the active region of the integrated circuit. This enables an end user to replace an integrated circuit before it fails due to crack propagation.The systems for detecting and monitoring cracks can be set up and calibrated to provide an approximate timeframe until the imminent failure of an integrated circuit.

[0086] The crack detection and monitoring systems disclosed herein may include bridging or tunneling connections with a detection and monitoring circuit that bypass and traverse one or more crack stoppers and / or one or more guide rails either over the top-of-line layers (BEOL) or over buried semiconductor wells in a semiconductor substrate of an integrated circuit. The crack detection and monitoring systems disclosed herein may also include intentionally created weak points that direct crack propagation to desired locations where a crack is fixed and its energy is dispersed.

[0087] The crack detection and monitoring systems disclosed here can include a multi-stage, serially connected (e.g., cascaded) arrangement of measuring circuits for monitoring structures (e.g., boundary lines) on an integrated circuit. Advantageously, a measuring circuit for stage N+1 is only activated when the measuring circuit for an upstream stage N has detected damage to its respective structure, and only then does it consume power.

[0088] The terminology used here serves only to describe certain embodiments and is not intended to limit the disclosure. The singular forms "a" and "the" are used here to include the plural forms unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "comprises" and / or "comprehensive" used in this description indicate the presence of the listed features, integers, steps, processes, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.“Optional” or “choice” means that the process or circumstance described below may or may not occur, and that the description includes cases in which the process occurs as well as cases in which it does not.

[0089] Approximation-designating phrases, as used throughout the description and in the claims, can serve to modify any quantitative representations where deviations are permissible without altering the fundamental function to which they refer. Accordingly, a value modified by one or more terms such as "approximately," "approximately," and "essentially" is not limited to the specified specific value. In at least some cases, the approximation-designating phrases may correspond to the accuracy of a measuring instrument used to measure the value. In the present case, and throughout the description and claims, limitations of ranges may be combined and / or interchanged, provided that these ranges are defined and include all sub-ranges contained therein, unless otherwise clearly indicated by the context and the wording.When “approximately” is applied to a specific value within a range, it applies to both values ​​and, unless otherwise dependent on the accuracy of the instrument used to measure the value, may indicate + / - 10% of the stated value(s).

[0090] The corresponding structures, materials, processes, and equivalents of all means or steps and functions of the elements in the following claims are intended to include any structure, material, or action for performing the function in combination with other claimed elements as specifically claimed. The description of this disclosure serves for illustration and description purposes but is not to be understood as exhaustive or limited to the disclosure as disclosed. Variations and modifications will be apparent to the person skilled in the art, but these do not represent a departure from the scope and spirit of the disclosure. The embodiment has been chosen and described to best explain the principles of the disclosure and its practical application, and to enable other persons skilled in the art to understand the disclosure for various embodiments with different modifications suitable for specific applications.

Claims

[1] System (100) for detecting and monitoring cracks (130), comprising: a plurality of electrically conductive structures (604, 606, 608) extending around a protective barrier (110) formed in an inactive region (108) of an integrated circuit (102), wherein an active region (106) of the integrated circuit (102) is enclosed within the protective barrier (110); and a plurality of stages of measuring circuits (610, 612, 614) connected in series and measuring a change in an electrical characteristic (RPL0, RPL1, RPL2) of each of the plurality of structures (604, 606, 608) and receiving an activation signal (ENN; CRACKN_S0, CRACKN_S1, CRACKN_S2), wherein each measuring circuit (610, 612, 614) is coupled to a respective structure (604, 606, 608) of the plurality of structures (604, 606, 608) and the change in the electrical characteristic (RPL0, RPL1, RPL2) indicates damage to the respective structure (604, 606, 608), wherein each measuring circuit (610, 612, 614) includes a circuit for selectively generating the activation signal (CRACKN_S0, CRACKN_S1) for a next measuring circuit (612, 614) of the plurality of stages of measuring circuits (610, 612, 614). [2] System (100) according to claim 1, wherein the plurality of structures (604, 606, 608) comprises a plurality of electrically conductive boundary lines, and the change in the electrical parameter (RPL0, RPL1, RPL2) indicates the presence of a crack (130) in the structure (604, 606, 608). [3] System (100) according to claim 1, wherein the electrical characteristic (RPL0, RPL1, RPL2) comprises an electrical resistance value of the structure (604, 606, 608). [4] System (100) according to claim 3, wherein the measuring circuit (610, 612, 614) of each stage of the plurality of stages of measuring circuits (610, 612, 614) further comprises: a voltage divider circuit (702, 704, 706) which is coupled to the activation signal (ENN; CRACKN_S0, CRACKN_S1, CRACKN_S2) received by the measuring circuit (610, 612, 614) in order to output a voltage input signal VIN to the measuring circuit (610, 612, 614) based on a damage status of the structure (604, 606, 608) coupled to the measuring circuit (610, 612, 614). [5] System (100) according to claim 4, wherein the voltage divider circuit (702, 704, 706) further comprises: a first resistor (RPL0, RPL1, RPL2) representing an electrical resistance value of the structure (604, 606, 608); and a reference resistor (R0, R1, R2) coupled to the first resistor (RPL0, RPL1, RPL2) at an output node (708, 710, 712), wherein the reference resistor (R0, R1, R2) has an electrical resistance value greater than the electrical resistance value (RPL0, RPL1, RPL2) of the structure (604, 606, 608) in an undamaged state and less than the electrical resistance value (RPL0, RPL1, RPL2) of the structure (604, 606, 608) in a damaged state. [6] System (100) according to claim 5, wherein the voltage divider circuit (702, 704, 706) further comprises: a first field-effect transistor (N0, N1, N2); and a second field-effect transistor (P0, P1, P2); wherein a first terminal of the first field-effect transistor (N0, N1, N2) is coupled to the output node (708, 710, 712), a second terminal of the first field-effect transistor (N0, N1, N2) is coupled to ground (VSS), a first terminal of the second field-effect transistor (P0, P1, P2) is coupled to the reference resistor (R0, R1, R2), and a second terminal of the second field-effect transistor (P0, P1, P2) is coupled to a supply voltage (VDD), and where a gate of the first field-effect transistor (N0, N1, N2) and a gate of the second field-effect transistor (P0, P1, P2) are coupled to the activation signal (ENN; CRACKN_S0, CRACKN_S1, CRACKN_S2). [7] System (100) according to claim 4, wherein the circuit for selectively generating the activation signal (ENN; CRACKN_S0, CRACKN_S1, CRACKN_S2) for the next measuring circuit (612, 614) further comprises: an input for receiving a reference voltage VREF; an input for receiving the voltage input signal VIN from the voltage divider circuit (702, 704, 706); a circuit for generating an output signal OUT based on the reference voltage VREF and the voltage input signal VIN; and (ENN; CRACKN_S0, CRACKN_S1, CRACKN_S2) a circuit for generating the activation signal for the next measurement circuit (612, 614) based on the OUT signal. [8] System (100) according to claim 7, which further comprises a circuit for outputting a flag (F0, F1, F2) indicating a damage status of the structure (604, 606, 608) coupled to the measuring circuit (610, 612, 614). [9] Method for detecting and monitoring a crack (130) in an integrated circuit (102), comprising: Providing a plurality of electrically conductive structures (604, 606, 608) in an inactive region (108) of the integrated circuit (102), wherein the plurality of electrically conductive structures (604, 606, 608) extends around a protective barrier (110) formed in the inactive region (108) of the integrated circuit (102), and an active region (106) of the integrated circuit (102) is enclosed within the protective barrier (110). Coupling a plurality of stages of measuring circuits (610, 612, 614) connected in series with the plurality of electrically conductive structures (604, 606, 608), wherein each measuring circuit (610, 612, 614) is coupled to a respective structure of the plurality of structures (604, 606, 608); Activating the measuring circuit (610, 612, 614) in one stage N of the plurality of stages of measuring circuits (610, 612, 614); Monitoring an electrical parameter (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614) by the activated measuring circuit (610, 612, 614); and Output of an activation signal (CRACKN_S0, CRACKN_S1, CRACKN_S2) to activate the measuring circuit (612, 614) in a downstream stage N+1 of the plurality of stages of measuring circuits (610, 612, 614) by the activated measuring circuit (612, 614) in response to detection of a change in the electrical parameter (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614). [10] Method according to claim 9, which further comprises outputting a flag (F0, F1, F2) indicating the change in the electrical characteristic (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614). [11] Method according to claim 10, which further comprises providing a warning message in response to the flag (F0, F1, F2), wherein the warning message indicates that the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614) has been damaged. [12] Method according to claim 10, wherein the change in the electrical characteristic (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614) is due to a crack (130) propagating through the inactive region (108) of the integrated circuit (102), and the method further comprises providing the warning message before the crack (130) has propagated from the inactive region (108) of the integrated circuit (102) into the active region (106) of the integrated circuit (102). [13] Method according to claim 9, which further comprises positioning the structure (608) coupled to stage N of the plurality of stages of measuring circuits (610, 612, 614) closer to the active area (106) of the integrated circuit (102) than the structure (604, 606) coupled to stage N+1 of the plurality of stages of measuring circuits (610, 612, 614). [14] Procedure that includes: Coupling a plurality of stages of measuring circuits (610, 612, 614) connected in series with a plurality of electrically conductive structures (604, 606, 608) on an integrated circuit (102), wherein each measuring circuit (610, 612, 614) is coupled to a respective structure (604, 606, 608) of the plurality of structures (604, 606, 608); Activating the measuring circuit (610, 612, 614) in one stage N of the plurality of stages of measuring circuits (610, 612, 614); Monitoring an electrical parameter (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614) by the activated measuring circuit (610, 612, 614); and Output of an activation signal (CRACKN_S0, CRACKN_S1, CRACKN_S2) to activate the measuring circuit (612, 614) in a downstream stage N+1 of the plurality of stages of measuring circuits (610, 612, 614) by the activated measuring circuit (610, 612, 614) in response to detection of a change in the electrical parameter (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614). [15] Method according to claim 14, which further comprises generating a warning message indicating damage to the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614). [16] The method of claim 15, further comprising: Monitoring the propagation of a crack (130) through the integrated circuit (102) based on the warning message. [17] Method according to claim 14, wherein the electrical parameter comprises a resistance value (RPL0, RPL1, RPL2) of the respective structure (604, 606, 608) coupled to the activated measuring circuit (610, 612, 614). [18] Method according to claim 14, wherein the plurality of electrically conductive structures (604, 606, 608) comprise electrically conductive boundary lines in an inactive region (108) of the integrated circuit (102), and the change in the electrical parameter (RPL0, RPL1, RPL2) indicates the presence of a crack (130) in a boundary line.

Images