Insulation structure for IGBT devices with an integrated diode and method

Abstract

Semiconductor device (100) comprising: a semiconductor substrate (102) having a transistor region (104) and a diode region (106), wherein the transistor region (104) comprises a plurality of IGBT cells (110) and a charge carrier compensation region (112) configured to to eject or admit minority charge carriers of the drift zone (130) based on an on state or an off state of the plurality of IGBT cells (110), wherein the diode region (106) comprises a plurality of diode cells (114); and an isolation structure (116) between the transistor region (104) and the diode region (106), wherein the isolation structure (116) comprises a first trench (118), which extends longitudinally along at least a portion of a circumference of the diode region (106), and comprises a second trench (120) arranged between the first trench (118) and the transistor region (104), wherein the charge carrier compensation region (112) extends to the second trench (120) of the isolation structure (116), but not to the first trench (118), such that the charge carrier compensation region (112) is electrically isolated from an anode potential of the diode region (106).

Description

BACKGROUNDPower semiconductor devices including an insulated gate bipolar transistor (IGBT) integrated diode often use a common metallization / polysilicon layer to provide gate potential for trench gate electrodes of the IGBT and an emitter potential for the anode region of the diode. Often, there is no cell discontinuity between the trench layout in the IGBT and the diode regions. Separation between boundary IGBT and diode cells is provided by interrupting the common metallization / polysilicon layer. In this way, the common metallization / polysilicon layer provides a gate potential in the IGBT region and the emitter potential in the diode region.The IGBT region generally includes a p-doped region that protects the gate trench dielectric of the IGBT cells from excessively strong electric fields. The p-doped region typically continues from the last cell of the IGBT and contacts the first cell of the diode, such that there is no discontinuity of the p-doped region between the last cell of the IGBT and the first cell of the diode, or there is a close proximity between the p-doped region of the last IGBT cell and the first anode region of the diode.During the start of turn-on of the IGBT, an adjacent trench electrode in the diode region is at an emitter potential and the collector (back side) is at a higher potential. The potential in the drift zone near the diode trench is higher than zero volts. Thus, there is a risk that an inversion channel will form along the outermost trench in the diode region, which electrically connects the anode of the diode to the p-doped region of the IGBT. The p-doped region of the IGBT should normally be floating, but at the beginning of turn-on of the IGBT, the p-doped region may be grounded through the inversion channel.The input / gate capacitance of the IGBT increases at the beginning of the turn-on process when an inversion channel shorts the p-doped region of the IGBT to ground, thereby requiring more time to perform the turn-on process. That is, the effective gate charge experienced by the IGBT driver is higher when the p-doped region of the IGBT is shorted to ground by an inversion channel formed in the diode region than when the p-doped region remained electrically floating. The p-doped region of the IGBT is typically connected around the entire IGBT region, so that the p-doped region is grounded everywhere, which exacerbates the problem. If the p-doped region were floating, it would instead follow the gate potential of the IGBT. However, when the p-type region is short-circuited to ground at the beginning of turn-on of the IGBT, the speed at which the IGBT turns on is reduced.Thus, there is a need for a power semiconductor device having a diode integrated with an IGBT and improved turn-on performance.EP 1 078 402 B1 describes a power semiconductor device in which two adjacent insulating trenches are provided in a substrate in order to separate two adjacent doped regions. The trenches may have a depth that is less than the depth of the doped regions.SUMMARYThe invention is set forth in the independent claims. Features of some exemplary embodiments are set forth in the dependent claims.According to an embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate having a transistor region and a diode region, wherein the transistor region comprises a plurality of insulated gate bipolar transistor (IGBT) cells and a charge carrier compensation region configured to expel or admit minority charge carriers of the drift zone based on an on state or an off state of the plurality of IGBT cells, wherein the diode region comprises a plurality of diode cells; and an isolation structure between the transistor region and the diode region, the isolation structure comprising a first trench extending longitudinally along at least a part of a periphery of the diode region and a second trench arranged between the first trench and the transistor region, wherein the charge carrier compensation region extends to the second trench of the isolation structure but not to the first trench, such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.According to an embodiment of a method for manufacturing a semiconductor device, the method comprises: forming a transistor region and a diode region in a semiconductor substrate, wherein the transistor region comprises a plurality of insulated gate bipolar transistor (IGBT) cells and a charge carrier compensation region configured to eject or insert minority charge carriers of the drift zone based on an on state or an off state of the plurality of IGBT cells, wherein the diode region comprises a plurality of diode cells; and forming an isolation structure between the transistor region and the diode region, the isolation structure comprising a first trench extending longitudinally along at least a part of a periphery of the diode region and a second trench arranged between the first trench and the transistor region, wherein the charge carrier compensation region extends to the second trench of the isolation structure but not to the first trench, such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE FIGURESThe elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals designate like parts, respectively. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. In the drawings, there are shown embodiments which will be described in detail in the following description. FIG. 1 illustrates a partial plan view of an embodiment of a semiconductor device having an isolation structure separating adjacent IGBT and diode cells. FIG. 2 illustrates a cross-sectional view of a portion of the semiconductor device along the line labeled A-A' in FIG. 1, according to an embodiment. FIG. 3 illustrates a cross-sectional view of a portion of the semiconductor device taken along the line labeled A-A' in FIG. 1, according to another embodiment. FIG. 4 illustrates a cross-sectional view of a portion of the semiconductor device taken along the line labeled A-A' in FIG. 1, according to another embodiment. FIG. 5 illustrates a plan view in a region where the transistor region of the semiconductor device is adjacent to the diode region according to an embodiment. FIG. 6 illustrates a plan view in a region where the transistor region of the semiconductor device is adjacent to the diode region according to another embodiment. FIG. 7 illustrates a plan view in a region where the transistor region of the semiconductor device is adjacent to the diode region according to another embodiment. FIG. 8 illustrates a plan view in a region where the transistor region of the semiconductor device is adjacent to the diode region according to another embodiment. FIG. 9 illustrates a cross-sectional view of a portion of the semiconductor device along the line labeled B-B' in FIG. 8, according to an embodiment.DETAILED DESCRIPTIONA power semiconductor device with an improved electrical decoupling between boundary cells of an IGBT and boundary cells of a diode integrated with the IGBT and corresponding manufacturing methods is described here. The IGBT includes a charge carrier compensation region configured to eject or gate minority charge carriers of the drift zone (holes in the case of an n-type drift zone and electrons in the case of a p-type drift zone) based on an on state or an off state of the IGBT. An isolation structure between the transistor region and the diode region of the semiconductor device improves an electrical decoupling between the IGBT and the diode cells adjacent to each other. The isolation structure includes a first trench extending longitudinally along at least a portion of a perimeter of the diode region and a second trench disposed between the first trench and the transistor region. The charge carrier compensation region of the transistor region, which protects the gate trench dielectric of the IGBT cells from excessively strong electric fields, extends to the second trench of the isolation structure, but not to the first trench, so that the charge carrier compensation region is electrically insulated from the anode potential of the diode region. Accordingly, the charge carrier compensation region of the transistor region remains electrically floating when the IGBT is turned on, thereby maintaining the fixed speed at which the IGBT turns on. It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.FIG. 1 illustrates a partial plan view of a semiconductor device 100. The semiconductor device 100 includes a semiconductor substrate 102 having a transistor region 104, a diode region 106, and an isolation region 108 separating the transistor region 104 and the diode region 106. The transistor region 104 includes a plurality of insulated gate bipolar transistor (IGBT) cells 110 and a carrier compensation region 112 configured to eject or insert minority carriers of the drift zone (holes in the case of an n-type drift zone and electrons in the case of a p-type drift zone) based on an on state or an off state of the IGBT cells 110. The diode region 106 includes a plurality of diode cells 114. In the embodiment shown in FIG. 1, the IGBT cells 110 are square and the diode cells 114 are stripe-shaped. The IGBT cells 110 and the diode cells 114 may have, for example, other layouts, cell types, periodicity, etc., as described later herein.FIG. 2 illustrates a cross-sectional view of a portion of the semiconductor device 100 along the line labeled A-A' in FIG. 1. In the isolation region 108 separating the transistor region 104 and the diode region 106, an isolation structure 116 is provided between the transistor region 104 and the diode region 106. The isolation structure 116 includes a first trench 118 extending longitudinally (direction 'X' in FIG. 1 ) along at least a portion of the perimeter of the diode region 106. The isolation structure 116 also includes a second trench 120 disposed between the first trench 118 of the isolation structure 116 and the transistor region 104. The first and second trenches 118, 120 of the isolation structure 116 extend in the longitudinal direction (direction 'X' in FIG. 1 ) parallel to each other and may laterally surround the entire perimeter of the diode region 116 or only a part thereof, for example the part adjacent to the transistor region 104.The charge carrier compensation region 112 protecting the gate trench dielectric 122 of the IGBT cells 110 from too strong electric fields extends into the isolation region 108, to the second trench 120 of the isolation structure 116, but not to the first trench 118, such that the charge carrier compensation region 112 is electrically isolated from the anode potential of the diode region 106 at any time of the IGBT turn-on process. Accordingly, even if an inversion channel 113 is formed along the sidewall of the outermost field electrode trenches 146 of the diode region 106, the inversion channel would not be connected to the charge carrier compensation region 112 because two trenches 118, 120 that are not part of the IGBT or the diode devices are used to separate the transistor region 104 from the diode region 106. The transistor region 104 and the diode region 106 will be described in more detail next.The semiconductor substrate 102 in which the transistor region 104 and the diode region 106 are formed may include one or more of various semiconductor materials used to form integrated circuit devices, such as, but not limited to, silicon (Si), silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor substrate 102 may be a bulk semiconductor material or may include one or more epitaxial layers grown on the bulk semiconductor material. As explained above, the IGBT cells 110 included in the transistor region 104 may be square-shaped, and the diode cells 114 included in the diode region 106 may be stripe-shaped, as shown in FIG. 1.Each IGBT cell 110 in the transistor region 104 includes an emitter region 124 of a first conductivity type, a body region 126 of a second conductivity type, and a gate trench 128 extending through the emitter region 124 and the body region 126 and into a drift zone 130 of the first conductivity type. The gate trenches 128 extend perpendicular (direction 'Z' in FIG. 2 ) to a first main surface 132 of the semiconductor substrate 102. The gate trench electrodes 128 may also include a gate electrode 134 for controlling a conductive channel 136 in the body region 126 of each IGBT cell 110. The IGBT cells 110 may also include an additional trench (not shown) having a field electrode for forming the electric field potential in the semiconductor substrate 102 during operation of the IGBT. The field electrodes may be electrically connected to a different potential than the gate electrode 134. For example, the field electrodes may be electrically connected to emitter potential, ground, or may be electrically floating.Still referring to the IGBT cells 110, the body region 126 separates the corresponding emitter region 124 of the IGBT cell 110 from the drift zone 130. The emitter region 124 is electrically connected to the drift zone 130 when the conductive channel 136 of the corresponding IGBT cell 110 is present. The conductive channels 136 are controlled by the voltage applied to the gate electrodes 134 of the IGBT cells 110.The IGBT also includes a collector region 138 on the opposing surface 140 of the semiconductor substrate 102 with respect to the emitter regions 124. The emitter regions 124, the drift zone 130 and the conductive channels 136 are of a first conductivity type, and the body regions 126 and the collector region 138 are of a second conductivity type opposite the first conductivity type. In the case of n-type channels 136, the emitter regions 124 and the drift zone 130 are, for example, n-type and the body regions 126 and the collector region 138 are p-type. Conversely, in the case of p-type conductive channels 136, the emitter regions 124 and the p-type drift zone 130, and the body regions 126 and the n-type collector region 138 are. An optional field stop region 142 of the first conductivity type may be formed between the drift zone 130 and the collector region 138 in the semiconductor substrate 102. The field stop region 142 may be omitted in the diode region 106 even if provided in the transistor region 104.Referring now to diode region 106, each diode cell 114 includes a second conductivity type anode region 144 and a field electrode trench 146 extending through anode region 144 and into a first conductivity type cathode region 148. The field electrode trenches 146 extend perpendicular (direction 'Z' in FIG. 2 ) to the first main surface 132 of the semiconductor substrate 102 and each include a field electrode 150 insulated from the surrounding semiconductor substrate 102 by an insulating layer 152 that may be made of the same material as the gate trench dielectric 122 or of a different material.The cell construction of the diode region 106 may be similar to that of the transistor region 104. In contrast, however, the emitter regions 124 are omitted from the diode region 106. Furthermore, the diode region 106 includes a cathode region 148 of the first conductivity type instead of the collector region 138 of the second conductivity type at the second main surface 140 of the semiconductor substrate 102.The charge carrier compensation 112 is of the second conductivity type, like the collector region 138. The isolation structure 116 formed in the isolation region 108 of the semiconductor device 100 electrically isolates the charge carrier compensation region 112 from the anode region 144 of the diode cells arranged along the perimeter of the diode region 106.An electrically conductive layer 154 formed over the semiconductor substrate 102 includes a first portion 156 and a second portion 158 separated from each other. The electrically conductive layer 154 may be formed of the same material as the gate electrodes 134 in the transistor region 104 and the field electrodes 150 in the diode region 106. For example, the electrically conductive layer 154 and the trench electrodes 134, 150 may be formed of polysilicon. The electrically conductive layer 154 may instead be formed of a different material (e.g., metal) than the gate electrodes 134 in the transistor region 104 and the field electrodes 150 in the diode region 106 (e.g., polysilicon).In any case, the first portion 156 of the electrically conductive layer 154 provides a gate potential for the gate electrode 134 in the gate trenches 128 of the IGBT cells 110, and the second portion 158 of the electrically conductive layer 154 provides an emitter potential for the field electrode 150 in the field electrode trenches 146 of the diode cells 114, wherein the gate potential and the emitter potential are different from each other.As shown in FIG. 2, the first part 156 and the second part 158 of the electrically conductive layer 154 may be separated from each other between the second trench 120 of the isolation structure 116 and the gate trench 128 of outermost of the IGBT cells 110 facing the diode region 106, such that the second part 158 of the electrically conductive layer 154 extends over both the first trench 118 and the second trench 120 of the isolation structure 116.FIG. 3 shows the same cross-sectional view as FIG. 2, but in FIG. 3 the second part 158 of the electrically conductive layer 154 terminates above the field electrode trenches 146 of the outermost of the diode cells 114 facing the transistor region 104, such that the second part 158 of the electrically conductive layer 154 does not extend beyond the second (outer) trench 120 of the isolation structure 116.In both FIGS. 2 and 3, above the first main surface 132 of the semiconductor substrate 102, a first metallization 160 is electrically connected to the emitter region 124 and the body region 126 of the IGBT cells 110 in the transistor region 104 and to the trench field electrode 150 and the anode region 144 of the diode cells 114 in the diode region 106. The gate electrodes 134 in the transistor region 104 are insulated from the first metallization 160 by an insulating material 162, such as a dielectric.The first metallization 160 is electrically connected to the emitter region 124 and the body region 126 of the IGBT cells 110 in the transistor region 104 through first contact openings 164 in the insulating material 162. The first metallization 160 is electrically connected to the anode region 144 of the diode cell 114 in the diode region 106 through second contact openings 166 in the insulating material 162. The second portion 158 of the electrically conductive layer 154 may be connected to the first metallization 160 through third contact openings 168 in the insulating material 162 to couple the trench field electrodes 150 in the diode region 114 to emitter potential.The insulating material 162 may fill the lateral gap 'G' between the first and second portions 156, 158 of the electrically conductive layer 154. The contact openings 164, 166, 168 in the insulating material 162 are shown in FIG. 1, but not the insulating material 162 itself, so that underlying regions of the semiconductor device 100 can be seen in FIG. 1.A second metallization 170 contacts the collector region 138 of the IGBT and the cathode region 148 of the diode at the second main surface 140 of the semiconductor substrate 102, as shown in FIGS. 2 and 3.During the start of the turn-on of the IGBT, the adjacent field electrode trenches 146 in the diode region 106 are at emitter potential and the collector region 138 at the back side is at a higher potential. The potential in the drift zone 130 near the field electrode trenches 146 in the diode region 106 is higher than zero volts. Thus, there is a risk that an inversion channel will form along the outermost trenches 146 in the diode region 106. However, the dual trench isolation structure 146 separates the transistor region 104 from the diode region 106 and prevents any inversion channel in the diode region 106 from reaching the charge carrier compensation region 112 of the adjacent IGBT cells 110. Accordingly, the charge carrier compensation region 112 of the transistor region 104 remains electrically floating during the entire turn-on of the IGBT.FIG. 4 illustrates a cross-sectional view of a portion of the semiconductor device 100 along the line labeled A-A' in FIG. 1, according to another embodiment. The embodiment shown in FIG. 4 is similar to the embodiment shown in FIG. 2. In contrast thereto, however, the semiconductor device 100 further includes a doped region 172 of the first conductivity type formed between the first trench 118 and the second trench 120 of the isolation structure 116 in the semiconductor substrate 102. The first conductivity type doped region 172 helps prevent the formation of an inversion channel between the anode region 144 of the outermost diode cells 114 and the charge carrier compensation region 112 of the adjacent IGBT cells 110. In particular, the first conductivity type doped region 172 increases the threshold voltage for an inversion channel along the second trench 120 of the isolation structure 116. The second portion 158 of the electrically conductive layer 154 may also terminate above the field electrode trenches 146 of the outermost of the diode cells 114 facing the transistor region 104, such that the second portion 158 of the electrically conductive layer 154 does not extend beyond the second (outer) trench 120 of the isolation structure 116, as shown in FIG. 3. Next, additional embodiments of the cell layout for the transistor and diode regions 104, 106 of the semiconductor device 100 will be described.FIG. 5 illustrates a top view in a region where the transistor region 104 is adjacent to the diode region 106, according to another embodiment. The electrically conductive layer 154 with the first and second parts 156, 158 being separated, the first metallization 160 and the insulating material 162 between the first metallization 160 and the electrically conductive layer 154 are not shown in FIG. 5, such that regions lying underneath are visible in FIG. 5. The field electrode trenches 146 in the diode region 106 are also illustrated in a simplified manner in FIG. 5 to improve the illustration of other features.In FIG. 5, the diode cells 114 are strip-shaped, for example rectangular, to increase the area of the anode region 144. The IGBT cells 110 are also strip-shaped. Although square IGBT cells 110 as shown in FIG. 1 may be preferred, stripe-shaped IGBT cells 110 as shown in FIG. 5 may be suitable for reverse-conduction IGBTs (RC-IGBTs).Separately or in combination, the charge carrier compensation region 112 may be continuous or non-continuous in the transistor region 104. Depending on the layout of the IGBT cells 110, the charge carrier compensation region 112 may be separated or not separated between the IGBT cells 110, for example.Separately or in combination, the isolation structure 116 may extend longitudinally along the entire perimeter of the diode region 106.Separately or in combination, the charge carrier compensation region 112 may be contiguous throughout the transistor region 110.Separately or in combination, the charge carrier compensation region 112 may be electrically floating.FIG. 6 illustrates a top view in a region where the transistor region 104 is adjacent to the diode region 106, according to another embodiment. The embodiment shown in FIG. 6 is similar to the embodiment shown in FIG. 5. In contrast to this, the gate trenches 128 end at ends 174 of the gate trenches 128 facing the diode region 106, but nearer to the diode region 106 than the emitter region 124 and the body region 126 of the IGBT cells 110. At this end 174 of the gate trenches 128, the charge carrier compensation region 112 extends from sidewall to sidewall of the gate trenches 128.FIG. 7 illustrates a top view in a region where the transistor region 104 is adjacent to the diode region 106, according to another embodiment. The embodiment shown in FIG. 7 is similar to the embodiment shown in FIG. 5. In contrast to this, however, the strip-shaped diode cells 114 extend in the longitudinal direction (direction 'Y' in FIG. 7 ) transversely to the strip-shaped IGBT cells 110. In one case, the longitudinal extension (direction 'Y' in FIG. 7 ) of the strip-shaped diode cells 114 extends perpendicular to the longitudinal extension (direction 'X' in FIG. 7 ) of the strip-shaped IGBT cells 110.FIG. 8 illustrates a top view in a region where the transistor region 104 is adjacent to the diode region 106, according to another embodiment. FIG. 9 is a cross-sectional view of a part of the semiconductor device taken along the line denoted by B-B' in FIG. 8. The embodiment shown in FIG. 8 is similar to the embodiment shown in FIG. 5. In contrast thereto, however, one or more contacts 176 may be provided for the body region 126 formed in the semiconductor substrate 102 between the first trench 118 and the second trench 120 of the isolation structure 116. As discussed hereinabove, the first conductivity type doped region 172 enhances commutation robustness for the IGBT device by helping to prevent the formation of an inversion channel between the anode region 144 of the outermost diode cells 114 and the charge carrier compensation region 112 of the adjacent IGBT cells 110. In contrast to the square IGBT cell layout shown in FIG. 4, the IGBT body regions 126 extend laterally from the transistor region 104 and into the isolation region 108. The IGBT body regions 126 may also extend laterally into the diode region 106. In this case, the anode region 144 may have the same or a different implantation dose as the IGBT diode regions 126.In both cases, according to the embodiment shown in FIGS. 8 and 9, the first conductivity type doped region 172 is formed under the IGBT body region 126 in the isolation region 108 so as to provide a pn junction therebetween to ensure blocking. One or more optional contacts 176 may be formed to connect the portion of the body region 126 that is above the doped region 172 in the isolation region 108, as shown in FIGS. 8 and 9.Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure.Example 1. a semiconductor device comprising: a semiconductor substrate having a transistor region and a diode region, the transistor region comprising a plurality of insulated gate bipolar transistor (IGBT) cells and a charge carrier compensation region configured to expel or admit minority charge carriers of the drift zone based on an on state or an off state of the plurality of IGBT cells, the diode region comprising a plurality of diode cells; and an isolation structure between the transistor region and the diode region, the isolation structure comprising a first trench extending longitudinally along at least a part of a periphery of the diode region and a second trench arranged between the first trench and the transistor region, wherein the charge carrier compensation region extends to the second trench of the isolation structure but not to the first trench, such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.Example 2. the semiconductor device of example 1, wherein each IGBT cell of the plurality of IGBT cells comprises an emitter region of a first conductivity type, a body region of a second conductivity type, and a gate trench extending through the emitter region and the body region and into a drift zone of the first conductivity type, wherein each diode cell of the plurality of diode cells comprises an anode region of the second conductivity type and a field electrode trench extending through the anode region and into a cathode region of the first conductivity type, wherein the charge carrier compensation region is of the second conductivity type, wherein the isolation structure electrically isolates the charge carrier compensation region from the anode region of the diode cells arranged along the perimeter of the diode region.Example 3. The semiconductor device of example 2, further comprising: an electrically conductive layer formed over the semiconductor substrate, wherein the electrically conductive layer has a first part and a second part separated from each other, wherein the first part provides a gate potential for a gate electrode in the gate trenches of the IGBT cells, wherein the second part provides an emitter potential for a field electrode in the field electrode trenches of the diode cells, wherein the gate potential and the emitter potential are different from each other, and wherein the first part and the second part of the electrically conductive layer between the second trench of the isolation structure and the gate trench are separated from each other from outermost ones of the IGBT cells facing the diode region, such that the second portion extends over the first trench and at least a portion of the second trench of the isolation structure.Example 4. the semiconductor device of example 3, further comprising: a doped region of the first conductivity type between the first trench and the second trench of the isolation structure.Example 5. the semiconductor device of example 4, wherein the doped region is formed under an IGBT body region.Example 6. the semiconductor device of any of examples 1 to 5, further comprising: a doped region of the first conductivity type between the first trench and the second trench of the isolation structure.Example 7. the semiconductor device of any one of Examples 1 to 6, wherein the IGBT cells are square, and wherein the diode cells are stripe-shaped.Example 8 The semiconductor device of any one of Examples 1 to 6, wherein the IGBT cells are stripe-shaped, and wherein the diode cells are stripe-shaped.Example 9. the semiconductor device of example 8, wherein at and end of the gate trenches facing the diode region, the gate trenches terminate closer to the diode region than the emitter region and the body region of the IGBT cells, and wherein the charge carrier compensation region extends from sidewall to sidewall of the gate trenches at the end facing the diode region.Example 10. The semiconductor device of example 8 or 9, wherein the stripe-shaped diode cells extend longitudinally transversely to the stripe-shaped IGBT cells.Example 11. The semiconductor device of any one of examples 1 to 10, wherein the first trench and the second trench of the isolation structure extend longitudinally parallel to each other.Example 12. The semiconductor device of any one of Examples 1 to 11, wherein the isolation structure extends longitudinally along the entire periphery of the diode region.Example 13. The semiconductor device of any of Examples 1 to 12, wherein the charge carrier compensation region is continuous throughout the transistor region.Example 14. The semiconductor device of any one of Examples 1 to 13, wherein the charge carrier compensation region is electrically floating.Example 15. a method of manufacturing a semiconductor device, the method comprising: forming a transistor region and a diode region in a semiconductor substrate, the transistor region comprising a plurality of insulated gate bipolar transistor (IGBT) cells and a charge carrier compensation region configured to eject or gate minority charge carriers of the drift zone based on an on state or an off state of the plurality of IGBT cells, the diode region comprising a plurality of diode cells; and forming an isolation structure between the transistor region and the diode region, the isolation structure comprising a first trench extending longitudinally along at least a part of a periphery of the diode region and a second trench arranged between the first trench and the transistor region, wherein the charge carrier compensation region extends to the second trench of the isolation structure but not to the first trench, such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.Example 16. The method of example 15, wherein each IGBT cell of the plurality of IGBT cells comprises an emitter region of a first conductivity type, a body region of a second conductivity type, and a gate trench extending through the emitter region and the body region and into a drift zone of the first conductivity type, wherein each diode cell of the plurality of diode cells comprises an anode region of the second conductivity type and a field electrode trench extending through the anode region and into a cathode region of the first conductivity type, wherein the charge carrier compensation region is of the second conductivity type, wherein the isolation structure electrically isolates the charge carrier compensation region from the anode region of the diode cells arranged along the perimeter of the diode region.Example 17. the method of example 16, further comprising: forming an electrically conductive layer over the semiconductor substrate, the electrically conductive layer having a first portion and a second portion; providing, over the first portion of the electrically conductive layer, a gate potential for a gate electrode in the gate trenches of the IGBT cells; providing, over the second portion of the electrically conductive layer, an emitter potential for a field electrode in the field electrode trenches of the diode cells, wherein the emitter potential is different from the gate potential; separating the first part and the second part of the electrically conductive layer between the second trench of the isolation structure and the gate trench from outermost ones of the IGBT cells facing the diode region, such that the second part extends over the first trench and at least a part of the second trench of the isolation structure.Example 18. The method of example 17, further comprising: forming a doped region of the first conductivity type between the first trench and the second trench of the isolation structure.Example 19. the method of example 18, wherein the doped region is formed under an IGBT body region.Example 20. The method of any of Examples 15 to 19, further comprising: forming a doped region of the first conductivity type between the first trench and the second trench of the isolation structure.Terms such as "first / r / s", "second / r / s", and the like are used to describe various elements, regions, portions, etc., and are not intended to be limiting. Like terms refer to like elements throughout the specification.As used herein, the terms "comprise," "include," "include," "comprising," and the like are open ended terms that indicate the presence of the stated elements or features, but do not exclude additional elements or features. The articles "a / e / r / es" and "the / s" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

Claims

A semiconductor device (100) comprising: a semiconductor substrate (102) having a transistor region (104) and a diode region (106), wherein the transistor region (104) comprises a plurality of IGBT cells (110) and a charge carrier compensation region (112) configured to expel or gate minority charge carriers of the drift zone (130) based on an on state or an off state of the plurality of IGBT cells (110), wherein the diode region (106) comprises a plurality of diode cells (114); and an isolation structure (116) between the transistor region (104) and the diode region (106), the isolation structure (116) comprising a first trench (118) extending longitudinally along at least a part of a perimeter of the diode region (106) and a second trench (120) disposed between the first trench (118) and the transistor region (104), the charge carrier compensation region (112) extending to the second trench (120) of the isolation structure (116) but not to the first trench (118) such that the charge carrier compensation region (112) is electrically isolated from an anode potential of the diode region (106).The semiconductor device (100) of claim 1, wherein each IGBT cell of the plurality of IGBT cells (110) comprises an emitter region (124) of a first conductivity type, a body region (126) of a second conductivity type, and a gate trench (128) extending through the emitter region (124) and the body region (126) and into a drift zone (130) of the first conductivity type, wherein each diode cell of the plurality of diode cells (114) comprises an anode region (144) of the second conductivity type and a field electrode trench (146) extending through the anode region (144) and into a cathode region (148) of the first conductivity type, wherein the charge carrier compensation region (112) is of the second conductivity type, wherein the isolation structure (116) electrically isolates the charge carrier compensation region (112) from the anode region (144) of the diode cells (114) arranged along the periphery of the diode region (106).The semiconductor device (100) of claim 2, further comprising: an electrically conductive layer (154) formed over the semiconductor substrate (102), the electrically conductive layer (154) having a first portion (156) and a second portion (158) separated from each other, the first portion (156) providing a gate potential to a gate electrode (134) in the gate trenches of the IGBT cells (110), the second portion (158) providing an emitter potential to the field electrode (150) in the field electrode trenches of the diode cells (114), the gate potential and the emitter potential being different from each other, and wherein the first part (156) and the second part (158) of the electrically conductive layer (154) between the second trench (120) of the isolation structure (116) and the gate trench (128) are separated from outermost ones of the IGBT cells (110) facing the diode region (106), such that the second part (158) extends over the first trench (118) and at least a part of the second trench (120) of the isolation structure (116).The semiconductor device (100) of claim 3, further comprising: a doped region (172) of the first conductivity type between the first trench (118) and the second trench (120) of the isolation structure (116).The semiconductor device (100) of claim 4, wherein the doped region (172) is formed under an IGBT body region (126).The semiconductor device (100) of claim 1, further comprising: a doped region (172) of a first conductivity type between the first trench (118) and the second trench (120) of the isolation structure (116).The semiconductor device (100) according to claim 1, wherein the IGBT cells (110) are square, and wherein the diode cells (114) are stripe-shaped.The semiconductor device (100) according to claim 1, wherein the IGBT cells (110) are strip-shaped, and wherein the diode cells (114) are strip-shaped.The semiconductor device (100) of claim 8, wherein at the ends (174) of the gate trenches (128) facing the diode region (106), the gate trenches (128) terminate closer to the diode region (106) than the emitter region (124) and the body region (126) of the IGBT cells (110), and wherein the charge carrier compensation region (112) extends from sidewall to sidewall of the gate trenches (128) at the end facing the diode region (106).The semiconductor device (100) according to claim 8, wherein the stripe-shaped diode cells (114) extend longitudinally transversely to the stripe-shaped IGBT cells (110).The semiconductor device (100) of claim 1, wherein the first trench (118) and the second trench (120) of the isolation structure (116) extend longitudinally parallel to each other.The semiconductor device (100) of claim 1, wherein the isolation structure (116) extends longitudinally along the entire periphery of the diode region (106).The semiconductor device (100) of claim 1, wherein the charge carrier compensation region (112) is contiguous throughout the transistor region (104).The semiconductor device (100) of claim 1, wherein the charge carrier compensation region (112) is electrically floating.A method of manufacturing a semiconductor device (100), the method comprising: forming a transistor region (104) and a diode region (106) in a semiconductor substrate (102), wherein the transistor region (104) comprises a plurality of IGBT cells (110) and a charge carrier compensation region (112) configured to expel or admit minority charge carriers of the drift zone (130) based on an on state or an off state of the plurality of IGBT cells (110); wherein the diode region (106) comprises a plurality of diode cells (114); and forming an isolation structure (116) between the transistor region (104) and the diode region (106), the isolation structure (116) comprising a first trench (118) extending longitudinally along at least a part of a perimeter of the diode region (106) and a second trench (120) arranged between the first trench and the transistor region (104), wherein the charge carrier compensation region (112) extends to the second trench (120) of the isolation structure (116) but not to the first trench (118), such that the charge carrier compensation region (112) is electrically isolated from an anode potential of the diode region (106).The method of claim 15, wherein each IGBT cell of the plurality of IGBT cells (110) comprises an emitter region (124) of a first conductivity type, a body region (126) of a second conductivity type, and a gate trench (128) extending through the emitter region (124) and the body region (126) and into a drift zone (130) of the first conductivity type, wherein each diode cell of the plurality of diode cells (114) comprises an anode region (144) of the second conductivity type and a field electrode trench (146) extending through the anode region (144) and into a cathode region (148) of the first conductivity type, wherein the charge carrier compensation region (112) is of the second conductivity type, wherein the isolation structure (116) electrically isolates the charge carrier compensation region (112) from the anode region (144) of the diode cells (114) arranged along the periphery of the diode region (106).The method of claim 16, further comprising: forming an electrically conductive layer (154) over the semiconductor substrate (102), the electrically conductive layer (154) having a first portion (156) and a second portion (158); providing, over the first portion (156) of the electrically conductive layer (154), a gate potential for a gate electrode (134) in the gate trenches of the IGBT cells (110); providing, over the second portion (158) of the electrically conductive layer (154), an emitter potential for the field electrode (150) in the field electrode trenches of the diode cells (114), the emitter potential being different than the gate potential; and separating the first part (156) and the second part (158) of the electrically conductive layer (154) between the second trench of the isolation structure (116) and the gate trench (128) from outermost ones of the IGBT cells (110) facing the diode region (106), such that the second part (158) extends over the first trench (118) and at least a part of the second trench (120) of the isolation structure (116).The method of claim 17, further comprising: forming a doped region (172) of the first conductivity type between the first trench and the second trench of the isolation structure (116).The method of claim 18, wherein the doped region (172) is formed under an IGBT body region (126).The method of claim 15, further comprising: forming a doped region (172) of the first conductivity type between the first trench (118) and the second trench (120) of the isolation structure (116).

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