Multigate selection switch for memory cells and its manufacturing process

Abstract

Memory structure (500) comprising: a first word line (120A); a second word line (120B); a high-k dielectric layer (104) disposed on the first word line and the second word line; a channel layer (140) disposed on the high-k dielectric layer and containing a semiconductor material; a first source electrode (122A) and a second source electrode (122B), wherein the first source electrode and the second source electrode each electrically contact the channel layer; a first drain electrode (124A) disposed on the channel layer between the first source electrode and the second source electrode; a memory cell (150) electrically connected to the first drain electrode; a bit line (132) electrically connected to the memory cell; a first upper gate electrode (121A) overlapping with the channel layer and the first word line; a second gate electrode (121B) overlapping with the channel layer and the second word line; a second drain electrode (124B) disposed on the channel layer between the first source electrode and the second source electrode; and an electrical contact (152) electrically connecting the first drain electrode and the second drain electrode; wherein the electrical contact electrically connects the first drain electrode and the second drain electrode to the memory cell.

Description

GENERAL STATE OF THE ART

[0001] Thin-film transistors (TFTs) are considered promising candidates for back-end-of-line (BEOL) control elements in memory devices. However, metal-oxide semiconductor materials used in TFTs can suffer from low inrush currents. Accordingly, there is a need for improved TFTs that provide higher inrush currents for improved memory cell switching.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2010 / 0 259 976 A1, US 2006 / 0 115 943 A1, US 7 932 547 B2 and US 2019 / 0 273 119 A1.

[0003] The invention is defined by the main claim and the subordinate claim. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A is a vertical cross-sectional view of an exemplary structure after formation of complementary metal oxide semiconductor (CMOS) transistors, metal interconnect structures embedded in layers of dielectric material, and a layer of dielectric material at the interconnect via level, in accordance with an embodiment of the present disclosure. Fig. 1B is a vertical cross-sectional view of the first exemplary structure during formation of the array of back-gate fin field effect transistors in accordance with an embodiment of the present disclosure. Fig. 1C is a vertical cross-sectional view of the first exemplary structure after formation of higher-level metal interconnect structures in accordance with an embodiment of the present disclosure. Fig. 2A-2N are each vertical cross-sectional views illustrating a sequence of steps in forming a memory structure in accordance with various embodiments of the present disclosure. Fig. 3A-3D are vertical cross-sectional views illustrating a sequence of steps in forming a memory structure in accordance with various embodiments of the present disclosure. Fig. 4 is a perspective view of a memory structure of Fig. 3D. Fig. 5A-5I are vertical cross-sectional views illustrating a sequence of steps in forming a memory structure in accordance with various embodiments of the present disclosure. Fig. 6 is a perspective view of a memory structure of Fig. 5I. Fig. 7A and Fig. 7B are vertical cross-sectional views of memory cells that may be incorporated into memory structures in accordance with various embodiments of the present disclosure. Fig. 8 is a flow diagram illustrating a method of forming a memory structure in accordance with various embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact with each other, but may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, terms of spatial relationships such as "beneath," "below," "low," "above," "upper," and the like may be used herein for the purpose of more easily describing the relationship of one element or feature illustrated in the figures to another element or feature. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be arranged in a different orientation (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference numeral is assumed to have the same material composition and a thickness within the same thickness range.

[0007] The present disclosure relates to semiconductor devices, and more particularly, to a vertical field-controlled current select switch having two gates operable in conjunction with a memory cell device, such as a memory cell select device. Various embodiments of the present disclosure may relate to a ferroelectric gate-controlled memory device and methods of forming the same.

[0008] Memory devices comprise a grid of independently functioning memory cells formed on a substrate. Memory devices can comprise volatile memory cells or non-volatile memory cells (NV memory cells). Emerging memory technologies aim to store more data at a lower cost than silicon chips, which are popular in consumer electronics but expensive to manufacture. Such emerging memory devices may be used in the near future to replace existing memory technologies, such as flash memory. While existing resistive random-access memory devices have generally been adequate for their intended purposes, they may no longer be satisfactory in all respects as devices continue to become smaller.Emerging non-volatile memory technologies may include, for example, resistive random access memory (RRAM or ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase-change memory (PCM).

[0009] RRAM is a type of NVRAM that works by varying the resistance across a solid-state dielectric material, often referred to as a memristor. MRAM is a type of NVRAM that stores data in magnetic domains. Unlike conventional RAM chip technologies, data in MRAM is stored not as electrical charge or current flows, but rather by magnetic storage elements. The elements are formed from two ferromagnetic plates, each capable of maintaining a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match an external field to store data. If the insulating layer is thin enough (typically a few nanometers), electrons can "tunnel" from one ferromagnet to the other.This design is known as a magnetic tunnel junction (MTJ) and represents the simplest structure for an MRAM bit.

[0010] Ferroelectric RAM (FeRAM, F-RAM, or FRAM) is a random-access memory device similar in construction to dynamic random access memory (DRAM), but uses a ferroelectric dielectric layer instead of a dielectric layer to achieve non-volatility. Phase-change memory (also known as PCM, PCME, PRAM, PCRAM, OUM (ovonic unit memory), and C-RAM or CRAM (chalcogenide RAM) is a type of NV-RAM. PRAMs exploit the unique behavior of chalcogenide glass. In the older generation of PCM, heat generated by passing an electric current through a heating element, usually made of titanium nitride (TiN), was used to either rapidly heat and quench the glass, causing it to become amorphous, or to hold it for a period of time at its crystallization temperature range, causing it to return to its crystalline state.PCM also has the ability to achieve a number of different intermediate states, making it possible to hold multiple bits in a single cell. In each of these memory technologies, a select transistor may be required to excite and select a specific memory cell to perform a read or write operation.

[0011] In some memory devices, CMOS transistors can be used as select transistors. However, the size limitation of CMOS transistor technology can become a limiting factor in improving the size and memory cell density of memory devices. To improve the size and memory cell density, which can be limited by CMOS transistors, thin-film transistors (TFTs) are being introduced as promising candidates for memory cell selection. Such TFT transistors can be formed in the back-end-of-line (BEOL), thereby freeing up valuable real estate on a substrate in the front-end-of-line (FEOL). However, metal-oxide semiconductor materials used in TFTs can have a problem with low inrush currents.The various embodiments described herein improve the size and memory cell density by forming ferroelectric gate-controlled memory devices in the BEOL. Various embodiments disclosed herein may provide a dual-gate device, which may provide an increase in the on-state current when selecting a particular memory cell.

[0012] Fig. 1A is a vertical cross-sectional view of an exemplary structure after formation of complementary metal oxide semiconductor (CMOS) transistors, metal interconnect structures embedded in layers of dielectric material, and a layer of dielectric material at the interconnect via level prior to formation of an array of memory structures in accordance with some embodiments of the present disclosure. Referring to Fig. 1 illustrates an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes complementary metal oxide semiconductor (CMOS) transistors and metal interconnect structures formed in layers of dielectric material. In particular, the first exemplary structure includes a substrate 8 including a semiconductor material layer 10. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, in which the semiconductor material layer extends continuously from a top surface of the substrate 8 to a bottom surface of the substrate 8, or a semiconductor-on-insulator layer including the semiconductor material layer 10 as a top semiconductor layer disposed over a buried insulator layer (such as a silicon oxide layer).Shallow trench isolation structures 12 containing a dielectric material, such as silicon oxide, may be formed in an upper portion of the substrate 8. Suitable doped semiconductor wells, such as p-wells and n-wells, may be formed within each of the regions, which may be laterally enclosed by a portion of the shallow trench isolation structures 12. Field-effect transistors may be formed over the upper surface of the substrate 8. For example, each of the field-effect transistors may include active source / drain regions 14, a semiconductor channel 15 comprising a surface portion of the substrate 8 extending between the active source / drain regions 14, and a gate structure 20. Each of the gate structures 20 may include a gate dielectric 22, a gate electrode strip 24, a gate cap dielectric 28, and a gate spacer dielectric 26.A source / drain metal-semiconductor alloy active region 18 may be formed on each of the source / drain active regions 14. Although planar field-effect transistors are illustrated in the drawings, embodiments are expressly contemplated in which the field-effect transistors additionally or alternatively comprise fin field-effect transistors (FinFETs), wrap-around gate field-effect transistors (GAA-FETs), or any other type of field-effect transistors (FETs).

[0013] The exemplary structure may include a memory array region 50, in which an array of memory elements may subsequently be formed, and a peripheral region 52, in which logic components that support the operation of the array of memory elements may be formed. In one embodiment, devices (such as field-effect transistors) in the memory array region 50 may include bottom electrode access transistors that provide access to bottom electrodes of memory cells to be subsequently formed. Top electrode access transistors that provide access to top electrodes of memory cells to be subsequently formed may be formed in the peripheral region 52 in this processing step.

[0014] Devices (such as field-effect transistors) in the peripheral region 52 may provide functions that may be required to operate the array of memory cells to be subsequently formed. In particular, devices in the peripheral region may be configured to control the programming, erasing, and reading of the array of memory cells. For example, the devices in the peripheral region may include a sense circuit and / or a top electrode bias circuit. The devices formed on the top surface of the substrate 8 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry 75.

[0015] Subsequently, various interconnect-level structures may be formed prior to the formation of an array of back-gate fin field-effect transistors, which are referred to herein as lower interconnect-level structures (Lo, L1, L2). If a two-dimensional array of TFTs is subsequently to be formed over two levels of interconnect-level metal lines, the lower interconnect-level structures (Lo, L1, L2) may include an interconnect-level structure Lo, a first interconnect-level structure L1, and a second interconnect-level structure L2. The dielectric material layers may, for example, include a contact-level dielectric material layer 31A, a first metal line-level dielectric material layer 31B, and a second line-and-via-level dielectric material layer 32.Various metal interconnect structures embedded in dielectric material layers can then be formed over the substrate 8 and the components (such as the field effect transistors).The metal interconnect structures may include device contact via structures 41V formed in the dielectric material layer at contact level 31A (interconnect level structure Lo) contacting a corresponding component of the CMOS circuit 75, first metal line structures 41L formed in the first dielectric material layer at metal line level 31B (interconnect level structure L1), first metal line via structures 42V formed in a lower portion of the second dielectric material layer at line-and-via level 32, and second metal line structures 42L formed in an upper portion of the second dielectric material layer at line-and-via level 32 (interconnect level structure L2).

[0016] Each of the dielectric material layers (31A, 31B, and 32) may include a dielectric material, such as an undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (41V, 41L, 42V, and 42L) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metallic filler material. Each of the metal conductive layers may include TiN, TaN, WN, TiC, TaC, and WC, and each of the metallic filler material portions may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the disclosure may also be used.In one embodiment, the first metal via structures 42V and the second metal line structures 42L may be formed as integrated line and via structures by a double damascene process, and the second metal via structures 43V and the third metal line structures 43L may be formed as integrated line and via structures.

[0017] The dielectric material layers (31A, 31B, and 32) may be arranged in a lower level relative to an array of memory cells to be subsequently formed. Thus, the dielectric material layers (31A, 31B, and 32) are referred to herein as lower-level dielectric material layers, that is, as layers of dielectric material arranged in a lower level relative to the array of memory cells to be subsequently formed. The metal interconnect structures (41V, 41L, 42V, and 42L) are referred to herein as lower-level metal interconnect structures.A subset of the metal interconnect structures (41V, 41L, 42V, and 42L) includes lower-level metal lines (such as the third metal line structures 42L) embedded in the lower-level dielectric material layers and having upper surfaces within a horizontal plane comprising a top surface of the lower-level dielectric material layers. Typically, the total number of metal line levels within the lower-level dielectric material layers (31A, 31B, and 32) may range from 1 to 3.

[0018] The exemplary structure may include various device regions, including a memory array region 50 in which at least one array of non-volatile memory cells may subsequently be formed. For example, the at least one array of non-volatile memory cells may include resistive random access memory (RRAM or ReRAM), magnetic / magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (FeRAM), and phase-change memory (PCM) devices. The exemplary structure may also include a peripheral logic region 52 in which electrical connections may subsequently be formed between each of the arrays of non-volatile memory cells and peripheral circuitry including field-effect transistors.Portions of the memory array region 50 and the logic region 52 may be used to form various elements of the peripheral circuitry.

[0019] Referring to Fig. 1B, an array 95 of non-volatile memory cells and TFT select devices may be formed in the memory array region 50 over the second interconnect level L2 structure. The details regarding the structure and processing steps for the array 95 of non-volatile, gate-controlled ferroelectric memory cells are described in detail below. A third interconnect level dielectric material layer 33 may be formed during the formation of the array 95 of non-volatile, gate-controlled ferroelectric memory cells. The group of all structures formed at the array 95 level of non-volatile memory cell devices and gate-controlled ferroelectric memory cell devices is referred to herein as a third interconnect level L3 structure.

[0020] Referring to Fig. 1C, third interconnect-level metal interconnect structures (43V, 43L) may be formed in the third interconnect-level dielectric material layer 33. The third interconnect-level metal interconnect structures (43V, 43L) may include second metal via structures 43V and third metal lines 43L. Additional interconnect-level structures may subsequently be formed and are referred to herein as upper interconnect-level structures (L4, L5, L6, L7). For example, the upper interconnect-level structures (L4, L5, L6, L7) may include a fourth interconnect-level structure L4, a fifth interconnect-level structure L5, a sixth interconnect-level structure L6, and a seventh interconnect-level structure L7.The fourth interconnect level structure L4 may include a fourth interconnect level dielectric material layer 34 having fourth interconnect level metal interconnect structures (44V, 44L) formed therein, which may include third metal via structures 44V and fourth metal lines 44L. The fifth interconnect level structure L5 may include a fifth interconnect level dielectric material layer 35 having fifth interconnect level metal interconnect structures (45V, 45L) formed therein, which may include fourth metal via structures 45V and fifth metal lines 45L. The sixth interconnect level structure L6 may include a sixth interconnect level dielectric material layer 36 having sixth interconnect level metal interconnect structures (46V, 46L) formed therein, which may include fifth metal via structures 46V and sixth metal lines 46L.The seventh interconnect level structure L7 may include a seventh interconnect level dielectric material layer 37 having sixth interconnect level metal via structures (47L) formed therein (which are seventh interconnect level metal interconnect structures) and metal bonding pads 47B. The metal bonding pads 47B may be configured for solder bonding (for which C4 ball bonding or wire bonding may be used), or may be configured for metal-to-metal bonding (such as copper-to-copper bonding).

[0021] Each of the interconnect-level dielectric material layers may be referred to as an interconnect-level dielectric material (ILD) layer 30 (i.e., 31A, 31B, 32, 33, 34, 35, 36, and 37). Each of the interconnect-level metal interconnect structures may be referred to as a metal interconnect structure 40. Each continuous combination of a metal via structure and an overlying metal line disposed within a same interconnect-level structure (L2-L7) may be formed sequentially as two individual structures using two individual damascene processes, or may be formed simultaneously as a unitary structure using a dual damascene process.Each of the metal interconnect structures 40 (i.e., 41V, 41L, 42V, 42L, 43V, 43L, 44V, 44L, 45V, 45L, 46V, 46L, 47V, 47B) may include a respective metal liner (such as a layer of TiN, TaN, or WN having a thickness in a range of 2 nm to 20 nm) and a respective metallic fill material (such as W, Cu, Co, Mo, Ru, other elemental metals, or an alloy, or a combination thereof). Other suitable materials for use as a metal liner and metallic fill material are contemplated within the scope of the disclosure. Various dielectric etch stop material layers and dielectric cap layers may be inserted between vertically adjacent pairs of ILD layers 30, or may be integrated into one or more of the ILD layers 30.

[0022] Although the present disclosure is described using an embodiment in which the array 95 of non-volatile memory cells and TFT select devices may be formed as a component of a third interconnect level structure L3, embodiments are also expressly contemplated herein in which the array 95 of non-volatile memory cells and TFT select devices may be formed as components of any other interconnect level structure (e.g., L1-L7). Further, although the present disclosure is described using an embodiment in which a set of eight interconnect level structures is formed, embodiments in which a different number of interconnect level structures are used are also expressly contemplated herein.Furthermore, embodiments are also expressly contemplated herein in which two or more arrays 95 of non-volatile memory cells and TFT select devices may be provided within multiple interconnect-level structures in the memory array region 50. Although the present disclosure is described using an embodiment in which an array 95 of non-volatile memory cells and TFT select devices may be formed in a single interconnect-level structure, embodiments are also expressly contemplated herein in which an array 95 of non-volatile memory cells and TFT select devices may be formed across two vertically adjacent interconnect-level structures.

[0023] The Fig. 2A-2N are vertical cross-sectional views illustrating the formation of a memory structure 200 in accordance with various embodiments of the present disclosure. Referring to Fig. 2A, a first dielectric layer 102 may be formed on a substrate 100. The substrate 100 may be any suitable substrate, such as an amorphous silicon substrate or a polysilicon semiconductor device substrate. In other embodiments, the substrate 100 may be the third dielectric material layer at interconnect level 33, as shown in Fig. 1C. The first dielectric layer 102 may be a pre-oxide layer formed on the substrate 100, for example, formed by a thermal process. In other embodiments, the first dielectric layer 102 may include a dielectric material such as silicon oxide (SiO2), undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. The first dielectric layer 102 may be deposited by any of a number of suitable deposition processes or grown over a dielectric material layer on interconnect level 30.

[0024] A photoresist layer 114 may be applied over the first dielectric layer 102. The photoresist layer 114 may be lithographically patterned to form a line and space structure having photoresist stripes extending along the first horizontal direction. An anisotropic etch process may be performed to etch the unmasked portions of the first dielectric layer 102. Lower gate trenches 103A and 103B extending along the first horizontal direction may be formed in areas not masked by the photoresist stripes. The anisotropic etch process may use any suitable etch process, such as a wet or dry etch process. The photoresist layer 114 may then be removed, for example, by ashing.

[0025] Referring to the Fig. 2A and Fig. 2B, the first wordline 120A and the second wordline 120B (e.g., lower gates) may be formed in the lower gate trenches 103A and 103B, respectively. In particular, an electrically conductive material may be deposited on the first dielectric layer 102 and in the lower gate trenches 103A and 103B. Herein, "suitable electrically conductive materials" may include copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, or the like. Other suitable electrically conductive materials are also within the contemplated scope of the disclosure.

[0026] The electrically conductive material may be deposited using any suitable deposition process. A "suitable deposition process" may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high-density plasma CVD (HDPCVD) process, a metal-organic CVD (MOCVD) process, a plasma-enhanced CVD (PECVD) process, a sputtering process, laser ablation, or the like.

[0027] A planarization process, such as a chemical mechanical polishing (CMP) process or the like, may then be performed to remove excess electrically conductive material from the top surface of the first dielectric layer 102 and to make the top surfaces of the wordlines 120A, 120B coplanar with the top surface of the first dielectric layer 102. The wordlines 120A, 120B may extend parallel to each other across the substrate 100. The wordlines 120A, 120B may be spaced apart according to a desired pitch between TFT devices.

[0028] Referring to Fig. 2C, a high-k dielectric layer 104 may be deposited on the wordlines 120A, 120B and the first dielectric layer 102. The high-k dielectric layer 104 may be formed by depositing any suitable high-k dielectric material using any suitable deposition process. Here, "suitable high-k dielectric materials" may have a dielectric constant greater than 3.9 and may include, but are not limited to, silicon nitride, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf 0,5 Zr 0,5O2) (HZO)), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), but are not limited to these. The scope of the disclosure also includes other suitable dielectric materials. In various embodiments, the high-k dielectric layer 104 may have a thickness t hk in the range of 0.5 - 5.0 nm, such as 1 - 4 nm, but larger or smaller thicknesses can also be used.

[0029] A channel layer 140 may be deposited on the high-k dielectric layer 104. The channel layer 140 may be formed by depositing any suitable semiconductor material using any suitable deposition process. Here, "suitable semiconductor materials" may include polysilicon, amorphous silicon, or a semiconductor oxide, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaOx, InOx, or the like. The scope of the disclosure also includes other suitable semiconductor materials.

[0030] A second dielectric layer 106 may be deposited on the channel layer 140. For example, the second dielectric layer 106 may be formed by depositing a dielectric material, such as silicon oxide or any other suitable high-k dielectric material, using any suitable deposition technique.

[0031] Referring to Fig. 2D, a photoresist layer 114 may be formed over the second dielectric layer 106. In a manner as discussed above, the photoresist layer 114 may be lithographically patterned. The pattern of the photoresist layer 114 may be transferred to the second dielectric layer 106 to form source trenches 105A, 105B and a common drain trench 107. For example, the second dielectric layer 106 may be etched using the photoresist layer 114 as a mask using any suitable etching process.

[0032] Referring to the Fig. 2D and Fig. 2E, an electrically conductive material may be deposited on the second dielectric layer 106 and in the trenches 105A, 105B, 107 to form a first source electrode 122A and a second source electrode 122B in the source trenches 105A, 105B, respectively, and to form a common drain electrode 124 in the drain trench 107. The electrodes 122A, 122B, 124 may be formed from any suitable electrically conductive material using any suitable deposition process. The top surfaces of the electrodes 122A, 122B, 124 and the second dielectric layer 106 may be planarized, for example, using a CMP process, to form a multi-gate transistor 210.

[0033] Referring to Fig. 2F, a memory stack 150S may be formed on the electrodes 122A, 122B, 124 and the second dielectric layer 106. The memory stack 150S may be formed by sequentially depositing different layers of a memory cell. In some embodiments, the memory cell stack 150 may include, for example, a bottom electrode layer 153, a non-magnetic metallic buffer layer 154, a synthetic antiferromagnetic layer 160, a non-magnetic tunnel barrier layer 155, a free magnetization layer 156, a top electrode layer 157, and a metallic etch mask layer 158. The layers within the memory cell stack 150S may be deposited by a corresponding chemical vapor deposition process or a corresponding physical vapor deposition process.

[0034] Each of the layers within stack 150S can be deposited as a planar cap material layer having a uniform thickness throughout. The non-magnetic metallic buffer layer 154, the synthetic antiferromagnetic layer 160, the non-magnetic tunnel barrier layer 155, and the free magnetization layer 156 are collectively referred to as memory material layers. In other words, the memory material layers are formed between the bottom electrode layer 153 and the top electrode layer 157.

[0035] Although the present disclosure is described using an embodiment in which the memory material layers comprise the non-magnetic metallic buffer layer 154, the synthetic antiferromagnetic layer 160, the non-magnetic tunnel barrier layer 155, and the free magnetization layer 156, the methods and structures of the present disclosure may be applied to any structure in which the memory material layers comprise a stack of different layers provided between a bottom electrode layer 153 and a top electrode layer 157, as well as material layers capable of storing information in any manner.Modifications of the present disclosure are also expressly contemplated herein in which the memory material layers comprise a phase change memory material, a ferroelectric memory material, or a vacancy modulated conductive oxide material.

[0036] The bottom electrode layer 153 contains at least one non-magnetic metallic material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, an alloy thereof, and / or a combination thereof. Other suitable materials within the contemplated scope of the disclosure may also be used. For example, the bottom electrode layer 153 may contain or consist essentially of an elemental metal, such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the bottom electrode layer 153 may range from 10 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0037] The non-magnetic metallic buffer layer 154 contains a non-magnetic material that can serve as a seed layer. In particular, the non-magnetic metallic buffer layer 154 can provide a crystalline template structure that aligns polycrystalline grains of the materials of the synthetic antiferromagnetic layer 160 along specific directions, maximizing the magnetization of a reference layer within the synthetic antiferromagnetic layer 160. The non-magnetic metallic buffer layer 154 can contain Ti, a CoFeB alloy, a NiFe alloy, ruthenium, or a combination thereof. The thickness of the non-magnetic metallic buffer layer 154 can range from 3 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0038] The synthetic antiferromagnetic layer (SAF layer) 160 may comprise a layer stack of a ferromagnetic hard layer 161, an antiferromagnetic coupling layer 162, and a reference magnetization layer 163. Both the ferromagnetic hard layer 161 and the reference magnetization layer 163 may each have a fixed magnetization direction. The antiferromagnetic coupling layer 162 provides an antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 161 and the magnetization of the reference magnetization layer 163, such that the magnetization direction of the ferromagnetic hard layer 161 and the magnetization direction of the reference magnetization layer 163 remain fixed during operation of the memory cells to be subsequently formed. The ferromagnetic hard layer 161 may contain a hard ferromagnetic material such as PtMn, IrMn, RhMn, FeMn, OsMn, etc.

[0039] The reference magnetization layer 163 may contain a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the contemplated scope of the disclosure may also be used. The antiferromagnetic coupling layer 162 may contain ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 162 may be selected such that the exchange interaction induced by the antiferromagnetic coupling layer 162 stabilizes the relative magnetization directions of the hard ferromagnetic layer 161 and the reference magnetization layer 163 in opposite directions, i.e., in an antiparallel orientation. In one embodiment, the net magnetization of the SAF layer 160 is achieved by adjusting the magnitude of the magnetization of the ferromagnetic hard layer 161 to the magnitude of the magnetization of the reference magnetization layer 163.The thickness of the SAF layer 160 can range from 5 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0040] The non-magnetic tunnel barrier layer 155 may include a tunnel barrier material, which may be an electrically insulating material having a thickness that enables electron tunneling. For example, the non-magnetic tunnel barrier layer 155 may include magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials within the contemplated scope of the disclosure may also be used. The thickness of the non-magnetic tunnel barrier layer 155 may range from 0.7 nm to 1.3 nm, although smaller and larger thicknesses may also be used.

[0041] The free magnetization layer 156 contains a ferromagnetic material having two stable magnetization directions aligned parallel or antiparallel to the magnetization direction of the reference magnetization layer 163. The free magnetization layer 156 contains a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the contemplated scope of the disclosure may also be used. The thickness of the free magnetization layer 156 may range from 1 nm to 6 nm, although smaller and larger thicknesses may also be used.

[0042] The upper electrode layer 157 comprises an upper electrode material, which may include any non-magnetic material that may be used for the lower electrode layer 153. Examples of metallic materials that may be used for the upper electrode layer 157 include, but are not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, an alloy thereof, and / or a combination thereof. Other suitable materials within the contemplated scope of the disclosure may also be used. For example, the lower electrode layer 153 may include or consist essentially of an elemental metal, such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the upper electrode layer 157 may range from 10 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0043] The metallic etch mask layer 158 includes a metallic etch stop material having high resistance to an anisotropic etch process to be subsequently used to etch a dielectric material (including, for example, undoped silicate glass, a doped silicate glass, or organosilicate glass). In one embodiment, the metallic etch mask layer 158 may include a conductive metal nitride material (such as TiN, TaN, or WN) or a conductive metal carbide material (such as TiC, TaC, or WC). In one embodiment, the metallic etch mask layer 158 includes and / or consists essentially of TiN. The metallic etch mask layer 158 may be deposited by chemical vapor deposition or physical vapor deposition.The thickness of the metallic etch mask layer 158 may range from 2 nm to 20 nm, such as from 3 nm to 10 nm, although smaller and larger thicknesses may also be used.

[0044] Referring to Fig. 2G, the metallic etch mask 158 may be patterned to form a structure that masks the underlying memory stack 150S. The pattern of the metallic etch mask 158 may be transferred to the underlying memory stack 150S through an anisotropic etch process to form a memory cell 150. The metallic etch mask 158 may be consumed by the anisotropic etch process that forms the memory cell 150.

[0045] Referring to Fig. 2H, a third dielectric layer 108 may be formed on the second dielectric layer 106 to cover the memory cell 150 and the source electrodes 122A, 122B, as well as the common drain electrode 124. The third dielectric layer 108 may be formed from any suitable dielectric material using any suitable deposition process.

[0046] Referring to Fig. 2I, a patterned photoresist layer 114 may be formed over the third dielectric layer 108. The pattern formed from the photoresist layer 114 may be transferred to the third dielectric layer 108 to form first via channels 109 exposing the upper surfaces of the source electrodes 122A, 122B. Patterning may include any suitable etching process, such as wet or dry etching processes.

[0047] Referring to Fig. 2J, the photoresist layer 114 may be removed, and any suitable electrically conductive material may be deposited in the first via channels 109 to form first via contacts 126. In particular, the first via contacts 126 may extend through the third dielectric layer and may electrically contact the source electrodes 122A, 122B. A planarization process, such as CMP, may be performed to planarize the top surfaces of the first via contacts 126 and the third dielectric layer 108.

[0048] Referring to Fig. 2K, a patterned photoresist layer 114 may be formed on the third dielectric layer 108. Then, the third dielectric layer 108 may be patterned using the photoresist layer PR as a mask to form a second via channel 111. Patterning may include any suitable etching process, such as wet or dry etching processes.

[0049] Referring to the Fig. 2K and Fig. 2L, the photoresist layer 114 may be removed, and any suitable electrically conductive material may be deposited in the second via channel 111 to form a second via contact 128. The second via contact 128 may electrically contact a top electrode of the memory cell 150. A planarization process, such as CMP, may be performed to planarize the top surfaces of the second via contact 128 and the third dielectric layer 108.

[0050] Referring to Fig. 2M, a fourth dielectric layer 110 may be formed on the third dielectric layer 108. The fourth dielectric layer 110 may be formed from any suitable dielectric material using any suitable deposition process.

[0051] A patterned photoresist layer 114 may be formed on the fourth dielectric layer 110. The fourth dielectric layer 110 may be etched using any suitable etching process by using the photoresist layer 114 as a mask to form source trenches 113 exposing the first via contacts 126 and a bit trench 115 exposing the second via contact 128.

[0052] Referring to the Fig. 2M and Fig. 2N, the photoresist layer 114 may be removed, and any suitable electrically conductive material may be deposited to form source lines 130 in the source channels 113, as well as a bit line 132 in the bit trench 115. The upper surfaces of the lines 130, 132, and the fourth dielectric layer 110 may be planarized, for example, using a CMP process, to form a memory structure including a multi-gate transistor 210.

[0053] The channel layer 140 may include first and second source regions 140S1, 140S2, first and second channel regions 140C1, 140C2, and a drain region 140D. The first and second source electrodes 122A, 122B may overlap with the first and second source regions 140S1, 140S2, respectively. The first and second word lines 120A, 120B may overlap with the first and second channel regions 140C1, 140C2, respectively, and the drain electrode 124 may overlap with the drain region 140D.

[0054] In operation, the source lines 130 can provide current to the source electrodes 122A, 122B via the via contacts 126 and the underlying source regions 140S1, 140S2. The word lines 120A, 120B can act as gates to control the flow of current from the first and second source electrodes 122A, 122B, and the first and second source regions 140S1, 140S2, respectively, through the first and second channel regions 140C1, 140C2, respectively, via the drain region 140D to the common drain electrode 124.

[0055] Current may be provided to a lower electrode 153 of memory cell 150 from drain electrode 124. Bitline 132 may be electrically connected to an upper electrode of memory cell 150 via via contact 128. Consequently, the dual-gate structure of transistor 210 may provide improved threshold voltage control. Furthermore, transistor 210 may be configured to provide current from both source electrodes 122A, 122B to drain electrode 124 via first and second channel regions 140C1, 140C2. Thus, transistor 210 may provide twice the current to memory cell 150 compared to a similar transistor having only a gate and a source electrode. Thus, transistor 210 may provide an improved RAM circuit with respect to memory cell 150.

[0056] The Fig. 3A-3D are vertical cross-sectional views illustrating the formation of an alternative embodiment of a memory structure 300 consistent with other embodiments of the present disclosure. Fig. Figure 4 is a perspective view of memory structure 300. Memory structure 300 may be similar to memory structure 200 and formed using similar methods. Consequently, only the differences between these structures will be discussed in detail.

[0057] Referring to Fig. 3A, a patterned photoresist layer 114 may be formed on the second dielectric layer 106 of a transistor 210, which may be formed as described above with reference to the Fig. 2A-2E. Furthermore, in various embodiments, the second dielectric layer 106 may be formed from a high-k dielectric material.

[0058] Referring to Fig. 3B, the second dielectric layer 106 may be etched using the photoresist layer 114 as a mask to form upper gate trenches 117A and 117B. The second dielectric layer 106 may be etched using any suitable etching process. After etching, the photoresist layer 114 may be removed. As shown in Fig. 3B, portions of the second dielectric layer 106 may remain beneath the upper gate trenches 117A and 117B.

[0059] Referring to the Fig. 3B and Fig. 3C, any suitable electrically conductive material may be deposited to form first and second upper gate electrodes 121A, 121B in the upper gate trenches 117A, 117B, respectively. Upper surfaces of the upper gate electrodes 121A, 121B and the second dielectric layer 106 may be planarized, for example, using a CMP process, to form a multi-gate transistor 310.

[0060] Referring to Fig. 3D, a third dielectric layer 108 and a fourth dielectric layer 110, a memory cell 150, via contacts 126, 128, source lines 130, and a bit line 132 may be formed on the transistor 310 using processes as described above with respect to the Fig. 2F - 2N described to form a memory structure 300.

[0061] Referring to the Fig. 3D and Fig. 4, the first source electrode 122A and the second source electrode 122B may overlap with the first source region 140S1 and the second source region 140S2 of the channel layer 140, respectively. The upper gate electrodes 121A, 121B may overlap with the word lines 120A, 120B on opposite sides of the first and second channel regions 140C1, 140C2 of the channel layer 140. Consequently, the memory structure 300 may include first and second multi-gate structures 125A, 125B, each including the overlapped upper gate electrodes 121A, 121B and overlapped portions of the word lines 120A, 120B (e.g., the lower gate electrodes). The drain electrode 124 may overlap a common drain region 140D of the channel layer 140.

[0062] In some embodiments, the memory structure 300 may include strips of dielectric material 112 disposed between the source and drain electrodes 122A, 122B, 124 and the upper gate electrodes 121A, 121B. In particular, the strips of dielectric material 112 may be configured to electrically isolate the upper gate electrodes 121A, 121B from the source and drain electrodes 122A, 122B, 124.

[0063] During operation, the first multi-gate structure 125A may be configured to control the current flow through the first channel region 140C1 to the drain region 140D according to a voltage applied thereto. Likewise, the second multi-gate structure 125B may be configured to control the current flow through the second channel region 140C1 to the drain region 140D according to a voltage applied thereto. Current may flow from the drain region 140D of the channel layer before flowing through the drain electrode 124 into the memory cell 150. Current may be output from the memory cell 150 to the bit line 132.

[0064] Consequently, the multi-gate structures 125A, 125B can each provide increased threshold voltage control compared to single-gate structures. Furthermore, by providing the dual multi-gate structures 125A, 125B, the drain electrode 124 can be supplied with twice the current than would be the case in a similar structure having only a dual gate structure.

[0065] The Fig. 5A-5I are each vertical cross-sectional views illustrating a sequence of steps in forming a memory structure 500 in accordance with various other embodiments of the present disclosure. Fig. 6 is a perspective view of memory structure 500. Memory structure 500 may be similar to memory structure 200 and formed using similar methods. Consequently, only the differences between these structures will be discussed in detail.

[0066] Referring to Fig. 5A, a patterned photoresist layer 114 may be formed on the second dielectric layer 106 of a semiconductor structure, which may be formed as described above with reference to the Fig. 2A-2C. In various embodiments, the second dielectric layer 106 may be formed from a high-k dielectric material. The second dielectric layer 106 may be etched using any suitable etching process to form source trenches 105A, 105B and drain trenches 107A, 107B. The photoresist layer 114 may be removed after the etching process.

[0067] Referring to Fig. 5B, any suitable electrically conductive material may be deposited using any suitable deposition method to form first and second source electrodes 122A, 122B in the source channels 105A, 105B, and first and second drain electrodes 124A, 124B in the drain trenches 107A, 107B. The electrically conductive material may be deposited using any suitable method. The top surfaces of the electrodes 122A, 122B, 124A, 124B and the second dielectric layer 106 may be planarized, for example, using a CMP process.

[0068] Referring to Fig. 5C, a patterned photoresist layer PR may be formed on the second dielectric layer 106. The second dielectric layer 106 may be etched using the photoresist layer 114 as a mask to form upper gate trenches 117A, 117B. The second dielectric layer 106 may be etched using any suitable etching process. After etching, the photoresist layer 114 may be removed. As shown in Fig. 5C, portions of the second dielectric layer 106 may remain beneath the upper gate trenches 117A and 117B.

[0069] Referring to the Fig. 5C and Fig. 5D, any suitable electrically conductive material may be deposited to form first and second upper gate electrodes 121A, 121B in the upper gate trenches 117A, 117B. Upper surfaces of the upper gate electrodes 121A, 121B and the second dielectric layer may be planarized, for example, using a CMP process, to form a multi-gate transistor 410.

[0070] Referring to Fig. 5E, a patterned photoresist layer 114 may be formed on transistor 410. Photoresist layer 114 may include an opening 119 exposing drain electrodes 124.

[0071] Referring to the Fig. 5E and Fig. 5F, any suitable electrically conductive material may be deposited using any suitable deposition process to form an electrical contact 152 in the opening 119. Then, the photoresist layer 114 may be removed. For example, the photoresist layer 114 may be removed using a laser ablation process such that any electrically conductive material deposited thereon is removed during the removal process. The electrical contact 152 may be a metal line or layer that electrically connects the drain electrodes 124A, 124B.

[0072] Referring to Fig. 5G, a memory stack 150S may be formed on the electrodes 122A, 122B, 124 and the second dielectric layer 106. The memory stack 150S may be formed by sequentially depositing different layers of a memory cell, as described above with respect to Fig. 2F discussed.

[0073] Referring to the Fig. 5G and Fig. 5H, a metallic etch mask layer 158 may be patterned in the memory stack 150S. The pattern of the metallic etch mask layer 158 may be transferred to the remaining layers of the memory stack 150S using any suitable etching process to form a memory cell 150. In some embodiments, the memory cell 150 may be formed directly on the electrical contact 152. However, in other embodiments, the memory cell 150 may be formed directly on the drain electrodes 124A, 124B. In other words, the electrical contact 152 and the memory cell 150 do not overlap in a vertical direction perpendicular to a plane of the channel layer.

[0074] Referring to Fig. 5I, a third and a fourth dielectric layer 108, 110, via contacts 126, 128, source lines 130 and a bit line 132 may be formed by processes as described above with respect to the Fig. 2F - 2N described to form a memory structure 500.

[0075] Referring to the Fig. 5I and Fig. 6, the electrical contact 152 may electrically connect the drain electrodes 124 to the memory cell 150. Consequently, the electrical contact 152 may form a common drain that provides current to the memory cell from both drain electrodes 124.

[0076] Although the Fig. While FIGS. 2A-6 illustrate the fabrication of memory structures 200, 300, 500 combining an MJT memory cell 150 and a multi-gate transistor 210, 310, 410, in various embodiments, the memory cell 150 may also include other types of memory devices. For example, the memory cell 150 may be a metal-ferro-metal capacitor, a magnetoresistive random access memory (MRAM) cell, a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FeRAM) cell, a phase-change random access memory (PCRAM) cell, or a combination thereof.

[0077] Fig. For example, Figure 7A is a cross-sectional view of a memory cell 150 that may be used in the memory structures 300, 500 in accordance with various embodiments of the present disclosure. Referring to Fig. 7A, in some embodiments, the memory cell 150 may be a PCM memory cell including a bottom electrode 400, a top electrode 403, a heater element 401, and a phase-change material layer 402. The phase-change material layer 402 may function as a data storage layer.

[0078] The heating element 401 may be formed from a thin layer of TiN, TaN, or TiAlN having a thickness in a range of about 5 to about 15 nm to provide Joule heating of the phase-change material layer 402. Furthermore, the heating element 401 may serve as a heat sink during quenching (while the current applied to the heating element 401 is abruptly discontinued to "freeze" the amorphous phase).

[0079] In some embodiments, the phase change material layer 402 comprises a binary system material of Ga-Sb, In-Sb, In-Se, Sb-Te, Ge-Te, and Ge-Sb; a ternary system material of Ge-Sb-Te, In-Sb-Te, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, and Ga-Sb-Te; or a quaternary system material of Ag-In-Sb-Te, Ge-Sn-Sb-Te, Ge-Sb-Se-Te, Te-Ge-Sb-S, Ge-Sb-Te-O, and Ge-Sb-Te-N. In some embodiments, the phase change material layer 402 comprises a chalcogenide alloy comprising one or more elements from Group VI of the Periodic Table, such as a GST, a Ge-Sb-Te alloy (e.g., Ge2Sb2Te5), having a thickness of 5 to 100 nm.

[0080] The phase-change material layer 402 may comprise other phase-change resistive materials, such as metal oxides including tungsten oxide, nickel oxide, copper oxide, etc. The phase transition between the crystalline phase and the amorphous phase of the phase-change material is related to the interplay between the long-range order and the short-range order of the phase-change material's structure. For example, the breakdown of the long-range order creates the amorphous phase. The long-range order in the crystalline phase enables electrical conduction, while the amorphous phase inhibits electrical conduction and results in high electrical resistance. To tune the properties of the phase-change material layer 402 for different requirements, the phase-change material layer 402 can be doped with different amounts of different elements to adjust the ratio between long-range order and short-range order within the material's interconnect structure.The doped element can be any element used for semiconductor doping, for example through the use of ion implantation.

[0081] Fig. 7B is a cross-sectional view of another embodiment of the memory cell 150 that may be used in the memory structures 200, 300, 500 in accordance with various embodiments of the present disclosure. Referring to Fig. 7B, in some embodiments, the memory cell 150 may be a PCRAM memory cell comprising a bottom electrode 400, a top electrode 403, and a ferroelectric material layer 405, such as a lead zirconate titanate (PZT) layer. The ferroelectric material layer 405 may function as a data storage layer.

[0082] In other embodiments, memory cell 150 may operate as a ferroelectric tunnel junction (FTJ). In particular, ferroelectric material layer 405 may be an FE tunnel barrier. The FE tunnel barrier may be a ferroelectric film thin enough to allow electrons to tunnel through it. For example, the FE tunnel barrier may be about 1 nanometer (nm) to about 50 nm thick, such as from about 5 nm to about 25 nm, or about 10 nm thick.

[0083] In various embodiments, a memory device is provided, which may include an array of memory structures 200, 300, 500. In some embodiments, the memory device may include multiple arrays of memory structures 200, 300, 500 stacked on the substrate 100.

[0084] Fig. 8 is a flow diagram illustrating steps for forming a memory structure 300, 500 in accordance with various embodiments of the present disclosure. Referring to the Fig. 8 and 2A-5I, at step 801, first and second word lines 120A, 120B may be formed in a first dielectric layer 102. For example, word lines 120A, 120B may be formed in trenches 103A, 103B formed in first dielectric layer 102.

[0085] At step 802, a high-k dielectric layer 104 may be deposited on the first dielectric layer 102. The high-k dielectric layer 104 may cover the word lines 120A, 120B. A channel layer 140 may then be deposited on the high-k dielectric layer 104.

[0086] At step 803, a second dielectric layer 106 may be deposited on the channel layer 140. At step 804, source electrodes 122A, 122B and one or two drain electrodes 124 may be formed in the second dielectric layer 106. In particular, the electrodes 122A, 122B, 124 may be formed in trenches 105A, 105B, 107A, and 107B formed in the second dielectric layer 106. If two drain electrodes 124 are formed, step 805 may include forming an electrical contact 152 that electrically connects the drain electrodes 124 to each other.

[0087] At step 805, a memory cell 150 may be formed on the drain electrode 124 or the electrical contact 152. The memory cell 150 may include an FTJ cell, an MRAM cell, an RRAM cell, an FeRAM cell, a PCRAM cell, or the like.

[0088] At step 806, a third dielectric layer 108 may be deposited on the second dielectric layer 106. In particular, the third dielectric layer 108 may cover the memory cell 150.

[0089] At step 807, via contacts 126, 128 may be formed in the third dielectric layer 108. In particular, the via contacts 126, 128 may be formed in via channels 109, 111 formed in the third dielectric layer 108.

[0090] At step 808, a fourth dielectric layer 110 may be deposited on the third dielectric layer 108. The fourth dielectric layer 110 may cover the via contacts 126, 128.

[0091] At step 809, source lines 130 and a bit line 132 may be formed in the fourth dielectric layer 110. For example, the source lines 130 may be formed in source channels 113, and the bit line 132 may be formed in a bit trench 115 formed in the fourth dielectric layer 110.

[0092] In various embodiments, a memory structure is provided that includes a memory cell 150 connected to a drain electrode 124 of a transistor 210, 310, 410. The transistor 210, 310, 410 may include a channel layer 140 having a common drain region 140D disposed between a first and a second channel region 140C1, 140C2. The transistor 210, 310, 410 may include gate electrodes (120A, 120B, 121A, 121B) that control current flow through the channel regions 140C1, 140C2 to the common drain region 140D. Consequently, the memory structure may provide improved threshold voltage control and higher current flow to the memory cell 150.

[0093] Various embodiments provide a memory structure comprising: a first word line 120A; a second word line 120B; a high-k dielectric layer disposed on the first word line 120A and the second word line 120B; a channel layer 140 disposed on the high-k dielectric layer 120A and comprising a semiconductor material; a first source electrode 122A and a second source electrode 122B electrically contacting the channel layer; a first drain electrode 124 disposed on the channel layer 140 between the first source electrode 122A and the second source electrode 122B; a memory cell 150 electrically connected to the first drain electrode 124; and a bit line 132 electrically connected to the memory cell 150.

[0094] Various embodiments provide a memory structure comprising: a first word line 120A; a second word line 120B; a high-k dielectric layer disposed on the first word line 120A and the second word line 120B; a channel layer 140 disposed on the high-k dielectric layer 120B and comprising a semiconductor material; a first source electrode 122A and a second source electrode 122B electrically contacting the channel layer 140; a first upper gate electrode 121A overlapping with a first channel region 140C1 of the channel layer and the first word line 120A; a second upper gate electrode 121B overlapping with a second channel region 140C2 of the channel layer 140 and the second word line 120B; a first drain electrode 124 disposed between the first source electrode 122A and the second source electrode 122B and in electrical contact with a drain region 140D of the channel layer 140;a memory cell 150 electrically connected to the first drain electrode 124; and a bit line 132 electrically connected to the memory cell 150.

[0095] Various embodiments provide a method of forming a memory structure, comprising: forming first and second word lines 120A, 120B on a substrate; depositing a high-k dielectric layer 104 on the first and second word lines 120A, 120B; depositing a channel layer 140 comprising a semiconductor material on the high-k dielectric layer; forming first and second source electrodes 122A, 122B, each electrically contacting a first source region 140S1 and a second source region 140S2 of the channel layer, respectively; forming a first drain electrode 124, which electrically contactes a drain region 140D of the channel layer 140, which is arranged between the first source region 140S1 and the second source region 140S2;Forming a first upper gate electrode 121A and a second upper gate electrode 121B, which overlap with the first word line 120A and the second word line 120B, respectively, and the first channel region 140C1 and the second channel region 140C2 of the channel layer 140, respectively; and forming a memory cell 150 that electrically contacts the first drain electrode 124.

Claims

[1] Memory structure (500) comprising: a first word line (120A); a second word line (120B); a high-k dielectric layer (104) disposed on the first word line and the second word line; a channel layer (140) disposed on the high-k dielectric layer and containing a semiconductor material; a first source electrode (122A) and a second source electrode (122B), wherein the first source electrode and the second source electrode each electrically contact the channel layer; a first drain electrode (124A) disposed on the channel layer between the first source electrode and the second source electrode; a memory cell (150) electrically connected to the first drain electrode; a bit line (132) electrically connected to the memory cell; a first upper gate electrode (121A) overlapping with the channel layer and the first word line; a second gate electrode (121B) overlapping with the channel layer and the second word line; a second drain electrode (124B) disposed on the channel layer between the first source electrode and the second source electrode; and an electrical contact (152) electrically connecting the first drain electrode and the second drain electrode; wherein the electrical contact electrically connects the first drain electrode and the second drain electrode to the memory cell. [2] The memory structure of claim 1, wherein: the first word line overlaps with a first channel region of the channel layer; the second word line overlaps with a second channel region of the channel layer; and the first drain electrode overlaps with a drain region of the channel layer arranged between the first channel region and the second channel region. [3] The memory structure of claim 1 or 2, wherein the channel layer contains an oxide semiconductor material. [4] A memory structure according to any one of the preceding claims, wherein the memory cell comprises a magnetic tunnel junction memory cell, MTJ memory cell, a magnetoresistive random access memory cell, MRAM cell, a resistive random access memory cell, RRAM cell, a ferroelectric random access memory cell, FeRAM cell, or a phase change random access memory cell, PCRAM cell. [5] A memory structure according to any one of the preceding claims, wherein: the first word line and the second word line are embedded in a first dielectric layer (102) disposed beneath the high-k dielectric layer; the first source electrode and the second source electrode and the first drain electrode are embedded in a second dielectric layer (106) disposed above the channel layer; the memory cell is embedded in a third dielectric layer (108) disposed over the second dielectric layer; and a first source line (130), a second source line (130) and the bit line are embedded in a fourth dielectric layer (110) arranged on the third dielectric layer. [6] The memory structure of claim 5, further comprising: Via connections (126) extending through the third dielectric layer and connecting the first source electrode to the first source line, connecting the second source electrode to a second source line, and electrically connecting the memory cell to the bit line. [7] A memory structure according to any one of the preceding claims, wherein: the first upper gate electrode is electrically connected to the first word line; and the second upper gate electrode is electrically connected to the second word line. [8] A memory structure according to any preceding claim, wherein the first upper gate electrode and the second upper gate electrode are electrically isolated from the channel layer, the first source electrode, the second source electrode and the first drain electrode by a dielectric layer (106). [9] The memory structure of claim 8, wherein the dielectric layer includes a high-k dielectric material. [10] Memory structure according to one of claims 1 to 7, further comprising: a further high-k dielectric layer (106) configured to electrically isolate the first upper gate electrode and the second upper gate electrode from the channel layer, the first source electrode, the second source electrode, the first drain electrode, and the second drain electrode. [11] Memory structure according to one of the preceding claims, further comprising: a source line (130) electrically connected to the first source electrode; and another source line (130) electrically connected to the second source electrode. [12] A method for manufacturing a memory structure (500), comprising: Forming a first word line (120A) and a second word line (120B) on a substrate (100); depositing a high-k layer (104) on the first word line and the second word line; depositing a channel layer (140) containing a semiconductor material on the high-k layer; Forming a first source electrode (122A) and a second source electrode (122B) that electrically contact a first source region and a second source region of the channel layer; Forming a first drain electrode (124A) electrically contacting a drain region of the channel layer disposed between the first source region and the second source region; Forming a first upper gate electrode (121A) and a second upper gate electrode (121B) that overlap the first word line and the second word line and a first channel region and a second channel region of the channel layer; Forming a memory cell (150) that electrically contacts the first drain electrode; Forming a second drain electrode (124B) electrically contacting the drain region; and Forming a contact (152) electrically connecting the first drain electrode and the second drain electrode to the memory cell.

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