Stackable 3D storage and manufacturing process

Abstract

Memory device (850) comprising: a resistive memory array (600) comprising a first resistive memory cell (613); a step contact structure (800) adjacent to the resistive memory array (600); an intermetal dielectric layer (803) over the step contact structure (800); a first diode (801, D1) and a second diode (801, D2) over the intermetal dielectric layer (803); a first conductive via (807) which electrically couples the first diode (801, D1) to a first resistor (R1) of the first resistive memory cell (613); and a second conductive via (807) which electrically couples the second diode (801, D2) to a second resistor (R2) of the first resistive memory cell (613).

Description

BACKGROUNDSemiconductor devices (devices) are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric material, layers of conductive material, and semiconductor layers over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated on a given area.Stackable 3D memories are known from the publications DE 10 2021 111 318 A1, DE 10 2020 123 746 A1, DE 10 2020 134 374 A1 and U.S. Pat. No. 2019) / 0 013 414 A1.The object is to improve such memory devices.The object is achieved by the memory components according to claims 1 and 8 and by the method according to claim 16.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with common industry practice. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 illustrates a cross-sectional view of a device structure that may be formed over a substrate, in accordance with some embodiments. FIGS. 2-7 illustrate perspective views, cross-sectional views, and top views of intermediate stages of manufacturing a 3D stackable resistive random access memory (RRAM) array embodiments. FIG. 8 illustrates a perspective view of a 3D memory device including the stackable 3D RRAM array and a first staircase contact structure, in accordance with some embodiments. FIGS. 9, 10A, and 10B illustrate cross-sectional views of intermediate steps in forming the first staircase contact structure, in accordance with some embodiments. FIG. 11 is a two-dimensional illustration illustrating a cross-sectional view of a stacked memory cell and the first staircase contact structure of the 3D memory device, in accordance with some embodiments. FIG. 12 is a circuit diagram of the equivalent circuit of the stacked memory cell according to some embodiments. FIG. 13 illustrates a cross-sectional view of an interconnect structure, in accordance with some embodiments. FIG. 14A illustrates a perspective view of a second 3D memory device including the stackable 3D RRAM array and a second staircase contact structure, in accordance with some other embodiments. FIG. 14B illustrates a cross-sectional view of the stair contact structure, in accordance with some embodiments. FIG. 15 is a two-dimensional illustration illustrating multiple cross-sectional views of a stacked memory cell and the second staircase contact structure of the second 3D memory device, in accordance with some embodiments. FIG. 16 illustrates a cross-sectional view of the stair contact structure, in accordance with some other embodiments. FIG. 17 is a two-dimensional illustration illustrating a cross-sectional view of a stacked memory cell and the staircase contact structure of the second 3D memory device, in accordance with some other embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments for implementing different features of the invention. In order to simplify the present disclosure, concrete examples of components and arrangements will be described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower / r / s," "above," "upper / r / s," and the like may be used herein to simplify the description to describe the relationship of an element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The object may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly.Various embodiments of the present disclosure provide a three-dimensional (3D) memory array (e.g., an RRAM memory array) that includes a plurality of stacked memory cells (e.g., 1T2R memory cells) and that includes forming a first diode over and electrically connected to a first resistor of the memory cell and a second diode over and electrically connected to a second resistor of the memory cell. Therefore, the first diode and the second diode may be referred to herein as BEOL compatible diodes. In addition, the 3D memory array and the staircase contact structure may be formed from a multilayer stack of materials used in the fabrication process. The resulting 3D memory array may also have a reduced height and / or an increasing device density. Further, embodiments of the present disclosure provide a memory cell (e.g., type 1T2R) that avoids problems with write disturbances in writes to a targeted resistance of the memory cell. For example, during a write operation to a non-referenced resistor of a memory cell, leakage currents are prevented from flowing through the bit line of the non-referenced resistor of the memory cell due to the diode electrically connected to the non-referenced resistor.FIGS. 1-7 illustrate cross-sectional views of various intermediate steps of fabricating a 3D memory array, in accordance with some embodiments. In FIG. 1, a device structure 103 is illustrated. The device structure 103 includes a substrate 50, which may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an isolation layer. The isolation layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or Galliumindiumarsenidphosphid; or combinations thereof.FIG. 1 further illustrates circuits of the device structure 103 that may be formed over the substrate 50. The circuits include active devices (e.g., transistors) on a top surface of the substrate 50. The transistors may include gate dielectric layers 202 over top surfaces of the substrate 50 and gate electrodes 204 over the gate dielectric layers 202. Source / drain regions 206 are provided in the substrate 50 on opposite sides of the gate dielectric layers 202 and the gate electrodes 204. Gate spacers 208 are formed along sidewalls of the gate dielectric layers 202 and separate the source / drain regions 206 from the gate electrodes 204 by appropriate lateral distances. In some embodiments, the transistors may be planar field effect transistors (FETs), fin field effect transistors (FinFETs), nano field effect transistors (nano FETs), or the like.A first ILD 210 surrounds and isolates the source / drain regions 206, the gate dielectric layers 202, and the gate electrodes 204, and a second ILD 212 overlies the first ILD 210. Source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and gate contacts 216 extend through the second ILD 212 and are electrically coupled to the gate electrodes 204. An interconnect structure 220 including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224 overlies the second ILD 212, the source / drain contacts 214, and the gate contacts 216. Although FIG. 1 illustrates two of the stacked dielectric layers 224, it should be understood that the interconnect structure 200 may include any number of stacked dielectric layers 224 having conductive features 222 provided therein. The interconnect structure 220 may be electrically connected to the gate contacts 216 and the source / drain contacts 214 to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure 220 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, and the like, or combinations thereof. Although FIG. 1 discusses transistors formed over the substrate 50, other active devices (e.g., diodes or the like) and / or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits.In FIG. 2, a first multilayer stack 101 is formed over the device structure 103 of FIG. 1. For simplicity and clarity, detailed features of the device structure 103 (e.g., the substrate 50, the transistors, the ILDs, and the interconnect structure 120) may be omitted in the following drawings. Although the first multilayer stack 101 is illustrated adjacent to and in physical contact with the device structure 103, any number of intermediate layers may be provided between the device structure 103 and the first multilayer stack 101. For example, one or more interconnect layers (e.g., redistribution structures) comprising conductive features in insulating layers (e.g., low-k dielectric layers) may be provided between the device structure 103 and the first multilayer stack 101. In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines to active devices embedded within device structure 103.As illustrated in FIG. 2, the first multilayer stack 101 according to some embodiments includes a first series 105 aof material layers and a second series 105 bof material layers stacked over the first series of material layers 105 a. In some embodiments, the first sequence 105 aof layers may be used in later formation of a first circuit (e.g., a first resistive random access memory (RRAM) cell) and the second sequence 105 bmay be used in later formation of a second circuit (e.g., a second RRAM cell) stacked over the first circuit in an arrangement such as a 3D RRAM stacked device. In addition, the first multilayer stack 101 may be further used in later formation of a first access transistor used to access the first circuit and a second access transistor used to access the second circuit. According to some embodiments, the first and second access transistors are formed as nanostructure field effect transistors (NSFETs) and coupled to the first circuit and the second circuit in a common access transistor configuration for a circuit design, such as a 1T2R-3D RRAM stacked device or the like.Although embodiments of the first multilayer stack 101 are illustrated as having two multilayer sequences (e.g., 105 aand 105 b) of material layers, it should be appreciated that any suitable number of multilayer sequences of material layers may be formed in the multilayer stack 101, depending on a desired design of a 3D RRAM stacked device. For example, the first multilayer stack 101 may be formed from more than two multilayer strings 105 of material layers, for example three, four or even more than four multilayer strings 105 of material layers. In addition, the NSFET transistors may be formed as common access transistors or the like. All such combinations of the first multilayer stack 101 and the access transistors are within the scope of the embodiments.According to some embodiments in which a 1T2R RRAM device is later formed, the first multilayer stack 101 is formed to include isolation layers 107, channel layers 109, metal line layers 111, and dielectric storage layers 113.The first multilayer stack 101 may be formed by first depositing a first layer of the metal line layers 111 over the device structure 103. The metal line layers 111 may include one or more layers such as adhesive layers, barrier layers, diffusion layers, and fill layers, and the like, and may be formed using metals and / or metal alloys such as aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), ruthenium (Ru), tungsten (W), platinum (Pt), alloys thereof, or the like. In some embodiments, the metal line layers 111 include an adhesive layer and a conductive layer. The adhesive layer may be formed of a metal nitride (e.g., titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, or the like). The conductive layer may be formed of a metal (e.g., tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or the like). The material of the adhesive layer is a material having good adhesion to the material of the upper surface of the device structure 103, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer. The adhesive layer and the conductive layer may each be formed by an acceptable deposition process such as atomic layer deposition, chemical vapor deposition, or the like. After deposition, the material of the metal line layers 111 may be planarized using an optional planarization process.A first layer of the dielectric storage layers 113 may be formed over the metal line layer 111. The dielectric storage layers 113 may be formed as a conformal thin oxide film. According to some embodiments, the dielectric storage layers 113 may be formed using one or more layers of acceptable dielectric material suitable for storing digital values, such as hafnium oxide (HfO 2); hafnium zirconium oxide (Hf (1-x) Zr x O 2); zirconium oxide (ZrO 2); titanium oxide (TiO 2); nickel oxide (NiO); tantalum oxides (TaO x); copper oxide (Cu 2 O); niobium pentoxide (Nb 2 O 5); Alumina (Al 2 O 3); combinations; or the like. The material of the dielectric storage layers 113 may be formed by an acceptable deposition process such as ALD, CVD, PVD, or the like. After deposition, the material of the dielectric storage layers 113 may be planarized using a process such as chemical mechanical planarization, an etch back process, combinations thereof, or the like.Once the dielectric storage layer 113 has been formed, a second layer of the metal line layers 111 may be formed over the dielectric storage layer 113 using any of the layers, materials, and processes suitable for forming the first layer of the metal line layers 111. In some embodiments, the second layer of the metal line layers 111 includes an adhesive layer and a conductive layer. The adhesive layer may be formed of a metal nitride having good adhesion to the material of the dielectric storage layer 113, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer. Once the metal line layer 111 has been deposited, the optional planarization process may be performed to planarize the material of the metal line layer 111.Once the second layer of metal layers 111 has been formed, a first layer of channel layers 109 may be formed over metal layer 111. According to some embodiments, the channel layer 109 may be formed by depositing a thin film oxide semiconductor material (e.g., zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), poly-Si, a-Si, indium gallium zinc tin oxide (IGZTO), combinations, or the like) using, for example, a deposition process such as CVD, ALD, PVD, combinations, or the like. However, any suitable materials and deposition processes may be used to form the channel layers 109. According to some embodiments, a material such as IGZO, IGZTO, or the like may be used to form the thin film oxide semiconductor material as the first layer of the channel layers 109. Such materials may be used to form structurally solid features at low temperatures, such as temperatures used in front-end-of-line (FEOL) processes. Therefore, the first layer of the channel layers 109 may be formed as a structurally solid layer of thin film oxide semiconductor material in an FEOL process for forming such channel layers 109.Once the first layer of channel layers 109 has been formed, a third layer of metal line layers 111 may be formed over dielectric storage layer 113 using any of the layers, materials, and processes suitable for forming the first layer of metal line layers 111. In some embodiments, the third layer of the metal line layers 111 includes an adhesive layer and a conductive layer. The adhesive layer may be formed of a metal nitride having good adhesion to the material of the channel layers 109, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer. Once the metal line layer 111 has been deposited, the optional planarization process may be performed to planarize the material of the metal line layer 111.Once the third layer of the metal line layers 111 has been formed, a second layer of the dielectric memory layers 113 may be formed over the metal line layer 111 using any of the layers, materials, and processes suitable for forming the first layer of the dielectric memory layers 113. In some embodiments, the second layer of the dielectric storage layers 113 may be formed as a conformal thin oxide film using the same oxide film material (e.g., zinc oxide (ZnO)) as the first layer of the dielectric storage layers 113. In other embodiments, different oxide film materials may be used for the first layer and the second layer of the dielectric storage layers 113.Once the second layer of the dielectric storage layers 113 has been formed, a fourth layer of the metal line layers 111 may be formed over the dielectric storage layer 113 using any of the layers, materials, and processes suitable for forming the first layer of the metal line layers 111. In some embodiments, the fourth layer of the metal line layers 111 includes an adhesive layer and a conductive layer. The adhesive layer may be formed of a metal nitride having good adhesion to the material of the dielectric storage layers 113, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer. Once the metal line layer 111 has been deposited, the optional planarization process may be performed to planarize the material of the metal line layer 111. Thus, a first sequence 105 aof material layers has been formed.Once the first series 105 aof material layers has been formed, a first of the isolation layers 107 may be deposited as a solid layer (e.g., oxide) over the first series 105 aof material layers. The isolation layers 107 may be made of a dielectric material (e.g., silicon oxide (SiO 2), SiN, SiON, or the like). The isolation layers 107 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. After the deposition of the isolation layers 107, an optional annealing process (e.g., rapid thermal annealing, oxidation compaction, or the like) and / or an optional planarization process (e.g., chemical mechanical planarization) may be performed thereon to cure and / or planarize them. In some embodiments, prior to forming the first sequence 105 aof material layers, an optional layer of the isolation layers 107 is deposited over the device structure 103.Once the isolation layer 107 has been formed over the first series 105 aof material layers, the second series 105 bof material layers may be formed over the first series 105 a. The second series 105 bof layers may be formed using any of the layers, materials, and processes suitable for forming the first series of layers 105 a. In some embodiments, the second series 105 bof layers includes the same material layers and the same order of layers as the first series 105 a, but the material layers and the order of layers may be different. In the illustrated embodiment, the second series 105 bincludes the same material layers and the same order of layers as the first series 105 a.In some embodiments, further series of material layers may be formed in the first multilayer stack 101 stacked until a desired uppermost series of material layers has been formed. In the first multilayer stack 101, any suitable number of sequences of material layers may be formed. In the illustrated embodiment, the first multilayer stack 101 includes two series of material layers: the first series 105 aof layers and the second series 105 bof layers stacked over the first series of layers 105 a.FIG. 2 further illustrates a first region 115 of the first multilayer stack 101. According to some embodiments, the first region 115 may be referred to as forming a 3D stacked memory array. Additionally, a second region 117 of the first multilayer stack 101 is adjacent to the first region 115 and may be referred to as forming a staircase contact structure for external connection to the stacked 3D memory array.FIG. 3 illustrates the formation of gate trenches 201 within wordline regions 203 of the first multilayer stack 101 in accordance with some embodiments. The word line region 203 can also be referred to herein as a word line region. The gate trenches 201 may be formed by first forming a photoresist (not shown) over the first multilayer stack 101. The photoresist may be formed using a spin-on technique and patterned using acceptable photolithography techniques. The photoresist may be patterned to expose the surface of the top layer of the first multilayer stack 101 at desired positions of the gate trenches 201. The gate trenches 201 may be patterned using one or more photolithography processes, including dual or multi-patterning processes.According to some embodiments, a first etch chemistry selective to an uppermost exposed layer of the first multilayer sequence 105 of material layers and comparatively non-selective to a layer of the first multilayer sequence 105 underlying the uppermost exposed layer may be used to form the gate trenches 201 through the uppermost exposed layer of the first multilayer sequence 105, stopping at the layer of the first multilayer sequence 105 underlying the uppermost exposed layer. Thus, the layer of the first multilayer sequence 105 that is below the uppermost exposed layer becomes the next uppermost exposed layer of the first multilayer sequence 105 of material layers. A second etch chemistry that is selective to the next uppermost exposed layer of the first multilayer stack 105 and is comparatively non-selective to the layer of the first multilayer stack 105 that is below the next uppermost exposed layer. Thus, the layer of the first multilayer stack 105 that lies below the next uppermost exposed layer becomes the next uppermost exposed layer of the first multilayer stack 105. This process may be continued using etch chemistries suitable to remove and stop the next uppermost exposed layer of the first multilayer sequence 105 at the layer of the first multilayer sequence 105 that is below the next uppermost exposed layer of the first multilayer sequence 105 until the gate trenches 201 have been etched through the first multilayer stack 101 and stopped at the uppermost layer of the device structure 103. For example, a chlorine or fluorine-based gas, such as chlorine (Cl 2) or hydrogen fluoride (HF), or the like, may be used to selectively etch the material of the channel layers 109 (e.g., ZnO) without substantially removing the dielectric material of the isolation layers 107 (e.g., SiO 2) of the first multilayer stack 105. The isolation layers 107 may be selectively etched using a wet etch chemistry comprising phosphorus (e.g., H 3 PO 4 or the like) without substantially removing the material of the channel layers 109 and / or the metal line layers 111 (e.g., Ti). In other embodiments, a single etching process may be used to remove and stop all materials of the sequence of material layers at the top layer of the device structure 103, for example, with an etching process selective to all materials of the first multi-layer stack 101 and / or using a time-controlled etching process.In accordance with some embodiments, timed etch processes may be used to stop the etching of the gate trenches 201 after the trenches have reached a desired depth. For example, the timed etch process may be timed to stop at the surface of the device structure 103, but the timed etch process may also be timed to etch to a desired depth into the device structure 103. According to some embodiments, an optional contact etch stop layer (not shown) may be provided at an interface between the device structure 103 and the first multi-layer stack 101. The optional contact etch stop layer may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of an overlying layer of the first multilayer stack 101. In such embodiments, prior to forming the first multilayer stack 101, the optional contact etch stop layer is formed over the device structure 103 by a suitable deposition process (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like), and the first multilayer stack 101 is formed over the optional contact etch stop layer. Additionally, an additional etching process may be used to remove material of the optional contact etch stop layer such that the device structure 103 may be exposed at the bottom of the gate trenches 201.After patterning, the remaining portions of the first multilayer stack 101 between the gate trenches 201 form a plurality of stripes 205. Therefore, the gate trenches 201 are separated by the stripes 205. Although the embodiment illustrated in FIG. 3 shows each of the strips 205 having the same width, the widths of the strips 205 of one stacked 3D memory array located in one region of the first multilayer stack 101 may be greater or less than the strips 205 of another stacked 3D memory array located in another region of the first multilayer stack 101. According to some embodiments, each of the gate trenches 201 may have a uniform width. In other embodiments, the gate trenches 201 and thus the strips 205 may have beveled sidewalls such that the width of each of the strips 205 increases steadily in a direction toward the substrate 50. In such embodiments, each of the layers of the first multilayer stack 101 may have a different width in a direction perpendicular to the sidewalls of the strips 205. Furthermore, the gate trenches 201 may also extend into the second region 117 (shown in FIG. 2 ), thereby dividing the second region 117 into separate regions for the later formation of a staircase contact structure, as described below with reference to FIG. 8.FIG. 4 illustrates a wire release process for forming nanostructures 301 from the channel layers 109. Once the gate trenches 201 have been formed, in accordance with some embodiments, the spacers and / or the photoresist used to form the gate trenches 201 (shown in FIG. 2 ) may be removed, and a mask layer (not shown) for use in the wire release process may be formed over the first multilayer stack 101 and patterned to expose the wordline regions 203. In other embodiments, the spacers and / or the photoresist layer used to form the gate trenches 201 may remain, and the mask layer for use in the wire release process is formed over the spacers and the photoresist layer. In such embodiments, the mask layer may be formed over the photoresist and / or the spacers and then patterned to expose the portions of the photoresist and / or the spacers covering the gate trenches 201 and / or the strips 205 (shown in FIG. 2 ) within the wordline regions 203.According to some embodiments, the mask layer may be made of a conductive or a non-conductive material and may be selected from a group including silicon nitride, silicon oxynitride, amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The mask layer may be deposited by physical vapor deposition (PVD), CVD, ALD, sputtering deposition, or other techniques for depositing the selected material. Once the mask layer material is deposited, it may be patterned, e.g., using a photolithographic masking and etching process. Once the mask layer has been patterned, the exposed portions of the photoresist and / or spacers are removed using one or more suitable removal processes (e.g., ashing, selective etching, combinations, or the like).Once the mask layer has been formed, the sidewalls of the gate trenches 201 and thus the sidewalls of the strips 205 are exposed, as illustrated in FIG. 4. Therefore, the material of the first multilayer stack 101 of the strips 205 between the channel layers 109 and between the device structure 103 and the channel layers 109 may be removed in a wire release process step. Therefore, the remaining material of the strips 205 (e.g., the channel layers 109) form the nanostructures 301 between the source / bit line regions 303 of the first multilayer stack 101. The nanostructures 301 can also be referred to herein as wires, nanowires, sheets and / or nanosheets. In an embodiment, the material to be removed of the strips 205 is removed using a wet etching process that selectively removes this material without substantially removing the material of the channel layers 109 within the wordline regions 203 and without substantially removing material in the source / bitline regions 303 of the first multilayer stack 101. However, any other suitable removal process may be used.For example, in an embodiment, an etch chemistry including phosphorus (e.g., H 3 PO 4) may be used to selectively remove the other materials of the first multilayer stack 101 without substantially removing the material of the semiconductor channel regions (e.g., zinc oxide (ZnO)) and / or the material of the device structure 103. However, in other embodiments, any other suitable etchant may be used to selectively remove other materials of the first multilayer stack 101 without substantially removing the material of the channel layers 109 (e.g., zinc oxide (ZnO)) and / or the material of the device structure 103.By removing the other materials of the first multilayer stack 101, the sides of the nanostructures 301 within the wordline regions 203 are exposed and separated from each other. The nanostructures 301 form a channel structure between opposing source / bit line regions 303. In some embodiments, a matching selectivity of the etching process is used to form the nanostructures 301, and may be adjusted such that the nanostructures 301 form with smooth surfaces or comprise a plurality of faceted surfaces. Therefore, the nanostructures 301 may be formed with different profile shapes (e.g., round, square, rectangular, hexagonal, octagonal, or the like). In the illustrated embodiment, the nanostructures 301 are formed to have a square profile in which the channel width is approximately equal to the original thickness of the nanostructures 301, however, the etching processes may also be used to reduce that thickness.Once nanostructures 301 have been formed, any remaining portions of the mask layer, the remaining spacers, and / or the remaining photoresist may be removed using one or more suitable removal processes (e.g., wet etching, dry etching, or the like) that utilize one or more etchants that are selective to the materials of the mask layer, the remaining spacers, and / or the remaining photoresist. However, any suitable removal process may be used.FIG. 5 illustrates the formation of the gate dielectric material 401 on sidewalls of the source / bit line regions 303 in the word line regions 203 of the first multilayer stack 101 and on exposed areas of the nanostructures 301 between sidewalls of the source / bit line regions 303 within the word line regions 203 of the first multilayer stack 101. The gate dielectric material 401 is formed as a conformal thin film. According to some embodiments, the gate dielectric material 401 may be formed using one or more layers of acceptable dielectric material suitable for storing digital values, such as multilayer dielectrics (e.g., oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON), or the like); other dielectrics (e.g., silicon oxynitride (SiON), silicon nitride (SiN), or the like); ferroelectric (FE) materials, such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); undoped hafnium oxide (HfO); In addition, the following may be used: doped hafnium oxides (e.g., HfLaO using lanthanum (La) as a dopant, HfSiO using silicon (Si) as a dopant, HfAlO using aluminum (Al) as a dopant, or the like); combinations; or the like. The material of the gate dielectric material 401 may be formed by an acceptable deposition process such as ALD, CVD, PVD, or the like.FIG. 6 illustrates the formation of encircling wordline structures 501 formed over the gate dielectric material 401 within the wordline regions 203 of the first multilayer stack 101. Once the gate dielectric material 401 has been deposited, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed to remove the gate dielectric material 401 at the top of the first multilayer stack 101. Therefore, the metal line layers 111 may be exposed for further processing. The encircling wordline structures 501 may include one or more layers, such as adhesive layers, barrier layers, diffusion layers and fill layers, and the like. In some embodiments, the encircling wordline structures 501 include an adhesive layer and a conductive layer. The adhesive layer may be formed of metal nitride such as titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, or the like. The conductive layer may be formed of a metal such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. The material of the adhesive layer is a material having good adhesion to the material of the gate dielectric material 401, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer. In embodiments where the gate dielectric material 401 is formed of an oxide, such as an oxide-nitride-oxide (ONO) film, the adhesive layer may be titanium nitride and the conductive layer may be tungsten. The adhesive layer and the conductive layer may each be formed by an acceptable deposition process such as ALD, CVD, PVD, or the like. The material of the encircling wordline structures 501 may fill and overfill the remaining opening in the wordline regions 203 and may be formed over the top surfaces of the first multilayer stack 101 outside the wordline regions 203. The conductive layer fills the remaining area of the gate trenches 201. After deposition, the material of the encircling wordline structures 501 and the gate dielectric material 401 may be planarized with the top layer of the first multilayer stack 101 using a process such as chemical mechanical planarization, an etch back process, combinations thereof, or the like.Reference is now made to FIG. 7. This figure illustrates the formation of a stacked 3D memory array 600 from the structure illustrated in FIG. 6, in accordance with some embodiments. The stacked 3D memory array 600 includes a plurality of first stacked memory cells 613 (e.g., 1T2R memory cells). In the illustrated embodiment, each of the first stacked memory cells 613 includes a transistor (e.g., a first transistor T 1, a second transistor T 2), and two resistors (e.g., a first resistor R 1, a second resistor R 2) for which values may be set / reset during writes. For example, when a write voltage (V W) is applied to the metallic source / bit line 603 adjacent to the first resistor R 1 and a word line voltage (V WL) is applied to the 605 of the first transistor T 1, a write operation may be performed to set / reset a value stored for the first resistor R 1. Similarly, by applying the write voltage (Vw) to the metallic source / bit line 603 adjacent to the second resistor R1 and applying the write voltage (V WL) to the 605 of the first transistor T1, a write operation can be performed to set / reset the value stored for the second resistor R2. Similar writing operations may be performed for the second transistor T 2, the third resistor R 3, and the fourth resistor R 4. Although embodiments of the memory array 600 have been described using, e.g., the 1T2R configuration, other embodiments, e.g., a 2T2R configuration (not shown), may also be used. Instead of a common transistor with two resistors (e.g., 1T2R configuration), in the 2T2R configuration, each memory cell 613 may be formed with two transistors and two resistors (e.g., R1 and R2). The two transistors of the 2T2R configuration may be formed with independent channel regions 109 separated by an optional layer (not shown) of the isolation layers 107. Therefore, during writes, the two transistors of the 2T2R configuration can operate independently with either of the two resistors (e.g., R1 and R2).As discussed in detail below, in the later formation of a 3D memory device, the stacked 3D memory array 600 may also be formed with a staircase contact structure and BEOL-compatible diodes. Therefore, a robust design is provided for the stacked memory cells 613, which prevents problems with write disturbances from occurring during writes to the resistors. Further details of the operation of the stacked memory cells 613 are provided below with reference to an equivalent circuit of the memory circuit 1200. The isolation layers 107 isolate the stacked memory cells 613 from each other. In addition, gate isolation plugs 601 isolate the surrounding gates 605 of adjacent stacks of the first stacked memory cells from each other. In some embodiments, the encompassing gates 605 and the gate isolation plugs 601 may be formed by first forming wordline gaps through the encompassing wordline structures 501 (shown in FIG. 6 ). The wordline gaps may be formed using any photolithography and etching techniques suitable for etching the material of the encircling wordline structures 501. The etching may be anisotropic. In some embodiments, the wordline gaps may be formed by a sequence of appropriate etches (e.g., dry and / or wet etches). According to some embodiments, a dry etching is performed using a fluorine-based gas (e.g., C 4 F 6), which is mixed with hydrogen (H 2) or oxygen (O 2) to remove the conductive layer of the encompassing wordline structures 501, and a wet etching is performed using a solution of nitric acid (HNO 3) and hydrofluoric acid (HF) to remove the adhesive layer of the encompassing wordline structures 501. However, other suitable removal processes may be used to remove the material from the wordline columns. Therefore, the encompassing word line structures 501 are separated by the word line column into individual structures of the encompassing gates 605.Once the wordline gaps have been formed through the encircling wordline structures 501, the gate isolation plugs 601 may be formed using any of the acceptable dielectric materials and / or deposition processes used to form the gate dielectric material 401. For example, the gate isolation plugs 601 may be formed using a dielectric material (e.g., silicon oxide) and an acceptable deposition process (e.g., ALD) to fill and overfill the wordline gaps, respectively. After filling and / or overfilling, the gate isolation plugs 601 may be planarized (e.g., by CMP) to remove excess material of the gate isolation plugs 601 outside the wordline gaps and to remove excess material of the gate dielectric material 401 over the top surface of the first multilayer stack 101. Thus, the tops of the gate isolation plugs 601, the gate dielectric material 401, and the encompassing gates 605 are coplanar with a top of the first multilayer stack 101, and the separated structures of the encompassing gates 605 are insulated from each other by the gate isolation plugs 601. The nanostructures 301 (shown in FIG. 4 ) of the first transistor T 1 and the second transistor T 2 are formed from the channel layers 109 and, as described above, are surrounded by the gate dielectric 401. The surrounding gate 605 surrounds the channel regions of the first transistor T 1 and the second transistor T 2 and is separated from the nanostructure 301 by the gate dielectric material 401. The metal source / bit lines 603 of the first transistor T 1 and the second transistor T 2 are formed from the metal line layers 111 during the above-described wire releasing process. The gate dielectric material 401 isolates the surrounding gate 605 from the sidewalls of the channel layers 109 and the metallic source / bit lines 603. The gate dielectric material 401 further isolates the surrounding gate 605 from the sidewalls of the first resistor R 1 and the second resistor R 2.In the illustrated embodiment, the first resistor R 1 is coupled to the metallic source / bit lines 603 on a first side of the first transistor T 1. The second resistor R 2 is coupled to the metal source / bit lines 603 on a second side of the first transistor T 1. Each of the first resistors R 1 and the second resistors R 2 includes a resistive memory film 611 and an upper electrode 609. During the wire releasing process described above, the resistive memory films 611 are formed of the dielectric memory layer 113. The resistive memory films 611 are coupled to a respective one of the metallic source / bit lines 603 on opposite sides of the first transistor T 1. The upper electrodes 609 are formed of the metal lead layers 111 during the above-mentioned wire releasing process. Each of the upper electrodes 609 is coupled to the resistive memory films 611 of the first resistor R 1 and the second resistor R 2, respectively. The resistive memory films 611 may have at least two states: a high impedance state and a low impedance state, which may correspond to two logic states, namely a set state and a reset state. The state of the resistive memory films 611 may be determined by applying a voltage to the resistive memory films 611 and determining a current flowing through the resistive memory films 611 (e.g., by determining whether the resistive memory films 611 have a high or a low impedance state to read a corresponding bit stored by the resistive memory films 611). In the illustrated embodiment, the resistive memory films 611 of the first resistor R 1 are coupled to the metallic source / bit lines 603 on one side of the channel layers 109 of the first transistor T 1, and the resistive memory films 611 of the second resistor R 2 are coupled to the metallic source / bit lines 603 on the other side of the channel layers 109 of the first transistor T 1. Therefore, the first transistor T 1 may be a common access transistor for enabling read / write operations of either the first resistor R 1 or the second resistor R 2.In the illustrative embodiment of FIG. 7, a second stacked memory cell 613 is formed from the second series 105 bof material layers and stacked over the first stacked memory cells 613 formed from the first series 105 aof material layers. In the illustrated embodiment, each of the first stacked memory cells 613 includes a second transistor T 2 and two resistors (e.g., a third resistor R 3 and a fourth resistor R 4). The resistive memory films 611 of the third resistor R 3 are coupled to the metallic source / bit lines 603 on one side of the channel layer 109 of the second transistor T 2, and the resistive memory films 611 of the fourth resistor R 4 are coupled to the metallic source / bit lines 603 on the other side of the channel layer 109 of the second transistor T 2. Therefore, the second transistor T 2 may be a common access transistor for enabling read / write operations of either the third resistor R 3 or the fourth resistor R 4. In the illustrated embodiment, the gate dielectric material 401 isolates the surrounding gate 605 from the sidewalls of the multilayer stack 101 in the source / bit line regions 303. In addition, the gate isolation plugs 601 isolate the surrounding gates 605 of adjacent stacks of the first stacked memory cells 613.FIG. 8 is a perspective view of a second 3D memory device 850 having a staircase contact structure 800 adjacent to the second stacked 3D memory array 600 in accordance with some embodiments. In particular, FIG. 8 illustrates the formation of the staircase contact structure 800 in the second region 117 of the second multilayer stack 101 adjacent to the second stacked 3D memory array 600 formed within the first region 115 of the second multilayer stack 101, in accordance with some embodiments. Although the illustrated embodiment is directed to the formation of the staircase contact structure 800 in the second region 117 of the second multilayer stack 101, it should be appreciated that a staircase structure of similar design may be suitably formed within the second region 117 of the second multilayer stack 101 adjacent to the stacked 3D memory array 600. All such combinations of staircase structures and memory arrays are within the scope of the embodiments.FIG. 8 further illustrates the formation of a first inter-metal dielectric (IMD) layer 803 over the staircase contact structure 800. The first IMD layer 803 is formed within the gate trenches 201 extending into the second region 117 of the second multilayer stack 101 and over the exposed surfaces of the staircase contact structure 800. In addition, FIG. 8 illustrates diodes 801 formed over the first IMD layer 803, conductive contacts 805 formed over the diodes 801 and encompassing gates 605, and through interlayer vias (TIVs) 807 that electrically couple the diodes 801 and the conductive contacts 805 to the staircase contact structure 800.According to some embodiments, the portion of the staircase contact structure 800 associated with the first cut line A-A in FIG. 8 provides contact with the bitlines of the transistors formed within the second stacked 3D memory array 600. Therefore, the portion of the stair contact structure 800 associated with the first cut line A-A may be referred to herein as a bit line stair portion, a BL stair portion, a bit line stair, a BL stair, or the like. Also, in the illustrated embodiment, the portion of the staircase contact structure 800 associated with the second cut line B-B in FIG. 8 provides contact with the source lines of the transistors formed within the second stacked 3D memory array 600. Therefore, the portion of the stair contact structure 800 associated with the second cut line B-B may be referred to herein as a source line stair portion, a SL stair portion, a source line stair, a SL stair, or the like.FIG. 9 illustrates a cross-sectional view of the staircase contact structure 800 along a first cut line A-A of FIG. 8 In the illustrated embodiment, the staircase contact structure 800 is formed such that a portion of the metallic source / bit lines 603 and a portion of the top electrodes 609 of each of the second multi-layer strings 105 are exposed. For example, the staircase contact structure 800 may be formed by a plurality of etching processes, wherein each of the etching processes is performed with different etching duration to expose a different portion of the second 3D memory device 850 for removal using a different etch mask (e.g. a patterned resist) and to achieve different etching depths. The second stacked 3D memory array 600 may remain protected by the etch mask during the etching to form the staircase contact structure 800.As illustrated in FIG. 9, a portion of each of the multi-layered strings 105 that is laterally far from the second stacked 3D memory array 600 is removed to form the staircase contact structure 800. The area of the removed portions of the second multilayer sequence 105 increases in a vertical direction away from the device structure 103. For example, the higher (the farther away from the device structure 103) the metallic source / bit lines 603 and / or the top electrodes 609 are within the second multilayer sequence 105, the larger the area of the overlying layers within the second multilayer sequence 105 that is removed to expose portions of the metallic source / bit lines 603 and / or the top electrodes 609.The staircase contact structure 800 may be formed by first placing a resist 901 over the second multilayer stack 101 after forming the second stacked 3D memory array 600. The photoresist 901 may be formed using a spin-on technique and patterned using acceptable photolithography techniques. Patterning the photoresist 901 may expose a portion of the second multilayer stack 101 in the second region 117 while masking remaining portions of the second multilayer stack 101. Once the photoresist 901 has been patterned, one or more layers of the second multilayer stack 101 in the exposed portion (e.g., the first staircase region 903 a) may be removed using a suitable staircase etching process for the materials to be removed. The staircase etching process may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic.According to some embodiments, the etching may remove portions of one or more material layers of the second multilayer stack 101 exposed in the first staircase region 903 aand may stop at a material layer underlying the one or more material layers to be removed. In some embodiments, a recursive etching process may be used such that the photoresist 901 is patterned to expose a first desired portion of the top layer of the isolation layers 107 (e.g., the first staircase region 903 a), and then the patterned photoresist 901 is used as a mask in a step of the recursive etching process to transfer its pattern to the top layer of the isolation layers 107. After the transfer, portions of the second multilayer stack 101 are exposed and the top layer of the isolation layers 107 may be used as a hard mask in a further step of the recursive etching process to transfer the pattern of the hard mask to one or more layers of the second multilayer stack 101. After transfer, portions of an underlying layer of the second multilayer stack 101 are exposed in the staircase contact structure 800.In some embodiments, a layer of the second multilayer stack 101 may be used as an etch stop layer to control removal of material during individual etch steps of the recursive etch process. In some embodiments, the etching process may be a time-controlled process to control removal of material during the etching process. All such etching processes and all such combinations of such etching processes may be used to form the staircase contact structure 800 and are within the scope of the embodiments.Once the first staircase region 903 ais exposed, the exposed portions of the second multilayer stack 101 in the first staircase region 903 aare etched using the photoresist 901 as a mask in a staircase etching process. One or more etching steps may be performed in the first staircase region 903 auntil a desired layer has been exposed. Once the desired layer of the second multilayer stack 101 has been exposed, the photoresist 901 may be trimmed to expose another portion of the second multilayer stack 101 in a second staircase region 903 b, while masking remaining portions of the second multilayer stack 101 outside the second staircase region 903 b. The exposed portions of the second multilayer stack 101 in the second staircase region 903 bmay be etched by repeating the staircase etching process using the trimmed resist as a mask.The trimming of the resist 901 and the staircase etching process may be repeated until a desired number of staircase contact areas 905 have been exposed. In the illustrated embodiment, eight of the staircase contact areas (e.g., 905a, 905b, 905c, 905d, 905e, 905f, 905g, and 905h) are exposed, with the last trimming of the resist 901 exposing the eighth staircase contact area 905h. However, according to a desired structure of a 3D memory device, more or fewer staircase contact areas 905 may be formed. For example, in a second multilayer stack 101 comprising a fewer number of metallic source / bit lines 603 and / or top electrodes 609 (e.g., four), fewer staircase contact pads 905 (e.g., four) may be formed. In another example, in a second multilayer stack 101 comprising a larger number of metallic source / bit lines 603 and / or top electrodes 609 (e.g., nine, ten, eleven, twelve,... etc.), more staircase contact pads 905 (e.g., nine, ten, eleven, twelve,... etc.) may be formed. The stair contact structure 800 may be formed with any suitable number of stair contact surfaces 905.Continuing with FIG. 10A, after forming the stair contact structure 800, the first IMD layer 803 is formed over the stair contact structure 800. In some embodiments, prior to forming the first IMD layer 803, the stair contact structure 800 is separated into the bit line staircase portion and the source line staircase portion, as illustrated in FIG. 7. In such embodiments, the first IMD layer 803 fills the staircase trench and isolates the bit line staircase portion from the source line staircase portion.According to some embodiments, the first IMD layer 803 is formed using, for example, silicon oxide, silicon nitride, or the like, and is formed by a suitable method such as CVD, PVD, ALD, or the like. After formation, the first IMD layer 803 is then planarized with the coplanar surfaces of the isolation layers 107, the gate dielectric material 401, the gate isolation plugs 601, and the encompassing gate 605 in the first region 115 of the second multilayer stack 101, in accordance with some embodiments. The first IMD layer 803 may be planarized using a process such as chemical mechanical planarization (CMP). The photoresist 901 may be removed prior to planarization of the first IMD layer 803 using, e.g., an ashing process. In some embodiments, the photoresist 901 may be removed during planarization of the first IMD layer 803 using the CMP process, the ashing process, combinations, or the like.FIG. 10A further illustrates the formation of the conductive TIVs 807 through the bit line staircase portion of the stair contact structure 800, in accordance with some embodiments. In the illustrated embodiment, the conductive TIVs 807 are formed over the staircase contact areas 905 of the top electrodes 609 (e.g., 905 a, 905 d, 905 e, and 905 h, as shown in FIG. 9 ). According to some embodiments, the conductive TIVs 807 are also formed through the first IMD layer 803. The conductive TIVs 807 shown in FIG. 10A provide external connection to the top electrodes 609 of the bit line staircase structure of the second stacked 3D memory array 600.In an embodiment where the conductive TIVs 807 are conductive pillars (e.g., of tungsten, copper, aluminum, titanium, alloys, combinations, or the like), the conductive TIVs 807 may be formed by first forming the first IMD layer 803 over the first region 115 and the second region 117 of the second multilayer stack 101. After the formation, the first IMD layer 803 is patterned using suitable photolithography and etching processes to form openings through the first IMD layer 803 and expose areas of the staircase contact areas 905 at desired locations of the conductive TIVs 807. After the openings are formed, they may be filled and / or overfilled with a conductive fill material (e.g., W, Al, Cu, or the like) using a suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like). After deposition, a planarization process may be performed to collimate the top surfaces of the conductive TIVs 807 to be coplanar with a surface of the first IMD layer 803.FIG. 10A further illustrates formation of the diodes 801 from a first conductivity type oxide semiconductor layer 1001 and a second conductivity type oxide semiconductor layer 1003, in accordance with some embodiments. The diodes 801 may be formed by first depositing a bulk layer of a first conductivity type oxide semiconductor layer 1001 to a desired thickness over the coplanar surfaces of the first IMD layer 803 and the conductive TIVs 807. Suitable oxide materials that can be used for the oxide semiconductor layer 1001 of the first conductivity type include materials such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), or the like, and can be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. The oxide semiconductor layer 1001 of the first conductivity type may be doped to have a first conductivity type (e.g., p-type, n-type, p +- type, or the like) using any suitable doping process (e.g., in situ doping during epitaxial growth, post-deposition implantation, combinations, or the like). In embodiments where the first conductivity type is p-type, the oxide semiconductor layer 1001 of the first conductivity type may be doped using a dopant such as borohydride (e.g., diborane B 2 H 6). However, any suitable materials, deposition processes, dopants, and / or doping processes may be used to form the oxide semiconductor layer 1001 of the first conductivity type. In embodiments in which the first conductivity type is n-type, the oxide semiconductor layer 1001 of the first conductivity type may be doped using a dopant such as monophosphane (PH 3). However, any suitable materials, deposition processes, dopants, and / or doping processes may be used to form the oxide semiconductor layer 1001 of the first conductivity type.After deposition, the oxide semiconductor layer 1001 of the first conductivity type is planarized using, for example, CMP. Therefore, the oxide semiconductor layer 1001 of the first conductivity type is formed over the conductive TIVs 807 and electrically coupled via them through the first IMD layer 803 to the upper electrodes 609 of the bit line staircase structure.The second conductive type oxide semiconductor layer 1003 may be formed by depositing a bulk layer of a second oxide semiconductor material having a desired thickness over the first conductive type oxide semiconductor layer 1001. The oxide semiconductor layer 1003 of the second conductivity type may be formed using any of the oxide materials and processes suitable for forming the oxide semiconductor layer 1001 of the first conductivity type. The second oxide semiconductor material may be formed using the same oxide material as the first oxide semiconductor material, but other oxide materials may be used. However, the second oxide semiconductor material is formed to be doped opposite to the material of the oxide semiconductor layer 1001 of the first conductivity type. For example, in embodiments in which the oxide semiconductor layer 1001 of the first conductivity type is doped using p- or p-+- dopants, the oxide semiconductor layer 1003 of the second conductivity type is doped to have a second conductivity type (e.g., n-type). In other embodiments in which the oxide semiconductor layer 1001 of the first conductivity type is doped using n-type dopants, the oxide semiconductor layer 1003 of the second conductivity type is doped to have the second conductivity type (e.g., p-type or p+-type). After deposition, the oxide semiconductor layer 1003 of the second conductivity type is planarized using, for example, CMP. Therefore, the oxide semiconductor layer 1003 of the second conductivity type is formed over and electrically coupled to the oxide semiconductor layer 1001 of the first conductivity type.After the formation, the first conductive type oxide semiconductor layer 1001 and the second conductive type oxide semiconductor layer 1003 are patterned using appropriate photolithography and etching processes to form the diodes 801. The diodes 801 are formed at desired positions over the conductive TIVs 807 of the bit line staircase contact structure. Therefore, the formation of the diodes 801 is compatible with back-end-of-line (BEOL) processes.FIG. 10A further illustrates the formation of a first set of conductive contacts 805 for external connection to the diodes 801, in accordance with some embodiments. The conductive contacts 805 may be formed by first depositing a second IMD layer 1005 over the surface of the first IMD layer 803 and the diodes 801. In some embodiments, the second IMD layer 1005 may also be formed over coplanar surfaces of the isolation layers 107, the gate dielectric material 401, the gate isolation plugs 601, and the encompassing gate 605 in the first region 115 of the second multilayer stack 101. The second IMD layer 1005 may serve as a protective layer in the first region 115 during further processing of the staircase contact structure 800 in the second multilayer stack 101. In other embodiments, a separate protective layer (not shown) is formed over the first region 115 prior to forming the second IMD layer 1005. The second IMD layer 1005 may be formed using any of the materials and processes suitable for forming the first IMD layer 803. After formation, the second IMD layer 1005 is patterned using suitable photolithography and etching processes to form openings through the second IMD layer 1005 at desired locations of the conductive contacts 805. Therefore, the diodes 801 are exposed through the openings in the second IMD layer 1005.FIG. 10A further illustrates the formation of conductive contacts 805 for connection to the diodes 801, in accordance with some embodiments. In some embodiments, an optional silicide formation process using appropriate materials such as titanium, nickel, cobalt, or erbium to reduce the Schottky barrier height of the conductive contacts 805. However, other metals such as platinum, palladium, and the like may be used for the optional silicide formation process. In some embodiments, the optional silicide formation process is performed using blanket deposition of an appropriate metal layer in the openings and over the exposed areas of the diodes 801. The blanket deposition is followed by an anneal step that causes the metal layer to react with the underlying exposed second oxide semiconductor material (e.g., ZnO) of the diodes 801. Then, unreacted metal is removed, for example, by a selective etching process. In other embodiments, the optional silicide formation process is omitted.The conductive contacts 805 may be formed by depositing a conductive material such as W, Al, Cu, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations thereof, or the like into the openings and over the exposed areas of the diodes 801 or (if present) over the optional silicide contacts. The conductive material may be deposited using a process such as sputtering, chemical vapor deposition, electroplating, electroless plating, or the like to fill and / or overfill the openings. After filling, conductive material deposited outside the openings may be removed using a planarization process such as chemical mechanical polishing (CMP). However, any suitable deposition processes and planarization processes may be used.Once the first set of conductive contacts 805 to the diodes 801 have been formed, bit lines 1007 may be formed over the conductive contacts 805. FIG. 10A also denotes the first set of conductive contacts 805 as a first bit line BL 1 and a second bit line BL 2 associated with the first access transistor T 1 and a third bit line BL 3 and a fourth bit line BL 4 associated with the second access transistor T 2 of the second stacked 3D memory array 600. The conductive contacts 805 form an external connection between the bit lines 1007 of the second stacked 3D memory array 600 and underlying active devices and / or signal, power and ground lines in the device structure 103.Reference is now made to FIG. 10B. This figure illustrates the formation of a second set of conductive TIVs 807 by the source line staircase portion of the staircase contact structure 800, in accordance with some embodiments. The second set of conductive TIVs 807 provide external connection to the metallic source / bit lines 603 in the source line staircase structure associated with the second stacked 3D memory array 600. In the illustrated embodiment, the second set of conductive TIVs 807 are formed over the staircase contact areas 905 of the metallic source / bit lines 603 (e.g., 905 b, 905 c, 905 fand 905 g, as shown in FIG. 8 ) in the source line staircase portion. The second set of conductive TIVs 807 may be formed using any of the materials and processes described above for forming the first set of conductive TIVs 807 in the bit line staircase portion. The second set of conductive TIVs 807 may be formed during the process of forming the first set of conductive TIVs 807, but may be formed in other process steps.FIG. 10B further illustrates the formation of a second set of conductive contacts 805 for connection to the second set of conductive TIVs 807, in accordance with some embodiments. The second set of conductive contacts 805 may be formed by first forming openings through the second IMD layer 1005 and exposing the second set of conductive TIVs 807 at the desired locations of the second set of conductive contacts 805. The openings for the second set of conductive contacts 805 may be formed during the process of forming the openings for the first set of conductive contacts 805. The second set of conductive contacts 805 may be formed using any of the materials and processes suitable for forming the first set of conductive contacts 805. The second set of conductive contacts 805 are formed by depositing a conductive material into the openings and over the exposed areas of the second set of conductive TIVs 807 or (if present) over the optional silicide contacts and then planarizing. However, any suitable deposition processes and planarization processes may be used.After the second set of conductive contacts 805 to the conductive TIVs 807 have been formed in the source line portion of the staircase contact structure 800, source lines 1009 may be formed over the conductive contacts 805. FIG. 10B also denotes each of the source lines 1009 as a first source line SL 1 and a second source line SL 2 associated with the first access transistor T 1 and a third source line SL 3 and a fourth source line SL 4 associated with the second access transistor T 2 in the second stacked 3D memory array 600. The second set of conductive contacts 805 form an external connection between the source lines 1009 of the second stacked 3D memory array 600 and underlying active devices and / or signal, power and ground lines in the device structure 103.In addition, a third set of conductive contacts 805 may be formed to the encompassing gates 605 (shown in FIG. 8). In embodiments where the second IMD layer 1005 is formed over the first region 115, openings for the third set of conductive contacts 805 may be formed in the first region 115, and the third set of conductive contacts 805 may be formed during the process of forming the second set of conductive contacts 805 to the conductive TIVs 807 and / or the first set of conductive contacts 805 to the diodes 801 to the encompassing gates 605. The third set of conductive contacts 805 may thus use the same materials and techniques used to form the other sets of conductive contacts 805. However, the third set of conductive contacts 805 may also be formed in processing steps separate from those used to form the other sets of conductive contacts 805, and may be formed using materials and / or techniques different from those used to form the other conductive contacts 805. In some embodiments, the third set of conductive contacts 805 may be formed using materials and / or techniques suitable for forming the third set of conductive contacts 805 to the encompassing gates 605. Once the third set of conductive contacts 805 have been formed to the encompassing gates 605 of the second stacked 3D memory array 600, word lines 1101 (shown in FIG. 10 ) may be formed over the third set of conductive contacts 805 using any of the materials and processes suitable for forming the source lines 1009 and / or bit lines 1007. The third set of conductive contacts 805 provide external connection between the word lines 1101 of the second stacked 3D memory array 600 and underlying active devices and / or signal, power and ground lines in the semiconductor die.Further interlayer dielectric layers (not individually illustrated) and other conductive features (also not individually illustrated) may be formed over the conductive contacts 805, the source lines 1009, the bit lines 1007 and / or the word lines 1101 to provide additional external connection to the second 3D memory device 850. Examples of other conductive features include, but are not limited to, conductive vias, contact plugs, redistribution layers, contact traces, integrated passive devices, under bump metallization layers, fan-out integrated devices, interposers, and external contacts. However, any suitable dielectric layers and / or conductive features may be utilized.Reference is now made to Fig. 11. This figure is a two-dimensional illustration of the first stacked memory cell 613 (e.g., type 1T2R) in the second stacked 3D memory array 600 and the adjacent staircase contact structure 800, in accordance with some embodiments. Although the components of the first stacked memory cell 613 are illustrated in the two-dimensional illustration, it should be understood that the first source line SL 1, the second source line SL 2, the word line WL, the first bit line BL 1, and the second bit line BL 2 may be located in different cross-sections through the second 3D memory device 850 of FIG. 8.Continuing with FIG. 11, in such embodiments for the second stacked memory cell 613, the diodes 801 are formed adjacent to the first IMD layer 803 at an end of the conductive TIVs 807 opposite the top electrodes 609. The diodes 801 are embedded within the second IMD layer 1005, and the conductive contacts 805 are electrically coupled to the diodes 801 for external connection of bit lines (e.g., BL1, BL2) to the first stacked memory cell. In some embodiments, diodes 801 are formed as p-n diodes, with the p-type material of diodes 801 facing conductive TIVs 807 and the n-type material facing conductive contacts 805. In other embodiments, the diodes 801 may be formed with a reverse orientation such that the n-type material of the diodes 801 faces the conductive TIVs 807 and the p-type material faces the conductive contacts 805. The word lines 1101 are electrically coupled to the encompassing gate 605, which provides common access via the channel layer 109 between the first source line SL 1 and the first resistor R 1 or the second source line SL 2 and the second resistor R 2.FIG. 12 is a circuit diagram of a memory circuit 1200 equivalent to the first stacked memory cell 613 (e.g., type 1T2R) illustrated in FIG. 11, in accordance with some embodiments. FIG. 12 further illustrates a current 1201 through the memory circuit 1200 during a write operation to the first resistor R 1, in accordance with some embodiments. During the write operation, a write voltage V W may be applied to the first bit line BL 1 of the memory circuit 1200, a reference (e.g., ground (0 V)) may be applied to the second bit line BL 2, and a word line voltage V WL is applied to the word line WL to activate the second transistor T 2. Therefore, the current 1201 flows to the source line SL via the second transistor T 2, which sets a resistance value of the first resistor R 1 according to the write voltage V W applied to the first bit line BL 1. FIG. 12 further illustrates that leakage current 1203 cannot flow via second bit line BL 2 because write voltage V W is applied in the reverse direction for second diode D 2. Thus, during write operations to the first resistor R 1, write disturb states of the second resistor R 2 are avoided, which ensures that the second 3D memory device 850 comprises highly robust memory cells.During a write operation to the second resistor R 2, the write voltage V W is applied to the second bit line BL 2 and the reference voltage (e.g., 0 V) is applied to the first bit line BL 1. In response to the word line voltage V WL being applied to the word line WL to activate the second transistor T 2, the current 1201 flows to the source line SL via the second transistor T 2, setting a resistance value of the second resistor R 2 according to the write voltage V W. During write operations to the second resistor R 2, no leakage current 1203 flows via the first bit line BL 1, since the write voltage V W for the first diode D 1 is present in the reverse direction. During writes to the second resistor R 2, write disturb states of the first resistor R 1 are also avoided, which ensures that the second 3D memory device 850 comprises highly robust memory cells.FIG. 13 illustrates a cross-sectional view of an interconnect structure 1300 including conductive vias 1180 for electrically coupling one or more bit lines 1007, source lines 1009, and / or word lines 1101 of the second 3D memory device 850 to a first device region 1301 of the device structure 103, in accordance with some embodiments. In some embodiments, the first device region 1301 is adjacent to the staircase contact structure 800 and includes active devices and / or signal, power and ground lines of a first functional semiconductor die. The first device area 1301 may include embedded logic devices, such as central processing units (CPUs), signal processors, input / output ports, system memory, and / or secondary storage devices.According to some embodiments, the device structure 103 includes a substrate 50, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an isolation layer. The isolation layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or Galliumindiumarsenidphosphid; or combinations thereof.FIG. 13 further illustrates circuits that may be formed over the substrate 50 to form circuits embedded within the device structure 103. The circuits include active devices (e.g., transistors) on a top surface of the substrate 50. The transistors may include gate dielectric layers 202 over top surfaces of the substrate 50 and gate electrodes 204 over the gate dielectric layers 202. Source / drain regions 206 are provided in the substrate 50 on opposite sides of the gate dielectric layers 202 and the gate electrodes 204. Gate spacers 208 are formed along sidewalls of the gate dielectric layers 202 and separate the source / drain regions 206 from the gate electrodes 204 by appropriate lateral distances. In some embodiments, the transistors may be planar field effect transistors (FETs), fin field effect transistors (FinFETs), nano field effect transistors (nano FETs), or the like.A first ILD layer 210 surrounds and isolates the source / drain regions 206, the gate dielectric layers 202, and the gate electrodes 204, and a second ILD layer 212 overlies the first ILD layer 210. Source / drain contacts 214 extend through the second ILD layer 212 and the first ILD layer 210 and are electrically coupled to the source / drain regions 206, and gate contacts 216 extend through the second ILD layer 212 and are electrically coupled to the gate electrodes 204. An interconnect structure 220 including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more stacked dielectric layers 224 overlies the second ILD layer 212, the source / drain contacts 214, and the gate contacts 216. Although FIG. 12 illustrates two of the stacked dielectric layers 224, it should be understood that the interconnect structure 220 may include any number of stacked dielectric layers 224 having conductive features 222 provided therein. The interconnect structure 220 may be electrically connected to the gate contacts 216 and the source / drain contacts 214 to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure 220 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, and the like, or combinations thereof. Although FIG. 12 discusses transistors formed over the substrate 50, other active devices (e.g., diodes or the like) and / or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits.As discussed above, the interconnect structure 1300 is formed over the device structure 103 by first forming the first IMD layer 803 over the device structure 103 and the second IMD layer 1005 over the first IMD layer 803. Once the first IMD layer 803, the second IMD layer 1005, and (if provided) a top dielectric layer of the interconnect structure 220 have been formed, suitable photolithography and etching processes may be used to form openings through these ILD layers at desired locations of the conductive vias 1180. Thus, contact pads of the conductive features 222 are exposed through the openings.For example, the conductive vias 1180 may extend through the second IMD layer 1005, the first IMD layer 803, and / or the stacked dielectric layers 224 to electrically connect the bit lines 1007, the source lines 1009, and / or the word lines 1101 to the underlying circuits of the interconnect structure 220 and the active devices on the substrate 50. In some embodiments, the routing and / or power lines to and from the memory array may be provided by an interconnect structure formed over the second stacked 3D memory array 600 in addition to or in place of the interconnect structure 220. The second 3D memory device 850 may be completed accordingly.In an embodiment where the conductive contacts 805 are conductive pillars (e.g., of tungsten, copper, aluminum, titanium, alloys, combinations, or the like), the conductive contacts 805 may be formed by first forming the first IMD layer 803 over the first region 115 and the second region 117 of the second multilayer stack 101. After the formation, the first IMD layer 803 is patterned using suitable photolithography and etching processes to form openings through the interlayer dielectric layer and expose areas of the word lines 1101 and / or staircase contact pads 905 at desired locations of the conductive contacts 805. After the openings are formed, they may be filled and / or overfilled with a conductive fill material (e.g., W, Al, Cu, or the like) using a suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like). After the conductive contacts 805 are deposited, a planarization process may be performed to collimate the top surfaces of the conductive contacts 805 to be coplanar with a surface of the interlayer dielectric layer. According to some embodiments, the interlayer dielectric layer (not shown) may remain after the formation of the conductive contacts 805 to enable further processing of the second stacked 3D memory array 600.Reference is now made to FIG. 14A. This figure illustrates a third 3D memory device 1450, according to some other embodiments. The third 3D memory device 1450 is similar to the second 3D memory device 850 (shown in FIG. 8), except that the diodes 801 are formed adjacent the top electrodes 609 of the first resistors R 1 and the second resistors R 2 rather than being formed over the first IMD layer 803. According to some embodiments, the third 3D memory device 1450 may be formed using an inter-metal dielectric layer last (IMD) process.FIG. 14B illustrates the cross-sectional view of the cut line A-A through the staircase contact structure 800 of FIG. 14A. FIG. 14B is similar to FIG. 10A, except that the diodes 801 are provided adjacent to the top electrodes 609 instead of over the first IMD layer 803 and the conductive TIVs 807 are provided over the diodes 801. The stair contact structure 800 may be formed using the materials and processes indicated above with respect to FIG. 9. According to some embodiments, after forming the staircase contact structure 800, the diodes 801 may be formed by first placing a mask (e.g., a photoresist) over the first region 115 and the second region 117 of the third 3D memory device 1450. The mask (not shown) may be formed and patterned using any of the materials and processes used to form the photoresist 901 described above. After the formation, the mask is patterned to form openings through the mask at desired positions of the diodes 801 such that the upper electrodes 609 are exposed through the openings in the mask.After the formation of the openings, the oxide semiconductor layer 1001 of the first conductivity type is deposited using a selective growth process inside the openings and over the upper electrodes 609. According to some embodiments, the selective growth process may be a bottom-up process used to form the oxide semiconductor layers 1001 of the first conductivity type at the bottom of the openings without substantially forming along sidewalls of the openings. The selective growth process may be a time-controlled process such that the oxide semiconductor layers 1001 of the first conductivity type are formed to a desired thickness over the upper electrodes 609.In addition, the first conductive type oxide semiconductor layers 1001 may be formed using any of the materials suitable for forming the above-described bulk layer of the first conductive type oxide semiconductor layer 1001. The oxide semiconductor layer 1001 of the first conductivity type may be doped to have a first conductivity type (e.g., p-type) using any of the above-mentioned doping processes (e.g., in situ doping during epitaxial growth). However, any suitable materials, deposition processes, and / or doping processes may be used to form the oxide semiconductor layer 1001 of the first conductivity type. According to some embodiments, the oxide semiconductor layer 1001 of the first conductivity type may be planarized and / or reduced in thickness to a desired height, e.g., using an optional etching process. Therefore, the oxide semiconductor layer 1001 of the first conductivity type is formed over and electrically coupled to the upper electrodes 609 of the bit line portion of the staircase contact structure 800.The oxide semiconductor layer 1003 of the second conductivity type may be formed using a selective growth process having a desired thickness within the openings over the oxide semiconductor layers 1001 of the first conductivity type. According to some embodiments, the selective growth process may be a bottom-up process used to form the oxide semiconductor layers 1003 of the second conductivity type at the bottom of the openings over the oxide semiconductor layers 1001 of the first conductivity type without substantially forming along sidewalls of the openings. The selective growth process may be a time-controlled process such that the oxide semiconductor layers 1003 of the second conductivity type are formed to a desired thickness over the oxide semiconductor layers 1001 of the first conductivity type.In addition, the second conductive type oxide semiconductor layers 1003 may be formed using any of the materials suitable for forming the above-described bulk layer of the second conductive type oxide semiconductor layer 1003. The oxide semiconductor layer 1003 of the second conductivity type may be doped to have a second conductivity type (e.g., n-type) doped opposite to the first conductivity type (e.g., p-type) using any of the above-mentioned doping processes (e.g., in situ doping during epitaxial growth). However, any suitable materials, deposition processes, and / or doping processes may be used to form the oxide semiconductor layer 1003 of the second conductivity type. In some embodiments, the oxide semiconductor layer 1003 of the second conductivity type may be planarized and / or reduced in thickness to a desired height, e.g., using an optional etching process. Therefore, the diodes 801 including the oxide semiconductor layer 1001 of the first conductivity type and the oxide semiconductor layer 1003 of the second conductivity type are formed over and electrically coupled to the upper electrodes 609 in the bit line portion of the staircase contact structure 800. Once the diodes 801 have been formed, the mask may be removed using a suitable removal process (e.g., ashing).With the removal of the mask, the diodes 801 and the surfaces of the staircase contact structure 800 not covered by the diodes 801 are exposed. Therefore, the first IMD layer 803 may be formed over the staircase contact structure 800 and the diodes 801 using any of the suitable materials and processes noted above. In addition, the conductive TIVs 807 may be formed through the first IMD layer 803 to the diodes 801 by first forming openings through the first IMD layer 803. Once the openings have been formed through the first IMD layer 803, the diodes 801 are exposed at the bottom of the openings. The conductive TIVs 807 are then formed using any of the materials and processes set forth above to the diodes 801. After the formation, the conductive TIVs 807 are planarized with the surface of the first IMD layer 803.Further, the second IMD layer 1005 is formed over the planar surfaces of the first IMD layer 803 and / or the isolation layers 107, and the conductive contacts 805 are formed down through the second IMD layer 1005 toward the conductive TIVs 807, as described above. In addition, the conductive TIVs 807 are formed through the first IMD layer 803 to the metallic source / bit lines 603, and the conductive contacts 805 are formed over the conductive TIVs 807 in the source line pattern portion of the staircase contact pattern 800, as described above. Further, as described above, the conductive contacts 805 are formed over the encompassing gates 605 of the second stacked 3D memory array 600.After the formation of the conductive contacts 805, the bit lines 1007 are formed over the conductive contacts 805 for external connection to the diodes 801 in the staircase contact structure 800. Further, the source lines 1009 are formed over the conductive contacts 805 for external connection to the metallic source / bit lines 603 in the staircase contact structure 800. Moreover, as described above, the word lines 1101 are formed over the conductive contacts 805 for external connection to the encompassing gates 605 of the second stacked 3D memory array 600. According to some embodiments, the bit lines 1007, the source lines 1009, and the word lines 1101 electrically couple the third 3D memory device 1450 to the interconnect structure 1300 in the first device region 1301. As described above, the interconnect structure 1300 electrically couples one or more of the bit lines 1007, the source lines 1009, and / or the word lines 1101 to one or more active devices and / or signal, power, and / or ground lines of the first functional semiconductor die (e.g., embedded logic devices, central processing units (CPUs), signal processors, input / output ports, system memory, and / or secondary storage devices).Reference is now made to Fig. 15. This figure is a two-dimensional illustration of the first stacked memory cell 613 (e.g., type 1T2R) in the third 3D memory device 1450 and the adjacent staircase contact structure 800, in accordance with some embodiments. Although the components of the first stacked memory cell 613 are illustrated in the two-dimensional illustration, it should be appreciated that the first source line SL 1, the second source line SL 2, the word line WL, the first bit line BL 1, and the second bit line BL 2 may lie in different cross-sections through the third 3D memory device 1450 of FIG. 14A.Continuing with FIG. 15, this figure is similar to FIG. 11 except that the diodes 801 are formed adjacent to the top electrodes 609 instead of on top of the first IMD layer 803 and the conductive TIVs 807 are formed over the diodes 801. The diodes 801 are embedded within the second IMD layer 1005, and the conductive contacts 805 are electrically coupled to the conductive TIVs 807 for external connection of bit lines (e.g., BL1, BL2) to the first stacked memory cell. According to some embodiments, the diodes 801 are formed as p-n diodes, wherein the p-type material of the diodes 801 faces the top electrodes 609 and the n-type material faces the conductive TIVs 807. In other embodiments, the diodes 801 may be formed with a reverse orientation such that the n-type material of the diodes 801 faces the top electrodes 609 and the p-type material of the diodes 801 faces the conductive TIVs 807. The word lines 1101 are electrically coupled to the encompassing gate 605, which provides common access via the channel layer 109 between the first source line SL 1 and the first resistor R 1 or the second source line SL 2 and the second resistor R 2.Reference is now made to Fig. 16. This figure illustrates a cross-sectional view of the cut line A-A through the staircase contact structure 800 of the third 3D memory device 1450 formed using an IMD layer-first process, in accordance with some other embodiments. The formation of the staircase contact structure 800 illustrated in FIG. 16 is similar to the formation of the staircase contact structure 800 illustrated in FIG. 14B, except that the first IMD layer 803 is formed over the top electrodes 609 prior to the formation of the diodes 801.According to some embodiments, the stair contact structure 800 may be formed using the materials and processes indicated above with respect to FIG. 9. After the stair contact structure 800 is formed, the first IMD layer 800 may be formed over the stair contact structure 803 using any of the suitable materials and processes noted above. As described above, the diodes 801 may be formed by first placing the mask (e.g., the photoresist) over the first region 115 and the second region 117 of the third 3D memory device 1450. The mask (not shown) may be formed and patterned using any of the materials and processes used to form the photoresist 901 described above. After the formation, the mask is patterned to form openings through the mask at desired positions of the diodes 801 such that the first IMD layer 803 is exposed through the openings in the mask. The mask is then used to form openings through the first IMD layer 803 exposing the top electrodes 609 at the bottom of the openings.Once the upper electrodes 609 at the bottom of the openings have been exposed, the diodes 801 at the bottom of the openings may be formed by depositing the oxide semiconductor layers 1001 of the first conductivity type and the oxide semiconductor layers 1003 of the second conductivity type inside the openings and over the upper electrodes 609. The oxide semiconductor layer 1001 of the first conductivity type and the oxide semiconductor layer 1003 of the second conductivity type may be formed using the selective growth process (e.g., bottom-up deposition) without substantially forming along sidewalls of the openings at the bottom of the openings. The selective growth process may also be a time-controlled process such that the oxide semiconductor layers 1001 of the first conductivity type and the oxide semiconductor layers 1003 of the second conductivity type are formed over the upper electrodes 609 having the desired thickness of the diodes 801. In addition, as discussed above, each of the first conductive type oxide semiconductor layers 1001 and the second conductive type oxide semiconductor layers 1003 are doped in opposition (e.g., in situ doped during epitaxial growth). For example, the oxide semiconductor layers 1001 of the first conductivity type may be doped according to a first conductivity type (e.g., p-type), and the oxide semiconductor layers 1003 of the second conductivity type may be doped according to a second conductivity type (e.g., n-type).After the diodes 801 have been formed, a dielectric fill material 1601 is deposited over the diodes 801 to fill and / or overfill the openings. The dielectric fill material 1601 may be formed using any of the materials and processes suitable for forming the first IMD layer 803. According to some embodiments, the material used to form the dielectric fill material 1601 is the same material as that used to form the first IMD layer 803. In other embodiments, the material used to form the dielectric fill material 1601 is different from the material used to form the first IMD layer 803. After formation, the dielectric fill material 1601 may be planarized (e.g., by CMP) with the second IMD layer 1005 to remove any excess dielectric fill material 1601 present outside the openings.The conductive TIVs 807 may be formed by first forming openings through the dielectric fill material 1601 that expose the diodes 801 at the bottom of the openings. The openings may be formed through the dielectric fill material 1601 using any of the materials and processes listed above suitable for forming openings for the conductive TIVs 807 in the first IMD layer 803.After the openings are formed through the dielectric fill material 1601, the conductive TIVs 807 are then formed to the diodes 801 using any of the materials and processes noted above. After the formation, the conductive TIVs 807 are planarized with the surface of the first IMD layer 803 and the dielectric fill material 1601. Further, the second IMD layer 1005 may be formed as described above. The conductive contacts 805 may be formed through the second IMD layer 1005 and electrically connected to the conductive TIVs 807, as described above. According to some embodiments, the bit lines 1007 are formed to the conductive contacts 805 and couple one or more of the diodes to the interconnect structure 1300 in the first device region 1301.Further, the conductive TIVs 807 may be formed in the source line structure portion of the staircase contact structure 800 by first forming openings through the first IMD layer 803 exposing the metallic source / bit lines 603 through the openings. After the formation, the conductive TIVs 807, the second IMD layer 1005, the conductive contacts 805, the source lines 1009, and the word lines 1101 may be formed as described above.Reference is now made to Fig. 17. This figure is a two-dimensional illustration of the first stacked memory cell 613 (e.g., type 1T2R) in the third 3D memory device 1450 and the adjacent staircase contact structure 800, in accordance with some embodiments. Although the components of the first stacked memory cell 613 are illustrated in the two-dimensional illustration, it should be appreciated that the first source line SL 1, the second source line SL 2, the word line WL, the first bit line BL 1, and the second bit line BL 2 may lie in different cross-sections through the third 3D memory device 1450 of FIG. 14A.Continuing with FIG. 17, this figure is similar to FIG. 15 except that the dielectric fill material 1601 surrounds the conductive TIVs 807 provided over the diodes 801. The diodes 801, the dielectric fill material 1601, and the remaining conductive TIVs 807 are embedded within the second IMD layer 1005, and the conductive contacts 805 are electrically coupled to the conductive TIVs 807 for external connection of bit lines (e.g., BL1, BL2) to the first stacked memory cell 613. According to some embodiments, the diodes 801 are formed as p-n diodes, wherein the p-type material of the diodes 801 faces the top electrodes 609 and the n-type material faces the conductive TIVs 807. In other embodiments, the diodes 801 may be formed with a reverse orientation such that the n-type material of the diodes 801 faces the top electrodes 609 and the p-type material faces the conductive TIVs 807. The word lines 1101 are electrically coupled to the encompassing gate 605, which provides shared access between the first source line SL 1 and the first resistor R 1 and between the second source line SL 2 and the second resistor R 2 via the channel layer 109.The embodiments of the present disclosure have some advantageous features. forming a three-dimensional (3D) memory array (e.g., an RRAM memory array) comprising a plurality of stacked memory cells (e.g., 1T2R memory cells) and including forming a first diode over a first resistor of the memory cell and a second diode over a second resistor of the memory cell. Therefore, the first diode and the second diode may be referred to herein as BEOL compatible diodes. In addition, the source line and the bit line corresponding to the same memory cell are formed in the same layer, enabling a reduction in the height and aspect ratio of the multilayer stack used in the manufacturing process. The resulting 3D memory array may also have a reduced height and / or an increasing device density. Therefore, the storage density of the resulting 3D memory array may be twice the storage density of a memory array of the same chip size. Further, embodiments of the present disclosure provide a memory cell (e.g., type 1T2R) that avoids problems with write disturbances in writes to a targeted resistance of the memory cell. For example, during write operations to a non-addressed resistor of the memory cell, leakage currents are prevented from flowing through the bit line of the non-addressed resistor of the memory cell due to reverse bias of the diode connected to the non-addressed resistor.According to an embodiment, a memory device includes: a resistive memory array including a first resistive memory cell; a staircase contact structure adjacent to the resistive memory array; an inter-metal dielectric layer over the staircase contact structure; a first diode and a second diode over the inter-metal dielectric layer; a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell; and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell. In an embodiment of the memory device, the first conductive via is connected to a first top electrode of the first resistor and the second conductive via is connected to a second top electrode of the second resistor. In an embodiment of the memory device, a first bit line is electrically coupled to the first resistor and a second bit line is electrically coupled to the second resistor, wherein the first bit line and the second bit line are at least partially provided in the first resistive memory cell. In an embodiment of the memory device, the first bit line is connected to a first resistive memory film of the first resistor and the second bit line is connected to a second resistive memory film of the second resistor. In an embodiment of the memory device, the first resistive memory cell includes a first transistor and the memory device further includes a third conductive via connected to a first source line electrically coupled to the first transistor; and a fourth conductive via connected to a second source line electrically coupled to the first transistor. In an embodiment of the memory device, the first transistor includes a gate dielectric surrounding a channel region of the first transistor and a surrounding gate, wherein the channel region of the first transistor separates the first source line from the second source line and separates the first bit line from the second bit line. In an embodiment, the memory device further includes a second resistive memory cell over the first resistive memory cell; a third diode and a fourth diode over the inter-metal dielectric layer; a fifth conductive via electrically coupling the third diode to a third resistor of the second resistive memory cell; and a sixth conductive via electrically coupling the fourth diode to a fourth resistor of the second resistive memory cell.In another embodiment, a memory device includes a first memory cell including a first transistor, a first resistor, and a second resistor, the first resistor coupled to a first bit line and the second resistor coupled to a second bit line; a first diode connected to a first electrode of the first resistor; a second diode connected to a second electrode of the second resistor, the first electrode of the first resistor overlying the second electrode of the second resistor; a first conductive via connected to the first diode; a second conductive via connected to the second diode; and an inter-metal dielectric layer, the first diode, the second diode, the first conductive via, and the second conductive via being embedded in the inter-metal dielectric layer. In an embodiment of the memory device, the first diode includes a semiconductor oxide layer of a first conductivity type adjacent to the first electrode of the first resistor. In an embodiment of the memory device, the first diode includes a semiconductor oxide layer of a second conductivity type adjacent to the semiconductor oxide layer of the first conductivity type. In one embodiment of the memory device, the semiconductor oxide layer of the first conductivity type is p-conductive and the semiconductor oxide layer of the second conductivity type is n-conductive. In an embodiment, the memory device further includes a third conductive via connected to a first source line; and a fourth conductive via connected to a second source line, wherein the third conductive via and the fourth conductive via are embedded in the inter-metal dielectric layer. In an embodiment of the memory device, the first transistor includes a surrounding gate surrounding a first channel region of the first transistor. In an embodiment, the memory device further includes a second memory cell over the first memory cell, the second memory cell comprising a second transistor, a third resistor, and a fourth resistor, the third resistor coupled to a third bit line and the fourth resistor coupled to a fourth bit line; a third diode connected to a third electrode of the third resistor; a fourth diode connected to a fourth electrode of the fourth resistor, the third electrode of the third resistor overlying the fourth electrode of the fourth resistor; a fifth conductive via connected to the third diode; and a sixth conductive via connected to the fourth diode, the third diode, the fourth diode, the fifth conductive via, and the sixth conductive via being embedded in the intermetal dielectric layer. In an embodiment of the memory device, the surrounding gate surrounds a second channel region of the second transistor.In yet another embodiment, a method includes forming a resistive memory array in a first region of a multilayer stack of materials, the resistive memory array comprising a first memory cell; exposing a first resistor and a second resistor of the first memory cell by forming a staircase contact structure adjacent to the resistive memory array; forming a first diode over the staircase contact structure, the first diode electrically coupled to the first resistor; and forming a second diode over the staircase contact structure, the second diode electrically coupled to the second resistor. In an embodiment, the method further includes forming an inter-metal dielectric layer over the staircase contact structure; forming a first via through the inter-metal dielectric layer to the first resistor; and forming a second via through the inter-metal dielectric layer to the second resistor, wherein forming the first diode and the second diode includes depositing a first conductivity type semiconductor oxide layer over the inter-metal dielectric layer; depositing a second conductivity type semiconductor oxide layer over the first conductivity type semiconductor oxide layer; and forming the first diode connected to the first via and the second diode connected to the second via by patterning the first conductivity type semiconductor oxide layer and the second conductivity type semiconductor oxide layer. In an embodiment of the method, forming the first diode includes forming the first diode in direct contact with the first resistor, forming the second diode includes forming the second diode in direct contact with the second resistor, the method further including forming an inter-metal dielectric layer over the first diode, the second diode, and the staircase contact structure; forming a first via through the inter-metal dielectric layer to the first diode; and forming a second via through the inter-metal dielectric layer to the second diode. In an embodiment, the method further includes forming an inter-metal dielectric layer over the staircase contact structure; exposing the first resistor and the second resistor by forming openings in the inter-metal dielectric layer; forming diodes by depositing a semiconductor oxide material of a first conductivity type over the first resistor and the second resistor at the bottom of the openings and depositing a semiconductor oxide material of a second conductivity type over the semiconductor oxide material of the first conductivity type at the bottom of the openings; filling the openings with a dielectric material; and forming a conductive via through the dielectric material to each of the diodes. In an embodiment of the method, forming the first conductivity type semiconductor oxide material includes using a p-type dopant, wherein forming the second conductivity type semiconductor oxide material includes using an n-type dopant.

Claims

A memory device (850) comprising: a resistive memory array (600) comprising a first resistive memory cell (613); a staircase contact structure (800) adjacent to the resistive memory array (600); an inter-metal dielectric layer (803) over the staircase contact structure (800); a first diode (801, D1) and a second diode (801, D2) over the inter-metal dielectric layer (803); a first conductive via (807) electrically coupling the first diode (801, D1) to a first resistor (R1) of the first resistive memory cell (613); and a second conductive via (807) electrically coupling the second diode (801, D2) to a second resistor (R2) of the first resistive memory cell (613).The memory device (850) of claim 1, wherein the first conductive via (807) is connected to a first top electrode (609) of the first resistor (R1), and wherein the second conductive via (807) is connected to a second top electrode (609) of the second resistor (R2).The memory device (850) of claim 2, wherein a first bit line (BL1) is electrically coupled to the first resistor (R1) and a second bit line (BL2) is electrically coupled to the second resistor (R2), wherein the first bit line (BL1) and the second bit line (BL2) are at least partially provided in the first resistive memory cell (613).The memory device (850) of claim 3, wherein the first bit line (BL1) is connected to a first resistive memory film (611) of the first resistor (R1), and wherein the second bit line (BL2) is connected to a second resistive memory film (611) of the second resistor (R2).The memory device (850) of claim 4, wherein the first resistive memory cell (613) comprises a first transistor (T1), the memory device (850) further comprising: a third conductive via (807) connected to a first source line (SL1) electrically coupled to the first transistor (T1); and a fourth conductive via (807) connected to a second source line (SL2) electrically coupled to the first transistor (T1).The memory device (850) of claim 5, wherein the first transistor (T1) comprises a gate dielectric (401) surrounding a channel region of the first transistor (T1) and a surrounding gate (605), wherein the channel region of the first transistor (T1) separates the first source line (SL1) from the second source line (SL2) and separates the first bit line (BL1) from the second bit line (BL2).The memory device (850) of claim 6, further comprising: a second resistive memory cell (613) over the first resistive memory cell (613); a third diode (801, D3) and a fourth diode (801, D4) over the inter-metal dielectric layer (803); a fifth conductive via (807) electrically coupling the third diode (801, D3) to a third resistor (R3) of the second resistive memory cell (613); and a sixth conductive via (807) electrically coupling the fourth diode (801, D4) to a fourth resistor (R4) of the second resistive memory cell (613).A memory device (850) comprising: a first memory cell (613) comprising a first transistor (T1), a first resistor (R1) and a second resistor (R2), wherein the first resistor (R1) is coupled to a first bit line (BL1) and the second resistor (R2) is coupled to a second bit line (BL2); a first diode (801, D1) connected to a first electrode (609) of the first resistor (R1); a second diode (801, D2) connected to a second electrode (609) of the second resistor (R2), wherein the first electrode (609) of the first resistor (R1) overlies the second electrode (609) of the second resistor (R2); a first conductive via (807) connected to the first diode (801, D1); a second conductive via (807) connected to the second diode (801, D2); and an inter-metal dielectric layer (803), wherein the first diode (801, D1), the second diode (801, D2), the first conductive via (807), and the second conductive via (807) are embedded in the inter-metal dielectric layer (803).The memory device (850) of claim 8, wherein the first diode (801, D1) comprises a semiconductor oxide layer of a first conductivity type adjacent to the first electrode (609) of the first resistor (R1).The memory device (850) of claim 9, wherein the first diode (801, D1) comprises a semiconductor oxide layer of a second conductivity type adjacent to the semiconductor oxide layer of the first conductivity type.The memory device (850) of claim 10, wherein the first conductivity type semiconductor oxide layer is p-type and the second conductivity type semiconductor oxide layer is n-type.The memory device (850) of claim 11, further comprising: a third conductive via (807) connected to a first source line (SL1); and a fourth conductive via (807) connected to a second source line (SL2), wherein the third conductive via (807) and the fourth conductive via (807) are embedded in the inter-metal dielectric layer (803).The memory device (850) of claim 12, wherein the first transistor (T1) comprises a surrounding gate (605) surrounding a first channel region of the first transistor (T1).The memory device (850) of claim 13, further comprising: a second memory cell (613) over the first memory cell (613), the second memory cell (613) comprising a second transistor (T2), a third resistor (R3), and a fourth resistor (R4), the third resistor (R3) being coupled to a third bit line (BL3), and the fourth resistor (R4) being coupled to a fourth bit line (BL4); a third diode (801, D3) being connected to a third electrode (609) of the third resistor (R3); a fourth diode (801, D4) connected to a fourth electrode (609) of the fourth resistor (R4), the third electrode (609) of the third resistor (R3) overlying the fourth electrode (609) of the fourth resistor (R4); a fifth conductive via (807) connected to the third diode (801, D3); and a sixth conductive via (807) connected to the fourth diode (801, D4), the third diode (801, D3), the fourth diode (801, D4), the fifth conductive via (807) and the sixth conductive via (807) being embedded in the intermetal dielectric layer (803).The memory device (850) of claim 14, wherein the encompassing gate (605) surrounds a second channel region of the second transistor (T2).A method comprising: forming a resistive memory array (600) in a first region (115) of a multilayer stack (101) of materials, the resistive memory array (600) comprising a first memory cell (613); exposing a first resistor (R1) and a second resistor (R2) of the first memory cell (613) by forming a staircase contact structure (800) adjacent to the resistive memory array (600); forming a first diode (801, D1) over the staircase contact structure (800), wherein the first diode (801, D1) is electrically coupled to the first resistor (R1); and forming a second diode (801, D2) over the staircase contact structure (800), wherein the second diode (801, D2) is electrically coupled to the second resistor (R2).The method of claim 16, further comprising: forming an inter-metal dielectric layer (803) over the staircase contact structure (800); forming a first via (807) through the inter-metal dielectric layer (803) to the first resistor (R1); and forming a second via (807) through the inter-metal dielectric layer (803) to the second resistor (R2), wherein forming the first diode (801, D1) and the second diode (801, D2) comprises: depositing a first conductivity type semiconductor oxide layer over the inter-metal dielectric layer (803); depositing a second conductivity type semiconductor oxide layer over the first conductivity type semiconductor oxide layer; and forming the first diode (801, D1) connected to the first via (807) and the second diode (801, D2) connected to the second via (807) by patterning the first conductive type semiconductor oxide film and the second conductive type semiconductor oxide film.The method of claim 16, wherein forming the first diode (801, D1) comprises forming the first diode (801, D1) in direct contact with the first resistor (R1), wherein forming the second diode (801, D2) comprises forming the second diode (801, D2) in direct contact with the second resistor (R2), and wherein the method further comprises: forming an inter-metal dielectric layer (803) over the first diode (801, D1), the second diode (801, D2), and the staircase contact structure (800); forming a first via (807) through the inter-metal dielectric layer (803) to the first diode (801, D1); and forming a second via (807) through the inter-metal dielectric layer (803) to the second diode (801, D2).The method of claim 16, further comprising: forming an inter-metal dielectric layer (803) over the staircase contact structure (800); exposing the first resistor (R1) and the second resistor (R2) by forming openings in the inter-metal dielectric layer (803); forming diodes (801) by depositing a first conductivity type semiconductor oxide material over the first resistor (R1) and the second resistor (R2) at the bottom of the openings and depositing a second conductivity type semiconductor oxide material over the first conductivity type semiconductor oxide material at the bottom of the openings; filling the openings with a dielectric material (401); and forming a conductive via (807) through the dielectric material (401) to each of the diodes (801).The method of claim 19, wherein forming the first conductivity type semiconductor oxide material comprises using a p-type dopant, and wherein forming the second conductivity type semiconductor oxide material comprises using an n-type dopant.

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