Semiconducting metal oxide storage device and semiconductor device with hydrogen-mediated threshold voltage modulation and operating method thereof

Abstract

Storage device comprising: a first electrode (126); a storage layer stack arranged on the first electrode (126) and comprising at least one semiconducting metal oxide layer (130) and a plurality of hydrogen-containing metal layers (140) containing at least one metal selected from platinum, iridium, osmium, and ruthenium with an atomic percentage of at least 90% and containing hydrogen atoms, wherein one of the at least one semiconducting metal oxide layer (130) contacts two of the plurality of hydrogen-containing metal layers (140); and a second electrode (158) arranged above the storage layer stack.

Description

BACKGROUND

[0001] As semiconductor components become ever smaller, new types of semiconductor memory cells are in demand that offer a long service life and require low operating power consumption. US 2016 / 0 118 579 A1 discloses a memory device comprising two platinum electrodes, between which a semiconducting metal oxide layer containing mobile hydrogen ions is arranged. Further devices are also known from US 2016 / 0 049 584 A1, EP 2 139 054 A2, and KR 10 2004 0 021 771 A.

[0002] The task is to improve corresponding semiconductor devices.

[0003] The object is achieved by the memory device according to patent claim 1, the semiconductor device according to patent claim 10 and the operating method according to patent claim 15. Further embodiments emerge from the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1 is a vertical cross-sectional view of a first exemplary structure after formation of complementary metal oxide semiconductor (CMOS) transistors, metal interconnect structures embedded in dielectric material layers, and an interconnect via level dielectric layer according to a first embodiment of the present disclosure. Fig. 2 is a vertical cross-sectional view of the first exemplary structure after forming an array of interconnect via structures according to the first embodiment of the present disclosure. Fig. 3 is a vertical cross-sectional view of the first exemplary structure after forming a first electrode material layer, a memory material layer stack, and a second electrode material layer according to the first embodiment of the present disclosure. Fig. 4 is a vertical cross-sectional view of the first exemplary structure after patterning pillar structures comprising a first electrode, a memory layer stack, and a second electrode according to the first embodiment of the present disclosure. Fig. 5 is a vertical cross-sectional view of the first exemplary structure after formation of dielectric diffusion barrier spacers according to the first embodiment of the present disclosure. Fig. 6 is a vertical cross-sectional view of the first exemplary structure after formation of a memory level dielectric layer and memory level metal interconnect structures and planarization of the top electrodes according to the first embodiment of the present disclosure. Fig. 7 is a vertical cross-sectional view of a first alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. Fig. 8 is a vertical cross-sectional view of a second alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. Fig. 9 is a vertical cross-sectional view of a third alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. Fig. 10 is a vertical cross-sectional view of a fourth alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. Fig. 11 is a vertical cross-sectional view of a fifth alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. Fig. 12A is a vertical cross-sectional view of a second exemplary structure after forming a semiconducting metal oxide layer over a dielectric material layer according to a second embodiment of the present disclosure. Fig. 12B is a plan view of the second exemplary structure of Fig. 12A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 12A. Fig. 13A is a vertical cross-sectional view of the second exemplary structure after forming a hydrogen-containing metal layer and a gate electrode over the semiconducting metal oxide layer according to the second embodiment of the present disclosure. Fig. 13B is a plan view of the second exemplary structure of Fig. 13A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 13A. Fig. 14A is a vertical cross-sectional view of the second exemplary structure after formation of a dielectric diffusion barrier spacer, a source region, and a drain region according to the second embodiment of the present disclosure. Fig. 14B is a plan view of the second exemplary structure of Fig. 14A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 14A. Fig. 15A is a vertical cross-sectional view of the second exemplary structure after forming a source contact via structure, a drain contact via structure, and a gate contact via structure according to the second embodiment of the present disclosure. Fig. 15B is a plan view of the second exemplary structure of Fig. 15A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 15A. Fig. 16A is a vertical cross-sectional view of a first alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. Fig. 16B is a plan view of the first alternative configuration of the second exemplary structure of Fig. 16A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 16A. Fig. 17A is a vertical cross-sectional view of a second alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. Fig. 17B is a plan view of the second alternative configuration of the second exemplary structure of Fig. 17A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 17A. Fig. 18A is a vertical cross-sectional view of a third alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. Fig. 18B is a plan view of the third alternative configuration of the second exemplary structure of Fig. 18A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 18A. Fig. 19A is a vertical cross-sectional view of a fourth alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. Fig. 19B is a plan view of the fourth alternative configuration of the second exemplary structure of Fig. 19A. The vertical plane A - A' is the plane of the vertical cross-sectional view of Fig. 19A. Fig. 20 is a flowchart illustrating general processing steps of the methods of manufacturing a memory device according to the first embodiment of the present disclosure. Fig. 21 is a flowchart illustrating general processing steps of the methods of manufacturing a semiconductor device according to the second embodiment of the present disclosure. Fig. 22 is a flowchart illustrating general steps for operating a semiconductor device of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments and examples of implementing various features of the subject matter provided herein. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated throughout the various examples of the present disclosure.This repetition is for simplicity and clarity and does not necessarily dictate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "below," "above," "above," "upon," "above," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. These spatially relative terms are intended to encompass other orientations of the device during use or operation in addition to the orientation illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0007] Hydrides of all transition metals have been successfully synthesized to date, with the exception of those of the four platinum group metals and tungsten, as described in Antonov, VE [et al.]: The solubility of hydrogen in the platinum metals under high pressure. In: Johnson Matthey Technology Review, Vol. 28, 1984, No. 4, pp. 158-163. The "platinum metals" refers to platinum, iridium, osmium, and ruthenium. Regarding the platinum group metals, there have been numerous attempts to synthesize platinum, iridium, osmium, and ruthenium hybrids, but the failure to synthesize the platinum group metals is due to their low ability to accommodate hydrogen in their lattices. This inertness or resistance to hydrogen uptake is characterized by the fact that, although the chemical potential of hydrogen dissolved in metal can be very high, the solubilities of hydrogen corresponding to equivalent high external pressures of hydrogen gas are generally very low.

[0008] Thus, a hydrogen atom can be present in the platinum group metals (i.e., platinum, iridium, osmium, and ruthenium) without forming hydrides. Embodiments of the present disclosure recognize that hydrogen can be stored at a relatively high atomic concentration in a hydrogen-containing metal layer containing platinum, iridium, osmium, and / or ruthenium adjacent to a semiconducting metal oxide layer. Hydrogen can be reversibly incorporated into and / or extracted from a semiconducting metal oxide layer. The hydrogen atoms can be incorporated into interstitial sites of the semiconducting metal oxide material. The hydrogen atoms can act as a shallow donor, thereby lowering the threshold voltage of the semiconducting metal oxide material.

[0009] A stack of a hydrogen-containing metal layer and a semiconducting metal oxide layer may be provided between two electrodes or in a transistor configuration. An electric current may flow perpendicular to the interface between the hydrogen-containing metal layer and the semiconducting metal oxide layer. The electric current may have a variable conductivity depending on the amount of hydrogen incorporated into the semiconducting metal oxide layer. Alternatively, the electric current may flow along an in-plane (planar) direction within the semiconducting metal oxide layer, with different threshold voltages determined by the amount of hydrogen incorporated into the semiconducting oxide layer after application of a gate voltage to the hydrogen-containing metal layer. The various aspects of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0010] With reference to Fig. 1 illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes complementary metal-oxide-semiconductor (CMOS) transistors formed on a semiconductor substrate, for example, a single-crystal silicon substrate, and metal interconnect structures formed in dielectric material layers. In particular, the first exemplary structure includes a substrate 9, which may be a semiconductor substrate such as a commercially available silicon wafer. Shallow trench isolation structures 720 containing a dielectric material such as silicon oxide may be formed in an upper portion of the substrate 9. Suitable doped semiconductor wells, such as p-wells and n-wells, may be formed in any region laterally surrounded by a portion of the shallow trench isolation structures 720.Field-effect transistors may be formed over the top surface of substrate 9. For example, each field-effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735 comprising a surface portion of substrate 9 extending between source region 732 and drain region 738, and a gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a gate dielectric spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738.

[0011] In general, field-effect transistors may be formed on a semiconductor substrate, and electrodes of subsequently formed memory devices may be electrically connected to the respective field-effect transistors through metal interconnect structures formed over the semiconductor substrate in interconnect-level dielectric material layers. For example, the first exemplary structure may include a memory array region 100 in which an array of memory elements is subsequently formed, and a peripheral region 200 in which logic devices are formed that support the operation of the array of memory elements. In one embodiment, devices (e.g., field-effect transistors) in the memory array region 100 may include bottom electrode access transistors that enable access to the bottom electrodes of the subsequently formed memory cells.Top electrode access transistors, which enable access to the top electrodes of the memory cells to be subsequently formed, may be formed in the peripheral region 200 in this processing step. Devices (such as field-effect transistors) in the peripheral region 200 may provide functions required for the operation of the array of memory cells to be subsequently formed. In particular, the devices in the peripheral region may be configured to control the programming operation, the erasing operation, and the reading operation of the array of memory cells. For example, the devices in the peripheral region may include a sensing circuit and / or a top electrode bias circuit.The devices formed on the top surface of the substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.) and are collectively referred to as a CMOS circuit 700.

[0012] Various metal interconnect structures embedded in dielectric material layers may then be formed over the substrate 9 and the devices (e.g., field-effect transistors). The dielectric material layers may include, for example, a contact-level dielectric material layer 601, a first metal line-level dielectric material layer 610, a second line-and-via level dielectric material layer 620, a third line-and-via level dielectric material layer 630, and a fourth line-and-via level dielectric material layer 640. The metal interconnect structures may include device contact via structures 612 formed in the contact-level dielectric material layer 601 and contacting an associated component of the CMOS circuit 700, first metal line structures 618,formed in the first metal-level dielectric material layer 610, first metal via structures 622 formed in a lower portion of the second line-and-via level dielectric material layer 620, second metal line structures 628 formed in an upper portion of the second line-and-via level dielectric material layer 620, second metal via structures 632 formed in a lower portion of the third line-and-via level dielectric material layer 630, third metal line structures 638 formed in an upper portion of the third line-and-via level dielectric material layer 630, third metal via structures 642 formed in a lower portion of the fourth line-and-via level dielectric material layer 640, and fourth metal line structures 648,formed in an upper portion of the fourth line-and-via-level dielectric material layer 640. In one embodiment, the second metal line structures 628 may include source lines connected to a source-side power supply for an array of memory elements. The voltage provided by the source lines may be applied to the lower electrodes via the access transistors provided in the memory array region 100.

[0013] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the intended scope of disclosure may also be used.In one embodiment, the first metal via structures 622 and the second metal line structures 628 may be formed as integrated line and via structures by a dual damascene process, the second metal via structures 632 and the third metal line structures 638 may be formed as integrated line and via structures, and / or the third metal via structures 642 and the fourth metal line structures 648 may be formed as integrated line and via structures.While the present disclosure is described with reference to an embodiment in which an array of memory cells is formed over the fourth line and via level of the dielectric material layer 640, embodiments are expressly contemplated wherein the array of memory cells may be formed on a different metal interconnect level.

[0014] The dielectric material layers (601, 610, 620, 630, 640) are located at a lower level relative to an array of memory cells to be subsequently formed. Therefore, the dielectric material layers (601, 610, 620, 630, 640) are referred to herein as lower-level dielectric layers, i.e., a dielectric material layer that is located at a lower (bottom) level relative to the array of memory cells to be subsequently formed. The metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) are referred to herein as lower-level metal interconnect structures.A subset of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) includes lower-level metal lines (such as the fourth metal line structures 648) embedded in the lower-level dielectric layers and having upper surfaces within a horizontal plane that includes a top surface of the lower-level dielectric layers. Generally, the total number of metal line levels within the lower-level dielectric layers (601, 610, 620, 630, 640) may be 1 to 10.

[0015] A dielectric cap layer 108 and an interconnect via level dielectric layer 110 may be formed sequentially over the metal line structures and the dielectric material layers. For example, the dielectric cap layer 108 may be formed on the upper surfaces of the fourth metal line structures 648 and on the upper surface of the fourth line-and-via level dielectric layer 640. The dielectric cap layer 108 includes a dielectric cap material that may protect underlying metal interconnect structures such as the fourth metal line structures 648. In one embodiment, the dielectric cap layer 108 may include a material that provides high etch resistance, i.e., a dielectric material that may also serve as an etch stop material during a subsequent anisotropic etch process that etches the interconnect via level dielectric layer 110.The dielectric cap layer 108 may, for example, contain silicon carbide or silicon nitride and have a thickness of 5 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0016] The via level dielectric layer 110 may include any material that can be used for the dielectric material layers (601, 610, 620, 630, 640). For example, the via level dielectric layer 110 may include undoped silicate glass or a doped silicate glass deposited by decomposing tetraethyl orthosilicate (TEOS). The thickness of the via level dielectric layer 110 may be 50 nm to 200 nm, although smaller and larger thicknesses may also be used. The cap dielectric layer 108 and the via level dielectric layer 110 may be formed as covering (unstructured) layers having a respective planar top surface and a respective planar bottom surface that extends over the entire memory array region 100 and the peripheral region 200.

[0017] With reference to Fig. 2, via openings may be formed through the interconnect via level dielectric layer 110 and the dielectric capping layer 108. For example, a photoresist layer (not shown) may be applied over the interconnect via level dielectric layer 110 and patterned to form openings in portions of the memory array region 100 that overlie a respective one of the fourth metal line structures 648. An anisotropic etch may be performed to transfer the pattern in the photoresist layer through the interconnect via level dielectric layer 110 and the dielectric capping layer 108.The via cavities formed by the anisotropic etching process are referred to herein as bottom electrode contact via cavities because the bottom electrode connection via structures are subsequently formed in the bottom electrode contact via cavities. The bottom electrode contact via cavities may have tapered sidewalls with a taper angle (with respect to a vertical direction) of 1 degree to 10 degrees. A top surface of a fourth metal line structure 648 may be physically exposed at the bottom of each of the bottom electrode contact via cavities. The photoresist layer may then be removed, for example, by ashing.

[0018] A metal barrier layer may be formed as a material layer. The metal barrier layer may cover the physically exposed upper surfaces of the fourth metal line structures 648, the tapered sidewalls of the lower electrode contact via openings, and the upper surfaces of the interconnect via level dielectric layer 110 without having an opening therethrough. The metal barrier layer may include a conductive metallic nitride such as TiN, TaN, and / or WN. Other suitable materials within the scope of the disclosure may also be used. The thickness of the metal barrier layer may be 3 nm to 20 nm, although smaller and larger thicknesses may also be used.

[0019] A metal fill material, such as tungsten or copper, may be deposited into the remaining volumes of the bottom electrode contact via openings. Other suitable metal fill materials are within the scope of the disclosure. Portions of the metal fill material and the metal barrier layer that lie above the horizontal plane, including the topmost surface of the dielectric layer 110 at the interconnect via level, may be removed by a planarization process, such as chemical mechanical planarization. Each remaining portion of the metal fill material located within a respective via cavity comprises a metal via fill material portion 124. Each remaining portion of the metal barrier layer within a respective via cavity comprises a metal barrier layer 122.Each combination of a metal barrier layer 122 and a metal via fill material portion 124 filling a via cavity forms an interconnect via structure (122, 124). An array of interconnect via structures (122, 124) may be formed in the dielectric layer 110 at the interconnect via level on underlying metal interconnect structures. The array of interconnect via structures (122, 124) may contact the top surfaces of a subset of the fourth metal line structures 648. In general, the array of interconnect via structures (122, 124) contacts the top surfaces of a subset of lower-level metal lines located on the topmost level of the lower-level dielectric layers (601, 610, 620, 630, 640).In one embodiment, the array of interconnect via structures (122, 124) may be used as first metal interconnect structures that provide electrical connection to a first electrode of each memory cell to be subsequently formed.

[0020] Alternatively, the formation of the dielectric cap layer 108, the interconnect via level dielectric layer 110, and the array of interconnect via structures (122, 124) may be omitted, and a subset of metal line structures embedded in a line-and-via level dielectric layer or in a line-level dielectric layer may be used as first metal interconnect structures that electrically connect to a first electrode of each memory cell to be subsequently formed. For example, a subset of the fourth metal line structures 648 embedded in the fourth line-level dielectric material layer 640 and located in the memory array region 100 may be used as first metal interconnect structures that electrically connect to a first electrode of each memory cell to be subsequently formed.In general, first metal interconnect structures may be provided that are configured to establish an electrical connection to a first electrode (e.g., a bottom electrode) of each memory cell to be subsequently formed. The first metal interconnect structures may be provided as metal lines (e.g., a one-dimensional periodic array of metal lines extending along a common horizontal direction) or as metal via structures, such as a two-dimensional array of interconnect via structures (122, 124).In general, each first metal interconnect structure may be embedded in a first dielectric material layer, such as the interconnect via level dielectric layer 110 (in embodiments using a two-dimensional array of interconnect via structures (122, 124)), a dielectric material layer embedding metal lines (such as the fourth line-and-via level dielectric layer 640). Each bottom surface of a first electrode may then be formed on a top surface of a respective one of the first metal interconnect structures.

[0021] While the present disclosure is described with reference to an embodiment in which the interconnect via level dielectric layer 110 is used as the first dielectric material layer and the array of interconnect via structures (122, 124) is used as the first metal interconnect structures, embodiments in which an array of via structures located at a different level or an array of metal lines is used as the first metal interconnect structures are expressly contemplated herein.

[0022] With reference to Fig. 3, a first electrode material layer 126L, a memory material layer stack (130L, 140L), and a second electrode material layer 158L may be sequentially deposited over the top surface of a first dielectric material layer (such as the interconnect via level dielectric layer 110) embedding the array of interconnect via structures (122, 124).

[0023] The first electrode material layer 126L may include and / or consist essentially of a conductive metal nitride material and / or an elemental metal and / or an intermetal alloy. Conductive metal nitride materials may include a metal diffusion barrier material capable of blocking the diffusion of hydrogen. Conductive metal nitride materials that may be used for the first electrode material layer 126L include, for example, TiN, TaN, or WN. Elemental metals that may be used for the first electrode material layer 126L include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co, and Ni. In general, an elemental metal that is resistant to hydrogen diffusion may be used for the first electrode material layer 126L. In one embodiment, a refractory metal with a melting point greater than 2,000 degrees Celsius may be used for the first electrode material layer 126L.In general, elemental metals with a high melting point tend to provide a low mass diffusion coefficient for gases due to the relatively tight bonding between the atoms.

[0024] The first electrode material layer 126L can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the first electrode material layer 126L can be 1 nm to 100 nm, for example, 2 nm to 50 nm and / or 4 nm to 20 nm, although smaller and larger thicknesses can also be used. A stack of multiple metal layers can be used as the first electrode material layer 126L.

[0025] The storage material layer stack (130L, 140L) comprises at least one semiconducting metal oxide material layer 130L and at least one hydrogen-containing metal layer 140L. In general, the at least one semiconducting metal oxide material layer 130L may be a single semiconducting metal oxide material layer 130L or a plurality of semiconducting metal oxide material layers 130L, which may be vertically spaced from each other by the at least one hydrogen-containing metal layer 140L. The at least one hydrogen-containing metal layer 140L may be a single hydrogen-containing metal layer 140L or a plurality of hydrogen-containing metal layers 140L, which may be vertically spaced from each other by the at least one semiconducting metal oxide material layer 130L. In one embodiment, a single semiconducting metal oxide material layer 130L and a single hydrogen-containing metal layer 140L may be present in the storage material layer stack (130L, 140L).In this embodiment, the single hydrogen-containing metal layer 140L may be above or below the single semiconducting metal oxide material layer 130L. In another embodiment, a single semiconducting metal oxide material layer 130L and two hydrogen-containing metal layers 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, the single semiconducting metal oxide material layer 130L may be arranged between the two hydrogen-containing metal layers 140L. In another embodiment, two semiconducting metal oxide material layers 130L and one hydrogen-containing metal layer 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, the single hydrogen-containing metal layer 140L may be arranged between the two semiconducting metal oxide material layers 130L.In a further embodiment, at least two semiconducting metal oxide material layers 130L and at least two hydrogen-containing metal layers 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, the at least two semiconducting metal oxide material layers 130L and the at least two hydrogen-containing metal layers 140L may be arranged in a vertically alternating sequence, in which each vertically adjacent layer pair includes a respective semiconducting metal oxide material layer 130L and a respective hydrogen-containing metal layer 140L.

[0026] Each semiconducting metal oxide material layer 130L contains a semiconducting metal oxide material, i.e. a metal oxide material which, when suitably doped with electrical dopants (which may be p-type dopants or n-type dopants), has an electrical conductivity in a range from 1.0 S / m to 1.0 × 10 5S / m. In an intrinsic state or under the condition of low electrical doping, a semiconducting metal oxide material can be semiconducting or insulating and can have an electrical conductivity generally in the range of 1.0 × 10 -10 S / m to 1.0 × 10 S / m. Exemplary semiconducting metal oxide materials that may be used for the at least one semiconducting metal oxide material layer 130L include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. In one embodiment, the semiconducting metal oxide material layer 130L may include indium gallium zinc oxide.

[0027] The semiconducting metal oxide material of each semiconducting metal oxide material layer 130L may be deposited, for example, by physical vapor deposition (i.e., sputtering). The semiconducting metal oxide material of each semiconducting metal oxide material layer 130L may be deposited as a polycrystalline material, or it may be deposited as an amorphous material and subsequently annealed at an elevated temperature to form a polycrystalline material to increase the average grain size of the semiconducting metal oxide material. The thickness of each semiconducting metal oxide material layer 130L may be from 2 nm to 100 nm, for example, from 4 nm to 50 nm and / or 6 nm to 25 nm, although smaller and larger thicknesses may also be used.

[0028] Each hydrogen-containing metal layer 140L may contain and / or consist essentially of at least one of the platinum group metals (i.e., platinum, iridium, osmium, ruthenium, or combinations thereof) and hydrogen atoms. Platinum group metals refer to platinum, iridium, osmium, and ruthenium, each of which does not form metal hydrides under normal hydride-forming conditions, such as conditions where the hydrogen partial pressure is from 1 kbar to 50 kbar. The metal component of the hydrogen-containing metal layer 140L may be formed essentially of at least one of platinum, iridium, osmium, and ruthenium. In one embodiment, the metal component of the hydrogen-containing metal layer 140L may be formed essentially of platinum.

[0029] Each hydrogen-containing metal layer 140L may be formed by physical vapor deposition in a vacuum or in a hydrogen environment. The hydrogen partial pressure during the deposition process may be maintained at a level that does not hinder the deposition process, such as the physical vapor deposition process. In one embodiment, the hydrogen partial pressure during the deposition of each hydrogen-containing metal layer 140L may be 1.0 × 10-10 Torr to 1.0 × 10-3 Torr (1.333 × 10-10 mbar to 1.333 × 10-3 mbar). Alternatively, the hydrogen-containing metal layer 140L may be deposited in a hydrogen-free environment or in a low hydrogen pressure environment and annealed at an elevated temperature in a hydrogen-containing environment.In this embodiment, the annealing temperature may be 200 degrees Celsius to 500 degrees Celsius, for example, 300 degrees Celsius to 400 degrees Celsius, and the hydrogen partial pressure during the annealing process may be 100 mTorr to 760 Torr (133.3 x 10-3 mbar to 1013.25 mbar). Alternatively or additionally, hydrogen atoms may be implanted into each hydrogen-containing metal layer 140L after deposition of at least one of the elements platinum, iridium, osmium, and ruthenium in a hydrogen-free or low-hydrogen pressure environment.

[0030] The various processing parameters that influence the introduction of hydrogen into each hydrogen-containing metal layer 140L can be selected such that the atomic percentage of hydrogen atoms in each hydrogen-containing metal layer 140L is 0.001% to 10%, for example, 0.01% to 5% and / or 0.1% to 3%. The various processing parameters that influence the atomic proportion of hydrogen atoms in each hydrogen-containing metal layer 140L include, among others, the dose of hydrogen atoms during the hydrogen implantation process, the partial pressure of hydrogen during an annealing process in a hydrogen-containing environment, and the temperature and duration of the annealing process. In one embodiment, hydrogen implantation can be used to create a high atomic proportion of hydrogen in each hydrogen-containing metal layer 140L.In this embodiment, each hydrogen-containing metal layer 140L may contain hydrogen atoms at an atomic percentage greater than 1.0 percent, such as a percentage of 1.0 percent to 10%.

[0031] Each hydrogen-containing metal layer 140L may contain at least one of platinum, iridium, osmium, and ruthenium at an atomic percentage of at least 90% and may contain hydrogen atoms at an atomic percentage of 0.001% to 10% after the introduction of hydrogen. In one embodiment, each hydrogen-containing metal layer 140L may contain hydrogen atoms at an atomic percentage of 0.001% to 10% after the introduction of hydrogen, and the remainder of the atomic percentage may be the atomic percentage of the at least one of platinum, iridium, osmium, and ruthenium. In one embodiment, the at least one of platinum, iridium, osmium, and ruthenium may be platinum. In this embodiment, each hydrogen-containing metal layer 140L may contain hydrogen atoms at an atomic percentage of 0.001% to 10% after the introduction of hydrogen, and the atomic percentage of platinum may be the remainder of the atomic percentage of hydrogen atoms.

[0032] The thickness of each hydrogen-containing metal layer 140L can be from 2 nm to 100 nm, for example, from 4 nm to 50 nm and / or from 6 nm to 25 nm, although smaller and larger thicknesses can also be used. Each hydrogen-containing metal layer 140L does not contain a metal hydride, i.e., an MH compound in which M is a metal and hydrogen atoms occupy substitution sites of a lattice structure. Thus, a predominant portion or all of the hydrogen atoms present within each hydrogen-containing metal layer 140L are arranged at interstitial sites.

[0033] The second electrode material layer 158L may include and / or be formed essentially of a conductive metal nitride material and / or an elemental metal and / or an intermetal alloy. Conductive metal nitride materials may include a metallic diffusion barrier material capable of blocking the diffusion of hydrogen. Conductive metal nitride materials that may be used for the second electrode material layer 158L include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co, and Ni. In general, an elemental metal that is resistant to hydrogen diffusion may be used for the second electrode material layer 158L. In one embodiment, a refractory metal having a melting point above 2°C may be used for the second electrode material layer 158L.000 degrees Celsius. In general, elemental metals with a high melting point tend to provide a low mass diffusion coefficient for gases due to the relatively tight bonding between the atoms.

[0034] The second electrode material layer 158L can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the second electrode material layer 158L can be from 1 nm to 100 nm, for example from 2 nm to 50 nm and / or from 4 nm to 20 nm, although smaller and larger thicknesses can also be used. A stack of multiple metal layers can be used as the second electrode material layer 158L. The metal material of the second electrode material layer 158L can be the same as or different from the metal material of the first electrode material layer 126L.

[0035] With reference to Fig. 4, a photoresist layer 177 may be applied over the second electrode material layer 158L and lithographically patterned into an array of discrete photoresist material portions in the memory array region 100. Each patterned portion of the photoresist layer 177 may overlie a respective one of the interconnect via structures (122, 124). The sidewall(s) of each patterned portion of the photoresist layer 177 may be aligned with, laterally offset outwardly, or inwardly from, the edge region of a top surface of an underlying interconnect via structure (122, 124). The sidewall(s) of each patterned portion of the photoresist layer 177 may have a horizontal cross-sectional shape of a circle, an ellipse, a rectangle, a rounded rectangle, or any generally curved closed two-dimensional shape.

[0036] An anisotropic etch process may be performed to etch unmasked portions of the second electrode material layer 158L, the memory material layer stack (130L, 140L), and the first electrode material layer 126L. Each patterned portion of the second electrode material layer 158L comprises a second electrode 158. Each patterned portion of the memory material layer stack (130L, 140L) comprises a memory layer stack (130, 140). Each patterned portion of the first electrode material layer 126L comprises a first electrode 126. A set of remaining material portions of the material layer stack, comprising the second electrode material layer 158L, the memory material layer stack (130L, 140L), and the first electrode material layer 126L, forms a memory cell 150.Each memory cell 150 may be a columnar structure having a flat upper surface, a flat lower surface, and at least one straight sidewall extending between the flat upper surface and the flat lower surface. The at least one straight sidewall may be a single sidewall (e.g., a circular cylindrical sidewall) or multiple straight sidewalls (e.g., four flat sidewalls of a rectangular columnar structure or a combination of four flat sidewalls and four convex cylindrical sidewalls of a columnar structure with the horizontal cross-sectional shape of a rounded rectangle).

[0037] In general, any combination of a first electrode 126, a storage layer stack (130, 140), and a second electrode 158 may have a pillar structure having a top surface that is an upper surface of the second electrode 158, a bottom surface that is a lower surface of the first electrode 126, and a sidewall that extends straight between an edge region of the top surface of the second electrode 158 and an edge region of the lower surface of the first electrode 126.

[0038] Each storage layer stack (130, 140) includes at least one semiconducting metal oxide layer 130 and at least one hydrogen-containing metal layer 140. Each semiconducting metal oxide layer 130 is a patterned portion of a respective semiconducting metal oxide material layer 130L, as formed in the processing steps of Fig. 3. Each hydrogen-containing metal layer 140 is a patterned portion of a respective hydrogen-containing metal layer 140L, as formed in the processing steps of Fig. 3 is formed. In general, the at least one semiconducting metal oxide layer 130 may be a single semiconducting metal oxide layer 130 or a plurality of semiconducting metal oxide layers 130 vertically spaced from each other by the at least one hydrogen-containing metal layer 140. The at least one hydrogen-containing metal layer 140 may be a single hydrogen-containing metal layer 140 or a plurality of hydrogen-containing metal layers 140 vertically spaced from each other by the at least one semiconducting metal oxide layer 130. In one embodiment, a single semiconducting metal oxide layer 130 and a single hydrogen-containing metal layer 140 may be present in the memory material layer stack (130, 140). In this embodiment, the single hydrogen-containing metal layer 140 may be above or below the single semiconducting metal oxide layer 130.In another embodiment, a single semiconducting metal oxide layer 130 and two hydrogen-containing metal layers 140 may be present in the memory material layer stack (130, 140). In this embodiment, the single semiconducting metal oxide layer 130 may be arranged between the two hydrogen-containing metal layers 140. In another embodiment, two semiconducting metal oxide layers 130 and one hydrogen-containing metal layer 140 may be present in the memory material layer stack (130, 140). In this embodiment, the single hydrogen-containing metal layer 140 may be arranged between the two semiconducting metal oxide layers 130. In another embodiment, at least two semiconducting metal oxide layers 130 and at least two hydrogen-containing metal layers 140 may be present in the memory material layer stack (130, 140).In this embodiment, the at least two semiconducting metal oxide layers 130 and the at least two hydrogen-containing metal layers 140 may be arranged in a vertically alternating order in which each vertically adjacent layer pair comprises a respective semiconducting metal oxide layer 130 and a respective hydrogen-containing metal layer 140.

[0039] A two-dimensional array of memory cells 150 may be provided. Each memory cell 150 may include, from bottom to top, a first electrode 126, a memory layer stack (130, 140) overlying the first electrode 126 and including at least one semiconducting metal oxide layer 130 and at least one hydrogen-containing metal layer 140, and a second electrode 158 overlying the memory layer stack (130, 140). The first electrode 126 may be a first metal electrode formed substantially from at least one metal material. The second electrode 158 may be a second metal electrode formed substantially from at least one metal material.Each of the at least one hydrogen-containing metal layer may contain and / or be formed essentially of at least one metal selected from platinum, iridium, osmium, and ruthenium in an atomic percentage of at least 90%, and may contain and / or be formed essentially of hydrogen atoms in an atomic percentage of 0.001% to 10%. The second electrode.

[0040] In one embodiment, each of the at least one semiconducting metal oxide layer 130 contacts a horizontal surface of a respective one of the at least one hydrogen-containing metal layer 140 within each storage layer stack (130, 140). In one embodiment, the storage layer stack (130, 140) may include and / or be substantially formed of a single semiconducting metal oxide layer 130 and a single hydrogen-containing metal layer 140 in contact with each other. In one embodiment, the single semiconducting metal oxide layer 130 contacts one of the first electrode 126 and the second electrode 158, and the single hydrogen-containing metal layer 140 contacts the other of the first electrode 126 and the second electrode 158. The photoresist layer 177 may then be removed, for example, by ashing.

[0041] With reference to Fig. 5, a dielectric diffusion barrier material layer may be conformally deposited over the two-dimensional array of memory cells 150 using a conformal deposition technique, such as a chemical vapor deposition process. The dielectric diffusion barrier material layer includes a hydrogen diffusion barrier material layer that blocks the diffusion of hydrogen. The dielectric diffusion barrier material may include, for example, silicon nitride. The thickness of the dielectric diffusion barrier material layer may be 5 nm to 50 nm, for example, 10 nm to 25 nm, although smaller and larger thicknesses may also be used.

[0042] An anisotropic etch process may be performed to remove horizontal portions of the dielectric diffusion barrier material layer. The remaining, vertically extending portions of the dielectric diffusion barrier material layer include dielectric diffusion barrier spacers 156 that contact and laterally surround a respective pillar structure, which is a memory cell 150.

[0043] Each hydrogen-containing metal layer 140 serves as a hydrogen reservoir for one or two semiconducting metal oxide layers 130. The first electrode 126 and the second electrode 158 may contain metal materials that prevent hydrogen atoms from diffusing therethrough. The dielectric diffusion barrier spacers 156 serve as a confinement that prevents hydrogen atoms from escaping from a respective memory cell 150.

[0044] In general, the hydrogen atoms within each memory cell 150 may be moved between at least one hydrogen-containing metal layer 140 and at least one semiconducting metal oxide layer 130 by applying a programming pulse across the first electrode 126 and the second electrode 158. Thus, applying a first programming pulse of a first polarity to the second electrode 158 relative to the first electrode 126 may cause a selected memory cell 150 to be programmed to a hydrogenated state in which one or more and / or all of the at least one semiconducting metal oxide layer 130 contains hydrogen atoms at a high atomic concentration, which may be 0.001% to 10%, for example, 0.01% to 5% and / or 0.1% to 3%.Applying a second programming pulse having a second polarity to the second electrode 158 relative to the first electrode 126 may cause a selected memory cell 150 to be programmed to a dehydrated state in which one or more and / or all of the at least one semiconducting metal oxide layer 130 contains hydrogen atoms at a low atomic concentration, which may be from 0.0001% to 3.3%, for example, from 0.001% to 1.67% and / or from 0.01% to 1%. In general, the ratio of the atomic percentage of hydrogen atoms in the hydrogenated state of a semiconducting metal oxide layer 130 to the atomic percentage of hydrogen atoms in the dehydrated state of the semiconducting metal oxide layer 130 may be from 3 to 100, for example, from 5 to 10, although lower and higher ratios may be used.

[0045] Without loss of generality, it is assumed that applying a negative voltage to one side of a metal (such as the first electrode 126 or the second electrode 158) containing hydrogen atoms tends to attract hydrogen atoms because the hydrogen atoms are in a partial donor state, in which a portion of the negative charge of an electron can be donated to the common conduction band of the metal. The polarity of the programming pulses can be determined depending on the direction in which the hydrogen atoms are to be moved for the purpose of programming. The size of the programming pulses depends on the thickness and layer stack construction within each memory layer stack (130, 140). In an illustrative example, programming pulses with a magnitude of 3 V to 30 V can be used. Since the resistance of the current path within each memory cell 150, i.e.of the current path extending between the first electrode 126 and the second electrode 158 across each layer within the memory layer stack (130, 140) is relatively high, the electrical current through each selected memory cell 150 under programming may be small and the power consumption may be small despite relatively high operating voltages.

[0046] The presence of hydrogen atoms in each semiconducting metal oxide layer 130 increases the conductivity of the semiconducting metal oxide layer 130. Without loss of generality, it is assumed that the hydrogen atoms accommodated in the interstitial sites serve as small donors and increase the conductivity of the material of the semiconducting metal oxide layer 130. Thus, the hydrogenated state and the dehydrogenated state of each semiconducting metal oxide layer 130 can be distinguished by measuring the magnitude of the leakage current through each selected memory cell 150 between a respective first electrode 126 and the respective second electrode 158.

[0047] With reference to Fig. 6, a storage-level dielectric layer 170 may be formed around and over the array of memory cells 150 and the array of dielectric diffusion barrier spacers 156. The storage-level dielectric layer 170 includes / contains planarizable dielectric material, such as undoped silicate glass or doped silicate glass. The dielectric material of the storage-level dielectric layer 170 may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin-on coating). Optionally, the top surface of the storage-level dielectric layer 170 may be planarized, for example, by chemical-mechanical planarization.The vertical distance between the top surface of the memory level dielectric layer 170 and the top surfaces of the memory cells 150 may be 50 nm to 500 nm, although smaller or larger vertical distances may also be used.

[0048] At least one lithographic patterning step and at least one anisotropic etch process may be used to form interconnect cavities in the memory-level dielectric layer 170. For example, a first photoresist layer (not shown) may be applied over the memory-level dielectric layer 170 and lithographically patterned to form a series of discrete openings in the first photoresist layer. A first anisotropic etch process may be performed to form via openings in the memory-level dielectric layer 170. In one embodiment, a via cavity may be formed over each of the memory cells 150. After removing the first photoresist layer, a second photoresist layer (not shown) may be applied over the memory-level dielectric layer 170 and lithographically patterned to form line-shaped openings in the second photoresist layer.A second anisotropic etch process may be performed to form line-shaped cavities in the memory-level dielectric layer 170. The second photoresist layer may then be removed. In one embodiment, the interconnect cavities may be formed as integrated line and via cavities. In this embodiment, each integrated line and via cavity may include a line cavity located in an upper portion of the memory-level dielectric layer 170 and at least one via cavity adjacent to a lower portion of the line cavity and extending vertically through a lower portion of the memory-level dielectric layer 170.

[0049] In one embodiment, a two-dimensional array of vias may be formed in the memory array region 100 such that each of the upper surfaces of the memory cells 150 is physically exposed below a respective via within the two-dimensional array of vias. A top surface of an underlying metal interconnect structure, such as a fourth metal line structure 648 embedded in an upper portion of the fourth layer of dielectric line material 640, may be physically exposed at the bottom of at least a subset of the interconnect cavities in the memory level dielectric layer 170 in the peripheral region 200.In general, at least a subset of the interconnect cavities extending vertically between the top surface of the memory level dielectric layer 170 and the top surfaces of an underlying metal line structure may be formed by the memory level dielectric layer 170 in the peripheral region 200.

[0050] At least one metallic material may be deposited in the interconnect cavities in the memory array region 100 and in the peripheral region 200. The at least one metallic material is referred to herein as at least one memory level metallic material. In one embodiment, a metal barrier material layer (e.g., a TiN, TaN, and / or WN layer) and a metal fill material (e.g., W, Cu, Co, Ru, Mo, or an intermetal alloy) may be deposited in the interconnect cavities and over the memory level dielectric layer 170.

[0051] A planarization process, such as a chemical mechanical planarization process, may be performed to remove the at least one memory level metal material from above the memory level dielectric layer 170. Remaining portions of the at least one memory level metal material that fill the interconnect cavities in the memory array region 100 include array contact metal interconnect structures 664. Remaining portions of the at least one memory level metal material that fill the interconnect cavities in the peripheral region 200 include peripheral metal interconnect structures 666. The array contact metal interconnect structures 664 and the peripheral metal interconnect structure 666 are collectively referred to as memory level metal interconnect structures 666.

[0052] In general, first metal interconnect structures embedded in a first dielectric material layer may be formed prior to the formation of a two-dimensional array of memory cells 150. Each first metal interconnect structure may contact a bottom surface of a corresponding first electrode 126 within the two-dimensional array of memory cells 150. Second metal interconnect structures (such as array contact metal interconnect structures 664) embedded in a second dielectric material layer (such as memory level dielectric layer 170) may be formed on a top surface of a respective one of the second electrodes 158. In general, each first electrode 126 may be electrically connected to a node of an electrical switch, which may include one of the field-effect transistors disposed on a semiconductor substrate (such as substrate 9).Likewise, each second electrode 158 may be electrically connected to a node of an electrical switch, which may comprise another of the field effect transistors located on a semiconductor substrate (such as substrate 9).

[0053] With reference to Fig. 7 may show a first alternative configuration of the first exemplary structure from that shown in Fig. 6 by eliminating the formation of the dielectric diffusion barrier spacers 156. In this embodiment, the storage-level dielectric layer 170 may include a hydrogen diffusion-barrier dielectric material, such as silicon nitride. Alternatively, the storage-level dielectric layer 170 may include a layer stack including a layer of hydrogen diffusion-barrier material (e.g., silicon nitride) and an intermediate layer of dielectric material (e.g., a layer of undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material).

[0054] With reference to Fig. 8, a second alternative configuration of the first exemplary structure can be derived from the first exemplary structure by forming a combination of a permeable dielectric spacer 256 and a dielectric diffusion barrier spacer 156 instead of the respective dielectric diffusion barrier spacers 156. In this embodiment, a permeable dielectric material layer that is permeable to hydrogen atoms can be conformally formed after the photoresist layer 177 has been removed from the Fig. 4. The permeable dielectric material layer may include a dielectric material such as silicon oxide, organosilicate glass, or a porous dielectric material. An anisotropic etch may be performed to remove horizontal portions of the permeable dielectric material layer, and each remaining vertically extending portion of the permeable dielectric material layer forms a permeable dielectric spacer 256. Each permeable dielectric spacer 256 may have a lateral thickness of 1 nm to 50 nm, such as 3 nm to 20 nm, between an inner sidewall and an outer sidewall, although lesser and greater thicknesses may also be used.The upper surfaces of the permeable dielectric spacers 256 may be below the horizontal plane including the upper surfaces of the second electrodes 158 to facilitate coverage of the upper portions of the permeable dielectric spacers 256 by dielectric diffusion barrier spacers 156 that are subsequently formed.

[0055] The processing steps can then be Fig. 5 to form an array of dielectric diffusion barrier spacers 156. Each dielectric diffusion barrier spacer 156 can encapsulate one of the permeable dielectric spacers 256. The processing steps of Fig. 6 can subsequently be formed. In this configuration, the permeable dielectric spacers 256 serve as an additional reservoir for hydrogen atoms, and the dielectric diffusion barrier spacers 156 serve as encapsulation structures that prevent the escape of hydrogen atoms from each memory cell 150. For each memory cell 150 having a pillar structure, a permeable dielectric spacer 256 comprising a hydrogen-permeable dielectric material can contact and laterally surround the pillar structure, and a dielectric diffusion barrier spacer 156 comprising a hydrogen diffusion barrier material can contact and laterally surround the permeable dielectric spacer 256.

[0056] With reference to Fig. 9 may show a third alternative configuration of the first exemplary structure from that shown in Fig. 6 by swapping the positions of the semiconducting metal oxide layer 130 and the hydrogen-containing metal layer 140. In general, a hydrogen-containing metal layer 140 may be overlaid on a semiconducting metal oxide layer 130 with any stack of a hydrogen-containing metal layer 140 and a semiconducting metal oxide layer 130, as shown in Fig. 6, or a hydrogen-containing metal layer 140 may be disposed under a semiconducting metal oxide layer 130 with any stack of a hydrogen-containing metal layer 140 and a semiconducting metal oxide layer 130, as shown in Fig. 6. The polarity of the programming pulses can be reversed during programming, depending on whether a hydrogen-containing metal layer 140 lies above or below a semiconducting metal oxide layer 130.

[0057] With reference to Fig. 10 may illustrate a fourth alternative configuration of the first exemplary structure from each configuration of the first exemplary structure shown in Fig. 6-10, by using a plurality of hydrogen-containing metal layers 140. Asymmetry across the first electrode 126 and the second electrode 158 for the purpose of programming each memory cell 150 may be induced by using different thicknesses for the hydrogen-containing metal layers 140. A memory cell 150 may comprise a single hydrogen-containing metal layer 140 or a plurality of hydrogen-containing metal layers 140. In one embodiment, the at least one hydrogen-containing metal layer 140 within each memory cell 150 may comprise a plurality of hydrogen-containing metal layers 140, and one or more and / or each of the at least one semiconducting metal oxide layer 130 (which may be a single semiconducting metal oxide layer 130 or a plurality of semiconducting metal oxide layers 130) may contact two of the plurality of hydrogen-containing metal layers 140.

[0058] With reference to Fig. 11, a fifth alternative configuration of the first exemplary structure may be different from any configuration of the first exemplary structure as in Fig. 6-10 by using an interleaved layer stack of at least two hydrogen-containing metal layers 140 and at least two semiconducting metal oxide layers 130. The thickness of each hydrogen-containing metal layer 140 may be from 1 nm to 30 nm, for example, from 2 nm to 15 nm, although smaller and larger thicknesses may also be used. The thickness of each semiconducting metal oxide layer 130 may be from 1 nm to 30 nm, for example, from 2 nm to 15 nm, although smaller and larger thicknesses may also be used. The asymmetry between the first electrode 126 and the second electrode 158 for the purpose of programming each memory cell 150 may be brought about by matching the thicknesses of each layer within the interleaved layer stack of at least two hydrogen-containing metal layers 140 and at least two semiconducting metal oxide layers 130.For example, the thickness of each hydrogen-containing metal layer 140 may decrease with increasing distance from the first electrode 126 and the thickness of each semiconducting metal oxide layer 130 may increase with increasing distance from the first electrode, or vice versa.

[0059] Referring to FIGS. 12A and 12B, a second exemplary structure is illustrated that may be used to form a semiconductor device, such as a field-effect transistor, capable of storing a memory bit in the form of a resistance state of a channel region. A semiconducting metal oxide layer 30 may be formed over a dielectric material layer 20. The dielectric material layer 20 may comprise any of the Fig. 1, the first metal line level dielectric material layer 610, the second line and via level dielectric material layer 620, the third line and via level dielectric material layer 630, and the fourth line and via level dielectric material layer 640. Furthermore, the dielectric material layer 20 may be any of the dielectric material layers formed over the first exemplary structure of Fig. 1 or above the first exemplary structure of Fig. 6-11 may be formed. In this embodiment, the region in which the second example structure is formed is selected such that no metal interconnect structures are present on the portion of the dielectric material layer 20 over which the second example structure is formed. Alternatively, contact via structures (not shown) and metal lines (not shown) may be formed in an upper portion of the dielectric material layer 20 such that the contact via structures or metal lines contact a source region or a drain region of a field effect transistor when the source region and the drain region are formed. Alternatively, the dielectric material layer 20 may include a portion of a shallow trench isolation structure 720 extending over a relatively large area, such as a device area.Alternatively, the dielectric material layer 20 may be provided as an insulating material layer deposited over a substrate, such as a semiconductor substrate. Further alternatively, the dielectric material layer 20 may be provided as part of an insulating substrate. While only a single field-effect transistor is illustrated to describe the semiconductor device of the second embodiment of the present disclosure, embodiments are expressly contemplated in which an array of field-effect transistors (such as a two-dimensional array of field-effect transistors) is formed over a substrate.

[0060] The semiconducting metal oxide layer 30 may have the same material composition as the semiconducting metal oxide material layer 130L of the first example structure and may be formed by the same deposition process (such as a physical vapor deposition process). The thickness of the semiconducting metal oxide layer 30 may be from 1 nm to 100 nm, for example, from 2 nm to 50 nm and / or 4 nm to 25 nm, although smaller and larger thicknesses may also be used. The semiconducting metal oxide layer 30 may be patterned, for example, by applying a photoresist layer (not shown) over the semiconducting metal oxide layer 30, by lithographically patterning the photoresist layer to include a discrete portion of photoresist material, and by etching unmasked portions of the semiconducting metal oxide layer 30.A semiconducting metal oxide layer 30, as patterned by an etching process, may have a length along a first horizontal direction hd1 and a width along a second horizontal direction hd2. The length may be 50 nm to 1 micron, and the width may be 30 nm to 1 micron, although shorter and longer lengths and widths may also be used. The photoresist layer may then be removed, for example, by ashing. Optionally, a suitable cleaning process may be performed.

[0061] As in Fig. 13A and Fig. 13B, a hydrogen-containing metal layer and a gate electrode material layer may be deposited over the semiconducting metal oxide layer 30. The hydrogen-containing metal layer and the gate electrode material layer may be deposited as sheet material layers, i.e., as unpatterned material layers. The hydrogen-containing metal layer of the second example structure may have the same material composition as the hydrogen-containing metal layer 140L of the first example structure and may be formed by the same deposition process (e.g., a physical vapor deposition process). The thickness of the capping hydrogen-containing metal layer of the second example structure may be 1 nm to 100 nm, for example, 2 nm to 50 nm and / or 4 nm to 25 nm, although smaller and larger thicknesses may also be used.

[0062] The gate electrode material layer comprises a metallic gate electrode material. In one embodiment, the gate electrode material layer comprises one of the metal materials that can be used for the first electrode material layer or the second electrode material layer in the first example structure. For example, the gate electrode material layer can include and / or be formed essentially of a conductive metal nitride material and / or an elemental metal and / or an intermetal alloy. Conductive metal nitride materials that can be used for the gate electrode material layer include, for example, TiN, TaN, or WN. Elemental metals that can be used for the gate electrode material layer include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co, and Ni. In general, an elemental metal that is resistant to hydrogen diffusion can be used for the gate electrode material layer.In one embodiment, a refractory metal with a melting point of over 2,000 degrees Celsius can be used for the gate electrode material layer. The gate electrode material layer can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the gate electrode material layer can be 50 nm to 200 nm, although smaller and larger thicknesses can also be used. A stack of multiple metal layers can be used as the gate electrode material layer.

[0063] A photoresist layer may be applied over the gate electrode material layer (not shown), which may be lithographically patterned with a gate structure. For example, a rectangular region extending across a central portion of the semiconducting metal oxide layer 30 may be used as the masked region of the gate structure. An anisotropic etching process may be performed to etch the unmasked regions of the gate electrode material layer and the hydrogen-containing metal cap layer. In one embodiment, the anisotropic etching process may include a first anisotropic etching step that etches unmasked regions of the gate electrode material layer selectively relative to the material of the hydrogen-containing metal cap layer, and a second anisotropic etching step that etches unmasked regions of the hydrogen-containing metal cap layer selectively relative to the material of the semiconducting metal oxide layer 30.The photoresist layer can then be removed, for example by ashing.

[0064] A remaining portion of the gate electrode material layer overlying the semiconducting metal oxide layer 30 comprises a gate electrode 50. A remaining portion of the hydrogen-containing metal layer overlying the gate electrode 50 comprises a hydrogen-containing metal layer 40 embedded in the semiconductor device of the second example structure. A gate stack of a hydrogen-containing metal layer 40 and a gate electrode 50 may span a central portion of the semiconducting metal oxide layer 30 along the second horizontal direction hd2. The dimension of the gate stack (40, 50) along the first horizontal direction hd1 is referred to herein as the gate length, which may be 10 nm to 300 nm, for example, 30 nm to 100 nm, although shorter and longer gate lengths may also be used.

[0065] The hydrogen-containing metal layer 40 lies on a surface of the semiconducting metal oxide layer 30 and contains, and / or is essentially formed from, at least one metal selected from platinum, iridium, osmium, and ruthenium, with an atomic percentage of at least 90% and hydrogen atoms with an atomic percentage of 0.001% to 10%, such as 0.01% to 5% and / or 0.1% to 3%. The gate electrode 50 lies on the hydrogen-containing metal layer 40. Sidewalls of the gate electrode 50 and sidewalls of the hydrogen-containing metal layer 40 may coincide vertically, i.e., lie in common vertical planes.

[0066] With reference to Fig. 14A and Fig. 14B, suitable electrical dopants may be implanted into unmasked regions of the semiconducting metal oxide layer 30 by performing an ion implantation process. The gate electrode 50 may be used as an ion implantation mask during the ion implantation process. Electrical dopants that may form excess holes or excess electrons in the implanted regions of the semiconducting metal oxide layer 30 include, but are not limited to, Na, K, Mg, Ca, Sr, Y, La, B, Al, Ga, N, P, As, Sb, F, Cl, and other elements that may induce the formation of holes or excess electrons in the semiconducting metal oxide layer 30. Alternatively or additionally, a plasma treatment may optionally be performed to improve the electrical properties of the semiconducting metal oxide material in the semiconducting metal oxide layer 30.A source region 32 is formed in one side of the semiconducting metal oxide layer 30, and a drain region 38 is formed in another side of the semiconducting metal oxide layer 30. The non-implanted portion of the semiconducting metal oxide layer 30 forms a channel region 35 underlying the gate electrode 50.

[0067] A dielectric diffusion barrier material layer may be conformally deposited over the gate electrode 50 and the semiconducting metal oxide layer 30 using a conformal deposition process, such as a chemical vapor deposition process. The dielectric diffusion barrier material layer includes a hydrogen diffusion barrier material layer that blocks the diffusion of hydrogen. The dielectric diffusion barrier material may include, for example, silicon nitride. The thickness of the dielectric diffusion barrier material layer may be from 5 nm to 50 nm, for example, from 10 nm to 25 nm, although smaller and larger thicknesses may also be used.

[0068] An anisotropic etching process may be performed to remove horizontal portions of the dielectric diffusion barrier material layer. A remaining portion of the dielectric diffusion barrier material layer, extending vertically, comprises a dielectric diffusion barrier spacer 56 that contacts and laterally surrounds the gate stack (40, 50), including the hydrogen-containing metal layer 40 and the gate electrode 50. The hydrogen-containing metal layer 40 serves as a hydrogen reservoir for the channel region 35. Hydrogen atoms may be injected from the hydrogen-containing metal layer 40 into the channel region 35 to program the channel region 35 to a hydrogenated state. Additionally, the hydrogen atoms may be extracted from the channel region 35 into the hydrogen-containing metal layer 40 to program the channel region 35 to a dehydrogenated state.The gate electrode 50 may contain a metallic material that prevents the diffusion of hydrogen atoms through it. The dielectric diffusion barrier spacers 56 serve as an encapsulation that prevents the escape of hydrogen atoms from the field-effect transistor.

[0069] Programming the channel region 35 of the field-effect transistor into the hydrogenated state can generally be performed by applying a first programming pulse with a first polarity with respect to the respective source region 32 and / or the respective drain region 38 to the gate electrode 50. Programming the channel region 35 of the field-effect transistor into the dehydrated state can be performed by applying a second programming pulse with a second polarity, opposite to the first polarity, with respect to the respective source region 32 and / or the respective drain region 38 to the gate electrode 50. In one embodiment, the source region 32 and the drain region 38 can be biased with the same voltage during programming of the channel region 35 into the hydrogenated state or into the dehydrated state.

[0070] In one embodiment, the hydrogenated state of the channel region 35 contains hydrogen atoms at a high atomic concentration, which may be from 0.001% to 10%, for example, from 0.01% to 5% and / or 0.1% to 3%. The dehydrogenated state of the channel region 35 contains hydrogen atoms at a low atomic concentration, which may be from 0.0001% to 3.3%, such as from 0.001% to 1.67% and / or from 0.01% to 1%. In general, the ratio of the atomic percentage of hydrogen atoms in the hydrogenated state of the channel region 35 of a semiconducting metal oxide layer 30 to the atomic percentage of hydrogen atoms in the dehydrogenated state of the channel region 35 of the semiconducting metal oxide layer 30 may be from 3 to 100, such as from 5 to 10, although lower and higher ratios may also be used.

[0071] With reference to Fig. 15A and Fig. 15B, a dielectric material layer may be deposited over the gate electrode 50 and the semiconducting metal oxide layer 30. The dielectric material layer is referred to herein as a contact via level dielectric layer 70. The contact via level dielectric layer 70 may include a planarizable dielectric material such as undoped silicate glass or a doped silicate glass, or a self-planarizing dielectric material such as flowable oxide (FOX). Optionally, a chemical mechanical planarization process may be performed to planarize the top surface of the contact via level dielectric layer 70.

[0072] Contact via cavities may be formed through the contact via level dielectric layer 70. A top surface of the source region 32, a top surface of the drain region 38, and a top surface of the gate electrode 50 may be physically exposed at the bottom of the contact via cavities. At least one conductive material, such as a combination of a conductive metal liner material (e.g., TiN, TaN, and / or WN) and a conductive metal fill material (e.g., W, Cu, Co, Mo, Ru, another elemental metal, or an intermetal alloy), may be deposited in the contact via cavities. The deposition of the at least one conductive material may be performed by physical vapor deposition, chemical vapor deposition, electroplating, and / or electroless plating.Excess portions of the at least one conductive material may be removed above the horizontal plane encompassing the top surface of the contact via level dielectric layer 70 by a planarization process, such as a recess etch and / or a chemical mechanical planarization process. The remaining portions of the at least one conductive material filling the contact via cavities include a source contact via structure 72, a drain contact via structure 78, and a gate contact via structure 75. The source contact via structure 72 may contact the source region 32, the drain contact via structure 78 may contact the drain region 38, and the gate contact via structure 75 may contact the gate electrode 50.

[0073] With reference to Fig. 16A and Fig. 16B illustrates a first alternative configuration of the second exemplary structure that is different from the second exemplary structure of Fig. 15A and Fig. 15B by eliminating the formation of the dielectric diffusion barrier spacers 56. In this embodiment, the contact via level dielectric layer 70 may include a hydrogen diffusion barrier material such as silicon oxide. Alternatively, the contact via level dielectric layer 70 may comprise a layer stack including a hydrogen diffusion barrier layer (e.g., a silicon nitride layer) and an interlayer dielectric material layer (e.g., a layer of undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material).

[0074] With reference to FIGS. 17A and 17B, a second alternative configuration of the second exemplary structure can be derived by using a combination of a permeable dielectric spacer 456 and a dielectric diffusion barrier spacer 56 instead of a dielectric diffusion barrier spacer 56 in the second exemplary structure of Fig. 15A and Fig. 15B. In this embodiment, a permeable dielectric material layer that is permeable to hydrogen atoms may be conformally formed directly on the sidewalls of the gate stack (40, 50) after the formation of the source region 32 and the drain region 38. The permeable dielectric material layer may include a dielectric material such as silicon oxide, organosilicate glass, or a porous dielectric material. An anisotropic etch may be performed to remove horizontal portions of the permeable dielectric material layer, and any remaining portion of the permeable dielectric material layer that extends vertically forms a permeable dielectric spacer 456.Each permeable dielectric spacer 456 may have a lateral thickness of 1 nm to 50 nm, for example, 3 nm to 20 nm, between an inner sidewall and an outer sidewall, although smaller and larger thicknesses may be used. The upper surfaces of the permeable dielectric spacers 456 may be below the horizontal plane including the upper surfaces of the gate electrode 50 to facilitate the covering of an upper portion of the permeable dielectric spacer 456 by a subsequently formed dielectric diffusion barrier spacer 56.

[0075] Subsequently, a dielectric diffusion barrier spacer 56 may be formed on the permeable dielectric spacer 456. Each dielectric diffusion barrier spacer 56 may encapsulate one of the permeable dielectric spacers 456. The processing steps of Fig. 15A and Fig. 15B can subsequently be formed. In this configuration, the permeable dielectric spacers 456 serve as an additional reservoir for hydrogen atoms, and the dielectric diffusion barrier spacers 56 serve as encapsulation structures that prevent hydrogen atoms from escaping from the respective field-effect transistor. The permeable dielectric spacer 456, which includes a hydrogen-permeable dielectric material, can contact and laterally surround the gate stack (40, 50), and a dielectric diffusion barrier spacer 56, which includes a hydrogen diffusion barrier material, can contact and laterally surround the permeable dielectric spacer 456.

[0076] With reference to Fig. 18A and Fig. 18B may illustrate a third alternative configuration of the second exemplary structure of each of the configurations of the second exemplary structure as shown in Fig. 15A-17B by forming a recess trench in the dielectric material layer 20 prior to forming the semiconducting metal oxide layer 30, and by filling the recess trench with a metal line forming a back-side gate electrode 350 for the field-effect transistor. In embodiments in which the dielectric material layer 20 is an interconnect-level dielectric material layer located in a back-end-of-line structure, such as the contact-level dielectric material layer 601, the first metal line-level dielectric material layer 610, the second line-and-via level dielectric material layer 620, the third line-and-via level dielectric material layer 630, or the fourth line-and-via level dielectric material layer 640 as shown in Fig. 1, the back gate electrode 350 may be formed simultaneously with metal line structures embedded in the interconnect level dielectric material layer, such as the first metal line structures 618, the second metal line structures 628, the third metal line structures 638, or the fourth metal line structures 648. Furthermore, embodiments are expressly contemplated in which the back gate electrode 350 may comprise a metal line structure in a top metal interconnect structure overlying the fourth line level dielectric material layer 640. Alternatively, the dielectric material layer 20 may comprise a shallow trench isolation structure.

[0077] The thickness of the back gate electrode 350 may be 20 nm to 200 nm, although smaller and larger thicknesses may also be used. The back gate electrode 350 may include a metal that is resistant to hydrogen diffusion. For example, the back gate electrode 350 may include a conductive metal nitride material and / or an elemental metal and / or an intermetal alloy. Conductive metal nitride materials that may be used for the back gate electrode 350 include, for example, TiN, TaN, or WN. Elemental metals that may be used for the back gate electrode 350 include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co, and Ni. In general, an elemental metal that is resistant to hydrogen diffusion may be used for the back gate electrode 350. In one embodiment, a refractory metal with a melting point above 2 °C may be used for the back gate electrode 350.000 degrees Celsius. The semiconducting metal oxide layer 30 can be formed over a planarized upper surface of the back gate electrode 350. The surface of the back gate electrode 350 can overlap the surface of the gate electrode 50. The combination of the gate electrode 50 and the back gate electrode 350 results in a dual gate configuration, allowing tighter control of the threshold voltage. The back gate electrode 350 can provide a variable channel bias to compensate for the drift in the transistor characteristics of the field effect transistor, which includes the source region 32, the drain region 38, the channel region 35, the hydrogen-containing metal layer 40, and the gate electrode 50, which can be caused by the gradual loss of hydrogen atoms over a long period of use.

[0078] With reference to Fig. 19A and Fig. 19B may illustrate a fourth alternative configuration of the second exemplary structure of each of the configurations of the second exemplary structure as in Fig. 15A-17B by forming a recess trench in the dielectric material layer 20, forming a backside dielectric diffusion barrier spacer 356 containing a hydrogen-barrier dielectric barrier material (such as silicon nitride) around the sidewalls of the recess trench, and forming a stack of a backside gate electrode 350 and a backside hydrogen-containing metal layer 340 within the recess trench.

[0079] The backside dielectric diffusion barrier spacer 356 may be formed by conformally depositing a backside dielectric diffusion barrier layer and anisotropically etching the backside dielectric diffusion barrier layer. The backside gate electrode 350 may be formed by depositing at least one conductive material in the cavity laterally surrounded by the backside diffusion barrier spacer 356 and vertically recessing the at least one conductive material below the horizontal plane including the top surface of the dielectric material layer 20 using a planarization process including a recess etch process.For example, a chemical-mechanical planarization process may be used to remove the portion of the at least one conductive material above the horizontal plane, including the top surface of the dielectric material layer 20, and a recess etch process may be performed to vertically recess the top surface of a remaining portion of the at least one conductive material. A remaining portion of the at least one conductive material in the recess trench forms the backside gate electrode 350. The recess depth may be equal to the thickness of the backside hydrogen-containing metal layer 340 that is subsequently formed. For example, the recess depth may be from 1 nm to 100 nm, such as from 2 nm to 50 nm and / or from 4 nm to 25 nm, although smaller and larger recess depths may also be used.The back gate electrode 350 may include the same material as in the third alternative configuration of the second exemplary structure as shown in FIG. Fig. 18A and Fig. 18B.

[0080] The backside hydrogen-containing metal layer 340 may be formed by the same processing steps used to form a hydrogen-containing metal layer 140L in the first example structure. The backside hydrogen-containing metal layer 340 may have the same material composition and thickness range as each of the hydrogen-containing metal layers 140L that may be used in the first example structure. Subsequently, the processing steps of the Fig. 12A - 17B to provide the fourth configuration of the second exemplary structure as shown in Fig. 18A and Fig. 18B.

[0081] With reference to Fig. 12A-18B and related drawings, and in accordance with various embodiments of the present disclosure, a semiconductor device is provided comprising: a semiconducting metal oxide layer 30 overlying a dielectric material layer 20 and having a source region 32, a drain region 38, and a channel region 35 disposed between the source region 32 and the drain region 38; a hydrogen-containing metal layer 40 overlying a surface of the channel region 35 and including at least one metal selected from platinum, iridium, osmium, and ruthenium with an atomic percentage of at least 90% and including hydrogen atoms; and a gate electrode 50 overlying the hydrogen-containing metal layer 40.

[0082] In one embodiment, the semiconductor device comprises: a dielectric diffusion barrier spacer 56 containing a hydrogen diffusion barrier material and contacting and laterally surrounding the hydrogen-containing metal layer 40 and the gate electrode 50.

[0083] In one embodiment, the semiconductor device includes a permeable dielectric spacer 456 containing a hydrogen-permeable dielectric material and contacting and laterally surrounding the gate electrode 50 and the hydrogen-containing metal layer 40; and a dielectric diffusion barrier spacer 56 containing a hydrogen diffusion barrier material and contacting and laterally surrounding the permeable dielectric spacer 456.

[0084] In one embodiment, the semiconductor device includes a back gate electrode 350 embedded in the dielectric material layer 20; and a hydrogen-containing back metal layer 340 containing at least one additional metal selected from platinum, iridium, osmium, and ruthenium with an atomic percentage of at least 90% and containing hydrogen atoms with an atomic percentage of 0.001% to 10%, and located between a bottom surface of the channel region 35 and the back gate electrode 350. The at least one additional metal may be the same as or different from the at least one metal of the hydrogen-containing metal layer 40.

[0085] In one embodiment, the semiconductor device comprises: a back gate electrode 350 embedded in the dielectric material layer 20 and contacting a back surface of the channel region 35.

[0086] With reference to Fig. 20 is a flowchart illustrating the general processing steps of the methods for manufacturing a memory device of the first embodiment of the present disclosure. Referring to step 2010 and Fig. 1 and Fig. 2, a dielectric material layer (such as an interconnect via level dielectric layer 110, a fourth line-and-via level dielectric material layer 640, any other interconnect level dielectric layer, or a laterally extending portion of a shallow trench isolation structure 720) is formed over a substrate 9. With reference to step 2020 and Fig. 3, a material layer stack (126L, 130, 140L, 158L) comprising a first electrode material layer 126L, at least one semiconducting metal oxide material layer 130L, at least one hydrogen-containing metal layer 140L, and a second electrode material layer 158L may be formed over the dielectric material layer 20. With reference to step 2030 and Fig. 4, the material layer stack (126L, 130, 140L, 158L) can be structured into at least one column structure comprising a first electrode 126, a storage layer stack (130, 140) and a second electrode 158. Subsequently, the processing steps of Fig. 5-11 are carried out.

[0087] With reference to Fig. 21 is a flowchart illustrating the general processing steps of the methods for manufacturing a semiconductor device (which may be a memory device) of the second embodiment of the present disclosure. Referring to step 2110 and Fig. 12A and Fig. 12B, Fig. 18A and Fig. 18B and 19A and 19B, a semiconducting metal oxide layer 30 is formed over a dielectric material layer 20. With reference to step 2120 and Fig. 13A and Fig. 13B, Fig. 18A and Fig. 18B and 19A and 19B, a hydrogen-containing metal layer 40 and a gate electrode 50 may be formed over the semiconducting metal oxide layer 30. With reference to step 2130 and Fig. 14A and Fig. 14B, Fig. 18A and Fig. 18B and 19A and 19B, a source region 32 and a drain region 38 can be formed in the semiconducting metal oxide layer 30. Subsequently, further processing steps of Fig. 14A-19B.

[0088] With reference to Fig. 22 illustrates a flowchart of general steps for operating a semiconductor device of the present disclosure, which may be one of the first exemplary structures and the second exemplary structures. With reference to step 2210 and Fig.6-11 and 15A-19B, a semiconductor device is provided with a layer stack {(130, 140) or (30, 40)} between a first electrode (126 or 32) and a second electrode (158 or 38), the layer stack comprising at least one semiconducting metal oxide layer (130 or 30) and at least one hydrogen-containing metal layer (140 or 40) over a dielectric material layer {(110 or 640) or 20}. In the second exemplary structure, the source region 32 serves as the first electrode and the drain region serves as the second electrode. Each of the at least one hydrogen-containing metal layer (140 or 40) contains a metal selected from platinum, iridium, osmium and ruthenium with an atomic percentage of at least 90% and contains hydrogen atoms with an atomic percentage of 0.001% to 10%.

[0089] Referring to step 2220, the semiconductor device may be programmed to a hydrogenated state or a dehydrogenated state by applying a programming pulse across the first electrode 126 and the second electrode 158, or across a gate electrode 50 disposed on the at least one hydrogen-containing metal layer 40, and one of the first electrode (having a source region 32) and the second electrode (having a drain region 38). The hydrogenated state is a state in which the at least one semiconducting metal oxide layer (130, 30) is seeded with hydrogen atoms, and the dehydrogenated state is a state in which the at least one semiconducting metal oxide layer (130, 30) is hydrogen-depleted.Referring to step 2230, a memory state of the semiconductor device may be determined by measuring electrical conductivity of a measurement current path between the first electrode (126 or 32) and the second electrode (158 or 38) under a measurement bias condition.

[0090] In the first embodiment, the sense current path extends through each layer within the layer stack (130, 140) along a direction perpendicular to each interface between each adjacent pair of layers within the layer stack of semiconducting metal oxide. A sense amplifier can be used to measure the magnitude of the sense current and determine the memory state of a memory cell 150. In one embodiment, programming the semiconductor device to the hydrogenated state comprises applying a first programming pulse having a first polarity to the second electrode 158 relative to the first electrode 126, and programming the semiconductor device to the dehydrated state comprises applying a second programming pulse having a second polarity, opposite the first polarity, to the second electrode 158 relative to the first electrode 126.

[0091] In the second embodiment, the at least one semiconducting metal oxide layer comprises a semiconducting metal oxide layer 30 having a source region 32 (as the first electrode), a drain region 38 (as the second electrode), and a channel region 35 located between the source region 32 and the drain region 38. The first electrode comprises the source region 32, and the second electrode comprises the drain region 38. The electrically conductive path extends through the channel region 35 along a direction parallel to an interface between the channel region 35 and the at least one hydrogen-containing metal layer 40 contacting the channel region 35. A sense amplifier can be used to measure the magnitude of the sense current and determine the memory state of the semiconductor device, which includes a field-effect transistor with a variable threshold voltage modulated by hydrogen levels in the channel region 35.

[0092] In one embodiment, programming the semiconductor device to the hydrogenated state comprises applying a first programming pulse to the gate electrode 50 having a first polarity relative to one (or both) of the first electrode (including the source region 32) and the second electrode (including the drain region 38); and programming the semiconductor device to the dehydrogenated state comprises applying a second programming pulse having a second polarity, opposite the first polarity, to the gate electrode 50, to one (or both) of the first electrode and the second electrode.

[0093] The various embodiments of the present disclosure provide semiconducting metal oxide memory devices that utilize hydrogen-mediated threshold voltage modulation. In particular, the amount of hydrogen in the at least one semiconducting metal oxide layer (130, 30) determines the conductivity of the at least one semiconducting metal oxide layer (130, 30) and provides a hydrogen-mediated threshold voltage for the semiconducting metal oxide memory devices. The electric current flowing through the at least one semiconducting metal oxide layer (130, 30) may be above or below a predefined threshold depending on whether the at least one semiconducting metal oxide layer (130, 30) is in a hydrogenated state or in a dehydrogenated state. As such, the at least one semiconducting metal oxide layer (130, 30) may encode a bit in a non-volatile and reversible manner.The devices of the present disclosure can provide a long-life non-volatile memory device.

Claims

[1] Storage device comprising: a first electrode (126); a storage layer stack arranged on the first electrode (126) and comprising at least one semiconducting metal oxide layer (130) and a plurality of hydrogen-containing metal layers (140) containing at least one metal selected from platinum, iridium, osmium, and ruthenium with an atomic percentage of at least 90% and containing hydrogen atoms, wherein one of the at least one semiconducting metal oxide layer (130) contacts two of the plurality of hydrogen-containing metal layers (140); and a second electrode (158) arranged above the storage layer stack. [2] The storage device according to claim 1, further comprising: a first metal interconnect structure (122, 124) embedded in a first dielectric material layer (110) and contacting a lower surface of the first electrode (126); and a second metal interconnect structure (664) embedded in a second dielectric material layer (170) and contacting a top surface of the second electrode (158). [3] The storage device of claim 2, further comprising: a semiconductor substrate (9) underlying the first dielectric material layer (110); and Field effect transistors arranged on the semiconductor substrate (9), wherein the first electrode (126) or the second electrode (158) is electrically connected to one of the field effect transistors via additional metal interconnect structures (612-648) located between the semiconductor substrate (9) and the first dielectric material layer (110). [4] A memory device according to any one of the preceding claims, wherein each of the at least one semiconducting metal oxide layer (130) contacts a horizontal surface of a respective one of the plurality of hydrogen-containing metal layers (140). [5] A memory device according to any preceding claim, wherein each of the hydrogen-containing metal layers (140) contains hydrogen atoms at an atomic percentage of 0.001% to 10%. [6] The memory device of any preceding claim, wherein the memory device further comprises at least two semiconducting metal oxide layers (130) and the memory layer stack is an interleaved layer stack of the plurality of hydrogen-containing metal layers (140) and the at least two semiconducting metal oxide layers (130). [7] The memory device of any preceding claim, wherein a combination of the first electrode (126), the memory layer stack, and the second electrode (158) comprises a pillar structure having an upper surface that is an upper surface of the second electrode (158), a lower surface that is a lower surface of the first electrode (126), and a sidewall that extends straight between an edge region of the upper surface of the second electrode (158) and an edge region of the lower surface of the first electrode (126). [8] The storage device of claim 7, further comprising: a dielectric diffusion barrier spacer (156) containing a hydrogen diffusion barrier material, contacting and laterally surrounding the column structure. [9] The storage device of claim 7, further comprising: a permeable dielectric spacer (456) containing a hydrogen-permeable dielectric material and contacting and laterally surrounding the column structure; and a dielectric diffusion barrier spacer (156) containing a hydrogen diffusion barrier material, contacting and laterally surrounding the permeable dielectric spacer (156). [10] Semiconductor device comprising: a semiconducting metal oxide layer (30) disposed on a dielectric material layer (20) and having a source region (32), a drain region (38) and a channel region (35) disposed between the source region (32) and the drain region (38); a hydrogen-containing metal layer (40) disposed on a surface of the channel region (35) and containing at least one metal having an atomic percentage of at least 90% selected from platinum, iridium, osmium, and ruthenium, and containing hydrogen atoms; and a gate electrode (50) arranged on the hydrogen-containing metal layer (40). [11] The semiconductor device according to claim 10, further comprising: a dielectric diffusion barrier spacer (56) containing a hydrogen diffusion barrier material, contacting and laterally surrounding the hydrogen-containing metal layer (40) and the gate electrode (50). [12] A semiconductor device according to claim 10, further comprising: a permeable dielectric spacer (456) comprising a hydrogen-permeable dielectric material, contacting and laterally surrounding the gate electrode (50) and the hydrogen-containing metal layer (40); and a dielectric diffusion barrier spacer (56) comprising a hydrogen diffusion barrier material, contacting and laterally surrounding the permeable dielectric spacer (456). [13] A semiconductor device according to any one of claims 10 to 12, further comprising: a back gate electrode (350) embedded in the dielectric material layer (20); and a backside hydrogen-containing metal layer (340) containing at least one additional metal with an atomic percentage of at least 90% selected from platinum, iridium, osmium and ruthenium, and containing hydrogen atoms with an atomic percentage of less than 10%, and disposed between a lower surface of the channel region (35) and the backside gate electrode (350), wherein the at least one additional metal is different from the metal of the hydrogen-containing metal layer (340). [14] A semiconductor device according to any one of claims 10 to 12, further comprising a back gate electrode (350) embedded in the dielectric material layer (20) and in contact with a lower surface of the channel region (35). [15] A method of operating a semiconductor device, comprising: Providing a semiconductor device comprising a layer stack between a first electrode (126) and a second electrode (158), the layer stack including at least one semiconducting metal oxide layer (130) and at least one hydrogen-containing metal layer (140) over a dielectric material layer (110), each of the at least one hydrogen-containing metal layer (140) including at least one metal having an atomic percentage of at least 90% selected from platinum, iridium, osmium, and ruthenium, and including hydrogen atoms; Programming the semiconductor device into a hydrogenated state or a dehydrogenated state by applying a programming pulse via the first electrode (126) and the second electrode (158) or via a gate electrode (50) arranged on the at least one hydrogen-containing metal layer (140) and one of the first electrode (126) and the second electrode (158), wherein the hydrogenated state is a state in which the at least one semiconducting metal oxide layer (130) is impregnated with hydrogen atoms, and wherein the dehydrogenated state is a state in which the at least one semiconducting metal oxide layer (130) is hydrogen-depleted; and Determining a memory state of the semiconductor device by measuring the electrical conductivity of a measuring current path between the first electrode (126) and the second electrode (158) under a measuring bias condition. [16] The method of claim 15, wherein the measurement current path extends through each layer within the layer stack along a direction perpendicular to each interface between each adjacent pair of layers within the layer stack. [17] The method of claim 16, wherein: programming the semiconductor device to the hydrogenated state comprises applying a first programming pulse to the second electrode (158) having a first polarity relative to the first electrode (126); and programming the semiconductor device to the dehydrated state comprises applying a second programming pulse to the second electrode (158) having a second polarity opposite the first polarity relative to the first electrode (126). [18] The method of claim 15, wherein: the at least one semiconducting metal oxide layer (130) comprises a semiconducting metal oxide layer having a source region (32), a drain region (38) and a channel region (35) arranged between the source region (32) and the drain region (38); the first electrode (126) comprises the source region (32) and the second electrode (158) comprises the drain region (38); and the measuring current path extends through the channel region (35) along a direction that is parallel to an interface between the channel region (35) and the at least one hydrogen-containing metal layer (140) that is in contact with the channel region (35). [19] The method of claim 18, wherein: programming the semiconductor device to the hydrogenated state comprises applying a first programming pulse to the gate electrode (50) having a first polarity relative to one of the first electrode (126) and the second electrode (158); and programming the semiconductor device to the dehydrated state comprises applying a second programming pulse to the gate electrode (50) having a second polarity opposite to the first polarity to one of the first electrode (126) and the second electrode (158).

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