Semiconductor structure and method for its manufacture

Abstract

Semiconductor structure, exhibiting: a substrate (101); a dielectric stack (110) above the substrate (101), wherein the dielectric stack (110) has the following: a first layer (111) above the substrate (101); and a second layer (113) over the first layer (111); a gate layer (121) inserted into the dielectric stack (110) and comprising a first section (121A) and a second section (121B), wherein the first section (121A) extends through the second layer (113) from top to bottom and wherein the second section (121B) extends laterally between the first layer (111) and the second layer (113), such that the second section (121B) lies both above the first layer (111) and below the second layer (113); and a semiconductor channel layer (123) that conforms to a profile of the gate layer (121) and is wound around the second section (121B) so that the semiconductor channel layer (123) separates the second section (121B) from the dielectric stack (110).

Description

BACKGROUND

[0001] Over the past few decades, integrated circuit (IC) manufacturers have experienced exponential growth. With advancing IC development, the functional density (i.e., the number of interconnected components per chip area) has generally increased, while the geometric size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased.

[0002] However, as feature sizes continue to decrease, the manufacturing process becomes increasingly difficult to execute, and maintaining critical uniformity of component (or conduit) size becomes even harder. For example, a more complex operation may require more photomasks, leading to higher costs and consequently reduced throughput.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2006 / 0278916A1, US 6251737B1 and CN 111200015A.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood by referring to the following detailed description, when read in conjunction with the accompanying figures. It should also be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as desired for the clarity of the discussion. Fig. Figure 1A is a schematic drawing illustrating a perspective view of a semiconductor structure according to some embodiments of the present disclosure. Fig. Figure 1B illustrates a partially enlarged, fragmentary schematic view of section X of the semiconductor device. Fig. 1A according to some embodiments of the present disclosure. Fig. Figure 1B' illustrates a partially enlarged, fragmentary schematic view of section X of the semiconductor device from Fig. 1A according to some other embodiments of the present disclosure. Fig. Figure 1B illustrates a partially enlarged, fragmentary schematic view of section X of the semiconductor device. Fig. 1A according to some other embodiments of the present disclosure. Fig. Figure 1C illustrates a cross-sectional view of the reference cross-section C1-C1 of the semiconductor device. Fig. 1A according to some embodiments of the present disclosure. Fig. Figure 1D illustrates a cross-sectional view of the reference cross-section C2-C2 of the semiconductor device. Fig. 1A according to some embodiments of the present disclosure. Fig. Figure 1E illustrates a cross-sectional view of the reference cross-section C3-C3 of the semiconductor device. Fig. 1A according to some embodiments of the present disclosure. Fig. Figure 2 shows a flowchart of a process for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Fig. 3 to Fig. Figure 9 are cross-sectional views of a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. Fig. Figure 10A is a schematic drawing illustrating a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. Fig. Figure 10B illustrates a cross-sectional view of the reference cross-section C4-C4 of the semiconductor device made of Fig. 10A according to some embodiments of the present disclosure. Fig. Figure 10C illustrates a cross-sectional view of the reference cross-section C5-C5 of the semiconductor device. Fig. 10A according to some embodiments of the present disclosure. Fig. Figure 10D illustrates a cross-sectional view of the reference cross-section C6-C6 of the semiconductor device. Fig. 10A according to some embodiments of the present disclosure. Fig. Figure 11A is a schematic drawing illustrating a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. Fig. Figure 11B illustrates a cross-sectional view of the reference cross-section C7-C7 of the semiconductor device. Fig. 11A according to some embodiments of the present disclosure. Fig. Figure 11C illustrates a cross-sectional view of the reference cross-section C8-C8 of the semiconductor device. Fig. 11A according to some embodiments of the present disclosure. Fig. Figure 11D illustrates a cross-sectional view of the reference cross-section C9-C9 of the semiconductor device. Fig. 11A according to some embodiments of the present disclosure. Fig. Figure 12 is a schematic drawing illustrating a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or exemplary embodiments for implementing various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various discussed embodiments and / or configurations.

[0007] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the device in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0008] Notwithstanding the fact that the numerical ranges and parameters that demonstrate the broad scope of the disclosure are approximations, the numerical values ​​presented in the specific examples are given as accurately as possible. However, all numerical values ​​inherently exhibit certain errors that necessarily result from the standard deviations that occur in the corresponding test measurements. The terms "essentially," "approximately," or "about" generally mean within a value or range that may be considered acceptable by a person of average expertise. Alternatively, the terms "essentially," "approximately," or "about," when considered by a person of average expertise, mean within an acceptable standard error of the mean. A person of average expertise may understand that the acceptable standard error may vary according to different technologies. Outside of operational orUnless expressly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein, such as those used for quantities of material, durations, temperatures, operating conditions, ratios, and the like, are to be understood in all cases as modified by the terms "essentially," "approximately," or "about." Accordingly, unless otherwise stated, the numerical parameters set forth in this disclosure and the appended claims are approximations that may vary as necessary. Each numerical parameter should be interpreted at least with respect to the number of significant figures indicated and to allow for customary rounding. Ranges may herein be expressed as from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include the endpoints.

[0009] Storage devices are widely used in various applications, including data storage, data transmission, networking, computing, and more. For advanced applications such as 5G mobile networks or artificial intelligence, storage devices with higher speed, higher device density, lower latency, and higher bandwidth are in demand. However, the trend toward downscaling the geometry of semiconductor devices faces the challenge of complex manufacturing processes (such as intricate lithography processes that rely on numerous photomasks) and the associated costs.

[0010] The present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure to solve the aforementioned problems. For example, compared to other methods, the fabrication can be simplified and the number of lithography steps reduced. Furthermore, by increasing the device channel area, the speed and / or performance of the device can be improved.

[0011] Referring to Fig. 1A and Fig. 1B is Fig. 1A a schematic drawing illustrating a perspective view of a semiconductor structure, and illustrating Fig. 1B a partially enlarged, fragmentary schematic view of section X of the semiconductor device made of Fig. 1A according to some embodiments of the present disclosure. A semiconductor device 100 can include a substrate 101, a dielectric stack 110 above the substrate 101, a gate layer 121 in the dielectric stack 110, and conductive features 131A and 132A in the dielectric stack 110. In some embodiments, the substrate 101 includes silicon. Alternatively or additionally, the substrate 101 includes another material, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminium indium arsenide (AlInAs), aluminium gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.In some other embodiments, the substrate 101 includes one or more materials of Group III-V, one or more materials of Group II-IV, or combinations thereof. In some alternative embodiments, the substrate 101 may be undoped. In some other embodiments, the substrate 101 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate (SOI substrate), a silicon-germanium-on-insulator substrate (SGOI substrate), or a germanium-on-insulator substrate (GOI substrate). In some other embodiments, the substrate 101 may include active regions.

[0012] The dielectric stack 110 can include insulating material. In some embodiments, the dielectric stack 110 can include dielectric materials with multiple sections formed in different stages. In some embodiments, the dielectric stack 110 can include a multilayer composition, for example, a first layer 111, a second layer 113 above the first layer 111, and a spacer layer 112 with a section between the first layer 111 and the second layer 113. In some embodiments, the first layer 111 and the second layer 113 can include oxide. In some embodiments, a material of the first layer 111 can be similar to a material of the second layer 113. In some embodiments, a material of the spacer layer 112 can include an oxide-based material.In some cases, the material of the spacer layer 112 may be similar to or substantially identical with the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of the spacer layer 112 may differ from that of the first layer 111 and / or the second layer 113. For example, the material of the spacer layer 112 may include another oxide-based material, silicon nitride (SiN), silicon germanium (SiGe), or another insulating / film material.

[0013] Referring to Fig. 1B' illustrates Fig. 1B' a partially enlarged, fragmentary schematic view of section X of the semiconductor device Fig. 1A according to some embodiments of the present disclosure. Some alternative embodiments, which are described in Fig. The examples shown in 1B' are similar to the discussion in Fig. 1B, but one difference is that the material of the spacer layer 112 is identical to the material of the first layer 111 and the second layer 113. For example, the same material (such as oxide-based material) is used as the material of the first layer 111 and the second layer 113 (as in Fig. 3 discussed) and for filling into the spaces between two adjacent gate layers 121 (as in Fig. 8 to Fig. 9 discussed). If the material of the spacer layer 112 is identical to that of the first layer 111 and the second layer 113, the layers can be formed in different stages, as discussed below. Fig. 2 to Fig. 12 is discussed. In some embodiments, the material of the first layer 111, the second layer 113 and the spacer layer 112 may be fused together or integrated.

[0014] Referring to Fig. 1B'' illustrates Fig. 1B'' a partially enlarged, fragmentary schematic view of section X of the semiconductor device from Fig. 1A according to some embodiments of the present disclosure. Some alternative embodiments, which are described in Fig. The examples shown in 1B'' are similar to the discussion in Fig. 1B or Fig. 1B', but one difference is that the material of the spacer layer 112 differs from the material of the first layer 111 and the second layer 113, with a portion of the spacer layer 112 not being covered by the second layer 113. In some embodiments, the material of the spacer layer 112 may include an oxide-based material. In some cases, the material of the spacer layer 112 may be similar to the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of the spacer layer 112 may differ from the first layer 111 and / or the second layer 113. For example, the material of the spacer layer 112 may include another oxide-based material, silicon nitride (SiN), silicon germanium (SiGe), or another insulating / film material.

[0015] Referring to Fig. In some embodiments, 1A the width WB of the spacer layer 112 along the primary direction PD may be smaller than the width WA of the first layer 111 or the width WC of the second layer 113.

[0016] The semiconductor device 100 can include several gate layers 121 spaced apart in a primary direction PD. The gate layers 121 can include conductive material, such as tungsten (W) or the like. The gate layers 121 can be cross-shaped in a cross-sectional view (as shown in Fig. 1A, Fig. 1B, Fig. 1B' or Fig. (1B'' shown) and each of the gate layers 121 extends along a secondary direction SD, essentially perpendicular to the primary direction PD.

[0017] Referring to Fig. 1B, Fig. 1B' and Fig. 1B'' can include a gate layer 121 comprising a first section 121A traversing the second layer 113, a second section 121B extending between the first layer 111 and the second layer 113, and a third section 121C within the first layer 111 and proximal to the substrate 101. The second section 121B can overlap the first layer 111 and the second layer 113 from a top-down perspective (along a tertiary direction TD). In some embodiments, the first section 121A of the gate layer 121 can be exposed by the dielectric stack 110.

[0018] The semiconductor device 100 can further include a first high k-value material 122, a channel layer 123, and a second high k-value material 122' between the gate layer 121 and the dielectric stack 110. The second high k-value material 122' conforms to an outer profile of an outer side wall and a bottom surface of the gate layer 121. The channel layer 123 conforms to an outer profile of the second high k-value material 122'. The first high k-value material 122 conforms to an outer profile of the channel layer 123. In other words, the channel layer 123 is located between the first high k-value material 122 and the second high k-value material 122'. The first high k-value material 122, the channel layer 123, and the second high k-value material 122' extend along the secondary direction SD.

[0019] The first material with a high k-value of 122 can include a material suitable for use as a dipole layer, such as hafnium zirconium oxide (HfZrO; e.g., Hf). x Zr x O y or the like), other hafnium zirconium-based materials, or ferroelectric materials. The first high k-value 122 material can serve as a dipole layer to change a channel storage state. The second high k-value 122' material can include a different material than the first high k-value 122 material, such as hafnium oxide (e.g., HfO₂) or other materials suitable for improving channel support performance. For example, HfO₂ can provide an oxide vacancy to improve channel support performance.

[0020] The first high k-value material 122 can be in direct contact with a lower surface BS of the second layer 113, an upper surface TS of the first layer 111, and a side wall SW1 of the spacer layer 112. In some embodiments, a width W1, measured from a side wall of the first high k-value material 122 adjacent to the side wall SW1 of the spacer layer 112 to a side wall SW2 of the spacer layer 112 proximal to the first section 121A of the gate layer 121 (or a side wall SW3 of the spacer layer 112 proximal to the third section 121C of the gate layer 121), can be in a range of approximately 30 nm to 90 nm. In cases where the width is smaller than the aforementioned range, the performance of the device may be lower than desired due to the reduced device channel area.In cases where a width is greater than the aforementioned area, the difficulty of controlling associated operations (e.g., a lateral pullback operation, as described in . Fig. (4 discussed) may be undesirably increased. In some embodiments, a depth T1, measured from a surface of the first high k-value material 122 adjacent to the lower surface BS of the second layer 113 to another surface of the first high k-value material 122 adjacent to the upper surface TS of the first layer 111, may be in a range of approximately 50 nm to 80 nm. In cases where the depth is less than the aforementioned range, the device performance may be lower than desired due to the reduced device channel area, or the difficulty of forming the gate layer 121 may be increased. In cases where the depth is greater than the aforementioned range, the overall height of the semiconductor device 100 along the tertiary direction TD may be too large, making it difficult to meet the device size reduction requirements.

[0021] This configuration allows the second section 121B of the gate layer 121 to have a substantially vertical side wall and to represent a profile similar to a four-sided, rectangular or square profile in a cross-sectional view (as in Fig. 1B, Fig. 1B' or Fig. (1B'' shown). This allows the device channel area to be increased compared to a similar embodiment with a curved profile, thereby improving the device's performance (such as processing speed). In some embodiments, a first angle θ1 between a side wall of the spacer layer 112 and the lower surface BS of the second layer 113 can be in a range of approximately 80 degrees to approximately 90 degrees. Similarly, a second angle θ2 between the side wall SW2 of the second layer 113 proximal to the first section 121A of the gate layer 121 and the lower surface BS of the second layer 113 can be in a range of approximately 80 degrees to approximately 90 degrees.In cases where the angle is larger or smaller than the aforementioned area, a defect may occur, the formation of the first high k-value material 122, the channel layer 123 and the second high k-value material 122' may be difficult, or the device channel area may be too small.

[0022] Referring to Fig. 1A, Fig. 1C, Fig. 1D and Fig. 1E illustrates Fig. 1C a cross-sectional view of the reference cross-section C1-C1 of the semiconductor device from Fig. 1A, illustrated Fig. 1D a cross-sectional view of the reference cross-section C2-C2 of the semiconductor device from Fig. 1A, and illustrates Fig. 1E a cross-sectional view of the reference cross-section C3-C3 of the semiconductor device made of Fig. 1A according to some embodiments of the present disclosure. The semiconductor device 100 may further include conductive features 131A and 132A embedded in the dielectric stack 110 and between a pair of gate layers 121. The conductive features 131A and 132A traverse the second layer 113 and the spacer layer 112. In some embodiments, the conductive feature(s) 131A may represent the source layer(s) and the conductive feature(s) 132A may represent the drain layer(s). In some embodiments, the conductive features 131A and 132A may include conductive materials, such as tungsten (W) or the like. It should be noted that although in Fig. 1A and Fig. While only two conductive features 131A and one conductive feature 132A are shown in Figure 1C, the present disclosure is not limited thereto. The semiconductor device 100 can include several rows of conductive features 131A and 132A between other pairs of gate layers 121 or can have one or more conductive features 131A and 132A between two gate layers 121.

[0023] As in Fig. 1D or Fig. As shown in Figure 1E, a lower surface BS' of the conductive features 131A (or the conductive features 132A) is located on a plane lower than a plane of the upper surface TS of the first layer 111. In some embodiments, a section of the conductive features 131A and 132A may be laterally surrounded by the first layer 111. For example, a depth D1, measured from the lower surface BS' of the conductive features 131A (or the conductive features 132A) to the surface of the first high k-value material 122 adjacent to the upper surface TS of the first layer 111, may be in a range of about 20 nm to about 30 nm. Such a configuration may increase the contact area between the first high k-value material 122 and the conductive features 131A (or the conductive features 132A).In cases where the depth D1 is less than 20 nm or the upper surface TS of the first layer 111 lies above the lower surface BS' of the conductive features 131A (or the conductive features 132A), the total contact area between the first high k-value material 122 and the conductive features 131A (or the conductive features 132A) may be reduced, the etching process may be difficult to control, or the reliability may be impaired. In cases where the depth D1 is greater than 30 nm, the reliability (as a property of the first layer 111) may be impaired.

[0024] The semiconductor device 100 further includes an insulating layer 130 above the dielectric stack 110 and interconnection structures arranged within the dielectric stack 110. The interconnection structures may include a first conductive via 131B electrically connected to each of the conductive feature 131A, and a second conductive via 132B electrically connected to each of the conductive feature 131A. In some embodiments, the semiconductor device 100 further includes a conductive path 133 arranged within the insulating layer 130 and connected to the gate layer 121. In some embodiments, the conductive path 133 constitutes a word lead. In some embodiments, the first conductive via 131B, the second conductive via 132B, and the conductive path 133 may include conductive material, such as copper.

[0025] Referring to Fig. 2 shows Fig. 2 A flowchart of a process for fabricating a semiconductor structure according to some embodiments of the present disclosure. The process 1000 for fabricating a semiconductor device includes forming a first layer over a substrate (process step 1004, see for example ). Fig. 3) Forming a sacrificial layer above the first layer (process step 1007, see for example Fig. 3) Forming a second layer above the sacrificial layer (process step 1013, see for example Fig. 3) Forming a first depression to expose a side wall of the sacrificial layer (Procedure step 1018, see for example Fig. 4) Forming a material with a high k-value that conforms to a profile of the first well (process step 1022, see for example Fig. 5), and forming a gate material in the first well (process step 1027, see for example Fig. 6) one.

[0026] Referring to Fig. 3 is Fig. 3 A cross-sectional view of a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. A substrate 101 is provided. Details regarding the substrate 101 can be found in Figure 3. Fig. Reference is made to Figure 1A. A first layer 111 is formed over the substrate 101, wherein the first layer 111 may include an insulating material. In some embodiments, the first layer 111 may include an oxide-based material or another suitable material. A sacrificial layer 112S is formed over the first layer 111, wherein the material of the sacrificial layer 112S differs from the material of the first layer 111. The sacrificial layer 112S may, for example, include thin-film materials such as silicon nitride (SiN), silicon germanium (SiGe), or the like. A second layer 113 is formed over the sacrificial layer 112S, wherein the material of the second layer 113 differs from the material of the sacrificial layer 112S. In some embodiments, the material of the second layer 113 may be identical to or similar to the material of the first layer 111, such as an oxide-based material or another suitable insulating material.

[0027] Referring to Fig. 4 is Fig. 4 A cross-sectional view of a semiconductor structure during intermediate stages of fabrication processes according to some embodiments of the present disclosure. A cutting process, which may include an etching process and a photolithography process, is performed to remove a portion of the first layer 111, the sacrificial layer 112S, and the second layer 113, thereby forming a plurality of first wells R1. In alternative embodiments, only one first well R1 is formed. A sidewall of the sacrificial layer 112S is exposed at a sidewall of each of the first wells R1. In some embodiments, a portion of the substrate 101 is exposed after the etching and photolithography processes. In some embodiments, the etching process may be an anisotropic etching process. In some embodiments, the photolithography process may include the use of a photomask.

[0028] A lateral pullback process is performed to remove a section of the sacrificial layer 112S to extend each of the first wells R1. In some embodiments, a section of the sacrificial layer 112S is removed from the side wall of a first well R1 by a selective etching process, which may involve the application of a suitable chemical over the substrate 101. For example, in cases where silicon nitride is a material of the sacrificial layer 112S, phosphoric acid (H3PO4) at an elevated temperature (for example, around 170°C) or another suitable chemical may be applied over the substrate 101 to laterally remove a section of the sacrificial layer 112S. As another example, in cases where silicon germanium is a material of the sacrificial layer 112S, fluorine gas (F2) or another suitable chemical may be applied over the substrate 101 to laterally remove a section of the sacrificial layer 112S.The amount of sacrificial layer 112S removed during the lateral pullback process can be controlled by a time calculation.

[0029] By using the lateral pullback operation, a section of the lower surface of the second layer 113 and a section of the upper surface of the first layer 111 can be exposed and made visible through the sacrificial layer 112S. Furthermore, after the lateral pullback operation, the remaining sacrificial layer 112S can have a substantially vertical sidewall SW', and the first depressions R1 can be cross-shaped in a cross-sectional view. Similar to the discussion in Fig. 1A to Fig. 1E The lateral etch depth W1' of the lateral pullback operation can be in a range of approximately 30 nm to 90 nm. In cases where the lateral etch depth is less than the aforementioned range, the device performance may be lower than desired due to a reduced device channel area. In cases where the lateral etch depth is greater than the aforementioned range, the difficulty of controlling an associated operation may be undesirably increased, or in some cases, defects may occur due to over-etching.

[0030] Referring to Fig. 3 and Fig. 4. The thickness T1' of the sacrificial layer 112S can be in the range of approximately 50 nm to 80 nm. In cases where the thickness is smaller than the aforementioned range, the device performance may be lower than desired due to a reduced device channel area, or the difficulty of the lateral pullback operation may be increased due to a higher aspect ratio. In cases where the thickness is larger than the aforementioned range, the overall height of the semiconductor device along the tertiary direction TD may be too large, making it difficult to meet the device size reduction requirements.

[0031] Furthermore, the angle at a corner of the second layer 113 (corresponding to the one in Fig. 1B, Fig. 1B' or Fig. The second angle θ2 shown in Figure 1B'' may lie in a range of approximately 80 degrees to approximately 90 degrees. Furthermore, the angle at a corner between the side wall SW' of the remaining sacrificial layer 112S and the exposed lower surface of the second layer 113 (corresponding to the angle shown in Figure 1B'') may lie in a range of approximately 80 degrees to approximately 90 degrees. Fig. 1B, Fig. 1B' or Fig. The first angle θ1 shown in 1B'' lies in a range of approximately 80 degrees to approximately 90 degrees. In cases where both angles are larger or smaller than the aforementioned ranges, defects may occur, and the subsequent formation of the first high k-value material 122, the channel layer 123, and the second high k-value material 122' may be difficult (as shown in Fig. 5 to Fig. 6 discussed) or the device channel area may be too small.

[0032] Referring to Fig. 5 is Fig. 5 A cross-sectional view of a semiconductor structure during intermediate stages of fabrication processes according to some embodiments of the present disclosure. A first high k-value material 122 is formed such that it conforms to a profile of the first depressions R1. In some embodiments, the first high k-value material 122 further covers an upper surface of the second layer 113. In some embodiments, the first high k-value material 122 can be in direct contact with the exposed portion of the substrate 101. The first high k-value material 122 can include a material suitable for use as a dipole layer, such as hafnium zirconium oxide (HfZrO; e.g., Hf x Zr x O yor the like), other hafnium zirconium-based materials or ferroelectric materials. The channel layer 123 is formed over the first high k-value material 122, the channel layer 123 conforming to the profile of the first high k-value material 122 (as well as the profile of the first wells R1).

[0033] The second high k-value material 122' is formed above the channel layer 123, conforming to the profile of the channel layer 123 (and the profile of the first wells R1). This second high k-value material 122' may include a different material than the first high k-value material 122, such as hafnium oxide (e.g., HfO₂) or other materials suitable for improving channel support performance. For example, HfO₂ may provide an oxide void to enhance channel support performance.

[0034] The profile of the first recesses R1 formed by the lateral pullback process can facilitate the formation of the first high k-value material 122, the channel layer 123 and the second high k-value material 122' and can provide an adequate device channel area to improve the performance of the device.

[0035] Referring to Fig. 6 is Fig. 6 A cross-sectional view of a semiconductor structure during intermediate stages of fabrication processes according to some embodiments of the present disclosure. The gate material 121M is placed above the second high k-value material 122' and in the first wells R1 (as shown in Fig. (5 shown). The gate material 121M can include conductive material, such as tungsten (W) or the like.

[0036] Referring to Fig. 7 is Fig. Figure 7 shows a cross-sectional view of a semiconductor structure during intermediate stages of fabrication processes according to some embodiments of the present disclosure. A planarization operation, such as a chemical mechanical planarization operation (CMP operation), can be performed from a top surface of the gate material 121M to remove excess portions of the gate material 121M, the first high k-value material 122, the channel layer 123, and the second high k-value material 122'. A top surface of the second layer 113 is exposed by the planarization operation, and the remaining gate material 121M thereby forms the gate layers 121. A top surface of the gate layer 121, a top surface of the second layer 113, a top surface of the first high k-value material 122, a top surface of the channel layer 123, and a top surface of the second high k-value material 122' can be coplanar.As before in . Fig. 1A to Fig. As discussed in 1E, a gate layer 121 can be cross-shaped in a cross-sectional view, including a first section 121A traversing the second layer 113, a second section 121B extending between the first layer 111 and the second layer 113, and a third section 121C in the first layer 111 and proximal to the substrate 101.

[0037] Referring to Fig. 8 is Fig. Figure 8 shows a cross-sectional view of a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. In some embodiments, the remaining sacrificial layer 112S and a portion of the second layer 113 above the remaining sacrificial layer 112S can be removed by an etching process, thereby forming a plurality of second wells R2. In alternative embodiments, only one second well R2 is formed. In some embodiments, the entire remaining sacrificial layer 112S is removed. In some embodiments, the etching process can be controlled by a timing calculation. In some embodiments, a portion of the first layer 111 can be etched from its top surface. In some alternative embodiments, a portion of the sacrificial layer 112S can remain.

[0038] Referring to Fig. 9 is Fig. 9 A cross-sectional view of a semiconductor structure during intermediate stages of manufacturing processes according to some embodiments of the present disclosure. The material of the spacer layer 112 and / or the second layer 113 can be found in the second wells R2 (in Fig. 8) are formed. In some embodiments, as in Fig. As discussed in Figure 1B, the spacer layer 112 and the second layer 113 are formed above the second layer in the second recesses R2. In some embodiments, the spacer layer 112 material may include an oxide-based material. In some cases, the spacer layer 112 material may be similar to or substantially identical with the material of the first layer 111 or the second layer 113. In some alternative embodiments, the spacer layer 112 material may differ from the first layer 111 and / or the second layer 113. For example, the spacer layer 112 material may include another oxide-based material, silicon nitride (SiN), silicon germanium (SiGe), or another insulating / film material. In some embodiments, a planarization process (such as CMP) may be performed to remove excess material.

[0039] In some alternative embodiments, which relate to Fig. Referring to 1B', the material of the spacer layer 112 is identical to the material of the first layer 111 and the second layer 113, and this material is filled into the second recesses R2. In some embodiments, a planarization process (such as CMP) can be performed to remove excess material.

[0040] In some alternative embodiments, which relate to Fig. Referring to 1B'', the material of the spacer layer 112 differs from the material of the first layer 111 and the second layer 113, and the spacer layer 112 is formed in the second recesses R2. In some cases, the material of the spacer layer 112 may be similar to the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of the spacer layer 112 may differ from the first layer 111 and / or the second layer 113. The material of the spacer layer 112 may, for example, include another oxide-based material, silicon nitride (SiN), silicon germanium (SiGe), or some other insulating / film materials.In some embodiments, a planarization process (such as CMP) can be performed to remove excess material, and the spacer layer 112 can have an area that is exposed and made visible by the second layer 113.

[0041] By filling the second wells R2, the first layer 111, the second layer 113 and the spacer layer 112 thus form a dielectric stack 110.

[0042] Referring to Fig. 10A, Fig. 10B, Fig. 10C and Fig. 10D is Fig. 10A illustrates a schematic drawing that demonstrates a semiconductor structure during intermediate stages of manufacturing processes. Fig. 10B a cross-sectional view of the reference cross-section C4-C4 of the semiconductor device made of Fig. 10A, illustrated Fig. 10C a cross-sectional view of the reference cross-section C5-C5 of the semiconductor device from Fig. 10A and illustrated Fig. 10D a cross-sectional view of the reference cross-section C6-C6 of the semiconductor device from Fig. 10A according to some embodiments of the present disclosure. A plurality of third wells R131 and a fourth well R132 can be formed in the dielectric stack 110. In alternative embodiments, only one third well R131 is formed and a plurality of fourth wells R132 are formed. In alternative embodiments, a plurality of third wells R131 and a plurality of fourth wells R132 are formed alternately in the secondary direction SD.

[0043] At least one section of a sidewall SW4 of the first high k-value material 122 (which may be located proximal to the second section 121B of the gate layer 121) is exposed by the third wells R131 and the fourth well R132. In some embodiments, the formation of the third wells R131 and the fourth well R132 may involve a photolithography process and / or an etching process. The etching process may be controlled by a timing calculation. In some embodiments, the lower surfaces of the third wells R131 and the fourth well R132 are located on a plane that is lower by a distance D1' than the plane of an interface INT between an upper surface of the first layer 111 and the first high k-value material 122.For example, the lower surfaces of the third wells R131 and the fourth well R132 may lie on a plane below the upper surface of the first layer 111 (or the interface INT) in a range of about 20 nm to about 30 nm.

[0044] Referring to Fig. 11A, Fig. 11B, Fig. 11C and Fig. 11D is Fig. Figure 11A is a schematic drawing illustrating a semiconductor structure during intermediate stages of manufacturing processes. Fig. 11B a cross-sectional view of the reference cross-section C7-C7 of the semiconductor device made of Fig. 11A, illustrated Fig. 11C a cross-sectional view of the reference cross-section C8-C8 of the semiconductor device from Fig. 11A and illustrates Fig. 11D a cross-sectional view of the reference cross-section C9-C9 of the semiconductor device from Fig. 11A according to some embodiments of the present disclosure. In some embodiments, the conductive features 131A and 132A can be formed in the third wells R131 and the fourth well R132, respectively, wherein the conductive features 131A and 132A include conductive materials such as tungsten (W) or the like. The conductive features 131A and 132A can be in direct contact with the first high k-value material 122 (which matches the two adjacent gate layers 121) on two opposite side walls SW4 in the primary direction PD. In some embodiments, the conductive feature(s) 131A can represent the source layer and the conductive feature(s) 132A can represent the drain layer.

[0045] Referring to Fig. 12 is Fig. Figure 12 shows a schematic drawing illustrating a semiconductor structure during intermediate stages of fabrication processes according to some embodiments of the present disclosure. An insulating layer 130 is formed over the dielectric stack 110 and the interconnection structures formed in the dielectric stack 110. In some embodiments, the formation of the interconnection structure may include a photolithography process and an etching process. The interconnection structures may include a first conductive via 131B electrically connected to each of the conductive feature 131A and a second conductive via 132B electrically connected to the conductive feature 132A. In some embodiments, the semiconductor device 100 further includes a conductive path 133 arranged in the insulating layer 130 and connected to the gate layer 121.In some embodiments, the conductive path 133 represents a word lead. The first conductive via 131B, the second conductive via 132B, and the conductive path 133 can enclose conductive material, such as copper.

[0046] The present disclosure provides semiconductor structures that can be used in memory device applications. In particular, the present disclosure provides a gate layer 121 which, in a cross-sectional view, is substantially cross-shaped (as shown in the figure). Fig. 1A to Fig. 1E and Fig. (12 shown). The shape of the gate layer 121 increases the total contact area between the high k-value layers and the channel layer (as well as the contact area between the second high k-value material 122' and the gate layer 121), and the total device channel area can be increased compared to similar designs with an upright gate or a curved gate. This leads to improved device performance, such as higher processing speed or reliability.

[0047] Furthermore, the aforementioned profile of gate layer 121 (in Fig. 1A to Fig.(12 discussed) can be formed by a simplified process. In a comparative embodiment, where the gate layer is formed prior to forming the high k-value material, additional lithography operations can be employed to expose a portion of the gate layer in order to connect the gate layer to a word line. In some embodiments, the present disclosure can reduce the total number of lithography operations (for example, by two photomasks), thereby improving throughput and manufacturing efficiency.

[0048] Furthermore, the lateral pullback technique on the sacrificial layer 112S results in sacrificial layer 112S sidewalls with a vertical profile. These sidewalls of the remaining sacrificial layer 112S are used to form the high k-value materials 122 and 122' prior to forming the gate layer 121. In some cases, an additional etch stop layer can be omitted, which contributes to reducing the device size. Moreover, this configuration allows for the formation of a recess to expose a sidewall of the first high k-value material 122 from the sacrificial layer 112S using an etching process.

[0049] Similar techniques to those discussed in the present disclosure can be applied to various types of memory structures or other semiconductor structures, including, but not limited to, non-volatile memory devices, volatile memory devices, nanosheet devices, gate all-around devices, nanowire devices, Fin field-effect transistor (FinFET) structures, or other types of transistors.

[0050] Some embodiments of the present disclosure provide a semiconductor structure comprising: a substrate; a dielectric stack above the substrate comprising a first layer above the substrate and a second layer above the first layer; and a gate layer comprising a first section traversing the second layer and a second section extending between the first layer and the second layer.

[0051] Some embodiments of the present disclosure provide a semiconductor structure comprising: a substrate; a dielectric stack above the substrate comprising a first layer above the substrate and a second layer above the first layer; and a first high k-value material in direct contact with a lower surface of the second layer.

[0052] Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, which includes: forming a first layer over the substrate, wherein the first layer includes a first material; forming a sacrificial layer over the first layer, wherein the sacrificial layer comprises a second material that is different from the first material; forming a second layer over the sacrificial layer; forming a first well to expose a side wall of the sacrificial layer; and forming a gate material in the first well.

Claims

[1] Semiconductor structure, having: a substrate (101); a dielectric stack (110) above the substrate (101), wherein the dielectric stack (110) has the following: a first layer (111) above the substrate (101); and a second layer (113) over the first layer (111); a gate layer (121) inserted into the dielectric stack (110) and comprising a first section (121A) and a second section (121B), wherein the first section (121A) extends through the second layer (113) from top to bottom and wherein the second section (121B) extends laterally between the first layer (111) and the second layer (113), such that the second section (121B) lies both above the first layer (111) and below the second layer (113); and a semiconductor channel layer (123) that conforms to a profile of the gate layer (121) and is wound around the second section (121B) so that the semiconductor channel layer (123) separates the second section (121B) from the dielectric stack (110). [2] Semiconductor structure according to claim 1, wherein the semiconductor channel layer (123) is located on three different sides of the second projection. [3] Semiconductor structure according to claim 1 or 2, further comprising a conductive feature extending from top to bottom through the second layer (113), wherein the second section (121B) is located laterally between the conductive feature and the first section (121A) and limits the latter. [4] Semiconductor structure according to claim 3, wherein a lower surface of the conductive feature is located on a plane that is lower than a plane of an upper surface of the first layer (111). [5] Semiconductor structure according to claim 3 or 4, wherein the first layer (111) extends laterally in a closed path to surround the conductive feature. [6] Semiconductor structure according to one of claims 1 to 5, further comprising a first material with a high k-value (122) that is in direct contact with a lower surface of the second layer (113) and separates the second section (121B) from the dielectric stack (110). [7] Semiconductor structure according to claim 6, wherein the first high k-value material (122) has a side wall connected between the lower surface of the second layer (113) and an upper surface of the first layer (111), and wherein the angle between the side wall of the first high k-value material (122) and the lower surface of the second layer (113) is in a range of 80 degrees to 90 degrees. [8] Semiconductor structure, having: a substrate (101); a dielectric stack (110) above the substrate (101), wherein the dielectric stack (110) has the following: a first layer (111) above the substrate (101); and a second layer (113) over the first layer (111); a gate layer (121) extending from top to bottom through the dielectric stack (110) and having a cross-shaped profile; a first material with a high k-value (122) that is in direct contact with a lower surface of the second layer (113) and separates the gate layer (121) from the dielectric stack (110); and a channel layer (123) that conforms to an inner side wall of the first high k-value material (122) and separates the gate layer (121) from the first high k-value material (122). [9] The semiconductor structure according to claim 8, wherein the first high k-value material (122) is in direct contact with an upper surface of the first layer (111). [10] Semiconductor structure according to one of claims 8 or 9, wherein the first high k-value material (122) comprises hafnium zirconium oxide or hafnium zirconium. [11] Semiconductor structure according to one of claims 8 to 10, wherein the gate layer (121) has a pair of projections, the projections being located on opposite sides of the gate layer (121) and extending in opposite directions to locations both below the second layer (113) and above the first layer (111). [12] Semiconductor structure according to claim 11, further comprising a second high k-value material (122') in direct contact with an upper and lower surface of the projections, wherein a composition of the second high k-value material (122') differs from a composition of the first high k-value material (122). [13] Method for forming a semiconductor structure comprising: Forming a first layer (111) over a substrate (101), wherein the first layer (111) comprises a first material; Forming a sacrificial layer (112S) over the first layer (111), wherein the sacrificial layer (112S) has a second material that differs from the first material; Forming a second layer (113) above the sacrificial layer (112S); Forming an initial depression (R1) to expose a side wall of the sacrificial layer (112S); Lateral removal of a section of the sacrificial layer (112S) from the side wall; Forming a gate material (121, 121M) in the first well, wherein the gate material (121, 121M) lies below the second layer (113) and above the first layer (111) and has a cross shape in a cross-sectional view; and Forming a first material with a high k-value (122) that conforms to a profile of the first depression (R1) and is in direct contact with a lower surface of the second layer (113); and Forming a semiconductor channel layer (123) that lies above the first high k-value material (122) and conforms to a profile of the first high k-value material (122), wherein the semiconductor channel layer (123) extends along the lower surface of the second layer (113). [14] Method according to claim 13, wherein lateral removal of the section of the sacrificial layer (112S) comprises applying phosphoric acid over the substrate (101). [15] Method according to claim 13 or 14, wherein a section of a lower surface of the second layer (113) is exposed after lateral removal of the section of the sacrificial layer (112S). [16] Method according to any one of claims 13 to 15, further comprising: Forming a second well extending through the second layer (113) and exposing a sidewall of the first high k-value material (122) after forming the gate material (121, 121M) in the first well (R1). [17] Method according to any one of claims 13 to 16, further comprising: Replacing the sacrificial layer (112S) with a spacer layer.

Images