MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE PRODUCED BY METHOD

Abstract

Method for manufacturing a semiconductor device (1500) comprising the following steps: Establishing an initial word line (103) over a substrate (101); Establishing a bit line (301) over the first word line (103); After establishing the first word line (103), establish a first memory cell (800) and a second memory cell (800) on opposite sides of the bit line (301); Deposition of a second word line adjacent to the first memory cell (800) and in electrical connection with the first word line (103); Separation of a third word line adjacent to the second memory cell (800); and After the separation of the third word line, a fourth word line (1201) is produced over and in electrical connection with the third word line.

Description

background

[0001] Semiconductor memory is used in integrated circuits for electronic devices such as radios, televisions, mobile phones, and personal computers. One type of semiconductor memory is resistive random-access memory (RRAM), which stores values ​​in materials with varying resistances. These materials can be switched between a low-resistance phase and a high-resistance phase to represent bit codes.

[0002] Document US 2018 / 0 083 188 A1 discloses a semiconductor structure containing a variable-resistance memory structure. Document US 2015 / 0 263 073 A1 discloses an RRAM array containing multiple horizontal electrode leads extending in a horizontal direction. Document US 2017 / 0 005 138 A1 discloses an electronic device containing a semiconductor memory. Document US 2020 / 0 006 428 A1 discloses a memory device. Document US 2020 / 0 395 408 A1 discloses a memory device. Document DE 10 2018 127 048 A1 describes a memory cell. The objective is to improve corresponding semiconductor devices. Brief description of the drawings

[0003] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1A and Fig. Figure 1B shows the production of a first word line according to some embodiments. The Fig. 2A and Fig. Figure 2B shows a deposition of a bit line material according to some embodiments. The Fig. 3A and Fig. Figure 3B shows the construction of a bit line according to some embodiments. The Fig. 4A and Fig. Figure 4B shows a deposition of an RRAM material according to some embodiments. The Fig. 5A and Fig. Figure 5B shows a structuring of the RRAM material according to some embodiments. The Fig. 6A and Fig. Figure 6B shows the manufacture of a selector according to some embodiments. The Fig. 7A and Fig. Figure 7B shows a deposition of a functional word-line material according to some embodiments. The Fig. 8A and Fig. Figure 8B shows a production of functional word lines according to some embodiments. The Fig. 9A and Fig. Figure 9B shows a production of a dielectric layer according to some embodiments. The Fig. 10A and Fig. Figure 10B shows the creation of an opening through the dielectric layer according to some embodiments. The Fig. 11A and Fig. Figure 11B shows a deposition of a second word-conducting material according to some embodiments. The Fig. 12A and Fig. Figure 12B shows the production of a second word line according to some embodiments. The Fig. Figures 13A to 13C show the production of a dielectric layer according to some embodiments. Fig. Figure 14 shows a production of metallization layers according to some embodiments. Fig. Figure 15 shows a memory area adjacent to a logic area according to some embodiments. The Fig. 16A and Fig. Figure 16B shows the placement of a first hard mask according to some embodiments. The Fig. 17A and Fig. Figure 17B shows a production of functional word lines, wherein the first hard mask remains in place, according to some embodiments. The Fig. 18A and Fig. Figure 18B shows a production of a second word line, with the first hard mask remaining in place, according to some embodiments. Fig. Figure 19 shows the deposition of a selector material prior to structuring the RRAM material according to some embodiments. Fig. Figure 20 shows a structuring of the RRAM material with the selector material to create an L-shape according to some embodiments. Fig. Figure 21 shows a fabrication of the second word line with the structured RRAM material in the L-shape according to some embodiments. Fig. Figure 22 shows a deposition of the RRAM material in the L-shape, with the first hard mask remaining in place, according to some embodiments. Detailed description

[0004] The problem is solved by the methods for manufacturing a semiconductor device according to claims 1 and 8, as well as the semiconductor device according to claim 15. Further embodiments of the invention are described in the dependent claims. The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention.For example, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, so that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] Examples of a specific embodiment are described below, in which RRAM devices (RRAM: resistive random-access memory) are connected to word lines located on opposite sides of the RRAM devices to provide single-bit operation capabilities for multiple functional vertical RRAM cells (e.g., in a 1S1R structure) per bit line. However, the embodiments described here are intended only to illustrate the concepts, as they can be used in a wide range of embodiments and are not intended to be limited to those specifically described here.

[0007] In the Fig. 1A and Fig. Figure 1B shows the creation of a first word line 103 over a substrate 101, wherein Fig. 1A a top-down view of the structure of Fig. 1B along a line A - A' shows and Fig. 1B a sectional view of Fig. 1A shows a line B - B'. Substrate 101 can be solid silicon, doped or undoped, or an active layer of a semiconductor-oriented insulator (SOI) substrate. Generally, an SOI substrate has a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used are multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0008] Furthermore, the substrate 101 can have active devices (not shown individually) fabricated in and / or above the substrate 101, and first metallization layers 102 above the active devices. Many different active and passive devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional requirements of the design of a semiconductor device, and they can be fabricated by suitable methods. For example, in some embodiments, the active devices can be FinFET devices, wherein fins are fabricated from semiconductor materials, gate stacks are fabricated above the fins of the FinFET devices, STI regions (STI: shallow trench insulation) are created between the fins, and source / drain regions are created in the fins on opposite sides of the gate stacks.For the sake of clarity, the STI areas and the source / drain areas are not shown individually.

[0009] The first metallization layers 102 are produced over the active devices and are designed to connect the various active devices to form functional circuits. In one embodiment, the first metallization layers 102 are produced from alternating layers of dielectric materials (e.g., dielectric low-k materials, dielectric extremely low-k materials, dielectric ultra-low-k materials, combinations thereof, or the like) and conductive materials, and they can be produced by a suitable process such as deposition, single-damascene process, dual-damascene process, etc.

[0010] In one embodiment, the metallization layers 102 can comprise a first metal layer, a second metal layer, a third metal layer, and a fourth metal conductor 111 (where, for clarity, only the fourth metal conductor 111 is shown). Furthermore, the first metallization layers 102 have a dielectric layer 110 over the fourth metal conductor 111 and a first metallization via 113 extending through the dielectric layer 110. However, any suitable number of metal layers, conductive layers, and vias can be used.

[0011] After the substrate 101 has been provided or otherwise prepared, the first word lines 103 can be fabricated over the substrate 101 and in electrical connection with the first metallization via 113. In one embodiment, the first word lines 103 can be fabricated by first producing a first dielectric layer 105 over the substrate 101. The first dielectric layer 105 can be produced by a process such as CVD (chemical vapor deposition), PVD (physical vapor deposition), or PECVD (plasma-enhanced CVD), but other processes such as LPCVD (low-pressure chemical vapor deposition) can also be used. The first dielectric layer 105 can consist of dielectric materials such as doped or undoped silicon dioxide, silicon nitride, doped silicate glass, other high-k materials, combinations thereof, or the like.In one embodiment, the first dielectric layer 105 may comprise a material such as boron phosphosilicate glass (BPSG), but any suitable dielectrics may be used for each layer.

[0012] After its production, the first dielectric layer 105 can be planarized, for example, using a CMP process (CMP: chemical-mechanical polishing). However, another suitable planarization method can also be used to reduce the first dielectric layer 105 to the desired height and to create a flat profile for the first dielectric layer 105.

[0013] After the first dielectric layer 105 has been produced, the first word line 103 can be produced in the first dielectric layer 105. In one embodiment, the production of the first word line 103 can begin with the creation of openings in the first dielectric layer 105. In one embodiment, the openings can be created using a suitable photolithographic masking and etching process. However, any suitable method for creating the openings can be used.

[0014] After the openings in the first dielectric layer 105 have been created, a first adhesive layer can be produced (in the Fig. 1A and Fig. (1B not shown separately) can be started. In one embodiment, the first adhesive layer is used to assist adhesion of the remainder of the first word line 103 to the underlying structure, and it can be produced, for example, from titanium, titanium niride, tantalum, tantalum nitride, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, or the like, by a process such as CVD, PECVD, PVD, atomic layer deposition (ALD), or the like.

[0015] After the first adhesive layer has been produced, the first word line 103 can be deposited such that it fills a residual portion of the opening in the first dielectric layer 105. In one embodiment, the first word line 103 can be produced from a conductive material such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, alloys thereof, or the like, using a process such as CVD, PECVD, PVD, ALD, or the like. However, any suitable materials and manufacturing processes can be used.

[0016] After the material for the first word line 103 has been deposited such that it fills and / or overfills the opening in the first dielectric layer 105, excess material is removed from the first adhesive layer and the first word line 103 that is located outside a second dielectric layer 107. In one embodiment, the removal process can be a planarization process, such as a CMP process. However, any suitable planarization process can be used.

[0017] Although a specific embodiment has been described above to illustrate how the first word line 103 can be fabricated, this description is intended to be illustrative only and not limiting. Rather, any suitable fabrication method can be used. For example, in other embodiments, the material for the first word line 103 can first be deposited, and then structured, for example, by a photolithographic masking and etching process. After deposition and structuring, the material for the first dielectric layer 105 can then be deposited and planarized to facilitate the fabrication of the first word lines 103.

[0018] In one embodiment, the first word lines 103 can be manufactured such that they have a first thickness T1 of about 80 nm to about 180 nm and are spaced apart from each other by a first spacing S1 of about 40 nm to about 80 nm. Furthermore, the first word lines 103 can be manufactured such that they have a first width W1 of about 40 nm to about 80 nm. However, any suitable dimensions can be used.

[0019] After the first word line 103 has been fabricated, a second dielectric layer 107 is fabricated over the first word line 103, and first vias 109 are fabricated through the second dielectric layer 107. In one embodiment, the second dielectric layer 107 is fabricated using similar materials and methods as the first dielectric layer 105 described above. However, any suitable methods and materials can be used.

[0020] After the second dielectric layer 107 has been fabricated, the first vias 109 can be made through the second dielectric layer 107 to connect to the first word lines 103. In one embodiment, the first vias 109 can be fabricated using similar materials and methods as the first word line 103 discussed above. For example, openings can be created in the second dielectric layer 107, the openings can be filled with a conductive material such as copper, and then the conductive material can be planarized. However, any suitable materials and methods can be used.

[0021] The Fig. 2A and Fig. Figure 2B shows a deposition of a bitline material 201 for bitlines 301 (which are in the Fig. 2A and Fig. 2B are not shown individually, but are described below with reference to the Fig. 3A and Fig. 3B described) via and in electrical connection with the first vias 109. Fig. 2A shows a top-down view of Fig. 2B along line A - A', and Fig. 2B shows a sectional view of Fig. 2A along line B - B'. In one embodiment, the bit conductor material 201 can be a conductive material such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, an alloy thereof, or the like. The one or more conductive materials can be deposited by a suitable deposition method such as ALD or CVD, a suitable plating method such as electroplating or electroless plating, or the like. However, any suitable materials and deposition methods can be used.

[0022] After the bit-line material 201 has been deposited, a first hard mask 203 can be deposited over the bit-line material 201. In one embodiment, the first hard mask 203 can be a material such as silicon nitride, but any suitable mask material can be used, such as silicon oxide, silicon nitride oxide, SiCON, SiC, or SiOC. The first hard mask 203 can be produced by a deposition process such as CVD or PVD. However, any suitable process can be used.

[0023] The Fig. 3A and Fig. Figure 3B shows a structuring of the bit line material 201 to produce the bit lines 301. Fig. 3A shows a top-down view of Fig. 3B along line A - A', and Fig. 3B shows a sectional view of Fig. 3A along line B - B'. In one embodiment, after the first hard mask 203 has been deposited over the bit-line material 201, the first hard mask 203 can be structured, for example, by one or more photolithographic masking and etching processes. However, any suitable method for structuring the first hard mask 203 can be used.

[0024] After the first hard mask 203 has been structured, the structure of the first hard mask 203 can be transferred to the bit line material 201 to fabricate the bit lines 301. In one embodiment, the structure can be transferred by one or more etching processes in which the first hard mask 203 is used as a masking material. However, any suitable method can be used.

[0025] In some embodiments, the first hard mask 203 can be removed after the bit lines 301 have been fabricated (if it has not already been removed during the structuring of the bit lines 301). In some embodiments, the first hard mask 203 can be removed by a wet etching process, a dry etching process, a combination thereof, or the like. However, any suitable method can be used.

[0026] In one embodiment, the bit lines 301 can be manufactured such that they have a second thickness T2 of approximately 80 nm to approximately 180 nm and are spaced apart from each other by a second spacing S2 of approximately 40 nm to approximately 80 nm. Furthermore, the bit lines 301 can be manufactured such that they have a second width W2 of approximately 40 nm to approximately 80 nm. However, any suitable dimensions can be used.

[0027] Finally, by using word lines in different layers, a first spacing P1 between the first vias 109 can be larger than a second spacing P2 between the bit lines 301. In special embodiments, the first spacing P1 can be approximately twice as large as the second spacing P2, so that the first spacing P1 is about 160 nm to about 320 nm, while the second spacing P2 can be about 80 nm to about 160 nm. However, any suitable dimensions can be used.

[0028] The Fig. 4A and Fig. Figure 4B shows a deposition of an RRAM material 401 over the bit lines 301. Fig. 4A shows a top-down view of Fig. 4B, and Fig. 4B shows a sectional view of Fig. 4A along line B - B'. In one embodiment, the RRAM material 401 can be deposited as a conformal thin oxide layer. In some embodiments, the RRAM material 401 can be fabricated using one or more layers of dielectric materials suitable for storing digital values, such as hafnium oxide (Hf₂O₂), hafnium zirconium oxide (Hf₂O₃), or hafnium zirconia (Hf₂O₃). (1-x) Zr x O2), Zirconium oxide (ZrO2), Titanium oxide (TiO2), Nickel oxide (NiO), Tantalum oxides (TaO x Copper oxide (Cu₂O), niobium pentoxide (Nb₂O₅), aluminum oxide (Al₂O₃), combinations thereof, or the like. RRAM material 401 can be deposited using a suitable deposition process such as ALD, CVD, PVD, or the like. However, any suitable process and materials may be used.

[0029] The Fig. 5A and Fig. Figure 5B shows a structuring of the RRAM material 401 to produce non-contiguous RRAM spacers 501 on opposite sides of the bit lines 301. Fig. 5A shows a top-down view of Fig. 5B along line A - A', and Fig. 5B shows a sectional view of Fig. 5A along line B - B'. In one embodiment, the RRAM material 401 can be structured by an anisotropic etching process in which horizontal portions of the RRAM material 401 are removed, while vertical portions of the RRAM material 401 remain to form the RRAM spacers 501. The RRAM spacers 501 can be fabricated with a third thickness T3 of about 100 nm to about 180 nm and a first length L1 of about 3 nm to about 10 nm. However, any suitable method and thickness can be used to fabricate the RRAM spacers 501.

[0030] The Fig. 6A and Fig. Figure 6B shows the manufacture of selectors 601 adjacent to the RRAM spacers 501. Fig. Figure 6A shows a top-down view of Fig. 6B, and Fig. 6B shows a sectional view of Fig. 6A along line B - B'. In one embodiment, the selectors 601 can be fabricated as ovonic threshold layers (OTS layers) and can be made from a chalcogenide material comprising at least one chalcogen anion, e.g., selenium (Se), tellurium (Te), and the like, and an electropositive element, e.g., germanium (Ge), silicon (Si), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), zinc (Zn), nitrogen (N), boron (B), carbon (C), and the like. A suitable chalcogenide material is, among others, GeSb₂Te₅ (GST). The material for the selectors 601 is conformally deposited, for example, by PVD, CVD, ALD, or the like. However, any suitable materials and deposition methods can be used.

[0031] After the material for the selectors 601 has been deposited, it can be structured by one or more anisotropic etching processes (optionally together with suitable photolithographic masking and etching processes) that remove horizontal portions of the selector material 601 along with the second dielectric layer 107, while leaving non-contiguous vertical portions of the selector material 601 to form the selectors 601, and also leaving a horizontal portion of the selector material 601 along one top side of the bit lines 301 and the RRAM spacers 501. However, any suitable method for fabricating the selectors 601 can be used.

[0032] In one embodiment, the selectors 601 can be manufactured with a fourth thickness T4 of approximately 100 nm to approximately 180 nm. Furthermore, the selectors 601 can be manufactured such that they have a second length L2 adjacent to the RRAM spacers 501 of approximately 5 nm to approximately 30 nm and a third length L3 across the bit lines 301 of approximately 50 nm to approximately 120 nm. However, any suitable dimensions can be used.

[0033] The Fig. 7A and Fig. Figure 7B shows a separation of a functional word-lead material 701 around the selectors 601. Fig. Figure 7A shows a top-down view of Fig. 7B, and Fig. 7B shows a sectional view of Fig. 7A along line B - B'. In one embodiment, the functional word line material 701 can be made with similar materials and methods as the first word line 103 (described above with reference to the Fig. 1A and Fig. (as described in 1B) can be manufactured. The material for the first word line 103 can, for example, be tungsten deposited using a CVD process. However, any suitable methods and materials can be used.

[0034] After the functional word-line material 701 has been deposited, it can be planarized using the selectors 601. In one embodiment, the functional word-line material 701 can be planarized using a CMP process. However, other suitable methods, such as a grinding process or a series of etching processes, can also be used.

[0035] The Fig. 8A and Fig. Figure 8B shows that after the separation of the functional word line material 701 to fill areas between the bit lines 301, the functional word line material 701 can be structured into functional word lines 801 between the bit lines 301. Fig. Figure 8A shows a top-down view of Fig. 8B, and Fig. 8B shows a sectional view of Fig. 8A along line B - B'. In one embodiment, the functional word-conducting material 701 can be structured using a photolithographic masking and etching process. However, any suitable method can be used.

[0036] In one embodiment, the functional word lines 801 can be manufactured such that they have a third width W3 that is larger than the first width W1 of the first word lines 103. In one embodiment, the third width W3 can be approximately 40 nm to approximately 80 nm. Furthermore, a first part of the functional word lines 801 can extend between different sections of the selectors 601 with a first spacing D of approximately 40 nm to approximately 80 nm, while a second part can extend beyond the first word lines 103 with a second spacing D2 of approximately 5 nm to approximately 10 nm. However, any suitable dimensions can be used.

[0037] After the functional word lines 801 have been spaced apart, only some of the functional word lines 801 are electrically connected to the first word lines 103 among the functional word lines 801. For example, in the Fig. In the embodiment shown in Figure 8B, two of the three functional word lines 801 are in physical contact with the first vias 109, which electrically connect the functional word lines 801 to the first word lines 103. The remaining functional word line 801 (located between the two bit lines 301, which are in Fig. (as shown in Figure 8B) is not electrically connected to the first word lines 103 (or to any other word lines) at this point in the manufacturing process. Therefore, a separate connection can be made to the functional word line 801, which is located between the two bit lines 301, as will be explained later.

[0038] After the functional word lines 801 have been created and structured, combinations of the selectors 601 and the RRAM spacer 501 form several memory cells (which are located in the Fig. 8A and Fig. 8B (represented by dashed circles labeled 800) on opposite sides of the bit lines 301. Furthermore, at this stage of the manufacturing process, only one of the memory cells 800, which is adjacent to one of the bit lines 301, is controlled by the first word line 103.

[0039] The Fig. 9A and Fig. Figure 9B shows that after structuring the functional word lines 801, a third dielectric layer 901 can be deposited to separate and isolate the functional word lines 801 from each other. Fig. Figure 9A shows a top-down view of Fig. 9B, and Fig. 9B shows a sectional view of Fig. 9A along line B - B'. In one embodiment, the third dielectric layer 901 can be deposited using similar materials and methods as the first dielectric layer 105, described above with reference to the Fig. 1A and Fig. 1B has been described. However, any suitable materials and methods can be used to produce the third dielectric layer 901.

[0040] After the material for the third dielectric layer 901 has been deposited, it can be planarized with the bit lines 301. In one embodiment, the third dielectric layer 901 can be planarized using a CMP process. However, other suitable methods, such as a grinding process or a series of etching processes, can also be used.

[0041] The Fig. 10A and Fig. Figure 10B shows that after planarizing the third dielectric layer 901, a fourth dielectric layer 1001 can be deposited over the bit lines 301. Fig. Figure 10A shows a top-down view of Fig. 10B along line A - A', and Fig. 10B shows a sectional view of Fig. 10A along line B - B'. In one embodiment, the fourth dielectric layer 1001 can be deposited using similar materials and methods as the first dielectric layer 105, described above with reference to the Fig. 1A and Fig. 1B has been described. However, all suitable materials and methods may be used.

[0042] The Fig. 10A and Fig. Figure 10B also shows a structuring of the fourth dielectric layer 1001 to create a second opening 1003 in order to be connected to a second via 1103 (which are in the Fig. 10A and Fig. 10B are not shown, but are shown later in the Fig. 11A and Fig. (as shown in Figure 11B and described with reference to it). In one embodiment, the fourth dielectric layer 1001 can be structured, for example, using a photolithographic masking and etching process. However, any suitable method can be used.

[0043] The Fig. 11A and Fig. Figure 11B shows the deposition of a word-conductor material 1101 in the second opening 1003 and above the fourth dielectric layer 1001 to create the second vias 1103 (which are shown as separate from the rest of the word-conductor material 1101, but there may or may not be a physical separation) and to create second word-conductors 1201 (which are located in the Fig. 11A and Fig. 11B are not shown, but are shown later in the Fig. 12A and Fig. 12B are shown and described with reference to them) to begin. Fig. Figure 11A shows a top-down view of Fig. 11B, and Fig. 11B shows a sectional view of Fig. 11A along line B - B'. In one embodiment, the word line material 1101 can be deposited using similar materials and methods as the first word line 103, which is described above with reference to the Fig. 1A and Fig. As described in section 1B. For example, the word conductor material can be tungsten 1101 deposited using a CVD process. However, any suitable materials and methods can be used.

[0044] After the word conductor material 1101 has been deposited, it can be planarized to prepare it for further processing. In one embodiment, the word conductor material 1101 can be planarized using a CMP process. However, other suitable methods, such as a grinding process or a series of etching processes, can also be used.

[0045] Furthermore, several of the second vias 1103 are produced simultaneously (which is in the Fig. 11A and Fig. (11B is not explicitly shown), so that each of the functional word lines 801 is electrically connected to a different word line than the adjacent functional word lines. In this embodiment, the second vias 1103 can also be separated from each other by the first spacing P1. However, any suitable spacing can be used.

[0046] The Fig. 12A and Fig. Figure 12B shows that the word line material 1101 can be structured after its planarization to produce several of the second word lines 1201. Fig. Figure 12A shows a top-down view of Fig. 12B, and Fig. 12B shows a sectional view of Fig. 12A along line B - B'. In one embodiment, the word-conducting material 1101 can be structured using a photolithographic masking and etching process. However, any suitable method can be used.

[0047] In one embodiment, the second word lines 1201 can be manufactured such that they have a fourth width W4 that is larger than the third width W3 of the functional word lines 801. In one embodiment, the fourth width W4 can be approximately 40 nm to approximately 80 nm. Furthermore, the second word lines 1201 can be spaced apart from each other by a third spacing S3 of approximately 40 nm to approximately 80 nm. However, any suitable dimensions can be used.

[0048] After their fabrication, the second word lines 1201 are electrically connected to different portions of the functional word lines 801 that are not otherwise connected (e.g., not connected to the first word lines 103), and they thus control memory cells 800 on the side of the bit lines 301 that are opposite those controlled by the first word lines 103. Specifically, the second word lines 1201 are physically connected to the second vias 1103, which electrically connect the second word lines 1201 to those portions of the functional word lines 801 that are located between the bit lines 301. Therefore, each of the functional word lines 801 is connected to either the first word lines 103 or the second word lines 1201, with the different word lines located on opposite sides of the functional word lines 801.

[0049] The Fig. 13A and Fig. Figure 13B shows a deposition of a fifth dielectric layer 1301 for separating and insulating the second word lines 1201 from each other and for producing an embodiment of a double-sided word line structure 1300. Fig. Figure 13A shows a top-down view of Fig. 13B, and Fig. 13B shows a sectional view of Fig. 13A along line B - B'. In one embodiment, the fifth dielectric layer 1301 can be deposited using similar materials and methods as the first dielectric layer 105, described above with reference to the Fig. 1A and Fig. 1B has been described. However, all suitable deposition methods and materials can be used.

[0050] After the material for the fifth dielectric layer 1301 has been deposited, the fifth dielectric layer 1301 can be planarized to prepare it for further processing. In one embodiment, the fifth dielectric layer 1301 can be planarized using a CMP process. However, other suitable methods, such as a grinding process or a series of etching processes, can also be used.

[0051] Fig. Figure 13C shows an enlarged top-down view that aids in explaining the entire cell layout of the 800 memory cells together with their word lines, with other structures removed from this figure for clarity. As shown, 800 memory cells are arranged on both sides of the 301 bit lines, with the 800 memory cells on one side being electrically connected to the first word lines 103 via the first vias 109, and the 800 memory cells on the other side of the 301 being electrically connected to the second word lines 1201 via the second vias 1103.

[0052] Fig. Figure 14 shows that after the deposition and planarization of the fifth dielectric layer 1301, second metallization layers 1401 can be produced over the second word lines 1201 to electrically connect the second word lines 1201 to other functional circuits. In one embodiment, the second metallization layers 1401 can be produced in a similar manner and with similar materials as the first metallization layers 102 (described above with reference to the Fig. 1A and Fig. (as described in 1B). In a particular embodiment, the second metallization layers 1401 can comprise a dielectric layer 1407 with a second metallization via 1403 and a fifth metal conductor 1405 connected to the second metallization via 1403. However, any suitable or desired number of dielectric layers, metallization vias, and metal conductors can be used.

[0053] By fabricating the embodiments as described above, separate word lines (e.g., the first word lines 103 and the second word lines 1201) are produced as two separate layers above and below the functional word lines 801. Therefore, one word line (e.g., the first word line 103) can control the memory cells 800, which are arranged on one side of the bit lines 301, via a lower via connection, and a second word line (e.g., the second word line 1201) can control the memory cells 800, which are arranged on the other side of the bit lines 301, via an upper via connection. Thus, by arranging word lines in different layers, the number of cells in areas of the same size can be doubled without area disadvantage and without the use of dummy cells.

[0054] Fig. Figure 15 shows a further embodiment in which the double-sided word line structure 1300 is integrated into the metallization layers of a larger semiconductor device 1500. In this embodiment, the semiconductor device 1500 has a memory area 1501 and a logic area 1503 above the substrate 101. In the memory area 1501, the double-sided word line structure 1300 is fabricated between the first metallization layers 102 and the second metallization layers 1401 (e.g., between the fourth metal line 111 and the fifth metal line 1405). In one embodiment, the double-sided word line structure 1300 can be fabricated as described with reference to the Fig. has been explained in sections 1A to 14.

[0055] However, in logic region 1503, the semiconductor device 1500 contains active devices and other logic devices. Therefore, no memory structure, such as the double-sided word line structure 1300, is located in logic region 1503. Instead, these regions, which are located in logic region 1503 and on the same level as the double-sided word line structure 1300, are filled with one or more dielectric materials, such as dielectric layer 110, second dielectric layer 107, fourth dielectric layer 1001, dielectric layer 1407, and other dielectric materials. For clarity, these various dielectric layers are not shown as individual layers in logic region 1503, but rather as a single, generic layer.

[0056] Fig. Figure 15 also shows the fabrication of a third metallization via 1505 through one or more dielectric materials to connect the fourth metal conductor 111 and the fifth metal conductor 1405 in the logic area 1503. In one embodiment, the third metallization via 1505 can be fabricated using similar materials and methods to those described above for the second metallization via 1403. In more specialized embodiments, the third metallization via 1505 can be fabricated simultaneously with the second metallization via 1403, while in other embodiments, the third metallization via 1505 can be fabricated either before or after the second metallization via 1403.In these embodiments, the third metallization via 1505 can be produced using suitable lithographic masking and etching techniques, employing one or more anisotropic etching processes to create an opening through the dielectric materials to the fourth metal conductor 111. After creating the opening, it can be filled and / or overfilled with one or more conductive materials, which are then planarized. However, any suitable method can be used.

[0057] Integrating the double-sided word line structure 1300 into the metallization layers results in a more robust device. In particular, integrating the double-sided word line structure 1300 into the memory area 1501 of the semiconductor device 1500 and using multiple vertically overlapping word lines increases the routing flexibility, allowing the different word lines to be connected to different logic metal layers.

[0058] The Fig. 16A and Fig. Figure 16B shows another embodiment in which the double-sided word line structure 1300 can be produced. Fig. Figure 16A shows a top-down view of Fig. 16B, and Fig. 16B shows a sectional view of Fig. 16A along line B - B'. In this embodiment, the first hard mask 203, which is used to structure the bit lines 301, is not removed after the structuring of the bit lines 301 (as described above with reference to the Fig. 3A and Fig. 3B), but it will be left in place during subsequent processing. As the Fig. 16A and Fig. As can be seen from 16B, the first hard mask 203 continues to cover the top of the bit lines 301.

[0059] In this embodiment, after the bit lines 301 have been manufactured, the first hard mask 203 can be produced such that it has a fifth thickness T5 of approximately 5 nm to approximately 30 nm. Furthermore, the bit lines 301 can be produced such that they have a second width W2. However, any suitable dimensions can be used.

[0060] The Fig. 17A and Fig. Figure 17B shows that if the first hard mask 203 is still over the bit lines 301, the manufacturing process can continue in the manner set out above. Fig. Figure 17A shows a top-down view of Fig. 17B, ​​and Fig. 17B shows a sectional view of Fig. 17A along line B - B'. In a special embodiment, the RRAM spacers 501 are deposited and structured as described above with reference to the Fig. 5A and Fig. 5B has been set out; the selectors 601 are separated and structured as described above with reference to the Fig. 6A and Fig. 6B has been set out; and the functional word lines 801 are separated and structured as described above with reference to the Fig. 8A and Fig. as described in Section 8B. In these embodiments, however, the RRAM spacers 501, the selectors 601, and the functional word lines 801 can each have a sixth thickness T6, which is equal to the combined thickness of the bit lines 301 and the first hard mask 203 and is approximately 110 nm to approximately 200 nm. However, any suitable dimensions can be used.

[0061] The Fig. 18A and Fig. Figure 18B shows a continuation of the manufacturing process, with the first hard mask 203 remaining in place over the bit lines 301. Fig. Figure 18A shows a top-down view of Fig. 18B, and Fig. 18B shows a sectional view of Fig. 18A along line B - B'. In a special embodiment, the fourth dielectric layer 1001 is deposited and structured as described above with reference to the Fig. 10A and Fig. 10B has been set out; the second vias 1103 are produced as described above with reference to the Fig. 11A and Fig. 11B has been set out; and the second word lines 1201 are constructed as above with reference to the Fig. 12A and Fig. 12B has been explained. If necessary, after the production of the second word lines 1201, the second metallization layers 1401 (in the Fig. 18A and Fig. 18B not shown) shall be manufactured as described above with reference to Fig. As outlined in section 14. Of course, any other suitable procedures or steps may also be used.

[0062] As these figures show, during subsequent fabrication processes, where the first hard mask 203 remains in place, the fourth dielectric layer 1001 is deposited directly onto and in physical contact with the first hard mask 203. Therefore, the first hard mask 203 can help to increase the yield window and prevent leakage during subsequent fabrication processes, such as the fabrication of the second vias 1103. The first hard mask 203 also remains in place to continue electrically insulating the bit lines 301 even after the first hard mask 203 has been fabricated to create the bit lines 301. These measures contribute to improving the overall yield of the fabrication process by reducing defects and improving the operation of the fabricated structures.

[0063] The Fig. Figures 19 to 21 show a further embodiment in which an L-shaped RRAM structure (instead of the rod-shaped structure described above with reference to the Fig. (described in sections 1A to 18). In this embodiment, the first steps of the manufacturing process are similar to the steps described above with reference to the Fig. 1A to 4B have been described. In particular, the first word line 103 is produced, the bit lines 301 are produced above the first word line 103, and the RRAM material 401 is deposited above the bit lines 301.

[0064] In this embodiment, however, the RRAM material 401 is not structured into a rod shape as described above with reference to the Fig. 5A and Fig. 5B has been explained. Instead, the RRAM material 401 is not structured, and a selector material 1901 is deposited over the RRAM material 401, as shown in Fig. Figure 19 shows that in one embodiment, the selector material 1901 is deposited as described above with reference to the Fig. 6A and Fig. As outlined in section 6B, it is, for example, compliantly deposited over RRAM material 401. Any suitable methods and materials can be used.

[0065] Fig. Figure 20 shows that after depositing the selector material 1901 over the unstructured RRAM material 401, the selector material 1901 and the RRAM material 401 can be structured together. In one embodiment, the selector material 1901 and the RRAM material 401 can be structured by one or more anisotropic etchings (e.g., reactive ion etchings) to remove horizontal portions of the selector material 1901 and the RRAM material 401 in order to produce the RRAM spacers 501 and the selectors 601.

[0066] Because the structuring of the RRAM material 401 is delayed until the selector material 1901 has been deposited, a portion of the selector material 1901 remains in place to protect a horizontal part of the RRAM material 401 adjacent to the bit lines 301. Therefore, the selector material 1901 has a rod shape, separated from the second dielectric layer 107 by the RRAM spacers 501, while the RRAM spacers 501 assume an L-shape, with a portion of the RRAM spacers 501 extending along the second dielectric layer 107.

[0067] After fabrication, the selectors 601 can have a seventh length L7 of approximately 5 nm to approximately 30 nm. Since the selectors 601 protect the underlying portion of the RRAM material 401, the RRAM spacers 501 extend along the second dielectric layer 107 at a distance equal to the seventh length L7. However, any suitable dimensions can be used.

[0068] Fig. Figure 21 shows that after manufacturing the RRAM spacers 501 (with the L-shaped structure) and the selectors 601, the further processing can be carried out as described above with reference to the Fig. as described in sections 7A to 14. For example, in some embodiments the functional word lines 801 are produced, the fourth dielectric layer 1001 is deposited, and the second word lines 1201 are produced. However, any suitable methods and structures may be used.

[0069] Fig. Figure 22 shows a further embodiment in which the RRAM spacers 501 with the L-shaped structure are used. In this embodiment, however, the first hard mask 203 remains in place over the bit lines 301. In particular, the bit lines 301 and the first hard mask 203 are manufactured as described above with reference to the Fig. 16A and Fig. 16B has been set out, whereby the first hard mask 203 remains in place over the bit lines 301.

[0070] After the bit lines 301 have been fabricated, the RRAM material 401 is deposited over the bit lines 301 and the first hard mask 203. Similarly, the selector material 1901 is deposited over the RRAM material 401 without intermediate structuring of the RRAM material 401. After the deposition of the RRAM material 401 and the selector material 1901, the two materials are jointly structured as described above with reference to Fig. 20 has been explained. Therefore, the RRAM spacer 501 has an L-shape, and the structure also allows the existing first hard mask 203 to remain.

[0071] By manufacturing the embodiments in the manner described above (e.g., by using separate word lines on opposite sides of the memory cells), the physical limitations of the word lines can be eliminated, and the number of cells in a given area can be doubled. In particular, by manufacturing the first word lines 103 and the second word lines 1201 as two separate layers above and below the functional word lines 801, limitations that normally exist on adjacent word lines can be eliminated. Therefore, one word line (e.g., the first word line 103) can control one side of the cells via a lower via connection, and a second word line (e.g., the second word line 1201) can control the other side of the cells via an upper via connection.

[0072] According to one embodiment, a method for fabricating a semiconductor device comprises the following steps: fabricating a first word line over a substrate; fabricating a bit line over the first word line; after fabricating the first word line, fabricating a first memory cell and a second memory cell on opposite sides of the bit line; depositing a second word line adjacent to the first memory cell and in electrical connection with the first word line; depositing a third functional word line adjacent to the second memory cell; and after depositing the third functional word line, fabricating a fourth word line in electrical connection with the third functional word line.In one embodiment, fabricating the first memory cell further comprises: depositing an RRAM material; structuring the RRAM material; depositing a selector material after structuring the RRAM material; and structuring the selector material. In another embodiment, fabricating the first memory cell further comprises: depositing an RRAM material; depositing a selector material before structuring the RRAM material; structuring the selector material; and structuring the RRAM material. In another embodiment, fabricating the bit line comprises: depositing a bit line material; depositing and structuring a hard mask; structuring the bit line material to fabricate the bit line; and removing the hard mask.In one embodiment, the fabrication of the bit line comprises the following: depositing a bit line material; depositing and structuring a hard mask; and structuring the bit line material to fabricate the bit line, wherein the fabrication of the first memory cell with the hard mask is performed in place. In one embodiment, the first memory cell is fabricated in a memory area adjacent to a logic area. In another embodiment, the fabrication of the first word line over the substrate involves fabricating the first word line over initial metallization layers.

[0073] In a further embodiment, a method for fabricating a semiconductor device comprises the following steps: fabricating a lower word line over a substrate; fabricating a first bit line over the lower word line; depositing an RRAM material adjacent to the first bit line; depositing a selector material adjacent to the RRAM material; fabricating a first word line on a first side of the first bit line, the first word line being electrically connected to the lower word line; fabricating a second word line on a second side of the first bit line opposite the first side; and fabricating an upper word line over and in electrical connection with the second word line. In one embodiment, the method further comprises structuring the RRAM material into a rod shape. In another embodiment, the method further comprises structuring the RRAM material into an L-shape.In one embodiment, the method further comprises structuring the selector material into a rod shape. In one embodiment, fabricating the first bit line comprises: depositing a first material; depositing and structuring a hard mask; structuring the first material using the hard mask as a mask; and removing the hard mask. In one embodiment, fabricating the first bit line comprises: depositing a first material; depositing and structuring a hard mask; and structuring the first material using the hard mask as a mask, wherein, during the deposition of the RRAM material, the RRAM material is deposited adjacent to the hard mask. In one embodiment, the method further comprises structuring the RRAM material into an L-shape.

[0074] In a further embodiment, a semiconductor device comprises the following: a bit line arranged on a dielectric layer; a first memory cell arranged on a first side wall of the bit line; a second memory cell arranged on a second side wall of the bit line opposite the first side wall; a first word line arranged on the dielectric layer, wherein the first memory cell is located between the first side wall of the bit line and a side wall of the first word line; a second word line arranged on the dielectric layer, wherein the second memory cell is located between the second side wall of the bit line and a side wall of the second word line; an upper word line arranged above the bit line and electrically connected to the first word line;and a lower word line arranged below the bit line and electrically connected to the second word line. In one embodiment, the first memory cell comprises a rod-shaped RRAM material. In another embodiment, the first memory cell comprises an L-shaped RRAM material. In another embodiment, the semiconductor device further comprises a first hard mask in physical contact with the bit line, wherein the first hard mask and the bit line have oriented side walls. In another embodiment, the first memory cell comprises an L-shaped RRAM material. In another embodiment, the first memory cell is arranged in a memory area adjacent to a logic area.

Claims

[1] Method for manufacturing a semiconductor device (1500) comprising the following steps: Establishing an initial word line (103) over a substrate (101); Establishing a bit line (301) over the first word line (103); After establishing the first word line (103), establish a first memory cell (800) and a second memory cell (800) on opposite sides of the bit line (301); Deposition of a second word line adjacent to the first memory cell (800) and in electrical connection with the first word line (103); Separation of a third word line adjacent to the second memory cell (800); and After the separation of the third word line, a fourth word line (1201) is produced over and in electrical connection with the third word line. [2] The method of claim 1, wherein the production of the first memory cell (800) further comprises: Deposition of an RRAM material (401); Structuring the RRAM material (401); after structuring the RRAM material (401) depositing a selector material (1901); and Structuring the selector material (1901). [3] The method of claim 1, wherein the production of the first memory cell (800) further comprises: Deposition of an RRAM material (401); prior to structuring the RRAM material (401) depositing a selector material (1901); Structuring the selector material (1901); and Structuring the RRAM material (401). [4] Method according to any of the preceding claims, wherein the production of the bit line comprises: Deposition of a bit line material (201); Deposition and structuring of a hard mask (203); Structuring the bitline material (201) to create the bitline (301); and Removal of the hard mask (203). [5] Method according to any one of claims 1 to 3, wherein the production of the bit line comprises: Deposition of a bit line material (201); Deposition and structuring of a hard mask (203); and Structuring the bit line material (201) to create the bit line (301), whereby the creation of the first memory cell (800) with the hard mask (203) is carried out in place. [6] Method according to one of the preceding claims, wherein the first memory cell (800) is manufactured in a memory area (1501) adjacent to a logic area (1503). [7] Method according to one of the preceding claims, wherein in the production of the first word line (103) over the substrate (101) the first word line (103) is produced over first metallization layers. [8] Method for manufacturing a semiconductor device (1500) comprising the following steps: Establishing a lower word lead (103) over a substrate (101); Establishing a first bit line (301) over the lower word line (103); Deposition of an RRAM material (401) adjacent to the first bit line (301); Deposition of a selector material (1901) adjacent to the RRAM material (401); Establishing a first word line on a first side of the first bit line (301), wherein the first word line (103) is electrically connected to the lower word line; Establishing a second word line on a second side of the first bit line (301) opposite the first side of the first bit line; and Establishing an upper word line (1201) over and in electrical connection with the second word line. [9] Method according to claim 8, further comprising structuring the RRAM material (401) into a rod shape. [10] Method according to claim 8, further comprising structuring the RRAM material (401) into an L-shape. [11] Method according to any one of claims 8 to 10, further comprising structuring the selector material (1901) into a rod shape. [12] Method according to any one of claims 8 to 11, wherein the production of the first bit line (301) comprises: Separation of a first material (201); Deposition and structuring of a hard mask (203); Structuring the first material (201) using the hard mask (203) as a mask; and Removal of the hard mask (203). [13] Method according to any one of claims 8 to 11, wherein the production of the first bit line (301) comprises: Separation of a first material (201); Deposition and structuring of a hard mask (203); and Structuring the first material (201) using the hard mask (203) as a mask, wherein when depositing the RRAM material (401) the RRAM material (401) is deposited adjacent to the hard mask (203). [14] Method according to claim 13, further comprising structuring the RRAM material (401) into an L-shape. [15] Semiconductor device (1500) comprising: a bit line (301) that is on a dielectric layer (101, 105, 110) is arranged; a first memory cell (800) which is arranged on a first side wall of the bit line (301); a second memory cell (800) which is located on a second side wall of the bit line (301) opposite the first side wall; a first word line arranged on the dielectric layer (101, 105, 110), wherein the first memory cell (800) is arranged between the first side wall of the bit line (301) and a side wall of the first word line (103); a second word line arranged on the dielectric layer (101, 105, 110), wherein the second memory cell (800) is arranged between the second side wall of the bit line (301) and a side wall of the second word line; an upper word line (1201) arranged above the bit line (301) and electrically connected to the first word line; and a lower word line (103) which is located below the bit line (301) and is electrically connected to the second word line. [16] Semiconductor device (1500) according to claim 15, wherein the first memory cell (800) comprises a rod-shaped RRAM material. [17] Semiconductor device (1500) according to claim 15, wherein the first memory cell (800) comprises an L-shaped RRAM material. [18] Semiconductor device (1500) according to one of claims 15 to 17, further comprising a first hard mask (203) in physical contact with the bit line (301), wherein the first hard mask (203) and the bit line (301) have rectified side walls. [19] Semiconductor device (1500) according to any one of claims 15 to 18, wherein the first memory cell (800) has an L-shaped RRAM material. [20] Semiconductor device (1500) according to one of claims 15 to 19, wherein the first memory cell (800) is arranged in a memory area (1501) adjacent to a logic area (1503).

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