semiconductor device

Abstract

Semiconductor device comprising: a substrate (100) comprising an element isolation layer (105), the element isolation layer (105) defining an active region; a plurality of word lines (WL) crossing the active region in a first direction; and a plurality of bit line structures (140ST) on the substrate (100) connected to the active region, the plurality of bit line structures (140ST) extending in a second direction different from the first direction, wherein each of the plurality of bit line structures (140ST): a ruthenium wiring comprising a lower surface (143bs) and an upper surface (143us) opposite the lower surface (143bs), a lower graphene layer (148) which is in contact with the lower surface (143bs) of the ruthenium wiring (143) and which extends along the lower surface (143bs) of the ruthenium wiring, and a wiring line cover layer (144) extending along the upper surface (143us) of the ruthenium line wiring, wherein at least one of the plurality of bit line structures (140ST) further comprises a sidewall graphene layer (147) extending along a sidewall of the ruthenium wiring.

Description

BACKGROUND

[0001] Some exemplary embodiments relate to a semiconductor device, and more particularly to a semiconductor device that uses a capacitor as a data storage element.

[0002] With the increasing integration of semiconductor devices, individual circuit structures have been increasingly miniaturized to accommodate more semiconductor devices within the same area. For example, as the integration density of a semiconductor device increases, the design rule for semiconductor device components decreases.

[0003] As a critical dimension (CD) of an electrode becomes smaller and smaller, many studies are being conducted on a new integration density technique for a highly scaled semiconductor device.

[0004] US 2018 / 0 166 450 A1 discloses a method for manufacturing a semiconductor device. A cell region and a core region are defined in a substrate. A bit line structure disposed in the cell region is provided. A gate structure disposed in the core region is provided, and a core capping film disposed on the gate structure is provided. The height of the core capping layer is greater than the height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched using an etching process until the height of the first contact film is less than the height of the bit line structure.In the etching process, the etching rate for the first contact foil is greater than the etching rates for the bit line structure and the core cover foil.

[0005] Further state-of-the-art information can be found in the scientific publication ACHRA, S. [et al.]: Graphene-Ruthenium hybrid interconnects. In: International Interconnect Technology Conference 2019, Session 4, 2019, Paper 4.20, pp. 1-3. SUMMARY

[0006] It is an object of the present invention to solve the problems explained above.

[0007] This object is achieved by the subject matter of claims 1, 8 and 14. Advantageous further developments can be found in the respective subclaims.

[0008] According to some exemplary embodiments disclosing partial aspects of the present invention, a semiconductor device is provided comprising a substrate comprising an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction.Each of the plurality of bit line structures includes a ruthenium wiring having a bottom surface and an upper surface opposite the bottom surface, a bottom graphene layer in contact with the bottom surface of the ruthenium wiring and extending along the bottom surface of the ruthenium wiring, and a wiring line cap layer extending along the top surface of the ruthenium wiring.

[0009] According to some exemplary embodiments disclosing partial aspects of the present invention, a semiconductor device is provided comprising a substrate comprising an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures extending in a second direction different from the first direction on the substrate and connected to the active region.Each of the plurality of bit line structures includes a ruthenium wiring having a lower surface and an upper surface opposite the lower surface, an upper graphene layer in contact with the upper surface of the ruthenium wiring and extending along the upper surface of the ruthenium wiring, and a wiring line cap layer on the upper graphene layer extending along the upper graphene layer.

[0010] According to some exemplary embodiments disclosing partial aspects of the present invention, a semiconductor device is provided comprising a substrate comprising an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction.Each of the plurality of bit line structures includes a ruthenium wiring having a lower surface and an upper surface opposite the lower surface, a lower graphene layer contacting the lower surface of the ruthenium wiring and extending along the lower surface of the ruthenium wiring, an upper graphene layer contacting the upper surface of the ruthenium wiring and extending along the upper surface of the ruthenium wiring, and a wiring line cap layer on the upper graphene layer and extending along the upper graphene layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the inventive concepts will be better understood by considering some exemplary embodiments of these concepts with reference to the accompanying drawings, in which: Fig. 1 is a schematic layout diagram illustrating a semiconductor device according to some example embodiments; Fig. 2 is a cross-sectional view taken along line AA of Fig. 1 was carried out; Fig. 3 is a cross-sectional view taken along line BB of Fig. 1 was carried out; Fig. 4 is a schematic illustrating a semiconductor device according to some example embodiments; Fig. 5 is a schematic illustrating a semiconductor device according to some example embodiments; Fig. 6 is a schematic illustrating a semiconductor device according to some example embodiments; Fig. 7 and Fig. 8 schematics illustrating a semiconductor device according to some example embodiments; Fig. 9 is a schematic diagram illustrating a semiconductor device according to some example embodiments; Fig. 10 is a schematic diagram illustrating a semiconductor device according to some example embodiments; Fig. 11 is a schematic diagram illustrating a semiconductor device according to some example embodiments; Fig. 12 and Fig. 13 schematics illustrating a semiconductor device according to some example embodiments; Fig. 14 is a schematic illustrating a semiconductor device according to some example embodiments; Fig. 15 an enlarged view of section P from Fig. 14; Fig. 16 is a schematic diagram illustrating a semiconductor device according to some example embodiments; Fig. 17 an enlarged view of section P from Fig. 16; Fig. 18 is a schematic diagram illustrating a semiconductor device according to some example embodiments; Fig. 19 an enlarged view of section P from Fig. 18; Fig. 20 is a schematic diagram illustrating a semiconductor device according to some example embodiments; Fig. 21 and Fig. 22 schematics illustrating a semiconductor device according to some example embodiments; and Fig. 23 to 27 are views illustrating the intermediate steps of a manufacturing method for a semiconductor device according to some example embodiments. DETAILED DESCRIPTION OF SOME EXEMPLARY EMBODIMENTS

[0012] Fig. 1 is a schematic layout diagram illustrating a semiconductor device according to some example embodiments. Fig. 2 is a cross-sectional view taken along line AA of Fig. 1 was made. Fig. 3 is a cross-sectional view taken along line BB of Fig. 1 was made.

[0013] Although Fig. 1 illustrates an exemplary layout scheme of a dynamic random access memory (DRAM) except for a capacitor 190, inventive concepts are not limited thereto.

[0014] Referring to Fig. 1, a semiconductor device according to some exemplary embodiments may include a plurality of active regions ACT. The active region ACT may be defined by an element isolation layer 105 (see Fig. 1) formed in a substrate 100 (see Fig. 2).

[0015] As the design rule of the semiconductor device is reduced, as shown, the active region AR can be arranged in a diagonal or oblique bar shape. The active region ACT can have a bar shape extending in a third direction D3. A plurality of active regions ACT can extend collinearly along the third direction D3.

[0016] On the active regions ACT, a plurality of gate electrodes may be arranged in a first direction D1 across the active regions ACT. The plurality of gate electrodes may extend parallel to one another. The plurality of gate electrodes may, for example, be or correspond to a plurality of word lines WL.

[0017] The word lines WL can be arranged at equal intervals. The width of the word line WL, the spacing between adjacent word lines WL, and / or the interval between the word lines WL (e.g., the gap between the word lines WL) can be determined according to the design rule.

[0018] A plurality of bit lines BL may be located on the word lines WL, extending in a second direction D2 perpendicular to the word lines WL. The plurality of bit lines BL may extend in the second direction D2 across the active regions ACT. The second direction D2 may be at a right angle to the first direction D1; however, example embodiments are not limited thereto. Furthermore, the third direction D3 may be at an angle other than a right angle to the first direction D1, for example, at an angle of 45 degrees and / or 70 degrees; however, example embodiments are not limited thereto. The bit lines BL may also be referred to as digit lines.

[0019] The plurality of bit lines BL may extend parallel to each other. The bit lines BL may be arranged at equal intervals. The width of the bit line BL, the spacing between adjacent bit lines BL, and / or the interval between the bit lines BL (e.g., the gap) may be determined according to the design rule.

[0020] The semiconductor device according to some example embodiments may include various contact arrangements formed on the active regions ACT. Various contact arrangements may include, for example, digit line contacts (DC), buried contacts (BC), landing pads (LP), and / or the like.

[0021] Here, the digit line contact DC may refer to a contact that electrically connects the active region ACT to the bit line BL. The buried contact BC may refer to a contact that electrically connects the active region ACT to a lower electrode 191 (see Fig. 2) of the capacitor 190, e.g. directly connects (see Fig. 2).

[0022] In the arrangement structure, the contact area between the buried contact BC and the active region ACT may be small. Accordingly, in order to increase the contact area with the active region ACT and to reduce the contact area with the lower electrode 191 (see Fig. 2), a conductive landing pad LP can be introduced. This increase in contact area can lead to a reduction in resistance between the buried contact BC and the active region ACT.

[0023] The landing pad LP may be arranged between the active region ACT and the buried contact BC or may be arranged between the buried contact BC and the lower electrode 191 (see Fig. 2) of the capacitor 190. In the semiconductor device according to some exemplary embodiments of inventive concepts, the landing pad LP may be arranged between the buried contact BC and the lower electrode 191 (see Fig. 2) of the capacitor. By expanding the contact area by introducing the second landing pad LP, the contact resistance between the active region ACT and the lower electrode 191 (see Fig. 2) of the capacitor. The speed of the semiconductor device can be increased by reducing the contact resistance.

[0024] In the semiconductor device according to some exemplary embodiments, the digit line contact DC may be arranged in a central portion of the active region ACT. The buried contacts BC may be arranged at both ends of the active region ACT.

[0025] Since the buried contacts BC are arranged at both ends of the active region ACT, the landing pads LP can be arranged adjacent to both ends of the active region ACT so that they partially overlap the buried contacts BC.

[0026] For example, the buried contacts BC may be formed such that they are connected to the element isolation layer 105 (see Fig. 2) and the active regions ACT between the adjacent word lines WL and between the adjacent bit lines BL overlap.

[0027] The word lines WL may be formed such that they are buried in the substrate 100. The word lines WL may be arranged above the active regions ACT between the digit line contacts DC or the buried contacts BC.

[0028] As shown, two word lines WL may be arranged to cross an active region ACT. Since the active region ACT is arranged in an oblique shape, the word line WL may have an angle of less than 90 degrees with respect to the active region ACT.

[0029] The digit line contacts DC and the buried contacts BC may be arranged symmetrically. Accordingly, the digit line contacts DC and the buried contacts BC may be arranged in a straight line (e.g., collinear) along the first direction D1 and the second direction D2.

[0030] Unlike the digit line contacts DC and the buried contacts BC, the landing pads LP may again be arranged in a zigzag shape in the second direction DR2 in which the bit line BL extends. Furthermore, the landing pads LP may be arranged such that they overlap the same side surface of each bit line BL in the first direction D1 in which the word line WL extends.

[0031] For example, each of the landing pads LP in a first row may overlap with a left side surface of the corresponding bit line BL and each of the landing pads LP in a second row may overlap with a right side surface of the corresponding bit line BL.

[0032] Referring to Fig. 1 to 3, according to some example embodiments, the semiconductor device may include the element isolation layer 105, a plurality of gate structures 110, a plurality of bit line structures 140ST, a bit line contact 146, a memory contact 120, and an information storage unit 190.

[0033] The substrate 100 may be or include a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, a lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The substrate 100 may be doped, e.g., lightly doped with impurities such as phosphorus; however, exemplary embodiments are not so limited.

[0034] The element isolation layer 105 may be formed in the substrate 100. The element isolation layer 105 may have a shallow trench isolation (STI) structure with good, e.g., excellent, element isolation properties (or electrical isolation properties). The element isolation layer 105 may define the active region ACT in the substrate 100. The element isolation layer 105 may be included in the substrate 100.

[0035] The active region ACT defined by the element isolation layer 105 may have a long island shape with a short axis and a long axis, as shown in Fig. 1. The active region ACT may have an oblique shape such that it has an angle of less than 90 degrees with respect to the word line WL formed in the element isolation layer 105.

[0036] Furthermore, the active region ACT may have an oblique shape such that it has an angle of less than 90 degrees with respect to the bit line BL formed on the element isolation layer 105. For example, the active region ACT may extend in a third direction D3 having a specific (or alternatively predetermined) angle with respect to the first and second directions D1 and D2.

[0037] The element isolation layer 105 may, for example, include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer, but inventive concepts are not limited thereto. Although the element isolation layer 105 is illustrated as a single layer, inventive concepts are not limited thereto. For example, although not shown, the element isolation layer 105 may include an insulating liner and a filling insulating layer that fills a trench defined by the insulating liner. The element isolation layer 105 may be formed using deposition processes such as a high-density plasma (HDP) chemical vapor deposition (CVD) process and / or a spin-on-glass (SOG) process.

[0038] In Fig. 2, it was shown that the upper surface of the element isolation layer 105 and the upper surface of the substrate 100, which correspond to the active regions ACT, are at the same height, e.g., on the same plane. However, this is only for convenience of description, and inventive concepts are not limited thereto.

[0039] The gate structures 110 may be formed in the substrate 100 and the element isolation layer 105. The gate structures 110 may be formed across the element isolation layer 105 and the active regions ACT defined by the element isolation layer 105. For example, a gate structure 110 may be formed in the element isolation layer 105 and the substrate 100 positioned in the first direction D1 in which the gate structure 110 extends.

[0040] The gate structure 110 may include a gate trench 114 formed in the substrate 100 and the element isolation layer 105, a gate isolation layer 111, a gate electrode 112, and a gate capping structure 113. Here, the gate electrode 112 may correspond to the word line WL.

[0041] The gate insulating layer 111 may extend along the sidewall and a bottom surface of the gate trench 114. The gate insulating layer 111 may extend along at least a portion of the profile of the gate trench 114.

[0042] The gate insulating layer 111 may comprise silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k material having a higher dielectric constant than silicon oxide. In one embodiment, the high-k material may comprise, for example, at least one element selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and a combination thereof. The gate insulating layer 111 may be formed using an oxidation process, such as an in-situ steam generation (ISSG) process; however, example embodiments are not limited thereto.

[0043] The high-k material mentioned above was described with a focus on oxide. However, the high-k material may include, but is not limited to, one or more nitrides (e.g., hafnium nitride) or oxynitrides (e.g., hafnium oxynitride) of the above metal material (e.g., hafnium).

[0044] The gate electrode 112 may be formed on the gate insulating layer 111. The gate electrode 112 may fill a portion of the gate trench 114.

[0045] The gate electrode 112 may comprise a metal, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, doped semiconductor material such as doped polysilicon, conductive metal oxynitride, and / or conductive metal oxide.The gate electrode 112 may, for example, comprise at least one of the group consisting of or comprising titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), Molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and / or a combination thereof.

[0046] The gate cap structure 113 may be formed on the gate electrode 112. The gate cap structure 113 may fill the remaining portion of the gate trench 114 in which the gate electrode 112 is formed. The gate cap structure 113 may comprise, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or a combination thereof.

[0047] In Fig. 3, it was shown that the upper surface of the gate cap structure 113 and the upper surface of the element isolation layer 105 are on the same plane. However, this is only for convenience of description, and inventive concepts are not limited thereto.

[0048] In addition, the gate insulating layer 111 is shown not to extend to the upper surface of the gate cap structure 113; however, it is not limited thereto.

[0049] Although not shown, an impurity-doped region may be formed on at least one side of the gate structure 110. The impurity-doped region may be or correspond to a source / drain region of a transistor. The impurity-doped region may be doped with an impurity such as boron, phosphorus, arsenic, carbon, or germanium; however, example embodiments are not limited thereto.

[0050] The bit line structure 140ST may include a wiring structure 140 and a wiring line cover layer 144.

[0051] The wiring structure 140 may be formed over the element isolation layer 105 and the substrate 100 in which the gate structures 110 are formed. The wiring structure 140 may cross the element isolation layer 105 and the active regions ACT defined by the element isolation layer 105.

[0052] For example, a wiring pattern 140 may be formed over the element isolation layer 105 and the substrate 100, positioned in the second direction D2 in which the wiring pattern 140 extends. The wiring pattern 140 may be formed to cross the gate patterns 110. Here, the wiring pattern 140 may correspond to or be the bit line BL.

[0053] The wiring structure 140 may include a first line wiring 143, a second line wiring 141, and a lower barrier layer 148.

[0054] The first wiring 143 may be arranged over the substrate 100 and the element isolation layer 105. The first wiring 143 may be elongated, e.g., it may extend along the second direction D2.

[0055] The first wiring 143 may include an upper surface 143us and a lower surface 143bs opposite each other. The upper surface 143us of the first wiring and the lower surface 143bs of the first wiring may be parallel to the upper surface of the substrate 100.

[0056] When the semiconductor device is scaled down or reduced in size, the width of the first line wiring 143 (width in the first direction D1) may decrease.

[0057] By using a material with a low resistivity and / or a high mean free path of electrons for the wiring, the performance of the semiconductor device can generally be improved. However, when the wiring width is less than or equal to 12 nm, the resistance of the wiring may increase by using the material having a high mean free path of electrons for the wiring. As the wiring width decreases, the frequency with which electrons in the material with the high mean free path collide with the wiring surface may increase. Due to the increase in the number of collisions, the resistance of the wiring may increase, resulting in a deterioration in performance, such as the speed and / or power of the semiconductor device.

[0058] When the semiconductor device is scaled down or reduced in size, the width of the wiring of the bit line BL (see Fig. 1). To improve the performance of the semiconductor device, a material with a short mean free path of electrons and low resistivity must be selected for use in the bit line wiring.

[0059] The first wiring 143 may, for example, comprise ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), RuAl, NiAl, NbB2, MoB2, TaB2, V2AlC, and / or CrAlC. In the semiconductor device according to some example embodiments, the first wiring 143 may comprise or consist of ruthenium. The first wiring 143 may, for example, be or correspond to a ruthenium wiring.

[0060] The lower barrier layer 148 may be disposed between the first wiring 143 and the substrate 100. The lower barrier layer 148 may extend along the lower surface 143bs of the first wiring. The lower barrier layer 148 may contact the first wiring 143.

[0061] The lower barrier layer 148 may, for example, comprise graphene and / or magnesium oxide (MgO). In the semiconductor device according to some example embodiments, the lower barrier layer 148 may comprise graphene, e.g., at least one monolayer of graphene. A thickness of the lower barrier layer may, for example, be between 0.334 nm and 3.185 nm; however, example embodiments are not limited thereto. For example, the lower barrier layer 148 may be or correspond to a lower graphene layer.

[0062] When the lower barrier layer 148 is a graphene lower layer, the lower barrier layer 148 may increase the size of a crystal grain structure of a metal material included in the first wiring 143. For example, a case where the first wiring 143 is a ruthenium wiring will be described; however, exemplary embodiments are not limited thereto.

[0063] The crystal grain size of a ruthenium layer formed on the graphene layer is larger than the crystal grain size of a ruthenium layer formed without the graphene layer. As the crystal grain size increases, a grain boundary between the crystal grains may decrease. Since the grain boundary can act as a resistance to electron transfer, the resistance of the ruthenium layer may decrease with increasing crystal grain size. For example, the lower graphene layer can reduce the resistance of the first lead wiring 143.

[0064] Alternatively or additionally, if the lower barrier layer 148 is a lower graphene layer, the lower graphene layer may improve current distribution between the wiring structure 140 and the bit line contact 146.

[0065] The second wiring 141 may be arranged between the lower barrier layer 148 and the substrate 100. The second wiring 141 may extend in the second direction D2 along the lower barrier layer 148.

[0066] The second wiring 141 may, for example, comprise a semiconductor material doped with impurities. The second wiring 141 may, for example, comprise impurity-doped silicon, impurity-doped silicon germanium, and / or impurity-doped germanium, and may be in a polycrystalline phase; however, exemplary embodiments are not limited thereto.

[0067] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the lower barrier layer 148, and the first wiring 143 sequentially stacked on the substrate 100.

[0068] The bit line contact 146 may be formed between the wiring structure 140 and the substrate 100. The wiring structure 140 may, for example, be formed on the bit line contact 146.

[0069] For example, the bit line contact 146 may be formed at a point where the wiring pattern 140 crosses a central portion of the active region ACT, which has a long island shape. The bit line contact 146 may be formed between the wiring pattern 140 and the substrate 100 in the central portion of the active region ACT.

[0070] The bit line contact 146 may electrically connect the wiring structure 140 to the substrate 100. The bit line contact 146 may electrically connect the wiring structure 140 to the active region ACT. For example, the bit line structure 140ST may be connected to the active region ACT through the bit line contact 146.

[0071] In particular, the bit line contact 146 may electrically connect the impurity-doped region of the substrate 100 between the adjacent gate structures 110 to the wiring structure 140. Here, the bit line contact 146 may correspond to the digit line (DC) contact, which is Fig. 2 was described.

[0072] For example, the depth from the top surface of the gate cap structure 113 to the bottom surface of the bit line contact 146 is less than the depth from the top surface of the gate cap structure 113 to the top surface of the gate electrode 112.

[0073] The bit line contact 146 may, for example, comprise a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and / or metal. In the semiconductor device according to some example embodiments, the bit line contact 146 may comprise a semiconductor material doped with impurities.

[0074] In Fig. 3, the wiring pattern 140 may include the first wiring 143 and the lower barrier layer 148 in a region overlapping the upper surface of the bit line contact 146. In a region not overlapping the upper surface of the bit line contact 146, the wiring pattern 140 may include the first wiring 143, the lower barrier layer 148, and the second wiring 141. In a manufacturing / production process, when the second wiring 141 is formed over the substrate 100 and then the bit line contact 146 is formed penetrating the second wiring 141, a shape as described above may appear.

[0075] Unlike the illustrated example, in a region overlapping with the upper surface of the bit line contact 146, the wiring structure 140 may include the first wiring 143, the lower barrier layer 148, and the second wiring 141. In a manufacturing / production process, when the bit line contact 146 is formed and then the second wiring 141 is formed on the bit line contact 146 and the substrate 100, a shape other than that shown in Fig. 3 shown appear.

[0076] The wiring line cover layer 144 may be disposed on the wiring structure 140. The wiring line cover layer 144 may extend in the second direction D2 along the upper surface 143us of the first wiring. In this case, the wiring line cover layer 144 may include, for example, a silicon nitride layer, a silicon oxynitride layer, and / or a silicon oxide layer, but example embodiments are not limited thereto.

[0077] A cell isolation layer 130 may be formed on the substrate 100 and the element isolation layer 105. In particular, the cell isolation layer 130 may be formed on the element isolation layer 105 and the substrate 100 on which the bit line contact 146 is not formed.

[0078] The cell insulation layer 130 may be formed between the substrate 100 and the wiring pattern 140 and between the element insulation layer 105 and the wiring pattern 140.

[0079] The cell insulating layer 130 may be a single layer, but, as shown, the cell insulating layer 130 may be a multilayer layer comprising a first cell insulating layer 131 and a second cell insulating layer 132. For example, the first cell insulating layer 131 may comprise an oxide layer, and the second cell insulating layer 132 may comprise a nitride layer, but they are not limited thereto.

[0080] A wiring spacer 150 may be disposed on the sidewalls of the wiring pattern 140 and the wiring cover layer 144. The wiring spacer 150 may be formed on the substrate 100 and the element isolation layer 105 in a portion of the wiring pattern 140 where the bit line contact 146 is formed. The wiring spacer 150 may extend in the second direction D2 on the sidewalls of the wiring pattern 140 and the wiring cover layer 144.

[0081] However, in the remaining portion of the wiring structure 140 where the bit line contact 146 is not formed, the wiring line spacer 150 may be disposed on the cell insulating layer 130. The wiring line spacer 150 may extend in the second direction D2 on the sidewalls of the wiring structure 140 and the wiring line cover layer 144.

[0082] The wiring line spacer 150 may be a single layer, but, as shown, the wiring line spacer 150 may be a multilayer layer comprising a first spacer 151 and a second spacer 152. The first and second spacers 151 and 152 may comprise, for example, but are not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride (SiON) layer, a silicon oxycarbonitride (SiOCN) layer, air, or a combination thereof.

[0083] The storage contact 120 may be formed between the adjacent wiring patterns 140. The storage contact 120 may overlap with the substrate 100 between the adjacent wiring patterns 140 and the element isolation layer 105. Here, the storage contact 120 may correspond to the buried contact BC.

[0084] The storage contact 120 may comprise, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and / or metal.

[0085] A memory pad 160 may be formed on the memory contact 120. The memory pad 160 may be electrically connected to the memory contact 120. Here, the memory pad 160 may correspond to the landing pad LP.

[0086] The storage pad 160 may overlap with a portion of the upper surface of the bit line structure 140ST. The storage pad 160 may comprise, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and / or metal.

[0087] A pad isolation insulating layer 180 may be formed on the memory pad 160 and the bit line pattern 140ST. The pad isolation insulating layer 180 may be disposed, for example, on the wiring line cap layer 144.

[0088] The pad isolation layer 180 may define a region of the memory pad 160 that forms a plurality of isolated regions. Furthermore, the pad isolation layer 180 may be patterned to expose a portion of the upper surface of the memory pad 160.

[0089] The pad isolation insulating layer 180 may comprise an insulating material to electrically isolate the plurality of memory pads 160 from each other. The pad isolation insulating layer 180 may comprise, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof; but is not limited thereto.

[0090] The information storage unit 190 may be formed on the pad separation insulating layer 180. The information storage unit 190 may be electrically connected to the storage pad 160. That is, the information storage unit 190 may be electrically connected to the storage contact 120.

[0091] The information storage unit 190 may include, for example, but is not limited to, a capacitor. The information storage unit 190 includes the lower electrode 191, a capacitor insulating layer 192, and an upper electrode 193.

[0092] The bottom electrode 191 may be disposed on the memory pad 160. The bottom electrode 191 is illustrated as having a columnar shape, but is not limited thereto. The bottom electrode 191 may have a cylindrical shape.

[0093] The capacitor insulating layer 192 is formed on the lower electrode 191. The capacitor insulating layer 192 may be formed along the profile of the lower electrode 191.

[0094] The upper electrode 193 is formed on the capacitor insulating layer 192. The upper electrode 193 may surround the outer wall of the lower electrode 191.

[0095] The bottom electrode 191 may, for example, comprise a doped semiconductor material, such as doped polysilicon, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), a conductive metal oxide (e.g., iridium oxide or niobium oxide), or the like, but inventive concepts are not limited thereto. In the semiconductor device according to some example embodiments, the bottom electrode 191 may comprise titanium nitride (TiN). Alternatively or additionally, in the semiconductor device according to some example embodiments, the bottom electrode 191 may comprise niobium nitride (NbN).

[0096] The capacitor insulating layer 192 may, for example, comprise an element selected from the group consisting of or including silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and a combination thereof, but is not limited thereto. Although the capacitor insulating layer 192 is illustrated as a single layer, this is for convenience of description only, and the inventive concepts are not limited thereto.

[0097] In the semiconductor device according to some example embodiments, the capacitor insulating layer 192 may include a stacked structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked.

[0098] In the semiconductor device according to some example embodiments, the capacitor insulating layer 192 may include a dielectric layer comprising hafnium (Hf).

[0099] In the semiconductor device according to some example embodiments, the capacitor insulating layer 192 may have a stacked structure including a ferroelectric material layer and a paraelectric material layer.

[0100] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may have a thickness sufficient to exhibit ferroelectric properties. The thickness range of the ferroelectric material layer with ferroelectric properties may vary depending on the ferroelectric material.

[0101] For example, the ferroelectric material layer may comprise a monometal oxide. The ferroelectric material layer may comprise a monometal oxide layer. Here, the monometal oxide may be a binary compound consisting of a metal and oxygen. The ferroelectric metal layer comprising a monometal oxide may comprise crystal grains having an orthorhombic crystal system.

[0102] For example, the metal included in the monometal oxide layer may be hafnium (Hf). The monometal oxide layer may be or include a hafnium oxide (HfO) layer. Here, the hafnium oxide layer may have a chemical formula that conforms to stoichiometry or it may have a chemical formula that does not conform to stoichiometry.

[0103] As another example, the metal included in the monometal oxide layer may be a rare earth metal belonging to the lanthanides. The monometal oxide layer may be a rare earth metal oxide layer formed from a rare earth metal belonging to the lanthanides. Here, the oxide layer of a rare earth metal (belonging to the lanthanides) may have a chemical formula that conforms to a stoichiometry, or it may have a chemical formula that does not conform to the stoichiometry.

[0104] The ferroelectric material layer may further comprise a dopant doped into the monometal oxide layer. The doping concentration may vary depending on the type of dopant, but the doping concentration of the dopant included in the ferroelectric material layer may be 10% or less.

[0105] For example, if the monometal oxide layer is a hafnium oxide layer, the dopant may comprise gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (La), cerium (Ce), dysprosium (Dy), tantalum (Ta), strontium (Sr), and / or niobium (Nb). According to another example, if the monometal oxide layer is a rare earth metal oxide layer (belonging to the lanthanides), the dopant may comprise silicon (Si), aluminum (Al), hafnium (Hf), zirconium (Zr), and / or niobium (Nb).

[0106] According to another example, the ferroelectric material layer may not include a dopant doped into the monometal oxide layer.

[0107] When the ferroelectric material layer comprises a monometal oxide layer, the ferroelectric layer may have a thickness of, for example, 1 nm or more and 10 nm or less.

[0108] The ferroelectric material layer may comprise, for example, bimetallic oxide. The ferroelectric metal layer may comprise a bimetallic oxide layer. Here, the bimetallic oxide may be a ternary compound consisting of two metals and oxygen. The ferroelectric metal layer comprising bimetallic oxide may comprise crystal grains having an orthorhombic crystal system.

[0109] The metals included in the bimetallic oxide layer may be, for example, hafnium (Hf) and zirconium (Zr). The bimetallic oxide layer may be a hafnium zirconium oxide layer (HfxZr(1-x)O). In the bimetallic oxide layer, x may be 0.2 or more and 0.8 or less. Here, the hafnium zirconium oxide layer (HfxZr(1-x)O) may have a chemical formula that conforms to stoichiometry or it may have a chemical formula that does not conform to stoichiometry.

[0110] According to one example, the ferroelectric material layer may further comprise a dopant doped into the bimetallic oxide layer. The dopant may comprise gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (La), cerium (Ce), dysprosium (Dy), tantalum (Ta), and / or strontium (Sr). According to another example, the ferroelectric material layer may not comprise a dopant doped into the bimetallic oxide layer.

[0111] When the ferroelectric material layer comprises a bimetal oxide layer, the ferroelectric layer may have a thickness of, for example, 1 nm or more and 20 nm and less.

[0112] For example, the paraelectric material layer can be, but is not limited to, a dielectric layer comprising zirconium (Zr) or a stacked layer comprising zirconium (Zr). Although they have the same chemical formula, they can exhibit ferroelectric properties or paraelectric properties depending on the crystal structure of the dielectric material.

[0113] The paraelectric material may have a positive dielectric constant, and the ferroelectric material may have a negative dielectric constant within a specific (or alternatively, predetermined) range. For example, the paraelectric material may have a positive capacitance, and the ferroelectric material may have a negative capacitance.

[0114] When two or more capacitors with positive capacitance are connected in series, the total capacitance generally decreases. However, when a negative capacitor with negative capacitance and a positive capacitor with positive capacitance are connected in series, the total capacitance increases.

[0115] The top electrode 193 may, for example, comprise a doped semiconductor material, such as doped polysilicon, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metal (e.g., ruthenium, iridium, titanium, or tantalum), conductive metal oxide (e.g., iridium oxide or niobium oxide), or the like, but inventive concepts are not limited thereto. In the semiconductor device according to some example embodiments, the top electrode 193 may comprise titanium nitride (TiN). Alternatively or additionally, in the semiconductor device according to some example embodiments, the top electrode 193 may be or comprise niobium nitride (NbN).

[0116] Fig. 4 is a schematic diagram illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3.

[0117] Referring to Fig. 4, in a semiconductor device according to some example embodiments, the wiring structure 140 may further comprise a third line wiring 145.

[0118] The third wiring 145 may be arranged between the second wiring 141 and the lower barrier layer 148. The third wiring 145 may extend in the second direction D2 along the lower barrier layer 148.

[0119] The third line wiring 145 may be arranged on the bit line contact 146. The second line wiring 141 may extend along the third line wiring 145.

[0120] The third wiring 145 may, for example, comprise or consist of a metal silicide material. For example, the third wiring 145 may be a metal silicide wiring.

[0121] The third wiring 145 may include or consist of, for example, titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, ruthenium (Ru) silicide, and / or tungsten (W) silicide, but is not limited thereto.

[0122] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the third wiring 145, and the lower barrier layer 148 and the first wiring 143 sequentially stacked on the substrate 100.

[0123] Fig. 5 is a schematic diagram illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. 4 concentrate.

[0124] Referring to Fig. 5, in a semiconductor device according to some example embodiments, the wiring structure 140 may further comprise a fourth line wiring 142.

[0125] The fourth wiring 142 may be arranged between the third wiring 145 and the lower barrier layer 148. The fourth wiring 142 may extend in the second direction D2 along the lower barrier layer 148.

[0126] The fourth wiring 142 may, for example, include or be made of a conductive material comprising a metal. The fourth wiring 142 may, for example, include, but is not limited to, tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), and / or tungsten silicon nitride (WSIN).

[0127] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the third wiring 145, the fourth wiring 142, the lower barrier layer 148, and the first wiring 143 sequentially stacked on the substrate 100.

[0128] Fig. 6 is a schematic diagram illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3.

[0129] Referring to Fig. 6, in a semiconductor device according to some example embodiments, the wiring structure 140 may further include the fourth line wiring 142.

[0130] The fourth wiring 142 may be arranged between the second wiring 141 and the lower barrier layer 148. The fourth wiring 142 may extend in the second direction D2 along the lower barrier layer 148.

[0131] The fourth line wiring 142 may be disposed on the bit line contact 146. The second line wiring 141 may extend along the fourth line wiring 142.

[0132] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the fourth wiring 142, the lower barrier layer 148, and the first wiring 143 sequentially stacked on the substrate 100.

[0133] Fig. 7 and Fig. 8 are schematics illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3. Fig. 7 is a cross-sectional view taken along line AA of Fig. 1 was made. Fig. 8 is a cross-sectional view taken along line BB of Fig. 1 was made.

[0134] Referring to Fig. 7 and Fig. 8, in a semiconductor device according to some exemplary embodiments, the wiring structure 140 may include the first line wiring 143, the second line wiring 141, and an upper barrier layer 149. The wiring structure 140 does not include the lower barrier layer 148 (see Fig. 2 and Fig. 3).

[0135] The upper barrier layer 149 may be disposed between the first wiring 143 and the wiring cover layer 144. The upper barrier layer 149 may extend along the upper surface 143us of the first wiring. The upper barrier layer 149 may contact the first wiring 143. The wiring cover layer 144 may extend along the upper barrier layer 149.

[0136] The upper barrier layer 149 may, for example, comprise graphene and / or magnesium oxide (MgO). In the semiconductor device according to some example embodiments, the upper barrier layer 149 may be or comprise graphene. The upper barrier layer 149 may, for example, be an upper graphene layer and may have a thickness equal to or different from that of a lower barrier layer 148.

[0137] If a preliminary wiring line cover layer 144p (see Fig. 24) over a first preliminary conductive layer 143p (see Fig. 24), the upper barrier layer 149 may protect the first conductive wiring 143. Alternatively or additionally, in a case where the upper barrier layer 149 is a graphene upper layer, when electrons moving within the first conductive wiring 143 collide with the upper surface 143us of the first conductive wiring, the upper barrier layer 149 may allow the electrons to be reflected, e.g., they may be specularly reflected from the upper surface 143us of the first conductive wiring.

[0138] Furthermore, in a case where the upper barrier layer 149 is an upper graphene layer, during a manufacturing / production process, materials included in the second to fourth lead wirings 141, 145, and 142 (see Fig. 9 to 11) arranged between the first wiring 143 and the substrate 100 are diffused into the upper surface 143us of the first wiring, or the possibility of this can be reduced.

[0139] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the first wiring 143, and the upper barrier layer 149 sequentially stacked on the substrate 100.

[0140] Fig. 9 is a schematic illustrating a semiconductor device according to some example embodiments. Fig. 10 is a schematic diagram illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. 7 and Fig. 8 concentrate.

[0141] Referring to Fig. 9, in a semiconductor device according to some example embodiments, the wiring structure 140 may further include the third wiring 145 formed between the first wiring 143 and the second wiring 141.

[0142] The third wiring 145 may extend in the second direction D2 along the lower barrier layer 143bs of the first wiring. The third wiring 145 may be arranged on the bit line contact 146. The second wiring 141 may extend along the third wiring 145.

[0143] The third wiring 145 may, for example, comprise or consist of a metal silicide material. For example, the third wiring 145 may be a metal silicide wiring.

[0144] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the third wiring 145, the first wiring 143, and the upper barrier layer 149 sequentially stacked on the substrate 100.

[0145] Referring to Fig. 10, in a semiconductor device according to some example embodiments, the wiring structure 140 may further include the fourth wiring 142 formed between the first wiring 143 and the second wiring 141.

[0146] The fourth wiring 142 may extend in the second direction D2 along the lower barrier layer 143bs of the first wiring. The fourth wiring 142 may be arranged on the bit line contact 146. The second wiring 141 may extend along the fourth wiring 142.

[0147] The fourth wiring 142 may, for example, comprise or consist of a conductive material comprising a metal.

[0148] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the fourth wiring 142, the first wiring 143, and the upper barrier layer 149 sequentially stacked on the substrate 100.

[0149] Fig. 11 is a schematic diagram illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. 10 concentrate.

[0150] Referring to Fig. 11, in a semiconductor device according to some example embodiments, the wiring structure 140 may further include the third wiring 145 formed between the second wiring 141 and the fourth wiring 142.

[0151] The third line wiring 145 may be arranged between the fourth line wiring 142 and the second line wiring 141, and between the fourth line wiring 142 and the bit line contact 146. The third line wiring 145 may extend in the second direction D2 along the fourth line wiring 142.

[0152] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the third wiring 145, the fourth wiring 142, the first wiring 143, and the upper barrier layer 149, which are sequentially stacked on the substrate 100.

[0153] Fig. 12 and Fig. 13 are schematics illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3. Fig. 12 is a cross-sectional view taken along line AA of Fig. 1 was made. Fig. 13 is a cross-sectional view taken along line BB of Fig. 1 was made.

[0154] Referring to Fig. 12 and Fig. 13, the wiring structure 140 in a semiconductor device according to some example embodiments may further comprise the upper barrier layer 149.

[0155] The upper barrier layer 149 may be disposed on the upper surface 143us of the first conductive wiring. The upper barrier layer 149 may extend along the upper surface 143us of the first conductive wiring. The upper barrier layer 149 may contact the first conductive wiring 143.

[0156] The wiring line cover layer 144 may be disposed on the upper barrier layer 149. The wiring line cover layer 144 may extend along the upper barrier layer 149.

[0157] The wiring structure 140 may include the lower barrier layer 148 and the upper barrier layer 149 in contact with the first line wiring 143. In a case where the lower barrier layer 148 and the upper barrier layer 149 are or include graphene layers, the wiring structure 140 may include an upper graphene layer extending along the upper surface 143us of the first line wiring and a lower graphene layer extending along the lower surface 143bs of the first line wiring.

[0158] For example, a thickness t11 of the lower barrier layer 148 may be greater than a thickness t12 of the upper barrier layer 149. The thickness t11 and the thickness t12 may correspond to a number of layers of graphene, which may be an integer greater than or equal to one.

[0159] In the semiconductor device according to some example embodiments, the wiring structure 140 may include the second wiring 141, the lower barrier layer 148, and the first wiring 143 and the upper barrier layer 149 stacked sequentially on the substrate 100.

[0160] Although not shown, according to one example, the wiring structure 140 may further include the third line wiring 145 (see Fig. 4) arranged between the lower barrier layer 148 and the second wiring 141. For example, the wiring structure 140 may further include the fourth wiring 142 (see Fig. 6) arranged between the lower barrier layer 148 and the second wiring 141. According to another example, the wiring structure 140 may further include the third wiring 145 (see Fig. 5) and the fourth line wiring 142 (see Fig. 5) arranged between the lower barrier layer 148 and the second wiring 141.

[0161] Fig. 14 is a schematic illustrating a semiconductor device according to some example embodiments. Fig. 15 is an enlarged view of section P from Fig. 14. For the purpose of ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3.

[0162] Referring to Fig. 14 and Fig. 15, in a semiconductor device according to some example embodiments, the wiring structure 140 may further comprise a sidewall barrier layer 147 extending along a sidewall 143sw of the first wiring, the sidewall of the lower barrier layer 148, and the sidewall of the second wiring 141.

[0163] The wiring line spacer 150 covers the sidewall barrier layer 147. In a region where the wiring pattern 140 and the substrate 100 are electrically connected, the sidewall barrier layer 147 may be disposed on the sidewall of the bit line contact 146. If a part of the substrate 100 is exposed during a process for forming the bit line contact 146, the sidewall barrier layer 147 itself may be formed on the exposed substrate 100.

[0164] The sidewall barrier layer 147 may contact the first conductive wiring 143. The sidewall barrier layer 147 may, for example, contact the second conductive wiring 141 and the lower barrier layer 148.

[0165] The sidewall barrier layer 147 may, for example, comprise graphene and / or magnesium oxide (MgO). In the semiconductor device according to some example embodiments, the sidewall barrier layer 147 may be or comprise graphene. The sidewall barrier layer 147 may, for example, be a sidewall graphene layer.

[0166] In a case where the sidewall barrier layer 147 is a sidewall graphene layer, when electrons moving within the first wiring 143 collide with the sidewall 143sw of the first wiring, the sidewall barrier layer 147 may allow the electrons to be specularly reflected from the sidewall 143sw of the first wiring.

[0167] For example, the thickness t11 of the lower barrier layer 148 may be less than or equal to a thickness t13 of the sidewall barrier layer 147.

[0168] Although not shown, according to an example, when the wiring structure 140 further includes the third line wiring 145 (see Fig. 4) between the lower barrier layer 148 and the second wiring 141, the sidewall barrier layer 147 may be formed on the sidewall of the third wiring 145. Alternatively or additionally, if the wiring structure 140 further comprises the fourth wiring 142 (see Fig. 6) between the lower barrier layer 148 and the second wiring 141, the sidewall barrier layer 147 may be formed on the sidewall of the fourth wiring 142. Alternatively or additionally, if the wiring structure 140 further comprises the third wiring 145 (see Fig. 5) and the fourth line wiring 142 (see Fig. 5) between the lower barrier layer 148 and the second wiring 141, the sidewall barrier layer 147 may be formed on the sidewall of the third wiring 145 and the sidewall of the fourth wiring 142.

[0169] Fig. 16 is a schematic illustrating a semiconductor device according to some example embodiments. Fig. 17 is an enlarged view of section P from Fig. 16. For the purpose of ease of description, the following description will refer to differences from the description with reference to Fig. 7 and Fig. 8 concentrate.

[0170] It should be noted that since a description of the sidewall barrier layer 147 is similar to that described with reference to Fig. 14 and Fig. 15 was given, mainly describing the difference.

[0171] Referring to Fig. 16 and Fig. 17, in a semiconductor device according to some example embodiments, the wiring structure 140 may further include the sidewall barrier layer 147 extending along the sidewall of the upper barrier layer 149, the sidewall 143sw of the first wiring, and the sidewall of the second wiring 141.

[0172] For example, the sidewall barrier layer 147 may contact the first wiring 143, the second wiring 141, and the upper barrier layer 149.

[0173] For example, the thickness t12 of the upper barrier layer 149 may be greater than or equal to the thickness t13 of the sidewall barrier layer 147.

[0174] Although not shown, according to an example, when the wiring structure 140 further includes the third line wiring 145 (see Fig. 9) between the first power consumption 143 and the second wiring 141, the sidewall barrier layer 147 may be formed on the sidewall of the third wiring 145. Alternatively or additionally, if the wiring structure 140 further comprises the fourth wiring 142 (see Fig. 10) between the first wiring 143 and the second wiring 141, the sidewall barrier layer 147 may be formed on the sidewall of the fourth wiring 142. Alternatively or additionally, if the wiring structure 140 further comprises the third wiring 145 (see Fig. 11) and the fourth line wiring 142 (see Fig. 11) between the first wiring 143 and the second wiring 141, the sidewall barrier layer 147 may be formed on the sidewall of the third wiring 145 and the sidewall of the fourth wiring 142.

[0175] Fig. 18 is a schematic illustrating a semiconductor device according to some example embodiments. Fig. 19 is an enlarged view of section P from Fig. 18. For the purpose of ease of description, the following description will refer to differences from the description with reference to Fig. 12 and Fig. 13 concentrate.

[0176] It should be noted that since a description of the sidewall barrier layer 147 of the description with reference to Fig. 14 and Fig. 15 is similar, mainly the differences are described.

[0177] Referring to Fig. 18 and Fig. 19, in a semiconductor device according to some example embodiments, the wiring structure 140 may further include the sidewall barrier layer 147 extending along the sidewall of the upper barrier layer 149, the sidewall 143sw of the first wiring, the sidewall of the lower barrier layer 148, and the sidewall of the second wiring 141.

[0178] For example, the sidewall barrier layer 147 may contact the first wiring 143, the second wiring 141, the lower barrier layer 148, and the upper barrier layer 149.

[0179] For example, the thickness t12 of the upper barrier layer 149 may be greater than or equal to the thickness t13 of the sidewall barrier layer 147. The thickness t11 of the lower barrier layer 148 may be less than or equal to the thickness t13 of the sidewall barrier layer 147. The thickness t11 of the lower barrier layer 148 may be less than the thickness t12 of the upper barrier layer 149.

[0180] Unlike the illustrated example, the wiring structure 140 may further include the third line wiring 145 (see Fig. 4) and / or the fourth line wiring 142 (see Fig. 6) provided between the lower barrier layer 148 and the second wiring 141.

[0181] Fig. 20 is a schematic diagram illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3.

[0182] Referring to Fig. 20, in a semiconductor device according to some exemplary embodiments, the wiring structure 140 may include the first line wiring 143, the second line wiring 141, and the sidewall barrier layer 147. The wiring structure 140 does not include the lower barrier layer 148 (see Fig. 2 and Fig. 3).

[0183] For example, the sidewall barrier layer 147 may extend along the sidewall of the first conductive wiring 143 and the sidewall of the second conductive wiring 141. The sidewall barrier layer 147 may be formed on the sidewall of the bit line contact 146.

[0184] Since a description of the sidewall barrier layer 147 is substantially the same as with reference to Fig. 14 and Fig. 15, a detailed description is omitted below for the purpose of brevity of the description.

[0185] Unlike the illustrated example, the wiring structure 140 may further include the third line wiring 145 (see Fig. 4) and / or the fourth line wiring 142 (see Fig. 6) provided between the first line wiring 143 and the second line wiring 141.

[0186] Fig. 21 and Fig. 22 are schematics illustrating a semiconductor device according to some exemplary embodiments. For ease of description, the following description will refer to differences from the description with reference to Fig. Concentrate on 1 to 3. Fig. 21 is a cross-sectional view taken along line AA of Fig. 1 was made. Fig. 22 is a cross-sectional view taken along line BB of Fig. 1 was made.

[0187] Referring to Fig. 21 and Fig. 22, in a semiconductor device according to some example embodiments, the lower barrier layer 148 may contact the cell insulation layer 130 and the bit line contact 146.

[0188] The second line wiring 141 (see Fig. 2 and Fig. 3) is not provided between the lower barrier layer 148 and the cell insulation layer 130.

[0189] Fig. 23 to 27 are views illustrating the intermediate steps of a manufacturing method for a semiconductor device according to some example embodiments.

[0190] Referring to Fig. 23, the element isolation layer 105 is formed in the substrate 100. The substrate 100 includes the active regions ACT defined by the element isolation layer 105.

[0191] For example, an element isolation trench may be formed in the substrate 100. The element isolation trench may be filled with an insulating material to form the element isolation layer 105 in the substrate 100.

[0192] Referring to Fig. 24, a preliminary cell insulating layer 130p, a preliminary wiring pattern 140p including the preliminary bit line contact 146p connected to the substrate 100, and the preliminary wiring line cap layer 144p may be sequentially formed on the substrate 100.

[0193] Specifically, the preliminary cell insulating layer 130p may be formed on the substrate 100 and the element insulating layer 105. A second preliminary conductive layer 141p may be formed on the preliminary cell insulating layer 130p.

[0194] The preliminary cell insulating layer 130p may include a first preliminary cell insulating layer 131p and a second preliminary cell insulating layer 132p, but example embodiments are not limited thereto.

[0195] Subsequently, after a mask pattern which simultaneously covers the ends of the active regions ACT which are arranged in the first direction D1 in Fig. 1, the second preliminary conductive layer 141p and the preliminary cell insulating layer 130p may be removed using the mask pattern. Accordingly, a bit line contact opening 146_op may be formed. The preliminary bit line contact 146p filling the bit line contact opening 146_op may be formed.

[0196] A preliminary barrier layer 148p and a first preliminary conductive layer 143p may be sequentially formed on the preliminary bit line contact 146p and the second preliminary conductive layer 141p. A preliminary upper barrier layer 149p may be formed on the first preliminary conductive layer 143p.

[0197] In this way, the preliminary wiring structure 140p including the first and second preliminary conductive layers 143p and 141p, the preliminary lower barrier layer 148p, and the preliminary upper barrier layer 149p can be formed on the preliminary cell insulating layer 130p.

[0198] Subsequently, the preliminary wiring line cover layer 144p may be formed on the preliminary wiring pattern 140p.

[0199] Referring to Fig. 25, the preliminary wiring pattern 140p and the preliminary wiring line covering layer 144p are etched to form the first wiring 143, the second wiring 141, the lower barrier layer 148, the upper barrier layer 149, and the wiring line covering layer 144 extending in the second direction D2 (see Fig. 1) on the substrate 100 and the preliminary cell insulating layer 130p.

[0200] Furthermore, the preliminary bit line contact 146p may be provided with a structure to form the bit line contact 146 between the lower barrier layer 148 and the substrate 100.

[0201] The first wiring 143 may be, for example, a ruthenium wiring. After the etching process, an oxide of a metal included in the first wiring 143 may be formed on the sidewall of the first wiring 143. The metal oxide formed on the sidewall of the first wiring 143 may degrade the properties of the first wiring 143.

[0202] In order to prevent or reduce the likelihood of deterioration of the characteristics of the first wiring 143, a reduction process for reducing the area of ​​the first wiring 143 may be performed after the etching process for forming the first wiring 143.

[0203] The reduction process for reducing the area of ​​the first lead wiring 143 may be, for example, a heat treatment process using a reducing gas, a high-temperature plasma process using a reducing gas, and / or a radical process using a reducing gas. The reducing gas may include, for example, hydrogen (H2), but is not limited thereto.

[0204] According to one example, the etching process for forming the first conductive wiring 143 and the reduction process for reducing the area of ​​the first conductive wiring 143 may be performed in situ (e.g., within a chamber or within a tool). According to another example, an etching process for forming the first conductive wiring 143 and the reduction process for reducing the area of ​​the first conductive wiring 143 may be performed ex situ (e.g., with separate chambers and / or tools).

[0205] Referring to Fig. 26, the sidewall barrier layer 147 may be formed on the sidewall of the first wiring 143.

[0206] The sidewall barrier layer 147 may be formed on the sidewall of the second wiring 141, the sidewall of the lower barrier layer 148, and the sidewall of the upper barrier layer 149.

[0207] In this way, the wiring structure 140 comprising the first wiring 143, the second wiring 141, the lower barrier layer 148, the upper barrier layer 149, and the sidewall barrier layer 147 can be formed over the substrate 100. Furthermore, the bit line structure 140ST comprising the wiring structure 140 and the wiring line cap layer 144 can be formed over the substrate 100.

[0208] The sidewall barrier layer 147 may be formed on the sidewall of the bit line contact 146. Furthermore, the sidewall barrier layer 147 may be formed on the substrate 100 exposed through the bit line contact opening 146_op.

[0209] According to one example, a deposition process of the sidewall barrier layer 147 and the reduction process (described with reference to Fig. 25) to reduce the area of ​​the first wiring 143 may be performed in situ. According to another example, the deposition process of the sidewall barrier layer 147 and the reduction process to reduce the area of ​​the first wiring 143 may be performed ex situ.

[0210] Referring to Fig. 27, the wiring line spacer 150 may be formed on the side wall of the bit line structure 140ST.

[0211] The wiring line spacer 150 may be formed on the element isolation layer 105 and the substrate 100 in a portion of the wiring structure 140 in which the bit line contact 146 is formed. The wiring line spacer 150 may extend in the second direction D2 (see Fig. 1) extend along the sidewall of the bit line structure 140ST.

[0212] The preliminary cell insulation layer 130p, which does not overlap the bit line pattern 140ST and the wiring line spacer 150, may be removed. Between the bit line patterns 140ST, the substrate 100 and the element insulation layer 105 may be exposed.

[0213] Subsequently, with reference to Fig.18, a portion of the substrate 100 and the element isolation layer 105 between the bit line patterns 140ST may be removed to form the memory contact 120. Subsequently, the memory pad 160 and the information storage unit 190 may be formed.

[0214] Unlike above, it is possible that a part of the sidewall barrier layer 147, the lower barrier layer 148 and the upper barrier layer 149 are not formed.

Claims

[1] A semiconductor device comprising: a substrate (100) comprising an element isolation layer (105), the element isolation layer (105) defining an active region; a plurality of word lines (WL) crossing the active region in a first direction; and a plurality of bit line structures (140ST) on the substrate (100) connected to the active region, the plurality of bit line structures (140ST) extending in a second direction different from the first direction, wherein each of the plurality of bit line structures (140ST): a ruthenium wiring comprising a lower surface (143bs) and an upper surface (143us) opposite the lower surface (143bs), a lower graphene layer (148) which is in contact with the lower surface (143bs) of the ruthenium wiring (143) and which extends along the lower surface (143bs) of the ruthenium wiring, and a wiring line cover layer (144) extending along the upper surface (143us) of the ruthenium line wiring, wherein at least one of the plurality of bit line structures (140ST) further comprises a sidewall graphene layer (147) extending along a sidewall of the ruthenium wiring. [2] The semiconductor device according to claim 1, further comprising: a first conductive wiring (141) between the lower graphene layer (148) and the substrate, wherein the first conductive wiring (141) extends along the lower graphene layer (148). [3] The semiconductor device according to claim 2, wherein the first line wiring (141) comprises a doped semiconductor material. [4] A semiconductor device according to claim 3, further comprising: a metal silicide line wiring between the first line wiring (141) and the lower graphene layer (148). [5] The semiconductor device according to claim 2, wherein the first lead wiring (141) comprises a conductive material, the conductive material comprising a metal. [6] A semiconductor device according to claim 5, further comprising: a second wiring between the first wiring (141) and the substrate (100) extending along the first wiring (141), wherein the second wiring comprises a doped semiconductor material. [7] The semiconductor device according to claim 1, wherein a thickness of the sidewall graphene layer (147) is greater than or equal to a thickness of the lower graphene layer (148). [8] A semiconductor device comprising: a substrate (100) comprising an element isolation layer, the element isolation layer (105) defining an active region; a plurality of word lines (WL) crossing the active region in a first direction; and a plurality of bit line structures (140ST) extending in a second direction different from the first direction on the substrate (100) and connected to the active region, wherein each of the plurality of bit line structures (140ST): a ruthenium wiring comprising a lower surface (143bs) and an upper surface (143us) opposite the lower surface (143bs), an upper graphene layer (149) which is in contact with the upper surface (143us) of the ruthenium wiring and which extends along the upper surface (143us) of the ruthenium wiring, and a wiring line cover layer (144) on the upper graphene layer (149) extending along the upper graphene layer (149), wherein at least one of the plurality of bit line structures (140ST) further comprises a sidewall graphene layer (147) extending along a sidewall of the ruthenium wiring. [9] A semiconductor device according to claim 8, further comprising: a first wiring (141) between the ruthenium wiring and the substrate (100) extending along the ruthenium wiring, wherein the first wiring (141) comprises a doped semiconductor material. [10] A semiconductor device according to claim 9, further comprising: a metal silicide line wiring between the first line wiring and the ruthenium line wiring. [11] The semiconductor device according to claim 8, further comprising: a first wiring (141) between the ruthenium wiring (143) and the substrate, the first wiring (141) extending along the ruthenium wiring, wherein the first lead wiring (141) comprises a conductive material, wherein the conductive material comprises a metal. [12] The semiconductor device according to claim 11, further comprising: a second wiring between the first wiring and the substrate (100) extending along the first wiring, the second wiring (141) comprising a doped semiconductor material. [13] The semiconductor device according to claim 8, wherein a thickness of the sidewall graphene layer (147) is less than or equal to a thickness of the upper graphene layer (149). [14] Semiconductor device, comprising: a substrate (100) comprising an element isolation layer (105), the element isolation layer (105) defining an active region; a plurality of word lines (WL) crossing the active region in a first direction; and a plurality of bit line structures (140ST) on the substrate connected to the active region, the plurality of bit line structures (140ST) extending in a second direction different from the first direction, wherein each of the plurality of bit line structures (140ST): a ruthenium wiring comprising a lower surface (143bs) and an upper surface (143us) opposite the lower surface (143bs), a lower graphene layer (148) which is in contact with the lower surface (143bs) of the ruthenium wiring and which extends along the lower surface (143bs) of the ruthenium wiring, an upper graphene layer (149) which is in contact with the upper surface (143us) of the ruthenium wiring and which extends along the upper surface (143us) of the ruthenium wiring, and a wiring line cover layer (144) on the upper graphene layer (149) extending along the upper graphene layer (149), wherein at least one of the plurality of bit line structures (140ST) further comprises a sidewall graphene layer (147) extending along a sidewall of the ruthenium wiring. [15] The semiconductor device according to claim 14, further comprising: a first wiring (141) between the lower graphene layer (148) and the substrate, extending along the lower graphene layer (148), wherein the first wiring (141) comprises a doped semiconductor material. [16] The semiconductor device according to claim 15, further comprising: a metal silicide line wiring between the first line wiring and the ruthenium line wiring. [17] The semiconductor device according to claim 14, further comprising: a first wiring (141) between the lower graphene layer (148) and the substrate, extending along the lower graphene layer (148), wherein the first lead wiring (141) comprises a conductive material, wherein the conductive material comprises a metal.

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