PROCESS FOR PROCESSING DEFECTIVE CHIPS

Abstract

Procedure comprising: Identifying (102) a defective portion of a chip (200); physically cutting (104) the defective portion of the chip (200) from a functional portion of the chip; Polishing (106) a cut side of the functional portion of the chip, wherein the physical cutting (104) of the defective portion of the chip (200) from the functional portion of the chip comprises at least one vertical laser cut or a horizontal laser cut through the chip, wherein the vertical laser cut and / or the horizontal laser cut is performed in the defective portion of the chip.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to methods for optimizing the value of defective integrated circuits. BACKGROUND

[0002] The processes used to manufacture integrated circuits produce defects that limit the yield of these silicon chips. Manufacturers make significant efforts to minimize these defects, but some will always occur. It is desirable to find ways to bring the non-defective portions of defective chips to market, even if their value is reduced by the presence of a defect. This disclosure demonstrates ways to minimize the depreciation of such defective chips in the marketplace.

[0003] Until now, "floor sweeping" has generally been used as a method to salvage some value from defective chips. In floor sweeping, the defective portion of the chip is downgraded or shut down, and the remaining portion of the chip is then operated as a lower-quality chip than the larger chip originally intended. In the application, only the active portion of the chip is then used. However, floor sweeping still has some limitations. For example, a floor-sweeped chip that has the same performance as a smaller, defect-free chip may have the same static leakage as a larger, defect-free chip. This leakage results from the fact that a voltage is still applied across the entire area of ​​the larger chip, even though the defective portion of that area has been downgraded and does not contribute to performance.US 2019 / 0 195 947 A1 discloses a test system for chips that is performed in the chip's working environment. US 6 215 172 B1 discloses a method for polishing an edge of a chip. DE 102004 027 273 A1 discloses a semiconductor device and a method for manufacturing the same.

[0004] There is a need to solve these problems and / or other problems associated with the prior art and to provide a method in which the remaining functioning part of the chip has a lower scattering loss. SUMMARY

[0005] A method for processing a defective chip according to claim 1 is disclosed. Methods include, among other things, identifying a defective portion of a chip. Furthermore, the defective portion of the chip is physically cut away from a functional portion of the chip. Furthermore, the cut side of the functional portion of the chip is machined to ensure integrity over the chip's operational lifetime. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a flowchart of a method for processing a defective chip according to one embodiment. Fig. 2A illustrates a diagram of a chip with a functional portion and a defective portion according to one embodiment. Fig. Figure 2B illustrates the chip from Fig. 2A, in which the defective portion has been physically cut away from the functional portion according to one embodiment. Fig. Figure 2C shows, according to one embodiment, a reduced-size chip resulting after the cut side of the functional portion of the chip is Fig. 2B was polished. The Fig. 3A-3B show test structures that can be used to determine the area allowance required to implement the method of Fig. 1 is required. DETAILED DESCRIPTION

[0006] Fig. 1 illustrates a flowchart of a method 100 for processing a defective chip according to one embodiment. The method 100 involves physically processing a larger chip identified as having one or more defects. The method 100 may be performed by one or a combination of machines, for example, having cutting and polishing capabilities, as described below.

[0007] The chip can be a graphics processing unit (GPU), for example, with a graphics processing cluster. Of course, the chip can also be any other integrated circuit that can contain repeating subblocks.

[0008] In step 102, a defective portion of the chip is identified. In one embodiment, the defective portion of the chip may comprise one or more adjacent sub-blocks of the repeating sub-blocks. For example, the defective portion may comprise a contiguous portion of the chip (i.e., contiguous sub-blocks) in which one or more defects have been identified. Thus, the defective portion may be a selected region of the chip that includes one or more defects.

[0009] The defective portion of the chip can be identified based on the results of testing the chip. For example, the chip can be tested at the wafer level to find defects on the chip, and then a portion of the chip containing these defects can be identified. Any defect on the chip can typically prevent the chip from functioning as intended.

[0010] Additionally, in step 104, the defective portion of the chip is physically cut away from a functional portion of the chip. The functional portion of the chip may be a different portion of the chip than the defective portion of the chip. Therefore, the functional portion of the chip can function as intended.

[0011] According to the invention, physically cutting away the defective portion of the chip from the functional portion of the chip comprises a laser cut through the chip to cut the defective portion of the chip away from the functional portion of the chip. Depending on the location of the defective portion of the chip relative to the functional portion of the chip, the laser cut may be made vertically or horizontally through the chip. Of course, multiple laser cuts (i.e., vertical and / or horizontal) may be made in this manner to physically separate the defective portion of the chip from the functional portion of the chip. In another embodiment, the physical cutting may comprise sawing off the defective portion of the chip from the functional portion of the chip.

[0012] In another embodiment, the laser cut may be performed in a lane that exists between the defective portion of the chip and the remaining part of the chip. The lane may be a gap of a specific width that exists between two rows or two columns of repeating sub-blocks of the chip. The lane may have been created during chip manufacturing. In another embodiment, the laser cut may be performed in the defective portion of the chip.

[0013] Before physical cutting, the defective portion of the chip and the remaining portion of the chip may be connected by wires extending across the trace. For example, subblocks on both sides of the trace may be connected via the wires. In one embodiment, the trace may include scribe seals with openings through which the wires extend between the defective portion of the chip and the functional portion of the chip.

[0014] It should be noted that the physical cutting can be performed such that the wires are isolated from each other when cut. In other words, the physical cutting, which in one embodiment cuts the above-mentioned wires, can ensure that the cut ends of the wires on the functional portion of the chip are isolated from each other (e.g., are not in contact with each other, which could cause a short circuit of the functional portion of the chip).

[0015] As another option, the physical cutting can be performed in such a way that other wires within the remaining portion of the chip that are not connected to the defective portion of the chip (i.e., that do not extend beyond the trace) remain intact (i.e., are not accidentally cut). It can be ensured that these wires remain intact by performing the physical cut within the trace.

[0016] Furthermore, in step 106, the cut side of the functional portion of the chip is polished. The polishing or grinding may be performed by applying chemical mechanical polishing (CMP) to the cut side of the functional portion of the chip. Polishing may be used to trim back any cut wires exposed at the surface of the cut side of the functional portion of the chip. If the cut is made through the defective portion of the chip, polishing may also bring the cut side of the functional portion of the chip into the path existing between the defective portion of the chip and the functional portion of the chip.

[0017] Optionally, a sealant can also be applied to the polished cut side of the functional portion of the chip. The sealant can "seal" any cut wires exposed on the polished surface of the cut side of the functional portion of the chip. In one embodiment, the sealant can be a passivation layer. Such a passivation layer can optionally be a silicon oxide / silicon nitride stack or stacked silicon oxide / silicon nitride layers.

[0018] To this end, the method 100 can be used to recondition the functional portion of the chip in a manner that differs from the traditional floorsweeping of defective chips. The method 100, as described above, processes the defective chip by physically removing the defective portion of the chip from the functional portion of the chip. The smaller chip resulting from this processing operates at lower power than the original chip (if the original chip were not defective), but also with lower static leakage than the original chip due to the smaller physical size of the smaller chip compared to the original chip.

[0019] As a result of method 100, a reduced-size chip can be provided, which in particular includes a functional portion of a larger chip. The functional portion of the larger chip has a cut side from which a defective portion of the larger chip has been physically cut away. The cut side of the functional portion of the larger chip has also been polished, as previously described.

[0020] In one embodiment, the downsized chip may operate as a GPU. In another embodiment, the functional portion of the larger chip may comprise one or more adjacent sub-blocks from a plurality of repeating sub-blocks of the larger chip. Optionally, the downsized chip may also comprise a sealant applied to the polished cut side of the functional portion of the larger chip, where the sealant may be a passivation layer.

[0021] Further illustrative information will now be presented regarding various optional architectures and features that can be used to implement the above framework, depending on the user's preferences. It should be expressly noted that the following information is for illustrative purposes only and should not be construed as limiting in any way. Each of the following features may be optionally included, with or without the exclusion of other described features.

[0022] Fig. Figure 2A shows, according to one embodiment, a representation of a chip 200 with a functional portion and a defective portion. The chip 200 may be of the type previously described with respect to Fig. 1. In the present embodiment, chip 200 is a GPU. However, the following descriptions may also apply to other types of chips.

[0023] As shown, chip 200 includes a plurality of subblocks GPC0-GPC5 arranged in rows and columns. Each subblock GPC0-GPC5 is a circuit that can operate independently. However, the original chip 200 is designed so that the subblocks GPC0-GPC5 operate in combination with each other (e.g., in parallel) to increase the performance of chip 200.

[0024] A trace (a space) exists between each of the rows and each of the columns. Each trace has a specific width, which is defined by a design of the chip 200 and is formed as part of the chip 200 during the manufacturing of the chip 200. Each trace can be ~50 µm wide and extend across the entire height or width of the chip 200.

[0025] The subblocks GPC0-GPC5 are connected to each other via metal wires, as shown. In each track, only metal connections can be placed between the subblocks GPC0-GPC5, along with simple repeater transistors if necessary. Thus, the subblocks GPC0-GPC5 are entirely present on one side or the other of a track.

[0026] As also illustrated, the chip 200 has multiple defects in a portion of the subblocks GPC0-GPC5, as indicated by the stars. The defects are located in the subblocks GPC3-GPC5 of the right column of the chip 200 in this example. Thus, the defective portion of the chip 200 can be identified as the right column of the chip 200. It should be noted that the defects may be caused by errors in the design of the chip 200 and / or errors in the manufacturing of the chip 200. The defective chip 200 may, as further described in the Fig. 2B-C.

[0027] Fig. 2B shows the chip 200 from Fig. 2A, in which the defective portion has been physically cut away from the functional portion according to one embodiment.

[0028] Once the defective portion of the chip is identified, the defective portion is physically cut away from the remaining (i.e., functional) portion of the chip. Specifically, chip 200 is sawed or laser cut to remove most of the unwanted, defective silicon. Immediately following this process, the edge of chip 200 is frayed and contains a large amount of conductive stray material.

[0029] In the embodiment shown, the cut is made through the sub-blocks present in the defective portion of chip 200. In another embodiment, however, the cut may also be made through the vertical path existing between the left column of sub-blocks and the right column of sub-blocks. However, the cut is made at a certain distance from the functional portion of chip 200 to avoid cracking in the functional portion of chip 200.

[0030] Due to the jagged nature of the cut side of the functional portion of chip 200, the cut side of the functional portion of chip 200 is polished. If the cut is made through the subblocks comprising the defective portion of chip 200, a CMP step can be used to bring the cut edge into the previously described trajectory. In any case, polishing results in a much smoother silicon edge than the jagged edge resulting from the physical cut. The chemical component of this CMP step can include a chemistry that is a mild etchant for Cu / Ti / Ta / Co to push back the interconnect metal at the surface of the cut edge.

[0031] Fig. Figure 2C shows a reduced-size chip 250 resulting after the cut side of the functional portion of the chip is Fig. 2B according to one embodiment. In the illustrated embodiment, the polished cut side is formed in the vertical path originally present between the left and right columns of the sub-blocks.

[0032] In one embodiment (not shown), a passivation layer may be applied to the polished edge. This may be a silicon oxide / silicon nitride stack, or it may be another material applied only to the polished silicon edge.

[0033] The Fig. 3A-B show test structures that can be used to determine the area allowance (i.e., minimum width) required to implement the Fig. 1. In particular, the path must be wide enough to ensure that the processing of the cut and polished edge does not touch the circuitry in the good portion of the chip. However, if this path is too wide, it may not be economically viable to implement this concept, as the area overhead for all chips manufactured with this mask set, including non-defective ones, would be too costly.

[0034] Fig. 3A shows a test chip with a 50 µm wide track according to one embodiment. Fig. 3B shows a test chip with a 10 µm wide track according to another embodiment.

[0035] The Fig. The lines shown in Figures 3A-B are wires within each sub-block and connect the sub-blocks across the track. While the larger track of the Fig. 3A can better insulate the functional portion of the chip from cracks during cutting by providing a larger buffer between the location of the cut and the functional portion of the chip, this larger trace comes at the expense of a larger chip.

[0036] On the other hand, while the smaller track of the Fig. 3B the size of the chip compared to the size that was used with the design in Fig.3A, this smaller trace may increase the possibility of the functional portion of the chip cracking during dicing due to the reduced distance between the cut location and the functional portion of the chip. Based on testing with the test chips, a minimum required trace width may be determined. The chip may then be designed with a trace having the minimum required (or greater) width, balancing the size of the resulting chip with the desire to eliminate the likelihood of cracking when the defective portion of the chip is physically removed from the functional portion of the chip.

Claims

[1] Procedure comprising: Identifying (102) a defective portion of a chip (200); physically cutting (104) the defective portion of the chip (200) from a functional portion of the chip; Polishing (106) a cut side of the functional portion of the chip, wherein the physical cutting (104) of the defective portion of the chip (200) from the functional portion of the chip comprises at least one vertical laser cut or a horizontal laser cut through the chip, wherein the vertical laser cut and / or the horizontal laser cut is performed in the defective portion of the chip. [2] The method of claim 1, wherein the chip (200) is a graphics processing unit (GPU). [3] The method of claim 1 or 2, wherein the chip (200) comprises repeating sub-blocks. [4] The method of claim 3, wherein the defective portion of the chip (200) comprises one or more adjacent sub-blocks of the repeating sub-blocks. [5] A method according to any one of the preceding claims, wherein the defective portion of the chip (200) is identified from results of testing the chip. [6] The method of claim 1, wherein the vertical laser cut and / or the horizontal laser cut is performed in a path existing between the defective portion of the chip (200) and the functional portion of the chip. [7] The method of claim 6, wherein prior to the physical cutting, the defective portion of the chip (200) and the functional portion of the chip are connected by wires extending across the track. [8] The method of claim 1, wherein the polishing brings the cut side of the functional portion of the chip (200) into a trajectory existing between the defective portion of the chip and the functional portion of the chip. [9] A method according to any preceding claim, wherein the physical cutting ensures that wires within the functional portion of the chip (200) that are not connected to the defective portion of the chip remain intact. [10] The method of any preceding claim, wherein polishing the cut side of the functional portion of the chip (200) comprises applying chemical mechanical polishing (CMP) to the cut side of the functional portion of the chip. [11] A method according to any one of the preceding claims, further comprising: Applying a sealant to the polished cut side of the functional portion of the chip (200). [12] The method of claim 11, wherein the sealing agent is a passivation layer. [13] The method of claim 12, wherein the passivation layer is a silicon oxide / silicon nitride stack.

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