HALL EFFECT SENSORS

Abstract

Comprehensive structure: a multitude of Hall effect sampling blocks (20, 30, 40, 50), each of which comprises a multitude of contacts (22a-c, 32a-c, 42a-c, 52a-c); a first switching element connected to a first set of scanning blocks of the plurality of scanning blocks (20, 30, 40, 50); and a second switching element connected to a second set of scanning blocks of the plurality of scanning blocks (20, 30, 40, 50), wherein the scanning blocks (20, 40) of the first set of scanning blocks and the scanning blocks (30, 50) of the second set of scanning blocks are arranged in alternating order, and wherein the first switching element is connected by a wiring (56) to the respective contacts (22a-c, 42a-c) in each of the scanning blocks (20, 240) of the first set of scanning blocks and the second switching element is connected by a wiring (56) to the respective contacts (32a-c, 52a-c) in each of the scanning blocks (30, 50) of the second set of scanning blocks.

Description

AREA OF INVENTION

[0001] The present disclosure relates to semiconductor structures and in particular Hall-effect sensors, manufacturing processes and operating modes. BACKGROUND

[0002] A Hall effect sensor is used to measure the magnitude of a magnetic field. Its output voltage is directly proportional to the magnetic field strength passing through the sensor. Hall effect sensors can be used in many different applications, ranging from proximity sensing and positioning to speed detection and current sensing. In fact, Hall effect sensors are commonly used in the automotive industry to time the speed of wheels and shafts. These include the rotation timing of internal combustion engine ignitions, speedometers, anti-lock braking systems, and brushless DC motors.

[0003] A Hall effect sensor can be configured as four separate 3-contact vertical Hall (3C-Vhall) elements or 5-contact vertical Hall (5C-Vhall) elements. The 3C-Vhall elements are commonly used to achieve better symmetry and improve offset / residual voltage; however, these 3-contact elements suffer from low sensitivity due to a voltage drop in bias feed elements, resulting in a lower applied sensing voltage. The 5C-Vhall element could eliminate the undesired voltage drop, but the device is not symmetrical, resulting in a large offset / residual voltage.

[0004] Hall effect sensors consisting of four separate vertical 3-contact Hall elements are known, for example, from US 2016 / 0 011 281 A1 and US 2015 / 0 115 950 A1. Hall effect sensors consisting of vertical 5-contact Hall elements are known, for example, from US 2019 / 0 025 384 A1. BRIEF SUMMARY

[0005] In one aspect of the disclosure, a structure comprises: a plurality of Hall-effect scanning blocks, each of which comprises a plurality of contacts; a first switching element coupled to a first set of scanning blocks of the plurality of scanning blocks; and a second switching element connected to a second set of scanning blocks of the plurality of scanning blocks, wherein the scanning blocks of the first set of scanning blocks and the scanning blocks of the second set of scanning blocks are arranged in alternating order, and wherein the first switching element is connected by wiring to the respective contacts in each of the scanning blocks of the first set of scanning blocks, and the second switching element is connected by wiring to the respective contacts in each of the scanning blocks of the second set of scanning blocks.

[0006] In one aspect of the disclosure, a structure comprises: a first plurality of Hall-effect scanning blocks, each comprising a plurality of contacts; a second plurality of scanning blocks, each comprising a plurality of contacts; and a fixed connection between the first plurality of scanning blocks and the second plurality of scanning blocks, wherein the first plurality of scanning blocks comprises a first set of scanning blocks and a second set of scanning blocks, the scanning blocks of the first set being arranged in alternating order with the scanning blocks of the second set, the plurality of contacts in the first set of scanning blocks being interconnected by wiring, and the plurality of contacts in the second set of scanning blocks not being interconnected by wiring, and wherein the second plurality of scanning blocks comprises a first set of scanning blocks and a second set of scanning blocks.the scanning blocks of the first set are arranged in alternating order with the scanning blocks of the second set, the plurality of contacts in the first set of scanning blocks are not connected to each other by wiring, and the plurality of contacts in the second set of scanning blocks are connected to each other by wiring.

[0007] In one aspect of the disclosure, a method for operating a Hall-effect sensor structure comprises the following steps: switching on a first switching element for a first sampling block and a third sampling block of the Hall-effect sensor structure, wherein a second switching element for a second sampling block and a fourth sampling block of the Hall-effect sensor structure is switched off; applying a bias voltage between terminals of the first sampling block and the third sampling block; and measuring a voltage drop across the second sampling block and the fourth sampling block. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is described in detail below with reference to the aforementioned multitude of drawings, using non-limiting examples of exemplary embodiments of the present disclosure. Fig. Figure 1 shows a circuit diagram of a Hall effect sensor with switching elements according to aspects of the present disclosure. Fig. 2A and Fig. Figure 2B shows representative examples of the different switching modes of structure 10. Fig. 1. Fig. 3A and Fig. Figure 3B shows cross-sectional views of the structure of Fig. 1 and respective switching modes of Fig. 2A and Fig. 2B, and related manufacturing processes according to aspects of the present disclosure. Fig. Figure 4 shows a circuit diagram of a vertical Hall-effect sensor with fixed connections according to aspects of the present disclosure. DETAILED DESCRIPTION

[0009] This disclosure relates to semiconductor structures, and in particular Hall-effect sensors, fabrication methods, and operating modes. Specifically, this disclosure provides Hall-effect sensors with four vertical 3-contact Hall elements (e.g., scanning blocks) with either fixed or switching / alternating connections. For example, the 3-contact scanning blocks may include a switching gate. Advantageously, by using the switching gate, it is possible to eliminate an undesired voltage drop in a bias feed element to achieve maximum voltage sensitivity (>20%) while maintaining symmetry in the structure to achieve improved offset / residual voltage (>80%). Regarding this latter advantage, the vertical 3-contact Hall elements described herein eliminate an undesired voltage drop in a feed bias.

[0010] The scanning blocks and switching elements of this disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools used are for forming structures with dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to fabricate the scanning blocks and switching elements of this disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films that are patterned on the top surface of a wafer by photolithographic processes.In particular, the manufacturing of the scanning blocks and switching elements uses three basic building blocks: (i) deposition of thin material films onto a substrate, (ii) application of a structured mask to the top of the films by photolithographic imaging, and (iii) etching the films selectively with respect to the mask.

[0011] Fig. Figure 1 shows a circuit diagram of a vertical Hall-effect sensor with switching elements according to aspects of the present disclosure. In particular, the circuit 10 comprises a plurality of scanning blocks (Hall-effect elements) 20, 30, 40, 50 in a sequential order. In embodiments, the scanning blocks 20, 30, 40, 50 each comprise three (3) contacts, e.g., contact pads. In particular, scanning block 20 comprises contact pads 22a, 22b, 22c, scanning block 30 comprises contact pads 32a, 32b, 32c, scanning block 40 comprises contact pads 42a, 42b, 42c, and scanning block 50 comprises contact pads 52a, 52b, 52c. The contact pads in each of the scanning blocks 20, 30, 40, 50 are provided in a respective well 24, 34, 44, 54. In embodiments, the contact pads can be n+ contacts and the wells can be N-type wells. The wells 24, 34, 44, 54 can be fabricated using conventional ion implantation processes, as discussed in more detail herein.

[0012] Referring further to Fig. 1. Each of the scanning blocks 20, 30, 40, 50 can be separated or isolated from one another by a trench insulation structure or a substrate material of a different conductivity type, representatively shown at reference numeral 52. For example, the well 52 can be a P-type well if the respective wells 24, 34, 44, 54 are N-type wells; or vice versa. On the other hand, the trench insulation structure 52 can be an oxide, polysilicon, or other insulating material fabricated using conventional lithography, etching, and deposition techniques, as further described herein.

[0013] In further embodiments, each of the scanning blocks 20, 30, 40, 50 comprises a switching element, e.g., a transistor. For example, scanning blocks 20 and 40 comprise a switching element S1; whereas scanning blocks 30 and 50 comprise a switching element S2. The switching element S1 can be a single switch, and the switching element S2 can be another single switch. The switching elements S1, S2 allow current flow between the scanning blocks 20, 30, 40, 50, as described in relation to Fig. 2A and Fig. 2B described. For example, the switching elements S1, S2 provide a current flow to the respective contacts in each of the respective scanning blocks 20, 30, 40, 50.

[0014] In Fig. 1. The switching elements S1, S2 and their respective contact pads can be connected to each other by a wiring connection 56. For illustration, each respective scanning block 20, 30, 40, 50 is connected in series (e.g., coupled) to the respective contact pads by a wiring connection 56, e.g., contact pad 22b with contact pad 32a, contact pad 32b with contact pad 42a, contact pad 42b with contact pad 52a, etc. The wiring connection 56 also connects the contact pads to the respective switching elements S1, S2.

[0015] Fig. 2A and Fig. Figure 2B shows representative examples of the different switching modes of structure 10. Fig. 1. By using the switching elements, e.g., switching switching elements S1 and S2 on and off, a voltage drop across a bias feed element is eliminated, and the entire voltage drop is concentrated at the sampling terminal to provide maximum voltage sensitivity. Simultaneously, the symmetry of the structure is maintained (e.g., sampling blocks 20 to 40 in a first switching mode and sampling blocks 30 to 50 in a second switching mode).

[0016] For example, and how representative in Fig. As shown in Figure 2A, a bias voltage applied to terminals T1 and T3 is, for example, ground, switching element S1 is switched on, and switching element S2 is switched off. In this way, a current is forced from sampling block 20 to sampling block 40, and a voltage difference between sampling blocks 30 and 50 is sampled. This configuration then provides maximum sensitivity in sampling blocks 30 and 50. On the other hand, as is representatively shown in Fig. As shown in Figure 2B, a bias voltage is applied to terminals T2 or T4, switching element S2 is turned on, and switching element S1 is turned off. In this way, a current is forced from sampling block 30 to sampling block 50, or vice versa, and a voltage difference between sampling blocks 20 and 40 is sampled. This configuration then provides maximum sensitivity in sampling blocks 20 and 40.

[0017] Fig. 3A and Fig. Figure 3B shows cross-sectional views of the structure of Fig. 1 and respective switching modes of Fig. 2A and Fig. 2B, and related manufacturing processes according to aspects of the present disclosure. The arrows in Fig. 2A and Fig. Figures 2B are representative of the current flow during the respective switching modes, as already described herein. Fig. In 3A, the switching element S2 is removed to represent that the switching element S1 is switched on and the switching element S2 is switched off; whereas in Fig. 3B the switching element S1 is removed to show representatively that the switching element S2 is switched on and the switching element S1 is switched off.

[0018] In the process for producing the structure of Fig. 1. How representative in Fig. 3A and Fig. As shown in Figure 3B, wells 24, 34, 44, 54 are formed in a substrate 60 for each respective scanning block 20, 30, 40, 50. The substrate 60 can be a P-type substrate. Wells 24, 34, 44, 54 can be fabricated using conventional ion implantation processes. For example, wells 24, 34, 44, 54 can be formed by introducing a dopant into the substrate 60, for example, by ion implantation. Wells 24, 34, 44, 54 can be formed with a conductivity opposite to that of the substrate 60.

[0019] In the manufacturing process, an implantation mask can be used to define selected areas exposed for the implantation process. The implantation mask used to select the exposed areas, e.g., wells 24, 34, 44, and 54, can comprise a layer of a photosensitive material, such as an organic photoresist, applied by a spin-coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and stopping power sufficient to block masked areas from receiving a dose of the implanted ions. An N-well is doped with n-type dopants, e.g., arsenic (As), phosphorus (P), and Sb; whereas a P-well is doped with p-type dopants, e.g., boron (B), among other suitable examples.

[0020] The contacts can be formed, for example, using a silicide process. The contacts can also be formed using conventional lithography, etching, and deposition techniques known to those skilled in the art. As should be clear to those skilled in the art, the silicide process begins with the deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over ion-implanted regions, e.g., wells 24, 34, 44, 54. After deposition of the material, the structure is heated, allowing the transition metal to react with exposed silicon (or another semiconductor material, as described herein) in the active regions of the semiconductor device (e.g., contact regions of wells 24, 34, 44, 54), forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions (e.g.,Tubs 24, 34, 44, 54) remain. The wiring 56 can be connected to the contact pads and to a voltage source.

[0021] The insulation regions 52 can be either part of the substrate, e.g., doped material of a conductivity type opposite to that of the troughs 24, 34, 44, 54, or a trench insulation structure. The trench insulation structures are formed by conventional lithography, etching, and deposition processes known to those skilled in the art. For example, a resist formed over the substrate 60 is exposed to energy (light) to form a structure (opening). An etching process using selective chemistry, e.g., reactive ion etching (RIE), is used to form one or more trenches in the substrate 60 through the openings of the resist. Following removal of the resist by a conventional oxygen ashing process or other known stripping agents, an insulator material can be deposited by any conventional deposition process, e.g.,Chemical vapor deposition (CVD) processes can be used to remove the remaining material. Any remaining material can be removed by conventional chemical mechanical polishing (CMP) processes.

[0022] The wiring 56 can also be formed by conventional lithography, etching, and deposition. Similar to that of the trench insulation structures, the wiring 56 would be formed by a resist formed over an insulator material above the substrate 60, which is exposed to energy (light) to form a structure (opening). An etching process using a selective chemistry, e.g., RIE, is used to form one or more trenches in the insulator material to expose the contact pads. Following removal of the resist, conductive material can be deposited by any conventional deposition process, e.g., CVD processes. Any remaining material can be removed by conventional chemical-mechanical polishing (CMP) processes.

[0023] The switching elements S1 and S2 can be conventional CMOS (complementary metal-oxide-semiconductor) structures, e.g., transistors. The transistors can be fabricated using any conventional front-end-of-line processes. For example, the conventional CMOS processes can be conventional lithography, etching, and deposition processes known to those skilled in the art, which are used to fabricate switching devices, e.g., transistors. These processes include gate-first or gate-last (e.g., substitute-gate) processes, which are known to those skilled in the art, so that no further explanation is required for a complete understanding of the present disclosure.

[0024] Fig. Figure 4 shows a circuit diagram of a vertical Hall-effect sensor with fixed connections between scanning blocks according to aspects of the present disclosure. In this implementation, the circuit 10a comprises two structures 100a, 100b, each of which includes four scanning blocks with three contacts, as also shown in Figure 4. Fig. 1 shown. In this configuration, the switching elements of Fig. 1 omitted.

[0025] In the Fig.In the configuration shown in Figure 4, contacts 22a, 22b, and 22c of scanning block 20 are connected to each other by wiring 56 in structure 100a. Similarly, contacts 42a, 42b, and 42c of scanning block 40 are connected to each other by wiring 56 in structure 100a. However, contacts 32a, 32b, and 32c of scanning block 30 and contacts 52a, 52b, and 52c of scanning block 50 are not connected to each other by wiring in structure 100a. Conversely, in structure 100b, contacts 22a, 22b, and 22c of scanning block 20a and contacts 42a, 42b, and 42c of scanning block 40a are not connected by wiring. In structure 100b, however, contacts 32a, 32b and 32c of the scanning block 30a and contacts 52a, 52b and 52c of the scanning block 50 are connected to each other by the wiring 56.

[0026] Additionally, the following fixed connections are provided by wiring 56: (i) the sampling block 20 of structure 100a is directly connected to the sampling block 30a of structure 100b; (i) the sampling block 30 of structure 100a is directly connected to the sampling block 40a of structure 100b; (i) the sampling block 40 of structure 100a is directly connected to the sampling block 50a of structure 100b; and (i) the sampling block 50 of structure 100a is directly connected to the sampling block 20a of structure 100b.

[0027] During operation, using the fixed connections, a current can be forced from scanning block 20 to scanning block 40 for the upper device 100a to measure a voltage difference between scanning element 30 / 40a and scanning element 50 / 20a. It should be noted that terminals 30 and 40a are the same terminal in this case because they are electrically connected. Similarly, 50 and 20a are the same terminal when electrically connected. In this way, the scanning blocks of each structure 100a and 100b are connected to form a symmetrical structure for higher sensitivity, directly eliminating any offset voltage without using the switching elements.

[0028] The vertical 3-contact Hall elements can be used in system-on-a-chip (SoC) technology. It should be clear to those in the know that an SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume far less power and occupy much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in mobile computing (such as in smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things (IoT).

[0029] The process(s) described above is / are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as bare die chips, or in a packaged form. In the latter case, the chip is mounted in a single-chip assembly (such as a plastic substrate with conductors attached to a motherboard or other higher-level support) or in a multi-chip assembly (such as a ceramic substrate having one or both surface interconnects or buried interconnects). In each case, the chip is then integrated with other chips, discrete switching elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that feature a display, a keyboard or other input device, and a central processor.

[0030] The descriptions of the various embodiments of the present disclosure are presented for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to those skilled in the art without altering the scope and concept of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application or technical improvement over commercially available technologies, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

[1] Structure encompassing: a multitude of Hall effect sampling blocks (20, 30, 40, 50), each of which comprises a multitude of contacts (22a-c, 32a-c, 42a-c, 52a-c); a first switching element connected to a first set of scanning blocks of the plurality of scanning blocks (20, 30, 40, 50); and a second switching element connected to a second set of scanning blocks of the plurality of scanning blocks (20, 30, 40, 50), wherein the scanning blocks (20, 40) of the first set of scanning blocks and the scanning blocks (30, 50) of the second set of scanning blocks are arranged in alternating order, and wherein the first switching element is connected by a wiring (56) to the respective contacts (22a-c, 42a-c) in each of the scanning blocks (20, 240) of the first set of scanning blocks and the second switching element is connected by a wiring (56) to the respective contacts (32a-c, 52a-c) in each of the scanning blocks (30, 50) of the second set of scanning blocks. [2] Structure according to claim 1, wherein the plurality of scanning blocks (20, 30, 40, 50) are four scanning blocks (20, 30, 40, 50) each comprising three contacts (22a-c, 32a-c, 42a-c, 52a-c). [3] Structure according to claim 1 or 2, wherein one of the contacts (22a-c, 32a-c, 42a-c, 52a-c) within each scanning block (20, 30, 40, 50) is connected to a bias voltage. [4] Structure according to claim 2 or 3, wherein each of the scanning blocks (20, 30, 40, 50) is connected in series to another by a wiring (56). [5] Structure according to any one of claims 1 to 4, wherein each of the scanning blocks (20, 30, 40, 50) comprises wells (24, 34, 44, 54) which are isolated from each other. [6] Structure according to any one of claims 1 to 5, wherein the first switching element is different from the second switching element. [7] Structure according to claim 1, wherein the first switching element is connected to a first scanning block (20) and a third scanning block (40), and the second switching element is connected to a second scanning block (30) and a fourth scanning block (50), and the first to fourth scanning blocks (20, 30, 40, 50) are in a sequential order. [8] Structure according to claim 7, wherein: when the first switching element is switched on and the second switching element is switched off, a current is forced from the first scanning block (20) to the third scanning block (40) or from the third scanning block (40) to the first scanning block (20), and a voltage difference between the second scanning block (30) and the fourth scanning block (50) is sampled. [9] Structure according to claim 7, wherein: when the second switching element is switched on and the first switching element is switched off, a current is forced from the second scanning block (30) to the fourth scanning block (50) or a current is forced from the fourth scanning block (50) to the second scanning block (30), and a voltage difference between the first scanning block (20) and the third scanning block (40) is sampled. [10] Structure encompassing: a first plurality of Hall effect sampling blocks (20, 30, 40, 50), each of which comprises a plurality of contacts (22a-c, 32a-c, 42a-c, 52a-c); a second set of scanning blocks (20a, 30a, 40a, 50a), each of which comprises a set of contacts (22a-c, 32a-c, 42a-c, 52a-c); and a fixed connection between the first set of sample blocks (20, 30, 40, 50) and the second set of sample blocks (20a, 30a, 40a, 50a), wherein the first plurality of scanning blocks (20, 30, 40, 50) comprises a first set of scanning blocks and a second set of scanning blocks, the scanning blocks of the first set being arranged in alternating order with the scanning blocks of the second set, the plurality of contacts in the first set of scanning blocks being interconnected by a wiring (56), and the plurality of contacts in the second set of scanning blocks not being interconnected by a wiring (56), and wherein the second plurality of scanning blocks (20a, 30a, 40a, 50a) comprises a first set of scanning blocks and a second set of scanning blocks, the scanning blocks of the first set being arranged in alternating order with the scanning blocks of the second set, the plurality of contacts in the first set of scanning blocks not being connected to each other by a wiring (56), and the plurality of contacts in the second set of scanning blocks being connected to each other by a wiring (56). [11] Structure according to claim 10, wherein the first plurality of scanning blocks (20, 30, 40, 50) are four scanning blocks and the second plurality of scanning blocks (20a, 30a, 40a, 50a) are four scanning blocks. [12] Structure according to one of claims 10 or 11, wherein the plurality of contacts (22a-c, 32a-c, 42a-c, 52a-c) comprise three contacts which are provided for each scanning block of the first plurality of scanning blocks (20, 30, 40, 50) and the second plurality of scanning blocks (20a, 30a, 40a, 50a). [13] Structure according to claim 10, wherein: the first set of sampling blocks of the first plurality of sampling blocks (20, 30, 40, 50) and the first set of sampling blocks of the second plurality of sampling blocks (20a, 30a, 40a, 50a) are the first and third sampling blocks (20, 40; 20a, 40a); and the second set of sampling blocks of the first plurality of sampling blocks (20, 30, 40, 50) and the second set of sampling blocks of the second plurality of sampling blocks (20a, 30a, 40a, 50a) are the second and fourth sampling blocks respectively (30, 50; 30a, 50a). [14] Structure according to claim 13, wherein: the first sampling block (20) of the first plurality of sampling blocks (20, 30, 40, 50) is connected to the second sampling block (30a) of the second plurality of sampling blocks (20a, 30a, 40a, 50a); the second sampling block (30) of the first plurality of sampling blocks (20, 30, 40, 50) is connected to the third sampling block (40a) of the second plurality of sampling blocks (20a, 30a, 40a, 50a); the third sampling block (40) of the first plurality of sampling blocks (20, 30, 40, 50) is connected to the fourth sampling block (50a) of the second plurality of sampling blocks (20a, 30a, 40a, 50a); and the fourth sampling block (50) of the first plurality of sampling blocks (20, 30, 40, 50) is connected to the first sampling block (20a) of the second plurality of sampling blocks (20a, 30a, 40a, 50a). [15] Structure according to any one of claims 10 to 14, wherein: the first set of sampling blocks (20, 30, 40, 50) are connected in series; and the second set of sample blocks (20a, 30a, 40a, 50a) are connected in series. [16] Structure according to any one of claims 10 to 15, wherein each of the scanning blocks of the first plurality of scanning blocks (20, 30, 40, 50) and of the second plurality of scanning blocks (20a, 30a, 40a, 50a) comprises troughs which are isolated from each other. [17] Structure according to claim 16, wherein the troughs are isolated from each other by a substrate material which is a conductivity type different from that of the troughs. [18] Method for operating a Hall effect sensor comprising the structure according to any one of claims 1 to 10, wherein the method comprises: Switching on the first switching element for a first scanning block (20) and a third scanning block (40) of the structure, wherein the second switching element for a second scanning block (30) and a fourth scanning block (40) of the structure is switched off; Applying a bias voltage between a terminal of the first sampling block (20) and the third sampling block (40); and Measuring a voltage drop across the second sampling block (30) and the fourth sampling block (50).

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