semiconductor device

Abstract

semiconductor device, comprising: - a semiconductor substrate (1) having an upper surface and a lower surface opposite to each other, and a drift layer (4) of a first conductivity type formed between the upper surface and the lower surface; - a base layer (5) of a second conductivity type formed between the drift layer (4) and the upper surface; - an emitter layer (6) of the first conductivity type and a contact layer (7) of the second conductivity type formed between the base layer (5) and the upper surface; - an active trench (8) penetrating the emitter layer (6) and the base layer (5) from the upper surface; - dummy trenches (9) sandwiching the active trench (8) and penetrating the contact layer (7) and the base layer (5) from the upper surface; - a trench gate electrode (10) formed in the active trench (8) with a gate insulating film (11) interposed therebetween; - a dummy trench gate electrode (12) formed in each of the dummy trenches (9) with a gate insulating film (11) interposed therebetween; - an embedded insulating film (13) formed on the trench gate electrode (10) in the active trench (8), formed on the dummy trench gate electrode (12) in the dummy trench (9) and having an upper end lower than the upper surface; - an emitter electrode (14) contacting the emitter layer (6) on the upper surface and on an inner wall of the active trench (8) and contacting the contact layer (7) on the upper surface and on an inner wall of the dummy trench (9); and - polysilicon (23) formed on the trench gate electrode (10) in the active trench (8) with the embedded insulating film (13) arranged therebetween and connected to the emitter electrode (14), wherein an upper end of the polysilicon (23) is lower than the upper surface.

Description

Background of the inventionArea

[0001] The present invention relates to a semiconductor device. background

[0002] From the perspective of energy saving, an IGBT and a diode have been used for a power module or the like for performing various speed controls of a three-phase motor, for example, in a general-purpose inverter / AC servo device. To reduce inverter loss, a device with low switching loss and low on-voltage has been required for the IGBT and diode.

[0003] Examples of a low switching loss device include a trench-gate type IGBT. In a trench-gate type IGBT, an IE effect is enhanced by narrowing the width of a mesa sandwiched between trench gates, so that the on-voltage can be reduced. However, the narrower the mesa width is made, the narrower the width of a contact hole for connecting an emitter electrode to an emitter layer and a contact layer becomes. Therefore, microfabrication is required, and the mesa cannot be easily miniaturized. On the other hand, a structure has been proposed in which an embedded insulating film is formed on a trench gate electrode in a trench (see, for example, Japanese Patent Application JP 2015-188104 A).As a result, the emitter electrode can be connected to the emitter layer and the contact layer without forming an interlayer insulating film and the contact hole. Accordingly, the mesa can be easily miniaturized.

[0004] US 2019 / 0 006 497 A1 relates to a semiconductor device comprising a semiconductor layer of a first conductivity type, a base region of a second conductivity type arranged in the front surface portion of the semiconductor layer, a plurality of trenches extending from a front surface of the semiconductor layer beyond a lower portion of the base region, with an active region defined therebetween, a plurality of emitter regions of a first conductivity type arranged in the active region and each connecting the adjacent trenches, a gate electrode embedded in the trench, an embedding insulating film embedded in the trench on the gate electrode and having an upper surface at the same height position as the front surface of the semiconductor layer or at a height position lower than the front surface, and an emitter electrode,which covers the active region and the embedding insulating film and is electrically connected to the base region and the emitter region.

[0005] GB 2 347 014 A shows a semiconductor device having a drain region, a body region overlying the drain region and defining a top surface, source regions extending from the top surface of the body region towards the drain region, and a series of recesses extending into and through the body region such that the lower sidewalls of each recess are defined by parts of the body region and the drain regions and the upper sidewalls of each recess are defined by the source region. A lower part of each recess is filled with a gate region insulated from the sidewalls by a first insulating layer and covered by a second insulating layer. A source conductor overlies the top surface and is electrically connected to the source regions, and a gate conductor is electrically connected to each gate region.The source conductor extends into the entire upper part of each well to contact portions of the upper sidewalls of the well defined by the source regions.

[0006] JP 2016-174029 A describes a semiconductor device that enables a reduction in recovery loss. The semiconductor device includes a diode part having an anode region of the first conductivity type provided on a first surface of a semiconductor substrate having the first surface and a second surface opposite the first surface, a cathode region of the second conductivity type provided on the second surface, and a drift region of the second conductivity type provided between the anode region and the cathode region and having a concentration of an impurity of the second conductivity type lower than that of the cathode region.and an IGBT part provided on the first surface and having a plurality of emitter regions of the second conductivity type with an areal density on the first surface decreasing toward the diode part, a collector region of the first conductivity type provided on the second surface, a base region of the first conductivity type provided between the emitter region and the collector region, and a drift region provided between the base region and the collector region;

[0007] US 2009 / 0 008 709 A1 relates to a semiconductor power device comprising a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite to the first conductivity type, and active trenches extending through the well region and into the drift region, the active trenches defining an active area. Formed within each of the active trenches are a first conductive gate electrode arranged along and insulated from a first trench sidewall, a second conductive gate electrode arranged along and insulated from a second trench sidewall, and a conductive shield electrode arranged between the first and second conductive gate electrodes, the shield electrode being insulated from and extending deeper into the trench than the first and second conductive gate electrodes.The device further includes source regions having the first conductivity type formed within the well region and adjacent to the active trenches. Electrical contact with the conductive shield electrode can be made within the active area. The device may further include a perimeter trench extending at least partially around the active trenches such that at least some of the active trenches are perpendicular to the perimeter trench, gate fingers extending from a perimeter gate poly runner located in the perimeter trench, and shield poly fingers extending from a perimeter shield poly runner located in the perimeter trench. The gate fingers are offset with respect to the shield poly fingers.

[0008] JP 2008-021918 A discloses a semiconductor device that can improve destruction resistance. The semiconductor device comprises a first electrically conductive collector layer; a second electrically conductive semiconductor layer formed on the collector layer; a first electrically conductive base region formed on the surface of a semiconductor layer; a second electrically conductive emitter region formed in a part of the surface of the base region; a first trench dug from the surface of the emitter region to the semiconductor layer; a first gate electrode embedded in the first trench via the first insulating film; a second trench dug from the surface of the base region excluding the emitter region to the semiconductor layer; a second gate electrode embedded in the second trench via the second insulating film.an emitter electrode connected to the base region and the emitter region; and a collector electrode connected to the collector layer, wherein the second trench is deeper than the first trench. Summary

[0009] However, the deeper a top end of the trench gate electrode becomes, the deeper the emitter layer needs to be made. Accordingly, the length in an up-down direction of a base layer decreases. A hole current flowing from a collector flows through a base layer in a transverse direction at the time of turn-off. When the length of the base layer is short, a resistance of a hole current path increases accordingly, and a potential of the base layer increases. As a result, an NPN transistor formed by an emitter layer, a base layer, and a drift layer operates, and a parasitic thyristor formed by an emitter layer, a base layer, a drift layer, and a collector layer is in a latch-up state, resulting in device destruction. Accordingly, there has been a problem that a latch-up tolerance deteriorates.

[0010] The present invention has been made to solve the above-described problem and is directed to obtaining a semiconductor device that makes miniaturization of a mesa easy and has a high latch-up tolerance.

[0011] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims

[0012] A semiconductor device according to the present invention comprises: a semiconductor substrate having an upper surface and a lower surface opposite to each other, and a drift layer of a first conductivity type formed between the upper surface and the lower surface; a base layer of a second conductivity type formed between the drift layer and the upper surface; an emitter layer of the first conductivity type and a contact layer of the second conductivity type formed between the base layer and the upper surface; an active trench penetrating the emitter layer and the base layer from the upper surface; dummy trenches sandwiching the active trench and penetrating the contact layer and the base layer from the upper surface; a trench gate electrode formed in the active trench with a gate insulating film interposed therebetween.a dummy trench gate electrode formed in each of the dummy trenches with a gate insulating film interposed therebetween; an embedded insulating film formed on the trench gate electrode in the active trench, formed on the dummy trench gate electrode in the dummy trench and having an upper end lower than the upper surface; and an emitter electrode contacting the emitter layer on the upper surface and at an inner wall of the active trench and contacting the contact layer on the upper surface and at an inner wall of the dummy trench.

[0013] The semiconductor device according to the invention further comprises polysilicon formed on the trench gate electrode in the active trench with the embedded insulating film therebetween and connected to the emitter electrode, an upper end of the polysilicon being lower than the upper surface.

[0014] In the present invention, the embedded insulating film is formed on the trench gate electrode in the active trench. As a result, the emitter electrode can be connected to the emitter layer and the contact layer without forming an interlayer insulating film and a contact hole. Accordingly, a mesa can be easily miniaturized. The contact layer not only contacts the emitter electrode on the upper surface of the semiconductor substrate but also contacts the emitter electrode on the inner wall of the dummy trench. Therefore, at the time of shutdown, holes are drained into the emitter electrode from not only the upper surface of the semiconductor substrate but also the inner wall of the dummy trench. Accordingly, holes are easily drained, so that a latch-up tolerance increases.

[0015] Other and further objects, features and advantages of the invention and its further technical background will appear more fully from the following description. Short description of the drawings Fig. 1 is a plan view illustrating a semiconductor device according to a first embodiment for explaining further technical background of the present invention. Fig. 2 is one along a Fig. 1 illustrated cross-sectional view taken along line I - II. Fig. 3 is one along a Fig. 1 illustrated cross-sectional view taken along line III - IV. Fig. 4 is one along a Fig. 1 illustrated cross-sectional view taken along line V - VI. Fig. 5 is a cross-sectional view illustrating a semiconductor device according to a second embodiment for explaining further technical background of the present invention. Fig. 6 is a cross-sectional view illustrating a semiconductor device according to a third embodiment for explaining further technical background of the present invention. Fig. 7 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment for explaining further technical background of the present invention. Fig. 8 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention. Fig. 9 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment for explaining further technical background of the present invention. Fig. 10 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment for explaining further technical background of the present invention. Fig. 11 is a cross-sectional view illustrating a semiconductor device according to an eighth embodiment for explaining further technical background of the present invention. Description of embodiments

[0016] With reference to the drawings, a semiconductor device according to embodiments of the present invention will be described to explain the further technical background of the present invention. The same components are denoted by the same symbols, and repeated descriptions thereof may be omitted. First embodiment for further technical background

[0017] Fig. Figure 1 is a plan view illustrating a semiconductor device according to a first embodiment for explaining further technical background of the present invention. A semiconductor substrate 1 has, in plan view, an active region 2 and a wiring region 3. Fig. 1, for example, an electrode and an interlayer insulating film on the substrate are omitted.

[0018] Fig. 2 is one along a Fig. 1. The semiconductor substrate 1 has an upper surface and a lower surface as opposite main surfaces, and a drift layer 4 of a first conductivity type formed between the upper surface and the lower surface. A base layer 5 of a second conductivity type is formed between the drift layer 4 and the upper surface of the semiconductor substrate 1. For example, the first conductivity type is n-type and the second conductivity type is p-type. An emitter layer 6 of the first conductivity type and a contact layer 7 of the second conductivity type are formed between the base layer 5 and the upper surface of the semiconductor substrate 1.

[0019] Active trenches 8 penetrate the emitter layer 6 and the base layer 5 from the top surface of the semiconductor substrate 1 to reach the drift layer 4. Therefore, the emitter layer 6 is formed on both sides of each of the active trenches 8. Dummy trenches 9 penetrate the contact layer 7 and the base layer 5 from the top surface of the semiconductor substrate 1 to reach the drift layer 4. Therefore, the contact layer 7 is formed on both sides of each of the dummy trenches 9.

[0020] The active trenches 8 and the dummy trenches 9 are arranged parallel to each other in plan view. One active trench 8 is sandwiched between the two dummy trenches 9. Therefore, the two active trenches 8 are not adjacent to each other. Accordingly, the emitter layer 6 does not touch the two active trenches 8.

[0021] A trench gate electrode 10 is formed in each of the active trenches 8, with a gate insulating film 11 interposed therebetween. A dummy trench gate electrode 12 is formed in each of the dummy trenches 9, with a gate insulating film 11 interposed therebetween. An embedded insulating film 13 is formed on the trench gate electrode 10 in the active trench 8 and is formed on the dummy trench gate electrode 12 in the dummy trench 9.

[0022] With respect to the upper surface of the semiconductor substrate 1, when D1 is a depth to an upper end of the embedded insulating film 13, D2 is a depth to respective upper ends of the trench gate electrode 10 and the dummy trench gate electrode 12, D3 is a depth to a lower end of the emitter layer 6, and D4 is a depth to a lower end of the contact layer 7, 0 < D1 < D2 < D3 < D4 holds. Since the upper end of the embedded insulating film 13 is deeper than the upper surface of the semiconductor substrate 1 (0 < D1), the contact layer 7 contacts an emitter electrode 14 even at an inner wall of the dummy trench 9.

[0023] The emitter electrode 14 contacts the emitter layer 6 on the upper surface of the semiconductor substrate 1 and an inner wall of the active trench 8, and contacts the contact layer 7 on the upper surface of the semiconductor substrate 1 and an inner wall of the dummy trench 9. A buffer layer 15 of the first conductivity type is formed under the drift layer 4. A collector layer 16 of the second conductivity type is formed under the buffer layer 15. A collector electrode 17 is connected to the collector layer 16.

[0024] As described above, in the present embodiment, the embedded insulating film 13 is formed on the trench gate electrode 10 in the active trench 8. As a result, the emitter electrode 14 can be connected to the emitter layer 6 and the contact layer 7 without forming an interlayer insulating film and a contact hole. Accordingly, a mesa can be easily miniaturized.

[0025] The contact layer 7 not only contacts the emitter electrode 14 on the upper surface of the semiconductor substrate 1, but also contacts the emitter electrode 14 on the inner wall of the dummy trench 9. Therefore, at the time of shutdown, holes are drained from not only the upper surface of the semiconductor substrate 1 but also the inner wall of the dummy trench 9 into the emitter electrode 14. Accordingly, holes are easily drained, so that a latch-up tolerance increases.

[0026] The lower end of contact layer 7 is located lower than the lower end of emitter layer 6 (D3 < D4). Accordingly, holes are easily diverted into contact layer 7 at the time of turn-off, thus increasing latch-up tolerance.

[0027] A region between the active trench 8 and the dummy trench 9, which are adjacent to each other, is referred to as an active mesa. Where W1 is the width of the active mesa, W2 is the width of the emitter layer 6 exposed at the top surface of the semiconductor substrate 1, and W3 is the width of the contact layer 7 exposed at the top surface of the semiconductor substrate 1, W1 = W2 + W3. In the active mesa, the width W3 of the contact layer 7 exposed at the top surface is larger than the width W2 of the emitter layer 6 exposed at the top surface (W3 > W2). As a result, a cross-sectional area of ​​the contact layer 7 is configured to be larger than that of the emitter layer 6 to expand a path for draining holes. As a result, a latch-up tolerance increases.

[0028] A first conductivity type charge storage layer 18 is formed between the drift layer 4 and the base layer 5. The impurity concentration of the charge storage layer 18 is higher than that of the drift layer 4. Electron injection through the charge storage layer 18 increases, and a charge carrier density in the drift layer 4 increases. Accordingly, an on-voltage is reduced.

[0029] The width of the emitter layer 6 narrows toward the lower surface of the semiconductor substrate 1 from its upper surface. As a result, the path for draining holes is expanded, so that latch-up tolerance can be improved.

[0030] Fig. 3 is one along a Fig. 1. In the wiring region 3, a well layer 19 of the second conductivity type is formed between the drift layer 4 and the upper surface of the semiconductor substrate 1. A gate electrode 21 is formed on the upper surface of the semiconductor substrate 1 with an interlayer insulating film 20 interposed therebetween. The embedded insulating film 13 is not formed in each of the active trenches 8, and an upper end of the trench gate electrode 10 is exposed on the upper surface of the semiconductor substrate 1. The trench gate electrode 10 is connected to the gate electrode 21 via an opening of the interlayer insulating film 20. As a result, the trench gate electrode 10 and the gate electrode 21 can be connected to each other without embedding a gate electrode 21 in the active trench 8.

[0031] Fig. 4 is one along a Fig. 1. In a part of the active region 2, the embedded insulating film 13 is not formed in each of the dummy trenches 9, and the upper end of the dummy trench gate electrode 12 is exposed on the upper surface of the semiconductor substrate 1 and connected to the emitter electrode 14. As a result, the dummy trench gate electrode 12 and the emitter electrode 14 can be connected to each other without embedding the emitter electrode 14 deeply into the dummy trench 9.

[0032] The emitter electrode 14 is made of a metal such as Al or AlSi. A barrier metal may be formed between the emitter electrode 14 and the emitter layer 6 and between the emitter electrode 14 and the contact layer 7. The barrier metal may be made of Ti, TiN, or TiSi, for example. A plug made of W or the like may be formed. Second embodiment for further technical background

[0033] Fig. 5 is a cross-sectional view illustrating a semiconductor device according to a second embodiment for explaining further technical background of the present invention. A region between dummy trenches 9 adjacent to each other without an active trench 8 being sandwiched therebetween is referred to as a dummy mesa. In the present embodiment, in the dummy mesa, an interlayer insulating film 20 is formed between an upper surface of a semiconductor substrate 1 and an emitter electrode 14 so that the semiconductor substrate 1 and the emitter electrode 14 are insulated from each other. As a result, holes can be prevented from coming from an upper part of the dummy mesa, and a carrier density in a drift layer 4 increases. Accordingly, an on-voltage is reduced. Third embodiment for further technical background

[0034] Fig. 6 is a cross-sectional view illustrating a semiconductor device according to a third embodiment for explaining further technical background of the present invention. In the present embodiment, the width of a dummy trench 9 is larger than the width of an active trench 8. Accordingly, the width of a dummy mesa decreases. The depth of the dummy trench 9 is larger than the depth of the active trench 8. As a result, holes can be prevented from coming from an upper part of the dummy mesa, and a carrier density in a drift layer 4 increases. Accordingly, an on-voltage is reduced. Fourth embodiment for further technical background

[0035] Fig. 7 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment for explaining further technical background of the present invention. In the present embodiment, a shield electrode 22 is formed under a trench gate electrode 10 in an active trench 8. The shield electrode 22 is connected to an emitter electrode 14. The trench gate electrode 10 and the shield electrode 22 are insulated from each other by an insulating film. An upper end of the shield electrode 22 is lower than a lower end of a base layer 5. As a result, a parasitic capacitance of the trench gate electrode 10 can be reduced. Fifth and inventive embodiment

[0036] Fig. 8 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention. Polysilicon 23 is formed on a trench gate electrode 10 with an embedded insulating film 13 interposed therebetween in an active trench 8. The polysilicon 23 is connected to an emitter electrode. An upper end of the polysilicon 23 is lower than an upper surface of a semiconductor substrate 1. In general, an embedding property of polysilicon is better than that of an insulating film. Accordingly, the embedding property in an upper part of the active trench 8 can be improved. Sixth embodiment for further technical background

[0037] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment for explaining further technical background of the present invention. In the present embodiment, the trench gate electrode 10 includes a first portion 10a in an active trench 8 and a second portion 10b protruding upward from an upper surface of a semiconductor substrate 1 in a part of a wiring portion 3. The second portion 10b is connected to a gate electrode 21 via an opening of an interlayer insulating film 20. The width of the second portion 10b is larger than that of the first portion 10a. As a result, even if a position or a dimension of the opening of the interlayer insulating film 20 varies, the opening is easily formed in a portion of the second portion 10b.Therefore, the probability that the opening of the interlayer insulating film 20 shifts so that the gate electrode 21 and the semiconductor substrate 1 contact each other decreases. Accordingly, an insulating property can be enhanced. Seventh embodiment for further technical background

[0038] Fig. 10 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment for explaining further technical background of the present invention. In the present embodiment, the width of an active trench 8 in a wiring region 3 is larger than the width of the active trench 8 in an active region 2. In this region, a trench gate electrode 10 and a gate electrode 21 are connected to each other via an opening of an embedded insulating film 13. As a result, the opening of the embedded insulating film 13 can be enlarged. Accordingly, an embedding property of the gate electrode 21 into the opening can be improved. Eighth embodiment for further technical background

[0039] Fig.11 is a cross-sectional view illustrating a semiconductor device according to an eighth embodiment for explaining further technical background of the present invention. In the present embodiment, the width of a dummy trench 9 is larger than that of an active trench 8 in a part of an active region 2. In the region, the dummy trench gate electrode 12 is connected to an emitter electrode 14 via an opening of an embedded insulating film 13. By thus increasing the width of the dummy trench 9, an embedding property of a metal between the dummy trench gate electrode 12 and the emitter electrode 14 can be improved.

[0040] In the embodiment described above, a case where the semiconductor device is an insulated gate bipolar transistor (IGBT) was described. A configuration according to the present invention is not limited to this, but is applicable to a power device such as a MOSFET or an RC-IGBT. A withstand voltage class and an FZ substrate / MCZ substrate / epitaxial substrate, for example, are not limited. A combination of various embodiments is also possible, and a configuration according to the other embodiment can be partially used for a specific field.

[0041] The semiconductor substrate 1 is not limited to a substrate formed of silicon, but may instead be formed of a wide-bandgap semiconductor having a wider bandgap than that of silicon. The wide-bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A semiconductor device formed of such a wide-bandgap semiconductor has high withstand voltage and high allowable current density and can thus be miniaturized. The use of such a miniaturized semiconductor device enables miniaturization and high integration of the semiconductor module in which the semiconductor device is incorporated.Furthermore, since the semiconductor device has high heat resistance, a radiating fin of a heat sink can be miniaturized, and a water-cooled part can be air-cooled, leading to further miniaturization of the semiconductor module. Furthermore, since the semiconductor device has low power loss and high efficiency, a highly efficient semiconductor module can be achieved.

Claims

[1] Semiconductor device, comprising: - a semiconductor substrate (1) having an upper surface and a lower surface opposite to each other, and a drift layer (4) of a first conductivity type formed between the upper surface and the lower surface; - a base layer (5) of a second conductivity type formed between the drift layer (4) and the upper surface; - an emitter layer (6) of the first conductivity type and a contact layer (7) of the second conductivity type formed between the base layer (5) and the upper surface; - an active trench (8) penetrating the emitter layer (6) and the base layer (5) from the upper surface; - dummy trenches (9) sandwiching the active trench (8) and penetrating the contact layer (7) and the base layer (5) from the upper surface; - a trench gate electrode (10) formed in the active trench (8) with a gate insulating film (11) interposed therebetween; - a dummy trench gate electrode (12) formed in each of the dummy trenches (9) with a gate insulating film (11) interposed therebetween; - an embedded insulating film (13) formed on the trench gate electrode (10) in the active trench (8), formed on the dummy trench gate electrode (12) in the dummy trench (9) and having an upper end lower than the upper surface; - an emitter electrode (14) contacting the emitter layer (6) on the upper surface and on an inner wall of the active trench (8) and contacting the contact layer (7) on the upper surface and on an inner wall of the dummy trench (9); and - polysilicon (23) formed on the trench gate electrode (10) in the active trench (8) with the embedded insulating film (13) arranged therebetween and connected to the emitter electrode (14), wherein an upper end of the polysilicon (23) is lower than the upper surface. [2] A semiconductor device according to claim 1, wherein a lower end of the contact layer (7) is lower than a lower end of the emitter layer (6). [3] A semiconductor device according to any one of the preceding claims, wherein in a region between the active trench (8) and the dummy trench (9) which are adjacent to each other, a width (W3) of the contact layer (7) exposed at the upper surface is larger than a width (W2) of the emitter layer (6) exposed at the upper surface. [4] A semiconductor device according to any one of the preceding claims, wherein a width of the emitter layer (6) narrows from the upper surface toward the lower surface. [5] A semiconductor device according to any one of the preceding claims, further comprising a carrier storage layer (18) of the first conductivity type formed between the drift layer (4) and the base layer (5) and having a higher impurity concentration than that of the drift layer (4). [6] A semiconductor device according to any one of the preceding claims, wherein an insulating film is formed between the upper surface and the emitter electrode (14) in a region between adjacent dummy trenches (9). [7] A semiconductor device according to any one of the preceding claims, wherein: - a width of the dummy trench (9) is greater than a width of the active trench (8) and - a depth of the dummy trench (9) is greater than a depth of the active trench (8). [8] Semiconductor device according to one of the preceding claims, further comprising a shielding electrode (22) formed under the trench gate electrode (10) in the active trench (8) and connected to the emitter electrode (14), wherein an upper end of the shielding electrode (22) is lower than a lower end of the base layer (5). [9] A semiconductor device according to any one of the preceding claims, wherein: - the semiconductor substrate (1) has an active region (2) and a wiring region (3) in plan view, - the emitter electrode (14) is formed on the upper surface in the active region (2), - a gate electrode (21) is formed on the upper surface with an interlayer insulating film (20) arranged therebetween in the wiring region (3), - the trench gate electrode (10) is connected to the gate electrode (21) via an opening of the interlayer insulating film (20). [10] The semiconductor device according to claim 9, wherein the trench gate electrode (10) has a first portion (10a) in an active trench (8) and a second portion (10b) projecting upward from the upper surface in a part of the wiring region (3), connected to the gate electrode (21) via the opening, and having a width greater than that of the first portion (10a). [11] The semiconductor device according to claim 9 or 10, wherein a width of the active trench (8) in a part of the wiring region (3) is larger than a width of the active trench (8) in the active region (2). [12] A semiconductor device according to any one of claims 9 to 11, wherein in a part of the active region (2), an upper end of the dummy trench gate electrode (12) is exposed at the upper surface and is connected to the emitter electrode (14). [13] A semiconductor device according to claim 12, wherein in a part of the active region (2), a width of a dummy trench (9) is larger than that of an active trench (8), and the dummy trench gate electrode (12) is connected to the emitter electrode (14) via an opening of the embedded insulating film (13). [14] A semiconductor device according to any one of the preceding claims, wherein the semiconductor substrate (1) is made of a wide band gap semiconductor.

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