MOUNTING A CHIP TO A SUBSTRATE

Abstract

Procedure (1200; 1300; 1400; 1500); showing: Dispensing (802; 1207) of at least two blobs of a volatile sticky adhesive (410; 1208) between a semiconductor chip (301; 401; 1101) and an organic laminate substrate (303; 403; 1103); at a bonding temperature (512; 612; 712; 812; 1209; 1309) bonding the semiconductor chip to the organic laminate substrate using solder, wherein an evaporation temperature of the volatile sticky adhesive is selected such that it is in a range of one to not more than ten degrees C lower than a solidus temperature of the solder used to bond the semiconductor chip to the organic laminate substrate, and / or that after bonding the semiconductor chip to the organic laminate substrate, nothing of the volatile sticky adhesive remains; without intermediate cooling from the bonding temperature to room temperature, dispensing (814; 1210) of underfill (815; 1211) between the semiconductor chip and the organic laminate substrate at an underfill dispensing temperature; and Hardening (814; 1210) of the underfill within a temperature range above the underfill dispensing temperature.

Description

BACKGROUND

[0001] The present invention relates to the fields of electrical engineering, electronics and computer science, in particular the assembly of chip packages for integrated circuits (ICs).

[0002] It is well known that the miniaturization of IC technology is progressing rapidly. The most recent technological milestone is the 5 nm (nanometer) transistor scale, which enables densities of 134 million transistors per square millimeter on a single chip. However, connecting a chip to an organic laminate substrate using high-density interconnects is challenging. The pin pitch (center-to-center distance between adjacent pins) limits how quickly data can be transferred to or from a chip and therefore represents a ceiling on achievable performance, not only in multi-chip packages but also in real-world single-chip packages using off-chip memory modules. A current target for chip-to-laminate interconnects is a sub-55 µm (micrometer) pitch.

[0003] Just as quantum tunneling poses a problem for increasing transistor density, short circuits between nearest neighbors during soldering are a problem when reducing chip pin pitch. One approach to reducing the risk of short circuits is to reduce the amount of solder applied to each controlled collapse chip connector (C4) bump on a chip.

[0004] Another problem with reducing the chip lead pitch is the expected deformation of chips and substrates that occurs during thermal excursions in typical processing steps. Thermal stress, caused by differences in the coefficients of thermal expansion (CTE) between semiconductor chips and organic laminate substrates, has always been a factor that must be considered when aligning chip leads to substrate contact fields. At tight pitches on the order of 55 µm or less, thermal stress is more likely to lead to misalignment and faulty connections.

[0005] The publication DE 692 05 134 T2 relates to a method for replacing a semiconductor chip that was bonded to a substrate with the contact side facing downwards and encapsulated with a resin.

[0006] Document US 2002 / 0119396A1 relates to a multilayer packaging substrate, specifically a structure and a method for manufacturing or forming multilayer packaging circuit structures. The method includes: providing a metallic support; depositing a first solder layer on the metallic support; and depositing a second solder layer on the first solder layer.

[0007] Publication JP 2015-103688 A relates to an interconnection method for joining a chip and a substrate, comprising the following steps: removing an oxide film from at least one electrode section of the chip and the substrate; applying a non-cleaning flux after removing the oxide film; placing the chip on the substrate with the respective electrode sections in contact; soldering between the electrode sections of the charged substrate and the chip; filling the space between the soldered chip and the substrate with a backing material.

[0008] Document US 2014 / 0131855A1 relates to a method for connecting a semiconductor chip to a substrate, wherein at least one of the semiconductor chip and the substrate has solder bumps.The process comprises aligning the semiconductor chip with the substrate; applying a compressive force to the semiconductor chip to deform the solder bumps between the semiconductor chip pads and the substrate pads, the compressive force being applied while the semiconductor chip and the substrate are held at a temperature above room temperature and below a temperature at which a liquid forms in at least one of the solder bumps; then applying an underfill material to fill the gap between the chip and the substrate; and then heating the assembled semiconductor chip and the substrate to an elevated temperature to cause the solder bumps to melt and fuse together, forming a metallurgical bond between the semiconductor chip hip pads and the substrate pads. SUMMARY

[0009] The basic concepts of the invention provide methods for mounting a chip to a substrate. In one embodiment, an exemplary method includes bonding a semiconductor chip to an organic laminate substrate using solder at a bonding temperature; dispensing underfill between the semiconductor chip and the organic laminate substrate at an underfill dispensing temperature without cooling from the bonding temperature to room temperature; and curing the underfill in a temperature range above the underfill dispensing temperature.

[0010] In another form, an exemplary process includes applying a first solder to contact fields of an organic laminate substrate; contacting a second solder on columns of a semiconductor chip with the first solder on the contact fields of the organic laminate substrate; and soldering the semiconductor chip to the organic laminate substrate.

[0011] In another embodiment, an exemplary device includes a semiconductor chip 401 having pillars 402 projecting from a lower surface thereof with a grid spacing of 55 µm (micrometers) or less, with caps 406 of first solder being attached to the lower ends of the pillars; an organic laminate substrate 403 having contact pads 404 projecting from an upper surface thereof with the same grid spacing as the semiconductor chip, with caps 408 of second solder being attached to the upper surfaces of the contact pads; and two or more blobs of volatile tacky adhesive 1208 bonding the upper surface of the organic laminate substrate to the lower surface of the semiconductor chip.

[0012] In this context, methods of the present invention can provide considerable advantageous technical effects. For example, one or more embodiments of one or more provide:

[0013] Underfilling reduces thermal stress and protects chip leads from shear stress during cooling from solder bond temperature to room temperature.

[0014] Improved reliability of solder joints from chip to organic substrate at C4 pitches below 55 µm.

[0015] In general, underfilling before cooling is an advantageous technology. It is extremely effective for bonding a large chip with closely spaced bumps to a curved substrate, but it can be used regardless of the chip size or the size of the microbumps, and it can also be used to bridge chip arrays. It can be used not only to bond a single chip but also multiple chips to the same substrate.

[0016] These and other features and advantages of the present invention will become clear from the detailed description below of illustrative embodiments thereof, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic of a prior art method for bonding a semiconductor chip to an organic substrate. Fig. Figure 2 shows the curvature of the in a diagram. Fig. 1 shown organic laminate substrate. Fig. Figure 3 shows a copper column and a non-restrictive exemplary contact field with Cu / Ni / Pd / Au surface coating with a solder cap on the column. Fig. Figure 4 shows a copper column and a gold / palladium contact field with a solder cap on the column and another solder cap on the contact field according to an exemplary embodiment. Fig. Figure 5 shows in a schematic diagram a method for binding a chip to a substrate according to an exemplary embodiment. Fig. Figure 6 shows in a schematic diagram a method for binding a chip to a substrate according to a further exemplary embodiment. Fig. Figure 7 shows in a scheme a method for binding a chip to a substrate according to yet another exemplary embodiment. Fig. Figure 8 shows in a schematic diagram a method for binding a semiconductor chip to an organic substrate according to an exemplary embodiment. Fig. Figure 9 shows a diagram comparing the procedures of Fig. 1 and Fig. 8. Fig. Figure 10 shows a cross-sectional view of a semiconductor chip manufactured according to the method of Fig. 1 is bound to a substrate. Fig. Figure 11 shows a cross-sectional view of a semiconductor chip manufactured according to the method of Fig. 8 is bound to a substrate. Fig. Figure 12 shows in a scheme another method for binding a semiconductor chip to an organic substrate according to an exemplary embodiment. Fig. Figure 13 shows in a scheme another method for binding a semiconductor chip to an organic substrate according to an exemplary embodiment. Fig. Figure 14 shows in a scheme another method for binding a semiconductor chip to an organic substrate according to an exemplary embodiment. Fig. Figure 15 shows in a scheme another method for binding a semiconductor chip to an organic substrate according to an exemplary embodiment. DETAILED DESCRIPTION

[0017] After Fig. A prior art method 100 for bonding a semiconductor chip 102 to an organic laminate substrate 104 comprises several steps. Step 106 involves immersing the chip 102 in a flux bath 108. Step 110 involves thermocompression bonding the flux-coated chip 102 to the substrate 104. Step 112 involves washing out the flux residue from between the chip 102 and the substrate 104. Step 114 involves dispensing and hardening an underfill 116 between the chip 102 and the substrate 104.

[0018] In step 106, immersion in flux is performed at room temperature. Fluidization of the flux solids is carried out at a higher temperature (typically between 90 °C and 150 °C). In step 110, thermocompression bonding is performed at an even higher temperature (typically between 235 °C and 245 °C; generally at least 20 °C to 30 °C hotter than the solidus temperature of the solder). In step 112, the flux is washed out at or near room temperature (typically between about 70 °C and 90 °C). In step 114, dispensing of underfill is performed at a slightly warmer temperature (typically between about 80 °C and 120 °C), followed by curing of the underfill at a further elevated temperature (typically between about 120 °C and 160 °C).

[0019] When we attempted to bond a large silicon chip with 40 µm pitch I / O to an organic substrate using conventional belt furnace remelting, the method commonly used for bonding silicon chips to organic substrates, we found it unsuccessful. One reason for this is the warping of the laminate, both at room temperature and near the solder's melting point, with the extent of the warping being greater than the solder height of the microbumps. In conventional chip-laminate assembly, it is common to use C4 solder with a diameter of 80 µm or more instead of microbumps, which works well because solder of this diameter can follow the laminate to some extent, even if it is warped. However, it is very difficult to directly bond a large, closely pitched silicon chip with microbumps to an organic substrate.

[0020] The thermal excursion due to cooling between step 110 (thermocompression bonding) and step 112 (flux washing) exerts a thermomechanical stress on the solder joints between the chip 102 and the substrate 104, the cause of which is the difference in the coefficients of thermal expansion (CTE) of these two components. In general, the organic laminate substrate 104 has a CTE 3 to 10 times higher than that of the chip. Therefore, as shown in Fig. Figure 2 shows a surface 120 of the substrate 104, which points towards the chip 102, closer to the chip at low temperature (e.g. room temperature) than at higher temperatures (e.g. binding temperature).

[0021] Repeated heating cycles of substrate 104 during or before chip assembly induce a condition similar to that described in Fig. 2. Curvature shown. A typical curvature results in substrate warping at room temperature with a magnitude of (in a non-limiting example) approximately 12 to 22 µm (micrometers) difference in the perpendicular distance between a 30 mm (millimeter) chip and the substrate, when comparing the edge to the center of the chip, between room temperature and typical solder bonding temperature. This exemplary value is the extent of curvature for this particular laminate only; the extent of curvature varies greatly depending on the thickness, size, material, and structure of the laminate. If, for example, the core material of the laminate is thin, the extent of curvature can exceed 100 micrometers. Even when a laminate with a thicker core is used to keep curvature low, as in this case, bonding is quite difficult if the chip is large and the bumps have a fine grid spacing. A typical curvature of substrate 104 produces undesirable results, such as…that large chips (on the order of 30 mm) can only wet the contact fields of the substrate with solder around their edges during melting or other joining processes.

[0022] Furthermore, with an Au surface coating on the contact pad, a problem arises with solder from the semiconductor chip wetting the sides of the contact pads on the organic laminate substrate instead of filling a connection between the pillars of the semiconductor chip and the contact pads of the substrate. This occurs because Au is a highly wettable material when solder melts.

[0023] For example, it shows Fig. 3 a chip assembly 300. The chip assembly 300 comprises a semiconductor chip 301 with a Cu column 320 with a sub-55 µm grid spacing and an organic laminate substrate 303 with a substrate connection contact field 304. A solder cap / microbump 306 is arranged on the column 302, as is common practice. Columns and microbumps are used instead of C4 beads for fine-grid connection. The columns consist of a high-melting-point material, such as Cu (and even Ni), and a solder cap of a low-melting-point material. The column composition is layered Cu / Ni / Cu / SnAg. The first Cu layer is used to increase the height, Ni is used as a barrier layer, and the second Cu layer reacts with the SnAg when it melts. The height H PThe column diameter is 5 to 30 µm. The contact field composition is layered Cu / Ni / Pd / Au with a gold coating layer. The layers are, for example, 5 to 20 µm Cu, 0.5 to 5 µm Ni, 0.02 to 0.2 µm Pd, and 0.01 to 0.2 µm Au. Column 302 and contact field 304 have comparatively high melting points due to their compositions, while the solder cap 306 has a lower melting point due to its composition. The diameter D of column 302 (approximately 10 to 30 µm) and the surface tension of the liquid solder limit the height H. sand the volume of the solder cap 306 is approximately a hemisphere with a radius of 5 to 15 µm. This solder volume is insufficient to wet both the sides and the top of the contact pad 304, so that during melting, the solder wets the sides of the contact pad 304 and very little solder remains on the top. The column 302 cannot be made thicker within the given specification of the terminal pitch. Therefore, no more solder can be placed on the column.

[0024] In one manifestation of the present disclosure, we considered that it might be possible to modify the conventional chip assembly process such that solder is also present on the contact pad 304 during the melting / bonding process. Accordingly, we show Fig. Figure 4 shows a detailed view of a chip arrangement 400, which includes a C4 column 400 projecting downwards from a chip 401 and a substrate contact pad 404 projecting upwards from a substrate 403. In an exemplary embodiment, a solder cap / microbump 406 is located on the column 402 and another solder cap / microbump 408 is located on the contact pad 404. The combined heights and volumes of the two solder caps 406, 408 accommodate the warp-induced gap between the chip 401 and the substrate 403 and provide sufficient solder at the bonding interface, even when it is wetted and spread over the side of the contact pad 404.

[0025] One or more embodiments advantageously achieve the results specified in Fig. The structure shown in section 4 is not known in conventional chip assembly. The disclosure provides several methods for producing the solder cap 408 on the substrate contact field 404 prior to melting / bonding the chip.

[0026] Fig. Figure 5 shows in a diagram a method 500 for bonding a chip 401 to a substrate 403 according to an exemplary embodiment. In this case, a transfer form 502 is provided, which forms the bumps 504 from solder with a low melting point, e.g., SnBi (tin-bismuth), as a specific example, Sn 42 Bi 58, exhibits. Such a solder has a eutectic melting point of 139 °C. At 506, the solder protrusion 504 is transferred from the transfer form 503 to the contact pads 404 of the substrate 403 by melting the solder at a comparatively low temperature, i.e., 139 °C to 150 °C. At 508, the transfer form 503 is withdrawn to leave the low-melting-point solder as a protrusion 408 on the contact pads 404. At 510, the chip 401 is provided, which has a solder protrusion 406 made of Sn-Ag (tin-silver) or similar solder on its pillars 402. SnAg solder has a melting point of approximately 221 °C. In step 512, the chip 401 is bonded to the substrate 403 by heating the assembly to a bonding temperature, e.g., 139 °C to 150 °C. Since the low-temperature solder SnBi is used, the bonding temperature is advantageously lower than a conventional range of 235 °C to 245 °C for melting SnAg solder or the like.The lower temperature reduces thermal excursions and associated thermomechanical stress, thereby decreasing warping of the substrate 403. Furthermore, it allows only local melting instead of the conventional complete melting of C4 solder. Localized melting reduces short circuits between nearest neighbors, thus enabling a reduced (finer) grid spacing. Since the SnAg solder of the cusps 406 will dominate the joint after melting (in one or more embodiments, the cusps 406 are larger than the cusps 408, and the Bi from cusps 408 will simply become part of a ternary composition with SnAg), the joint will not melt at the projected operating temperature of 150 °C.

[0027] Fig. Figure 6 shows a schematic diagram of a method 600 for bonding a chip 401 to a substrate 403 according to a further exemplary embodiment. Figure 602 provides a mold 603 containing only solder, which has protrusions 604 made of solder, e.g., SnAg solder. Figure 606 transfers a portion of each solder protrusion 604 onto contact pads 404 of the substrate 403 to form protrusions 408 on the contact pads 404. Figure 608 withdraws the mold 603 containing only solder. Figure 610 provides the chip 401 with columns 402 having solder protrusions 406. Figure 612 bonds the chip 401 to the substrate 403 by heating it to a temperature range of 235 °C to 245 °C to melt the solder protrusions 406, 408.

[0028] Fig. Figure 7 shows a schematic diagram of a method 700 for bonding a chip 401 to a substrate 403 according to a further exemplary embodiment. Figure 702 shows the chip 401 being placed with solder protrusions 703 on its columns 402. Figure 706 shows the transfer of solder protrusions 703 from the columns 402 to the contact pads 404 of the substrate 403 by melting to form protrusions 408 on the contact pads. Figure 708 shows the chip 401 being withdrawn to obtain additional solder. Step 710: The chip 401 is provided with (additional) solder bumps 406 on the columns 402. Step 712: The chip 401 is bonded to the substrate 403 by thermocompression bonding of the solder bumps 406, 408 in a temperature range of 235 °C to 245 °C.

[0029] Considering that the chip interconnection methods 500, 600, 700 incorporate a new structure which to some extent overcomes the known and persistent problem of substrate warping, which impairs suitable solder wetting, further manifestations of the present disclosure relate to additional advances that are possible with solder caps on both the column and the contact field.

[0030] For example, it shows Fig. 8 in a scheme a method 800 for binding a semiconductor chip 401 to an organic substrate 403 according to an exemplary embodiment.

[0031] At step 802, a volatile tacky adhesive (VTA) 410 is dispensed onto the substrate 403. The VTA 410 is placed at least at the corners of the base of the chip 401. VTAs generally evaporate at temperatures above 180 °C, e.g., between 190 °C and 250 °C, so that after melting, the volatile tacky adhesive is no longer present. Suitable VTAs include, for example, alcohols such as C-9-11-iso-C-1-rich alcohols, which have a viscosity above 30 kcP (kilocentipoise) at room temperature and a boiling point of about 180 to 250 °C. The VTA can be applied to the chip side instead of the substrate side.

[0032] At step 812, the chip 401 is bonded to the substrate 403. Bonding can be performed, for example, at a temperature of 235 °C to 245 °C: melting in a belt furnace capable of generating a formic acid atmosphere, in a chamber-type formic acid furnace, or in a thermocompression bonding (TCB) process where chip bonding is carried out in a formic acid atmosphere. Alternatively, if a method other than a formic acid atmosphere (e.g., HCI etching) is used to reduce the oxide films on the solder and components, bonding can be performed by melting in a belt or chamber furnace at a temperature of 235 °C to 245 °C under an atmosphere of less than 100 ppm oxygen. At step 812, the solder bumps on the chip columns fuse with the solder caps on the contact pads of the substrate. However, with this method, it is not absolutely necessary for the contact field on the laminate side to have solder.This method can be applied to chips and disks of any structure.

[0033] By using a VTA to fix the chip 401 to the substrate 403 immediately before bonding and by using a formic acid atmosphere instead of soldering flux, it is advantageously possible to proceed from bonding (step 812) to underfilling (step 814) without an intermediate cooling step to wash flux from under the chip. In other embodiments, HCI etching can be used instead of a formic acid atmosphere.

[0034] In one or more embodiments, no-clean flux can be used prior to bonding. The use of no-clean flux in a belt oven or similar, instead of a formic acid atmosphere, also allows underfilling without cooling for flux washing. Those skilled in the art are familiar with "no-clean" flux. No-clean flux is sometimes described as a flux that requires no cleaning; however, this does not mean that the components / ingredients are completely removed from the laminate surface before or during the bonding process. Some combinations with underfill can cause underfill voids that may impair reliability testing, so they should not be used for this reason.

[0035] At 814, dispensing of underfill 815 at approximately 100 °C (without prior cooling to room temperature after binding), followed by hardening of the underfill while maintaining it at a temperature between the binding temperature and room temperature, e.g. between 90 °C and 150 °C.

[0036] Fig. Figure 9 shows a diagram comparing procedures 100 and 800. Fig. 1 and Fig. 8. The person skilled in the art will recognize that the two methods diverge after the bonding of the chip 401 to the substrate 403, wherein in method 100 the housing progresses from step 110 (bonding) to step 112 (washing off flux with hot water at 60 °C to 80 °C) before step 114 (dispensing and hardening of underfill), whereas in method 800 the housing progresses from step 812 (bonding) directly to step 814 (underfill) without an intermediate excursion to low temperature.

[0037] Fig. Figure 10 shows a cross-sectional view of a semiconductor chip 1001 and a substrate 1003 after cooling of step 110 (binding) of the in Fig. In the method 100 shown in Figure 1, due to differing coefficients of thermal expansion, a significant thermal stress exists between the chip 1001 and the substrate 1003 at room temperature, such that the columns 1002 of the chip 1001 are not aligned with the contact fields 1004 of the substrate 1003. The person skilled in the art will see that the rightmost column 1006 is aligned between the rightmost contact field 1007 and the central contact field 1008, a classic example of nearest neighbor short circuit. Underfilling this structure will lock the misalignment.

[0038] On the other hand, it shows Fig. 11 A cross-sectional view of a semiconductor chip 1101 and a substrate 1103 after step 814 (underfilling) according to the in Fig. 8 shown in method 800. The person skilled in the art will see that, since only a small thermal excursion took place from step 812 (binding) to step 814 (underfilling), the step of dispensing and hardening underfill locked the good alignment of the columns 1102 on the contact fields 1104.

[0039] Fig. Figure 12 shows a further method 1200 for bonding a semiconductor chip 401 to an organic substrate 403 according to an exemplary embodiment. In 1201, a template 503 with solder bumps 504 is immersed in a flux bath 1202 at room temperature. In 1203, solder is transferred to the substrate 403 by thermocompression bonding. In 1204, the transfer form is withdrawn from the substrate. In 1205, the solder is melted at a temperature above its solidus temperature. In 1206, any remaining flux is washed off at a temperature slightly above room temperature (e.g., 80 °C to 100 °C). In 1207, at room temperature, an adhesive material 1208 is applied, which could be degraded and evaporated from the board at temperatures just below the melting temperature of the solder. At 1209, the chip 401 was bound to the substrate 403 using a belt oven in a formic acid atmosphere.For 1210, proceed directly to dispensing and hardening of the underfill 1211 without intermediate cooling to room temperature at a temperature suitable for the underfill material, e.g., 80 °C to 120 °C. It should be noted that in . Fig. 12. Microbumps are present between elements 401 and 403 in steps 1209 and 1210; these details are omitted to avoid overloading. Exemplary views of microbumps and underfill are shown in the other drawings of the figure.

[0040] Fig. Figure 13 shows another method 1300 for binding a chip 401 to a substrate 403. Steps 1201, 1203, 1204, 1205, 1206 are identical to that described in Figure 1300. Fig. The process described in section 1200 is called 12. However, after step 1206 (washing off flux), process 1300 proceeds to step 1309, thermocompression banding in a formic acid atmosphere. Then, at step 1210, without intermediate cooling to room temperature, it proceeds directly to dispensing and hardening of the underfill 1211 at a temperature suitable for the underfill material, e.g., 80 °C to 120 °C.

[0041] Fig. Figure 14 shows another process 1400 for bonding a chip 401 to a substrate 403. In 1403, the transfer form 503 is thermocompression bonded to the substrate 403. In 1204, the transfer form is withdrawn. In 1405, the solder is melted under a formic acid atmosphere. In 1309, the chip 401 is thermocompression bonded to the substrate 403. Step 1210 is identical to processes 1200 and 1300 and provides an underfill 1211 between the chip 401 and the substrate 403.

[0042] Fig. Figure 15 shows another process 1500 for bonding a chip 401 to a substrate 403. Step 1403 (transfer of solder by thermocompression bonding) is identical to process 1400. Step 1204 (withdrawal of the chip) is identical to process 1200. Step 1405 (melting of solder under a formic acid atmosphere) is identical to process 1400. Steps 1207 (application of sticky material 1208), 1209 (bonding of the chip 401 to the substrate 403 in a belt oven under a formic acid atmosphere), and 1210 (dispensing and hardening of underfill without intermediate cooling to room temperature) are identical to process 1200; note the underfill 1211. It should be noted that in Fig.15. Microbumps are present between elements 401 and 403 in steps 1209 and 1210; these details are omitted to avoid overloading. Exemplary views of microbumps and underfill are shown in the other drawings of the figure.

[0043] From the foregoing description, it is clear that, generally speaking, an exemplary method according to one embodiment of the invention comprises bonding a semiconductor chip to an organic laminate substrate using solder at a bonding temperature; dispensing underfill between the semiconductor chip and the organic laminate substrate at an underfill dispensing temperature without cooling from the bonding temperature to room temperature; and hardening the underfill in a temperature range above the underfill dispensing temperature.

[0044] In one or more embodiments, the bonding is carried out in a belt oven. One or more embodiments of the method also include dispensing at least two blobs of a volatile sticky adhesive between the semiconductor chip and the organic laminate substrate prior to bonding. In one or more embodiments, the bonding is carried out in a formic acid atmosphere. In one or more embodiments, the evaporation temperature of the volatile sticky adhesive is equal to or slightly lower (about 5 to 10 degrees Celsius) than the solidus temperature of the solder used to bond the semiconductor chip to the organic laminate substrate.The evaporation temperature of the volatile sticky adhesive is selected to be in a range corresponding to (equal to) or no more than ten degrees Celsius lower than the solidus temperature of the solder used to bond the semiconductor chip to the organic laminate substrate.

[0045] In one or more embodiments, an HCl etching is applied to the semiconductor chip prior to bonding, and an atmosphere with an oxygen concentration of 100 ppm or less is maintained during bonding.

[0046] In one or more embodiments, binding is carried out using a thermocompression binding tool. In one or more embodiments, binding is carried out in a formic acid atmosphere.

[0047] In one or more embodiments, binding is carried out at 235 °C to 245 °C, dispensing of underfill is carried out at 80 °C to 120 °C, and hardening of the underfill is carried out at 120 °C to 160 °C.

[0048] In another form, an exemplary process includes applying a first solder to contact fields of an organic laminate substrate; contacting a second solder on columns of a semiconductor chip with the first solder on the contact fields of the organic laminate substrate; and soldering the semiconductor chip to the organic laminate substrate.

[0049] In one or more embodiments, the first solder has a lower melting point than the second solder. In one or more embodiments, the first solder has a melting point of 135 °C to 145 °C.

[0050] In one or more embodiments, the first solder has the same melting point as the second solder.

[0051] In one or more embodiments, the exemplary method includes plating the first solder onto the columns and includes applying the first solder to the contact fields and melting the first solder from the columns onto the contact fields.

[0052] In one or more embodiments, the exemplary method includes plating the first solder onto a template and includes applying the first solder to the contact fields and melting the first solder from the template onto the contact fields.

[0053] In another embodiment, an exemplary device comprises a semiconductor chip 401 having pillars 402 projecting from a lower surface thereof with a grid spacing of 55 µm (micrometers) or less, with caps 406 of first solder being attached to the lower ends of the pillars; an organic laminate substrate 403 having contact pads 404 projecting from an upper surface thereof with the same grid spacing as the semiconductor chip, with caps 408 of second solder being attached to the upper surfaces of the contact pads; and two or more blobs of volatile tacky adhesive 1208 bonding the upper surface of the organic laminate substrate to the lower surface of the semiconductor chip.

[0054] In one or more embodiments, the second solder has a lower melting point than the first solder. In one or more embodiments, the second solder has a melting point of 135 °C to 145 °C.

[0055] In one or more embodiments, the second solder has the same melting point as the first solder. In one or more embodiments, both the first and second solders have a solidus temperature of 215 °C to 230 °C.

[0056] In one or more embodiments, the evaporation temperature of the volatile sticky adhesive is such that after soldering the semiconductor chip to the organic laminate substrate, nothing of the volatile sticky adhesive remains.

[0057] Although certain embodiments for binding a single chip to a substrate are described, embodiments of the invention are equally applicable for binding a chip package to a substrate, and whenever the term "semiconductor chip" appears in the claims, it applies equally to a package with multiple chips.

Claims

[1] Procedure (1200; 1300; 1400; 1500); showing: Dispensing (802; 1207) of at least two blobs of a volatile sticky adhesive (410; 1208) between a semiconductor chip (301; 401; 1101) and an organic laminate substrate (303; 403; 1103); at a bonding temperature (512; 612; 712; 812; 1209; 1309) bonding the semiconductor chip to the organic laminate substrate using solder, wherein an evaporation temperature of the volatile sticky adhesive is selected such that it is in a range of one to not more than ten degrees C lower than a solidus temperature of the solder used to bond the semiconductor chip to the organic laminate substrate, and / or that after bonding the semiconductor chip to the organic laminate substrate, nothing of the volatile sticky adhesive remains; without intermediate cooling from the bonding temperature to room temperature, dispensing (814; 1210) of underfill (815; 1211) between the semiconductor chip and the organic laminate substrate at an underfill dispensing temperature; and Hardening (814; 1210) of the underfill within a temperature range above the underfill dispensing temperature. [2] Method according to claim 1, wherein the binding is carried out in a belt furnace. [3] Method according to claim 1 or 2, further comprising applying HCl etching to the semiconductor chip before bonding, and maintaining an atmosphere with an oxygen concentration of 100 ppm or less during bonding. [4] Method according to claim 1, wherein the binding is carried out using a thermocompression binding tool. [5] Method according to any of the preceding claims, wherein the binding is carried out in a formic acid atmosphere. [6] Method according to any of the preceding claims, wherein binding is carried out at 235 °C to 245 °C, dispensing of underfill is carried out at 80 °C to 120 °C and hardening of underfill is carried out at 120 °C to 160 °C. [7] Method according to any one of the preceding claims, comprising: Application of a first solder (408) to contact fields (404; 1104) of the organic laminate substrate; Contacting a second solder (406) on columns (402; 1102) of the semiconductor chip with the first solder on the contact fields of the organic laminate substrate; the soldering process is carried out after the second solder is brought into contact with the first solder. [8] Method according to claim 7, wherein the first solder has a lower melting point than the second solder, wherein the first solder preferably has a melting point of 135 °C to 145 °C. [9] Method according to claim 7, wherein the first soldering material has the same melting point as the second soldering material. [10] Method according to claim 7, further comprising plating the first solder onto the columns, wherein applying the first solder to the contact fields includes melting the first solder from the columns onto the contact fields. [11] Method according to claim 7, further comprising plating the first solder onto a template form, wherein applying the first solder to the contact fields includes melting the first solder from the template form onto the contact fields. [12] Method according to any one of claims 1 to 6, wherein the semiconductor chip has columns (402; 1102) projecting from a lower surface thereof with a grid spacing of 55 µm or less; wherein the organic laminate substrate has contact fields (404; 1104) projecting from an upper surface thereof with the same grid spacing as the semiconductor chip; the procedure further features: Before binding, caps (406) made of second solder are attached to the lower ends of the columns; and Before binding, caps (408) made of first solder are applied to the tops of the contact fields. [13] Method according to claim 12, wherein the second solder has a lower melting point than the first solder, wherein the second solder preferably has a melting point of 135 °C to 145 °C. [14] Method according to claim 12, wherein the second soldering material has the same melting point as the first soldering material. [15] Method according to claim 14, wherein the first and the second soldering media have a solidus temperature of 215 °C to 230 °C.

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