TRANSISTOR WITH SELF-ALIGNED MULTI-LEVEL GATE AND SOURCE / DRAIN CONNECTIONS AND METHOD

Abstract

Comprehensive structure: comprising a stack of layers: a channel layer (103); a barrier layer (104) on the channel layer (103); and a dielectric layer (105) on the barrier layer (104); Source / drain connections (132); and a gate connection (131) which is positioned laterally between the source / drain connections (132), wherein each source / drain connection (132) comprises: a first source / drain section (132a) within a source / drain opening (112) extending through the dielectric layer (105) and the barrier layer (104) to the channel layer (103); and a second source / drain section (132b) above the first source / drain section (132a) and the dielectric layer (105), wherein the gate terminal (131) comprises: a first gate section (131a) within a gate opening (111) extending through the dielectric layer (105) and having a bottom above the barrier layer (104); and a second gate section (131b) above the first gate section (131a) and the dielectric layer (105), wherein the first source / drain section (132a) and the second source / drain section (132b) comprise a source / drain conductor material (122) and the first gate section (131a) and the second gate section (131b) comprise a gate conductor material (121) that is different from the source / drain conductor material (122), and wherein the upper surfaces of the gate terminal (131) and the source / drain terminals (132) are coplanar and wherein the gate terminal (131) further comprises an additional gate section (131c) comprising the source / drain conductor material (122) which is positioned at least laterally immediately adjacent to the second gate section (131b).

Description

BACKGROUND Area of ​​the invention

[0001] The present invention relates to transistors, such as III-V high electron mobility transistors (HEMTs), III-V metal-insulator-semiconductor HEMTs (MISHEMTs), or other types of transistors. In particular, the present invention relates to embodiments of a method for forming a transistor in such a way as to avoid pin misalignment, and to a structure formed according to the method. Description of the state of the art

[0002] III-V semiconductor devices, such as high electron mobility transistors (HEMTs) and metal-insulator-semiconductor HEMTs (MISHEMTs), have emerged as a leading technology for radio frequency (RF) and millimeter wave (mmWave) (e.g., 3–300 GHz) wireless applications. However, as device sizes continue to be reduced to enable better performance, HEMTs and MISHEMTs, as well as other transistor types, can suffer from defects due to terminal misalignment, and in particular, gate and source / drain misalignment during manufacturing. US 2014 / 0091365A1 and US 2011 / 0193096A1 concern a Compound semiconductor arrangement and a method for its fabrication. US 2010 / 0330754A1 concerns a process for manufacturing HEMTs in Enrichment mode with self-aligned field plate. US 2014 / 0264454A1 relates to a high electron mobility device structure comprising a heterostructure with a group III nitride channel layer and a group III nitride barrier layer forming a two-dimensional electron gas layer at an interface between the two layers. BRIEF SUMMARY

[0003] Embodiments of a semiconductor structure are disclosed. The semiconductor structure comprises a stack of layers on a substrate. The stack of layers comprises at least the following layers: a channel layer; a barrier layer on the channel layer; and a dielectric layer on the barrier layer. The semiconductor structure further comprises a transistor. This transistor comprises source / drain terminals and a gate terminal positioned laterally between the source / drain terminals. In particular, each source / drain terminal comprises a first source / drain section and a second source / drain section. The first source / drain section is located within a source / drain opening that extends through the dielectric layer and the barrier layer to the channel layer.The second source / drain section is located above the source / drain opening and, in particular, above and immediately adjacent to the first source / drain section, so that it is above the level of the upper surface of the dielectric layer. Optionally, the second source / drain section can be wider than the first source / drain section, such that it extends laterally onto the upper surface of the dielectric layer. The gate terminal comprises a first gate section and a second gate section. The first gate section is located within a gate opening that extends through the dielectric layer and has a base above the barrier layer in the stack (e.g., immediately adjacent to the upper surface of the dielectric layer).

[0004] The second gate section comprises a barrier layer or, in some embodiments, is physically separated from the upper surface of the barrier layer by a gate dielectric. The second gate section is located above the gate opening and, in particular, above and immediately adjacent to the first gate section, so as to be above the level of the upper surface of the dielectric layer. Optionally, the second gate section may be wider than the first gate section, such that it extends laterally onto the upper surface of the dielectric layer. In any case, the first source / drain section and the second source / drain section are, at least primarily, made of a source / drain conductor material, whereas the first gate section and the second gate section are, at least primarily, made of a gate conductor material that is different from the source / drain conductor material.

[0005] According to one variant, the upper surfaces of the gate terminal and the source / drain terminals are coplanar, and the gate terminal further comprises an additional gate section encompassing the source / drain conductor material, which is positioned at least laterally immediately adjacent to the second gate section.

[0006] According to an alternative variant, an upper surface of the gate terminal is above a level of upper surfaces of the source / drain terminals, and the gate terminal further comprises an additional gate section encompassing the source / drain conductor material, which is immediately adjacent to at least one upper surface of the second gate section.

[0007] Furthermore, embodiments of a method for forming the semiconductor structure described above are disclosed.

[0008] In general, the method implementations include forming a stack of layers on a substrate. This stack of layers comprises at least: a channel layer; a barrier layer on the channel layer; and a dielectric layer on the barrier layer. The method further comprises forming a transistor, as described above, within the stack.

[0009] In each embodiment of the method, the transistor can be formed by first creating multiple openings through the dielectric layer in parallel. These openings can be formed, for example, using conventional lithographic structuring and etching processes and can include source / drain openings and a gate opening positioned laterally between the source / drain openings. Optionally, the openings can be structured such that the gate opening is narrower than the source / drain openings.

[0010] In some embodiments, additional processing for forming the transistor may involve depositing a layer of gate conductor material over the dielectric layer and into the multiple openings. The gate conductor material layer may then be structured to form, for a gate terminal, a first gate section within the gate opening and a second gate section located above the gate opening, specifically above and immediately adjacent to the first gate section, such that it is above the level of the upper surface of the dielectric layer. Optionally, the gate conductor material may be structured such that the second gate section is wider than the first gate section, thus extending laterally onto the upper surface of the dielectric layer.In any case, the gate conductor material layer can be structured so that the source / drain openings are also exposed. The source / drain openings can then be extended deeper into the stack, and specifically down to the channel layer. A layer of source / drain conductor material, different from the gate conductor material, can subsequently be deposited over the partially completed structure. The source / drain conductor material layer can be structured to form, for each of the two source / drain connections, a first source / drain section within a source / drain opening and a second source / drain section above the source / drain opening, and specifically above and immediately adjacent to the first source / drain section, to be above the level of the upper surface of the dielectric layer.Optionally, the source / drain conductor material can be structured such that the second source / drain section of each source / drain connection is wider than the first source / drain section, thus extending laterally onto the upper surface of the dielectric layer. It should be noted that this source / drain conductor material structuring process also simultaneously performs final adjustments to the shape of the second gate section.

[0011] In other embodiments, additional processing for transistor formation may include forming a protective plug in the gate opening and sidewall spacers in the source / drain openings. As further discussed in the detailed description section, the formation of the protective plug in the gate opening and the sidewall spacers in the source / drain openings can be concurrent and achieved using a conventional sidewall spacer formation technique if the gate opening is narrower than the source / drain openings. In this case, the source / drain openings can be extended deeper into the stack, and specifically down to the channel layer. Optionally, the protective plug and sidewall spacers can be selectively removed at this point in the process. A layer of source / drain conductor material can then be deposited.The layer of a source / drain conductor material can be structured to form, for each of the two source / drain terminals, a first source / drain section within a source / drain opening and a second source / drain section above the source / drain opening, and specifically above and immediately adjacent to the first source / drain section, so that it is above the level of the upper surface of the dielectric layer. Optionally, the source / drain conductor material can be structured such that each second source / drain section is wider than the first source / drain section below it, thus extending the second source / drain sections laterally onto the upper surface of the dielectric layer. It should be noted that structuring the layer of a source / drain conductor material can also be performed to expose the gate opening.This means that any source / drain conductor material and, if applicable, the protective plug can be removed from the gate opening during this structuring process. A layer of gate conductor material, different from the source / drain conductor material, can then be deposited over the partially completed structure. This gate conductor material layer can be structured to form, for a gate connection, a first gate section within the gate opening and a second gate section above the gate opening, and specifically above and immediately adjacent to the first gate section, so that it is above the level of the top surface of the dielectric layer. Optionally, the gate conductor material can be structured such that the second gate section is wider than the first gate section, and thus extends laterally onto the top surface of the dielectric layer.It should be noted that this gate conductor material structuring process also simultaneously performs final adjustments to the shape of the first gate section.

[0012] Since in all process implementations the dielectric layer is structured concurrently with the gate opening for the first gate section for the gate connection and with the source / drain openings for the first source / drain sections of the source / drain connections, these first gate and source / drain sections at a lower level within the dielectric layer are considered self-aligned. Furthermore, since in all process implementations the final conductor material structuring process affects the final shapes of all sections at a higher level of the gate and source / drain connections (i.e., the second gate section and the second source / drain sections), these higher-level sections are also considered self-aligned. These self-aligned multi-level gate and source / drain connections avoid errors related to connection misalignment (e.g., when reducing device sizes). BRIEF DESCRIPTION OF THE MULTIPLE VIEWS OF THE DRAWINGS

[0013] The present invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which: Fig. 1A is a flowchart illustrating process implementation forms for forming a semiconductor structure; Fig. 1B is a flowchart that further illustrates exemplary process flows A and B, which occur at process step 12 of Fig. 1A can be used; Fig. 2A-2C cross-sectional diagrams are each illustrating three different partially completed structures formed according to process flow A or B; Fig. 3A-3C cross-sectional diagrams are three different partially completed structures, each illustrating one of three different structures formed according to process flow A or B; Fig. 4A-4C cross-sectional diagrams are each illustrating three different partially completed structures formed according to process flow A; Fig. 5A-5C cross-sectional diagrams are each illustrating three different partially completed structures formed according to process flow A; Fig. 6A-6C cross-sectional diagrams are each illustrating three different partially completed structures formed according to process flow A; Fig. 7A-7C are cross-sectional diagrams that each illustrate three different partially completed structures formed according to process flow A; Fig. 8A-8C are cross-sectional diagrams that each illustrate three different partially completed structures formed according to process flow A; Fig. 9A-9C are cross-sectional diagrams that each illustrate embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow A; Fig. 10A-10C are cross-sectional diagrams that each illustrate embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow A; Fig. 11A-11C are cross-sectional diagrams that each illustrate alternative embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow A; Fig. 12A-12C are cross-sectional diagrams that each illustrate alternative embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow A; Fig. Section diagrams 13A-13C illustrate alternative embodiments of a HEMT, a MISHEMT, and another MISHEMT formed according to process flow A; Fig. 14A-14C are cross-sectional diagrams that each illustrate alternative embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow A; Fig. 15A-15C are cross-sectional diagrams that each illustrate three different partially completed structures formed according to process flow B; Fig. 16A-16C are cross-sectional diagrams that each illustrate three different partially completed structures formed according to process flow B; Fig. 17A-17C are cross-sectional diagrams, each illustrating three different partially completed structures formed according to process flow B; Fig. 18A-18C are cross-sectional diagrams, each illustrating three different partially completed structures formed according to process flow B; Fig. 19A-19C are cross-sectional diagrams, each illustrating three different partially completed structures formed according to process flow B; Fig. 20A-20C are cross-sectional diagrams, each illustrating three different partially completed structures formed according to process flow B; Fig. 21A-21C are cross-sectional diagrams, each illustrating three different partially completed structures formed according to process flow B; Fig. 22A-22C are cross-sectional diagrams that each illustrate embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow B; Fig. 23A-23C are cross-sectional diagrams that each illustrate three different alternative partially completed structures formed according to process flow B; Fig. 24A-24C cross-sectional diagrams are each illustrating three different alternative partially completed structures formed according to process flow B; and Fig. 25A-25C are cross-sectional diagrams that each illustrate alternative embodiments of a HEMT, a MISHEMT and another MISHEMT formed according to process flow B. DETAILED DESCRIPTION

[0014] As mentioned above, III-V semiconductor devices, such as high electron mobility transistors (HEMTs) and metal-insulator-semiconductor HEMTs (MISHEMTs), have emerged as a leading technology for radio frequency (RF) and millimeter wave (mmWave) (e.g., 3–300 GHz) wireless applications. However, as device sizes continue to be reduced to enable better performance, HEMTs and MISHEMTs, as well as other transistor types, can suffer from defects due to lead misalignment, and in particular, gate and source / drain lead misalignment during manufacturing.

[0015] In light of the foregoing, embodiments of a semiconductor structure are disclosed herein, comprising a transistor (e.g., a high-electron-mobility transistor (HEMT), a metal-insulator-semiconductor (MISHEMT), etc.) with self-aligned multi-level gate and source / drain terminals, thus avoiding errors related to terminal misalignment (e.g., when device sizes are reduced). Also disclosed herein are various method embodiments for forming such a semiconductor structure. In particular, the method embodiments may include the simultaneous formation (e.g., lithographic patterning and etching) of a gate opening and source / drain openings by a top layer of a stack of layers, and in particular by a dielectric layer.In some embodiments, the method may further include: depositing and structuring gate conductor material such that the gate terminal comprises a first gate section within the gate opening and a second gate section above the gate opening, and such that the source / drain openings are exposed; extending the source / drain openings deeper within the stack; and depositing and structuring source / drain conductor material such that each source / drain terminal comprises a first source / drain section within a source / drain opening and a second source / drain section above the source / drain opening. This last conductor material structuring process also concurrently performs final adjustments to the shape of the second gate section.In other embodiments, the source / drain openings can extend any conductor material deposition, and the sequence of gate conductor material and source / drain conductor material deposition and structuring can be reversed.For example, in other embodiments, the method may further include: concurrently forming a plug in the gate opening and sidewall spacers in the source / drain openings; extending the source / drain openings deeper in the stack; depositing and structuring source / drain conductor material such that each source / drain connection comprises a first source / drain section within a source / drain opening and a second source / drain section above the source / drain opening, and such that the gate opening is exposed; and depositing and structuring gate conductor material for the gate connection such that the gate connection comprises a first gate section within the gate opening and a second gate section above the gate opening. This last conductor material structuring process also concurrently performs final adjustments to the shapes of the second source / drain sections.Since in all process implementations the dielectric layer is structured concurrently with the gate opening for the first gate section of the gate terminal and with the source / drain openings for the first source / drain sections of the source / drain terminals, those sections at a lower level within the dielectric layer are considered self-aligned. Furthermore, since in all process implementations the final conductor material structuring process affects the final shapes of the second gate section of the gate terminal and the second source / drain sections of the source / drain terminals, those sections at a higher level of the gate and the source / drain terminals that are above the dielectric layer are also considered self-aligned.

[0016] Fig. Figure 1A is a flowchart illustrating process implementations for forming a semiconductor structure. In general, the process implementations involve forming a stack of layers required to form a transistor (e.g., required to form a high-electron-mobility transistor (HEMT), required to form a metal-insulator-semiconductor HEMT (MISHEMT), or required to form any other similar transistor type) (see process step 10). The process implementations further involve using the stack to form a transistor (e.g., a HEMT, MISHEMT, etc.) with self-aligned multi-level gate and source / drain connections, thus avoiding errors related to connection misalignment (e.g., when reducing device sizes). Fig. 1B is a flowchart that further illustrates exemplary process flows A and B that can be used in process step 12 to form the transistor.

[0017] It should be noted that the process implementations are described below and illustrated in the figures with respect to the formation of a HEMT that does not require a gate dielectric layer, the formation of a MISHEMT that includes a conformal gate dielectric layer, and the formation of a MISHEMT with an embedded gate dielectric layer in the stack of layers. Thus, in the figures, each “A” figure represents a partially completed or completed HEMT structure, each “B” figure represents a partially completed or completed MISHEMT structure with a conformally deposited gate dielectric layer, and each “C” figure represents a partially completed or completed MISHEMT structure with an embedded gate dielectric layer in the stack of layers.

[0018] As mentioned above, in each of the process implementation forms a stack of layers required to form a transistor (see process step 10 and Fig. 2A-2C). The specific layers included in the stack may differ slightly depending on whether the transistor will be a HEMT, a MISHEMT where a conformal gate dielectric layer is deposited in a gate opening (referred to herein as MISHEMT#1), or a MISHEMT where a gate dielectric layer is incorporated into the stack (referred to herein as MISHEMT#2).

[0019] In particular, for the formation of a HEMT, a MISHEMT#1, or a MISHEMT#2, the stack of layers formed in process step 10 can comprise a substrate 101. This substrate 101 can be, for example, a silicon or silicon-based substrate (e.g., a silicon carbide (SiC) substrate), a sapphire substrate, a III-V semiconductor substrate (e.g., a gallium nitride (GaN) substrate or another suitable III-V semiconductor substrate), or any other suitable substrate for a III-V semiconductor device.

[0020] For the formation of a HEMT, a MISHEMT#1, or a MISHEMT#2, the stack of layers formed in process step 10 can further comprise several epitaxially grown layers. The epitaxially grown layers can include a buffer layer 102, which is epitaxially grown on the top surface of the substrate 101. Such a buffer layer 102 can be used as an anchor to achieve nucleation and to replicate an orientation in subsequently grown epitaxial layers. This buffer layer 102 can be doped or undoped. Optionally, the buffer layer 102 can be carbon-doped. The epitaxially grown layers can also include a channel layer 103, and in particular a III-V semiconductor channel layer, which is epitaxially grown on the top surface of the buffer layer 102 and which is used as the device channel layer.Those skilled in the art will recognize that a III-V semiconductor refers to a compound obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) (e.g., GaN, InP, GaAs, or GaP). It should be noted that the buffer layer 102 can also be used to allow the channel layer 103 to grow and to provide lattice constants for the substrate 101 below and the channel layer 103 above. The epitaxially grown layers may further include a barrier layer 104, which is epitaxially grown on the upper surface of the III-V semiconductor channel layer 103. The barrier layer 104 can have a band gap that is wider than the band gap of the III-V semiconductor channel layer 103 for the device channel.Experts will recognize that the barrier and channel materials can be selected such that a heterojunction is formed at the interface between the two layers, resulting in the formation of a two-dimensional electron gas (2DEG) in channel layer 103. This 2DEG in channel layer 103 can provide the conduction path for charge drift between the source and the drain.

[0021] In some embodiments, the buffer layer 102 could, for example, be a gallium nitride (GaN) buffer layer, an aluminum nitride (AlN) buffer layer, or a buffer layer made of any other material suitable for use as a buffer layer in a HEMT, a MISHEMT#1, or a MISHEMT#2. The III-V semiconductor channel layer 103 could, for example, be a gallium nitride (GaN) layer or a III-V semiconductor channel layer made of any other suitable III-V semiconductor compound suitable for use as a channel layer in such a transistor. Furthermore, the barrier layer 104 could, for example, be an aluminum gallium nitride (AlGaN) barrier layer, an aluminum nitride (AlN) barrier layer, or a barrier layer made of any other material suitable for use as a barrier layer in such a transistor.Techniques for the epitaxial growth of such layers are well known in engineering, and therefore the details thereof have been omitted from this specification to allow the reader to focus on the outstanding aspects of the disclosed embodiments.

[0022] In any case, the layers mentioned above can be epitaxially grown by metal-organic chemical vapor deposition (MOCVD) or any other suitable technique (e.g. molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), etc.).

[0023] For illustrative purposes, the figures and description above depict the epitaxially grown layers in the stack (e.g., buffer layer 102, channel layer 103, and barrier layer 104) as single layered structures (i.e., comprising a layer of buffer material, a layer of channel material, and a layer of barrier material). It is understood, however, that alternatively, any or more of the epitaxially grown layers in the stack could be multilayered structures (e.g., comprising multiple sublayers of different buffer materials, multiple sublayers of different III-V semiconductor channel materials, and / or multiple sublayers of different barrier materials).

[0024] Optionally, for the formation of a MISHEMT#2, the stack of layers formed in process step 10 can also include a gate dielectric layer 106 on the upper surface of the barrier layer 104 (e.g., as in Fig. (2C shown). This gate dielectric layer 106 can, for example, be a silicon dioxide (SiO2) layer, a high-k dielectric layer, or a layer of any other dielectric material suitable for use as a gate dielectric layer of a MISHEMT. Exemplary high-k dielectric materials that could be used include, but are not limited to, a hafnium (HF)-based dielectric (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, etc.) or any other suitable high-k dielectric (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.).

[0025] Finally, for the formation of a HEMT, a MISHEMT#1 or a MISHEMT#2, the stack of layers formed in process step 10 can include a blanket dielectric layer 105 on the upper surface of the barrier layer 104 (e.g. as in Fig. 2A or Fig. 2B) or, if applicable, comprise the upper surface of the gate dielectric layer 106 (e.g. as in Fig. (2C shown). This blanket dielectric layer 105 can, for example, be a silicon nitride (SiN) layer, a silicon dioxide (SiO2) layer, a low-k dielectric layer, or a layer of any other suitable dielectric material. Exemplary low-k dielectric materials that could be used include, but are not limited to, silicon boron carbon nitride (SiBCN), silicon oxygen carbon nitride (SiONC), silicon carbon nitride (SiCN), silicon oxycarbide (SiCO), and hydrogenated silicon oxycarbide (SiCOH).

[0026] The process implementation forms may also include forming a transistor (e.g., a HEMT, a MISHEMT#1, or a MISHEMT#2) using the stack (see process step 12 and Fig. 1B).

[0027] In particular, to form a HEMT, a MISHEMT#1 or a MISHEMT#2, several openings comprising source / drain openings 112 and a gate opening 111, which is positioned laterally between the source / drain openings 112, can be formed in the dielectric layer 105 (see process step 20 and Fig. 3A-3C). For example, a mask layer 107 can be formed on the upper surface of the dielectric layer 105. A structure of openings can be formed in the mask layer 107 (e.g., using conventional lithographic structuring and etching processes). In particular, the structure can include a gate opening 111 positioned laterally between source / drain openings 112.

[0028] Optionally, the gate opening 111 can be structured to be narrower than the source / drain openings 112, as illustrated. For example, the gate opening 111 can have a first width (w1), and the source / drain openings 112 can have a second width (w2) that is larger than the first width (w1). Alternatively, the first width (w1) of the gate opening 111 could be equal to or larger than the second width (w2) of the source / drain openings. Subsequently, this structure of a gate opening 111 and of source / drain openings 112 can be transferred into the stack of layers below, and in particular through only the dielectric layer 105, to the desired final depth for the gate opening 111 for the gate connection (e.g., using an anisotropic etching process).The anisotropic etching process used for the formation of gate and source / drain openings can be selective for the dielectric material of the dielectric layer 105, such that the etching stops at the barrier layer 104 (e.g. as in . Fig. 3A and 3B illustrated). In the case of a MISHEMT#2, where the gate dielectric layer 106 is embedded in the stack, the gate dielectric layer 106 can be made of a different dielectric material than the dielectric layer 105, and the anisotropic etching process can be selective for the dielectric material of the dielectric layer 105, such that the etching stops at the gate dielectric layer 106 (e.g., as in Fig. 3C illustrates this).

[0029] It should be noted that optionally, instead of enclosing a discrete gate dielectric layer 106 in the stack (e.g. as in Fig. (2C shown) a relatively thick blanket dielectric layer 105 (e.g., a silicon dioxide layer) could be used. In this case, the anisotropic etching process used to form the gate and source / drain openings could be timed so that the etching stops some distance above the barrier layer 104, and the remaining lower portion of the dielectric layer 105 at the bottom of the gate opening could then act as the gate dielectric. However, process control problems make this option less than ideal. In any case, the same mask layer 107 is used to simultaneously pattern the gate opening 111 and the source / drain openings 112 into the dielectric layer 105. Furthermore, the gate opening 111 and source / drain openings 112 are extended to the same depth (e.g., to the bottom of the dielectric layer 105, as in Fig. 3A-3C shown) etched. Then the mask layer 107 can be selectively removed.

[0030] Once the gate opening 111 and the source / drain openings 112 are formed at process step 20, some process execution forms can proceed with additional process steps, as shown in process flow A.

[0031] Referring in particular to process flow A, for the formation of a MISHEMT#1, where the gate dielectric layer is not embedded in the stack, a conformal gate dielectric layer 108 can be deposited to cover the top surface of the dielectric layer 105 and to line all of the openings (i.e. the gate opening 111 and the source / drain openings 112) (see Fig. 4B). This gate dielectric layer 108 can, for example, be a silicon dioxide (SiO2) layer, a high-k dielectric layer, or a layer of any other dielectric material suitable for use as a gate dielectric layer of a MISHEMT. Exemplary high-k dielectric materials that could be used include, but are not limited to, a hafnium (HF)-based dielectric (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, etc.) or any other suitable high-k dielectric (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.). Conformal deposition of a gate dielectric layer is not necessary for the formation of a HEMT (see Fig. 4A) or for the formation of a MISHEMT when the gate dielectric layer is embedded in the stack (see Fig. 4C).

[0032] Next, a layer of gate conductor material 121 can be deposited over the partially completed structure (see process step 30 and Fig. 5A-5C). In particular, the layer of gate conductor material 121 can be deposited to cover the top of the partially completed structure and further to completely fill all openings (i.e., the gate opening 111 and the source / drain openings 112). This layer of gate conductor material 121 is subsequently patterned in process step 31, which is discussed below, to form a gate terminal 131 (or a primary body thereof). For illustrative purposes, the figures and description depict this layer of the first conductor material 121 as a single layered structure (i.e., comprising one layer of gate conductor material). However, it is understood that alternatively, this layer of gate conductor material 121 could be a multilayered structure (i.e., comprising several sublayers of different gate conductor materials).Additionally, it should be noted that in process step 30, the types of conductor material(s) used for the gate conductor material 121 may vary depending on whether it is the formation of a HEMT (which requires that the gate connection be a Schottky contact) or a MISHEMT#1 or a MISHEMT#2 (which does not require that the gate connection be a Schottky contact).

[0033] For example, to form a HEMT that does not require a gate dielectric layer, the layer of gate conductor material 121 can be deposited such that it is immediately adjacent to the upper surface of the dielectric layer 105, such that it is immediately adjacent to vertical surfaces of the dielectric layer 105 on the side walls of the openings (i.e., on the side walls of the gate opening 111 and the source / drain openings 112), and furthermore such that it is immediately adjacent to the barrier layer 104 at the bottom of the openings (see Fig. 5A). The gate conductor material 121 is subsequently structured to form a Schottky contact gate terminal that controls a two-dimensional electron gas (2DEG) beneath the gate. Thus, the gate conductor material 121 must comprise a metal (metals) or metal alloy (metal alloys) that forms such a Schottky contact (i.e., a potential energy barrier for electrons) at the metal-semiconductor junction at the bottom of the gate opening. Exemplary metals or metal alloys that can be used for a Schottky contact gate terminal include, but are not limited to, gold (Au), titanium (Ti), nickel-gold (Ni-Au), or titanium-platinum-gold (Ti / Pt / Au).

[0034] For the formation of a MISHEMT#1 or a MISHEMT#2, the layer of a gate conductor material 121 can be deposited such that it is immediately adjacent to either a conformally deposited gate dielectric layer 108 (see Fig. 5B) or a built-in gate dielectric layer 106 (see Fig. 5C). Thus, in these devices, the layer of a gate conductor material is physically separated from the barrier layer 104 at the bottoms of the gate opening 111 and the source / drain openings 112 by a gate dielectric material. Since the formation of a Schottky contact gate termination is not required for MISHEMTs, the gate conductor material 121 could comprise one or more sub-layers of any suitable gate conductor material (e.g., gate metal(s), gate metal alloy(s), doped polysilicon, etc.).

[0035] In any case, the layer of gate conductor material 121 can be structured to form the gate terminal 131 (or its primary body) (see process step 31). In particular, a mask layer 109 can be formed on the upper surface of the gate conductor material 121 layer (see Fig. 6A-6C). The mask layer 109 can be structured (e.g., using conventional lithographic structuring and etching processes) such that the portion of the layer made of the gate conductor material that is aligned over the gate opening 111 is masked (i.e., protected), and such that the portions of the layer made of the gate conductor material 121 that are aligned over the source / drain openings 112 are exposed (i.e., unmasked, unprotected, etc.). The structure of the mask layer 109 can then be transferred (e.g., using a selective anisotropic etching process) into the layer made of the gate conductor material 121.This selective anisotropic etching process can result in a first gate section 131a of a gate terminal 131 within the gate opening 111 and a second gate section 131b of the gate terminal 131 above the gate opening 111, and in particular above and immediately adjacent to the first gate section 131a, so that it is above the level of the upper surface of the dielectric layer 105. Optionally, the layer of gate conductor material 121 can be structured such that the second gate section 131b is wider than the first gate section 131a, and thus extends laterally onto the upper surface of the dielectric layer 105. For example, the structured gate conductor material for the gate terminal 131 could be T-shaped, in the form of an inverted L, etc.In any case, this structuring of the layer of gate conductor material 121 can be carried out such that the source / drain openings 112 and the upper surface of the dielectric layer 105 surrounding the source / drain openings 112 are also exposed. It should be understood that if the gate conductor material layer is a multilayer structure, several selective anisotropic etching processes would be used so that the gate conductor material(s) is / are completely removed from the source / drain openings 112 and from the upper surface of the dielectric layer 105 adjacent to the source / drain openings.Furthermore, the specifications for the selective anisotropic etching process(s) can vary depending on the type of gate conductor material(s) used, so that etching essentially stops without significantly affecting materials exposed during the removal of the gate conductor material 121.

[0036] For the formation of a HEMT, process step 31 results in the upper surface of the barrier layer 104 being exposed at the bottom of the source / drain openings 112. For the formation of a MISHEMT#1, where a gate dielectric layer 108 was conformally deposited prior to the deposition of the layer from a gate conductor material 121 in process step 30, process step 31 results in the exposure of the gate dielectric layer 108, which lines the source / drain openings 112. For the formation of a MISHEMT#2, where a gate dielectric layer 106 is embedded in the stack, process step 31 results in the upper surface of the gate dielectric layer 106 being exposed at the bottom of the source / drain openings 112.

[0037] The source / drain openings 112 can then be extended deeper into the stack, and in particular down to the channel layer 103 (see process step 32 and Fig. 7A-7C).

[0038] For the formation of a HEMT, process step 32 can include a selective anisotropic etching process to etch through the barrier layer 104 at the bottom of the source / drain openings 112 to expose the upper surface of the channel layer 103 (see Fig. 7A).

[0039] For the formation of a MISHEMT#1, where a gate dielectric layer 108 lines the gate opening 111 and the source / drain openings 112, process step 32 can include several selective etching processes. For example, a first selective anisotropic etching process can be performed to remove exposed horizontal sections of the gate dielectric layer 108, thereby exposing the upper surface of the dielectric layer 105 around the source / drain openings 112 and the upper surface of the barrier layer 104 at the bottom of the source / drain openings 112. Then, a second selective anisotropic etching process can be performed to etch through the barrier layer 104 at the bottom of the source / drain openings 112 to expose the upper surface of the channel layer 103 (see Fig. 7B). Thus, as in Fig. Figure 7B illustrates the sidewalls of the upper sections of the source / drain openings 112 within the dielectric layer 105 being covered by the gate dielectric layer 108. Alternatively, the selective etching of the gate dielectric layer 108 within the source / drain openings 112 (prior to the selective anisotropic etching of the barrier layer 104) could be a selective isotropic etching process that completely removes the gate dielectric material from the source / drain openings 112 (not shown). For illustrative purposes, all subsequent process steps for the MISHEMT#1 are shown in relation to those in Fig. The partially completed structure shown in Figure 7B is now complete, and thus the final MISHEMT#1 structures are in Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B and Fig. Figure 14B shows a structure with a gate dielectric material within the source / drain openings 112. However, it should be understood that the same process steps could be carried out with respect to a partially completed structure where the gate dielectric material has been completely removed from the source / drain openings 112 by a selective isotropic etching process, such that any of the final MISHEMT#1 structures disclosed herein and discussed below could also be completely free of the gate dielectric material.

[0040] For the formation of a MISHEMT#2, where a gate dielectric layer 106 is embedded in the stack, process step 32 can also include several selective anisotropic etching processes. In particular, a first selective anisotropic etching process can be performed to etch through the gate dielectric layer 106 at the bottom of the source / drain openings 112 to expose the upper surface of the barrier layer 104. Then, a second selective anisotropic etching process can be performed to etch through the barrier layer 104 at the bottom of the source / drain openings 112 to expose the upper surface of the channel layer 103 (see Fig. 7C). It should be understood that the selective anisotropic etching process(s) mentioned above may vary depending on the type of gate dielectric (if applicable) and the barrier materials used, such that etching essentially stops without significantly etching other exposed materials or the channel layer 103 during the extension of the source / drain openings 112. Thus, following process step 32, the gate opening 111 extends to a first depth (d1) from the top surface of the dielectric layer 105 into the stack, and the source / drain openings 112 extend to a second depth (d2), greater than the first depth (d1), from the top surface of the dielectric layer 105 into the stack.

[0041] Next, a layer of a source / drain conductor material 122 can be deposited onto the upper surface of the dielectric layer 105 adjacent to the source / drain openings 112, in the source / drain openings 112, such that it is immediately adjacent to the channel layer 103, and so that it completely fills the source / drain openings 112, and furthermore above the second gate section 131b of the gate terminal 131 (see process step 33 and Fig. 8A-8C). For illustrative purposes, the drawings and description depict the layer of source / drain conductor material 122 as a single layered structure (i.e., comprising one layer of conductor material). However, it is understood that alternatively, this layer of source / drain conductor material 122 could be a multilayered structure (i.e., comprising several sub-layers of different conductor materials). For transistors, such as a HEMT, a MISHEMT#1, or a MISHEMT#2, the source / drain terminals 132 should be ohmic contact source / drain terminals at the metal-semiconductor junction at the bottom of the source / drain openings 112. Thus, exemplary metals or metal alloys that may be used for the source / drain conductor material 122 include, but are not limited to, Ti / Al / TiN, Ti / Al / Ti / Au, or Mo / Al / Mo / Au.

[0042] The layer of source / drain conductor material 122 can optionally be polished (see process step 34). The layer of source / drain conductor material 122 can further be structured to form source / drain connections 132, where each source / drain connection 132 comprises a first source / drain section 132a within a source / drain opening 112 and a second source / drain section 132b above the source / drain opening 112 and, in particular, above and immediately adjacent to the first source / drain section 132a, to be above the level of the upper surface of the dielectric layer 105 (see process step 35). Optionally, the structuring in process step 35 can be carried out such that in each source / drain connection 132 the second source / drain section 132b is wider than the first source / drain section 132a, such that it extends laterally onto the upper surface of the dielectric layer 105.Thus, the structured source / drain conductor material 122 could be, for example, T-shaped, in the form of an inverted L, etc. for each source / drain connection 132.

[0043] In particular, a conventional CMP (chemical mechanical planarization) process can optionally be performed in process step 34. Whether or not the CMP process is performed, structuring of the layer of source / drain conductor material 122 by using conventional lithographic structuring and etching processes can proceed. For example, a mask layer can be formed on the layer of source / drain conductor material 122. The mask layer can be structured into a first mask section oriented over the gate opening 111 and second mask sections oriented over the source / drain openings 112. The width of the first mask section can be less than, equal to, or wider than the second gate section 131b of the previously structured gate conductor material.Next, the structure of this mask layer can be transferred to the layer of source / drain conductor material 122 (e.g., using a selective anisotropic etching process). It should be understood that if the source / drain conductor material 122 layer is a multilayer structure, several selective anisotropic etching processes can be employed. Furthermore, the specifications for the selective anisotropic etching processes can vary depending on the type of conductor material(s) used for the source / drain conductor material 122, so that etching essentially stops without significantly affecting materials exposed during the structuring of the source / drain conductor material 122. Following the structuring of the source / drain conductor material 122 layer, additional processing can be performed to complete the HEMT or MISHEMT structures (see process step 36).This additional processing may include, but is not limited to, the deposition of one or more additional dielectric layers 195 (e.g., an optional conformal etch stop layer, an interlayer dielectric layer, etc.) over the partially completed structure, the formation of middle-of-line (MOL) contacts (e.g., see MOL contact 198 to the gate terminal 131 and MOL contacts 199 to the source / drain terminals 132).

[0044] It should be noted that the structure resulting from process flow A, and in particular the configuration of gate terminal 131 in the transistor, varies depending on several factors. For example, the configuration of the gate terminal depends on whether the optional CMP is performed in process step 34, and if so, whether the upper surface of the second gate section 131b of gate terminal 131 is exposed by the CMP. The configuration of gate terminal 131 also depends on how the layer of source / drain conductor material 122 is actually structured, and in particular, whether sidewalls of the second gate section 131b of gate terminal 131 are exposed during the structuring process.

[0045] For example, a CMP of the source / drain conductor material 122 can be performed in process step 34 such that the upper surfaces of the gate terminal 131 and the source / drain terminals 132 are coplanar, and such that the upper surface of the second gate section 131b is exposed. Subsequently, the layer of source / drain conductor material 122 can be structured in process step 35 such that the sidewalls of the second gate section 131b are also exposed (e.g., see the HEMT 901, the MISHEMT 902, or the MISHEMT 903, each in semiconductor structures 900A-900C). Fig. 9A-9C).

[0046] Alternatively, a CMP of the source / drain conductor material 122 can be performed in process step 34 such that the upper surfaces of the gate terminal 131 and the source / drain terminals 132 are coplanar, and such that the upper surface of the second gate section 131b is exposed. Subsequently, the layer of source / drain conductor material 122 can be structured in process step 35 such that the sidewalls of the second gate section 131b are not exposed. Thus, in the HEMT 1001, the MISHEMT 1002, and the MISHEMT 1003, the semiconductor structures 1000A-1000C are each comprised of Fig. 10A-10C the gate connector 131 further includes an additional gate section 131c, which is made of the source / drain conductor material 122 and is positioned laterally immediately adjacent to the side walls of the second gate section 131b.

[0047] Alternatively, a CMP of the source / drain conductor material 122 can be performed in process step 34 such that the upper surfaces of the gate terminal 131 and the source / drain terminals 132 are coplanar, but such that the upper surface of the second gate section 131b is not exposed (e.g., if the layer of source / drain conductor material is thicker than the height of the second gate section). Subsequently, the layer of source / drain conductor material 122 can be structured in process step 35 such that the sidewalls of the second gate section 131b are exposed. Thus, in the HEMT 1101, the MISHEMT 1102, and the MISHEMT 1103, the semiconductor structures 1100A-1100C are each comprised of Fig. 11A-11C the gate terminal 131 further includes an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to the upper surface of the second gate section 131b.

[0048] Alternatively, a CMP of the source / drain conductor material 122 can be performed in process step 34 such that the upper surfaces of the gate terminal 131 and the source / drain terminals 132 are coplanar, but such that the upper surface of the second gate section 131b is not exposed. Subsequently, the layer of source / drain conductor material 122 can be structured in process step 35 such that the sidewalls of the second gate section 131b are also not exposed. Thus, in the HEMT 1201, the MISHEMT 1202, and the MISHEMT 1203, the semiconductor structures 1200A-1200C are each comprised of Fig. 12A-12C the gate terminal 131 further includes an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to both the upper surface and the side walls of the second gate section 131b.

[0049] Alternatively, a CMP of the source / drain conductor material 122 can be skipped in process step 34, such that the upper surface of the gate terminal 131 is above the level of the upper surfaces of the source / drain terminals 132, and thus that the upper surface of the second gate section 131b remains covered by the source / drain conductor material 122. Subsequently, the layer of source / drain conductor material 122 can be structured in process step 35 such that the sidewalls of the second gate section 131b are exposed. Thus, in the HEMT 1301, the MISHEMT 1302, and the MISHEMT 1303, each within the semiconductor structures 1300A-1300C, this is achieved. Fig. 13A-13C the gate terminal 131 further includes an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to the upper surface of the second gate section 131b.

[0050] Alternatively, a CMP of the source / drain conductor material 122 can be skipped in process step 34, such that the upper surface of the gate terminal 131 is above the level of the upper surfaces of the source / drain terminals 132, and thus the upper surface of the second gate section 131b remains covered by the source / drain conductor material 122. Subsequently, the layer of source / drain conductor material 122 can be structured in process step 35 such that the sidewalls of the second gate section 131b are not exposed. Thus, in the HEMT 1401, the MISHEMT 1402, and the MISHEMT 1403, the semiconductor structures 1400A-1400C are each comprised of Fig. 14A-14C the gate terminal 131 further includes an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to both the upper surface and the side walls of the second gate section 131b.

[0051] Since in the above-described process implementations following process flow A the dielectric layer 105 is structured in parallel with the gate opening 111 for the first gate section 131a of the gate terminal 131 and with the source / drain openings 112 for the first source / drain sections 132a of the source / drain terminals 132, those lower / first gate and source / drain sections 131a and 132a within the dielectric layer 105 are considered to be self-aligned. Since the structuring of the layer of the source / drain conductor material 122 to form the second source / drain sections 132b of the source / drain terminals 132 can also simultaneously affect the final form of the second gate section 131b of the gate terminal 131, the sections at a higher level of the gate and the source / drain terminals (i.e.The second gate section 131b and the second source / drain sections 132b, all located above the dielectric layer 105, are also considered self-aligned. With these self-aligned multi-level gate and source / drain connections 131-132, errors related to connection misalignment are avoided (e.g., when device sizes are reduced).

[0052] Referring again to the flowchart of Fig. 1B, once the gate opening 111 and the source / drain openings 112 are formed at process step 20, other process execution forms with additional process steps can proceed, as outlined in process flow B (in contrast to the additional process steps of process flow A discussed above). Process flow B differs from process flow A in particular with respect to when the source / drain openings are extended deeper into the stack of layers and with respect to the order in which the gate and source / drain conductor materials are deposited and structured. However, it should be understood that the various materials used for components identified by the same reference symbol are the same.

[0053] In particular, process flow B can form a protective plug 113 in the gate opening 111 and sidewall spacers 114 in the source / drain openings 112 (see process step 40 and Fig. 15A-15C). The protective plug 113 and the sidewall spacers 114 can, for example, be formed concurrently using a conventional sidewall spacer formation technique if the gate opening 111 is narrower than the source / drain openings 112. That is, a plug and a spacer layer can be deposited conformally over the partially completed structure. Then, a selective anisotropic etching process can be performed to remove the plug and spacer layer from horizontal surfaces, leaving them behind on vertical surfaces.The thickness of the plug and the spacer layer and the etching specifications used can be tailored, given the different widths of the gate opening 111 and the source / drain openings 112, such that remaining sections of the plug and the spacer layer form a plug 113 that fills at least a lower section of the gate opening 111, and sidewall spacers 114 that are positioned laterally adjacent to the sidewalls of the source / drain openings 112 such that at least a central region of the lower surface of each source / drain opening 112 remains exposed (e.g., a central region of the barrier layer 104 at the bottom of each source / drain opening 112, as in ). Fig. 15A and Fig. 15B shown, or a central region of the gate dielectric layer 106 at the bottom of each source / drain opening 112, as shown in Fig. 15C). It should be noted that the plug and spacer layer may be made of polysilicon, an amorphous silicon, or any other suitable material that can be selectively etched during plug and sidewall spacer formation and selectively removed during subsequent processing (as discussed below).

[0054] The source / drain openings 112 can then be extended deeper into the stack and in particular down to the channel layer 103 (see process step 41 and Fig. 16A-16C).

[0055] Optionally, the protective plug 113 and the side wall spacers 114 can be selectively removed at this point in the process (see process step 42 and Fig. 17A-17C). It should be noted that Fig. 18A-18C to Fig. Figures 22A-22C illustrate the remaining process steps 43-48 when the protective plug 113 and the side wall spacers 114 have been removed in process step 42. Fig. 23A-23C to Fig. Figures 25A-25C illustrate the remaining process steps 43-48 if the protective plug 113 and the side wall spacers 114 have not been removed in process step 42.

[0056] In particular, after the protective plug 113 and the side wall spacers 114 have been selectively removed in process step 42, a layer of a source / drain conductor material 122 can be deposited over the partially completed structure (see process step 43 and Fig. 18A-18C). The layer of a source / drain conductor material 122 can be structured (e.g., using conventional lithographic structuring and etching processes) to form, for each of the two source / drain terminals 132, a first source / drain section 132a within a source / drain opening 112 and a second source / drain section 132b above the source / drain opening 112 and, in particular, above and immediately adjacent to the first source / drain section 132a, to be above the level of the upper surface of the dielectric layer 105 (see process step 44 and Fig. 19A-19C). Optionally, in process step 44, the source / drain conductor material 122 can be structured such that every second source / drain section 132b is wider than the first source / drain section 132a below it, and thus such that the second source / drain sections 132b extend laterally onto the upper surface of the dielectric layer 105. Therefore, the structured source / drain conductor material 122 for the source / drain connections 132 could, for example, be T-shaped, in the form of an inverted L, etc. It should be noted that the structuring of the layer from a source / drain conductor material 122 should also be carried out to expose the gate opening 111. This means that during this structuring process any source / drain conductor material can be removed from the gate opening 111 and from the upper surface of the dielectric layer 105 around the gate opening 111.

[0057] Only for a MISHEMT#2 can a conformal gate dielectric layer 108 be deposited over the partially completed structure, and in particular in such a way that it lines the gate opening 111 (see Fig. 20A-20C). Then a layer of a gate conductor material 121, which is different from the source / drain conductor material 122, can be deposited over the partially completed structure (see process step 45 and Fig. 21A-21C).

[0058] The layer of gate conductor material 121 can optionally be polished (see process step 46). Additionally, the layer of gate conductor material 121 can be structured to form, for a gate connection 131, a first gate section 131a within the gate opening 111 and the second gate section 131b above the gate opening 111, and in particular above and immediately adjacent to the first gate section 131a, so that it is above the level of the upper surface of the dielectric layer 105 (see process step 47 and 48). Fig. 22A-22C). Optionally, the layer of gate conductor material 121 can be structured such that the second gate section 131b is wider than the first gate section 131a, and thus such that the second gate section 131b extends laterally onto the upper surface of the dielectric layer 105. Therefore, the structured gate conductor material for the gate connection 131 could, for example, be T-shaped, in the form of an inverted L, etc.

[0059] Following the structuring of the layer from the source / drain conductor material 122, additional processing can be carried out to complete the HEMT or MISHEMT structures (see process step 48). This additional processing can include, but is not limited to, the deposition of one or more additional dielectric layers 195 (e.g., an optional conformal etch stop layer, an interlayer dielectric layer, etc.) over the partially completed structure, the formation of middle-of-line (MOL) contacts (e.g., see MOL contact 198 to the gate terminal 131 and MOL contacts 199 to the source / drain terminals 132).

[0060] As mentioned above, the removal of the protective plug 113 and the sidewall spacers 114 in process step 42 could alternatively be skipped. In this case, in process step 43, the layer of a source / drain conductor material 122 can be deposited over the partially completed structure, and in particular over the protective plug 113, within the gate opening 111 and into the source / drain openings 112, such that it covers the sidewall spacers 114 and is positioned laterally between them (see Fig. 23A-23C). The layer of a source / drain conductor material 122 can then be structured, as described above in process step 44, to form, for each of the two source / drain terminals 132, a first source / drain section 132a positioned within a source / drain opening 112 and laterally between the sidewall spacers 114, and a second source / drain section 132b above the source / drain opening 112 and, in particular, above and immediately adjacent to the first source / drain section 132a, to be above the level of the upper surface of the dielectric layer 105 ( Fig. 24A-24C). In this case, the structuring of the layer from a source / drain conductor material 122 in process step 44 should further be carried out in order to expose the gate opening 111 by removing any source / drain conductor material from the gate opening 111 and from the upper surface of the dielectric layer 105 around the gate opening 111, and further by removing the protective plug 113. Process steps 45-48 can proceed as described above (see Fig. 25A-25C).

[0061] It should be noted that the structures resulting from process flow B, and in particular the configuration of the source / drain ports 132 in the resulting structure, vary depending on several factors. For example, the configuration of the source / drain ports depends on whether the optional CMP is performed at process step 46, and if so, whether the top surface of the second source / drain section 132b of each source / drain port 132 is exposed by the CMP. The configuration of each source / drain port 132 also depends on how the layer of gate conductor material 121 is actually structured, and in particular, whether sidewalls of each second source / drain section 132b of each source / drain port 132 are exposed during the structuring process.

[0062] For example, a CMP of the layer made of a gate conductor material 121 can be performed in process step 46 such that the top surfaces of the gate terminal 131 and the source / drain terminals 132 are coplanar, and such that the top surfaces of the second source / drain sections 132b are exposed. Subsequently, the layer made of the gate conductor material 121 can be structured in process step 47 such that the sidewalls of the second source / drain sections 132b are exposed. See the HEMT 2201, the MISHEMT 2202, and the MISHEMT 2203, respectively, in the semiconductor structures 2200A-2200C of [reference missing]. Fig. 22A-22C; see also the HEMT 2501, the MISHEMT 2502 and the MISHEMT 2503, each in the semiconductor structures 2500A-2500C of Fig. 25A-25C.

[0063] Alternatively, CMP of the gate conductor material can be performed in process step 46 such that the top surfaces of the gate terminal and the source / drain terminals are coplanar, and such that the top surfaces of every second source / drain section are exposed. Subsequently, the layer of gate conductor material can be structured in process step 47 such that the sidewalls of the second source / drain sections are not exposed. Thus, each source / drain terminal further comprises an additional source / drain section fabricated from the gate conductor material and positioned immediately adjacent laterally to the sidewalls of the second source / drain section.

[0064] Alternatively, CMP of the gate conductor material can be performed in process step 46 such that the top surfaces of the gate terminal and the source / drain terminals are coplanar, but the top surfaces of the second source / drain sections are not exposed (e.g., if the gate conductor material layer is thicker than the height of the second source / drain sections). Subsequently, in process step 47, the gate conductor material layer can be structured so that the sidewalls of the second source / drain sections are exposed. Thus, each source / drain terminal can further include an additional source / drain section fabricated from the gate conductor material, immediately adjacent to the top surface of the second source / drain section.

[0065] Alternatively, CMP of the gate conductor material can be performed in process step 46 such that the top surfaces of the gate terminal and the source / drain terminals are coplanar, but the top surfaces of the second source / drain sections are not exposed. Subsequently, the layer of gate conductor material can be structured in process step 47 so that the sidewalls of the second source / drain sections are also not exposed. Thus, each source / drain terminal can further comprise an additional source / drain section fabricated from the gate conductor material, which is immediately adjacent to both the top surface and the sidewalls of the second source / drain section.

[0066] Alternatively, a CMP of the gate conductor material can be skipped in process step 46, such that the top surfaces of the source / drain terminals are above the level of the top surface of the gate terminals, and such that the top surfaces of the second source / drain sections are not exposed. Subsequently, the layer of gate conductor material can be structured in process step 47 such that the sidewalls of the second source / drain sections are exposed. Thus, each source / drain terminal further comprises an additional source / drain section fabricated from the gate conductor material, which is immediately adjacent to the top surface of the second source / drain section.

[0067] Alternatively, a CMP of the gate conductor material can be skipped in process step 46, such that the top surfaces of the source / drain terminals are above the level of the top surface of the gate terminal, and such that the top surfaces of the second source / drain sections are not exposed. Subsequently, the layer of gate conductor material can be structured in process step 47 such that the sidewalls of the second source / drain sections are not exposed. Thus, each source / drain terminal can further comprise an additional source / drain section fabricated from the gate conductor material, which is immediately adjacent to both the top surface and sidewalls of the second source / drain section.

[0068] Since in the above-described process implementations following process flow B, the dielectric layer 105 is structured in parallel with the gate opening 111 for the first gate section 131a of the gate terminal 131 and with the source / drain openings 112 for the first source / drain sections 132a of the source / drain terminals 132, those lower / first gate and source / drain sections 131a and 132a within the dielectric layer 105 are considered to be self-aligned. Furthermore, since the structuring of the layer from the gate conductor material 121 to form the second gate section 131b of the gate terminal 131 also simultaneously affects the final form of the second source / drain sections 132b of the source / drain terminals 132, those sections at a higher level of the gate and source / drain terminals (i.e.The second gate section 131b and the second source / drain sections 132b, all located above the dielectric layer 105, are also considered self-aligned. These self-aligned multi-level gate and source / drain connections 131-132 prevent errors related to connection misalignment (e.g., when device sizes are reduced).

[0069] Also disclosed herein are embodiments of a semiconductor structure formed according to the method embodiments described above. See, for example, any of the semiconductor structures 900A-900C of Fig. 9A-9C, 1000A-1000C from Fig. 10A-10C, 1100A-1100C from Fig. 11A-11C, 1200A-1200C from Fig. 12A-12C, 1300A-1300C from Fig. 13A-13C, 1400A-1400C from Fig. 14A-14C, 2200A-2200C from Fig. 22A-22C and 2500A-2500C from Fig. 25A-25C.

[0070] In particular, the semiconductor structure comprises a substrate 101 and, on the substrate 101, a stack of layers.

[0071] The stack of layers can include several epitaxial layers. The epitaxial layers include: a buffer layer 102 on the substrate 101; a channel layer 103, and in particular a III-V semiconductor channel layer on the buffer layer 102; and a barrier layer 104 on the channel layer 103. For illustrative purposes, the drawings and description above depict the epitaxial layers in the stack (e.g., the buffer layer 102, the channel layer 103, and the barrier layer 104) as single layered structures (i.e., comprising a layer of buffer material, a layer of channel material, and a layer of barrier material). However, it is understood that alternatively, any or more of the epitaxial layers in the stack could be multilayered structures (e.g.,comprising multiple sub-layers of different buffer materials, multiple sub-layers of different III-V semiconductor channel materials, and / or multiple sub-layers of different barrier materials). In some embodiments (e.g., see the 900C semiconductor structures from [company name]). Fig. 9C, Fig. 1000C from Fig. 10C, Fig. 1100C from Fig. 11C, Fig. 1200C from Fig. 12C, Fig. 1300C from Fig. 13C, Fig. 1400C from Fig. 14C, Fig. 2200C from Fig. 22C and Fig. 2500C from Fig. 25C) the stack of layers may further comprise a gate dielectric layer 106 on the upper surface of the barrier layer 104. Finally, the stack of layers may comprise a blanket dielectric layer 105 on the upper surface of the barrier layer 104 or, if applicable, on the upper surface of the gate dielectric layer 106.

[0072] The semiconductor structure further includes a transistor. This transistor can be a high-electron mobility transistor (HEMT) (e.g., see HEMTs 901, 1001, 1101, 1201, 1301, 1401, 2201, and 2501 in the "A" figures). Alternatively, the transistor can be a metal-insulator semiconductor HEMT (MISHEMT) with a conformally deposited gate dielectric layer 108 (e.g., see MISHEMTs 902, 1002, 1102, 1202, 1302, 1402, 2202, and 2502 in the "B" figures). Alternatively, the transistor could be a MISHEMT with a stack-embedded gate dielectric layer 106 (e.g., see MISHEMTs 903, 1003, 1103, 1203, 1303, 1403, 2203, and 2503 in the "C" figures). Alternatively, the transistor could be any other similar type of transistor.

[0073] Each transistor, within the stack of layers discussed above, comprises a gate opening 111 and source / drain openings 112. The gate opening 111 can be narrower than the source / drain openings 112, as illustrated. For example, the gate opening 111 can have a first width (w1), and the source / drain openings 112 can have a second width (w2) that is larger than the first width (w1). Alternatively, the first width (w1) of the gate opening 111 could be equal to or greater than the second width (w2) of the source / drain openings.

[0074] The gate opening 111 extends from the upper surface of the dielectric layer 105 to the lower surface of the dielectric layer 105. In some embodiments (e.g., see semiconductor structures 900A-900B from Fig. 9A-9B, 1000A-1000B of Fig. 10A-10B, 1100A-1100B from Fig. 11A-11B, 1200A-1200B from Fig. 12A-12B, 1300A-1300B from Fig. 13A-13B, 1400A-1400B from Fig. 14A-14B, 2200A-2200B from Fig. 22A-22B and 2500A-2500B from Fig. 25A-25B) the bottom of the gate opening 111 can be at the upper surface of the barrier layer 104. In other embodiments (e.g. see the semiconductor structures 900C of Fig. 9C, Fig. 1000C from Fig. 10C, Fig. 1100C from Fig. 11C, Fig. 1200C from Fig. 12C, Fig. 1300C from Fig. 13C, Fig. 1400C from Fig. 14C, Fig. 2200C from Fig. 22C and Fig. 2500C from Fig. 25C) can be the bottom of the gate opening 111 on the upper surface of the stack-embedded gate dielectric layer 106.

[0075] The source / drain openings 112 each extend from the upper surface of the dielectric layer 105 to the channel layer 103. Thus, in some embodiments (e.g., see semiconductor structures 900A-900B of Fig. 9A-9B, 1000A-1000B of Fig. 10A-10B, 1100A-1100B from Fig. 11A-11B, 1200A-1200B from Fig. 12A-12B, 1300A-1300B from Fig. 13A-13B, 1400A-1400B from Fig. 14A-14B, 2200A-2200B from Fig. 22A-22B and 2500A-2500B from Fig. 25A-25B) each source / drain opening 112 extends completely through the dielectric layer 105 and the barrier layer 104 to the channel layer 103. In other embodiments, (e.g., see semiconductor structures 900C of Fig. 9C, Fig. 1000C from Fig. 10C, Fig. 1100C from Fig. 11C, Fig. 1200C from Fig. 12C, Fig. 1300C from Fig. 13C, Fig. 1400C from Fig. 14C, Fig. 2200C from Fig. 22C and Fig. 2500C from Fig. 25C) each source / drain opening 112 completely through the dielectric layer 105, the stack-embedded gate dielectric layer 106 and the barrier layer 104 to the channel layer 103.

[0076] In some embodiments, each source / drain opening 112 can have a substantially uniform width (as illustrated) or a width that tapers slightly towards the channel layer 103 (e.g., see semiconductor structures 900A-900C from Fig. 9A-9C, 1000A-1000C from Fig. 10A-10C, 1100A-1100C from Fig. 11A-11C, 1200A-1200C from Fig. 12A-12C, 1300A-1300C from Fig. 13A-13C and 1400A-1400C from Fig. 14A-14C). In other embodiments, each source / drain opening 112 may have a lower narrow section that is within the barrier layer 104 and, if present, the stack-embedded gate dielectric layer 106, and an upper wider section that is above the lower narrow section within the dielectric layer 105 (e.g., see semiconductor structures 2200A-2200C of Fig. 22A-22C and 2500A-2500C from Fig. 25A-25C). Optionally, in embodiments where each source / drain opening 112 has a lower narrow section and an upper wide section, sidewall spacers 114 can be positioned within the upper wider section above the barrier layer 104 (or, if applicable, above the gate dielectric layer 106) and further laterally adjacent to the sidewalls of the opening (e.g., see semiconductor structures 2500A-2500C of Fig. 25A-25C).

[0077] Each transistor further comprises a gate terminal 131. The gate terminal 131 includes a first gate section 131a and a second gate section 131b. The first gate section 131a is located within a gate opening 111 that extends through the dielectric layer 105 and has a base above the barrier layer 104 in the stack. The second gate section 131b is located above the gate opening 111 and, in particular, above and immediately adjacent to the first gate section 131a, so as to be above the level of the upper surface of the dielectric layer 105. The first gate section 131a and the second gate section 131b of the gate terminal 131 can be made of a structured layer of a gate conductor material 121. Optionally, the second gate section 131b can be wider than the first gate section 131a, such that it extends laterally onto the upper surface of the dielectric layer 105.Thus, the gate connection 131 could be T-shaped, in the form of an inverted L, etc. For illustrative purposes, the drawings and description depict the first and second gate sections 131a-131b (in combination) as a single layered structure (i.e., comprising one layer of a gate conductor material). However, it is understood that alternatively, the first and second gate sections 131a-131b (in combination) could be a multilayered structure (i.e., comprising several sub-layers of different conductor materials).

[0078] It should be noted that if the transistor is a HEMT (see the “A” figures), the gate terminal 131 can be a Schottky contact gate terminal, and the ground of the first gate section 131a can be immediately adjacent to the barrier layer 104. As discussed in more detail above with respect to the method embodiments, the gate conductor material 121 used for the gate terminal 131 of the HEMT must comprise a metal or metal alloy forming such a Schottky contact (i.e., a potential energy barrier for electrons) at the metal-semiconductor junction at the ground of the gate opening 111. Alternatively, if the transistor is a MISHEMT (see the “B” figures), a conformal gate dielectric layer 108 can line the gate opening 111 and the sides and bottom of the first gate section 131a can be immediately adjacent to the gate dielectric layer 108.Alternatively, if the transistor is a different MISHEMT (see the “C” figures) where a gate dielectric layer 106 is embedded in the stack, then the bottom of the first gate section 131a can be immediately adjacent to the gate dielectric layer 106. As discussed in more detail above with respect to the method embodiments, since such MISHEMTs do not require a Schottky contact gate termination, the gate conductor material 121 used for the gate termination of the MISHEMTs could comprise one or more sub-layers of any suitable gate conductor material (e.g., gate metal(s), gate metal alloy(s), doped polysilicon, etc.).

[0079] Each transistor further comprises a source / drain terminal 132. Each source / drain terminal 132 comprises a first source / drain section 132a and a second source / drain section 132b. The first source / drain section 132a is within a source / drain opening 112 that extends through the dielectric layer 105 and the barrier layer 104 to the channel layer 130. The second source / drain section 132b is above the source / drain opening 112 and, in particular, above and immediately adjacent to the first source / drain section 132a, so as to be above the level of the upper surface of the dielectric layer 105. In each source / drain connection 132, the first source / drain section 132a and the second source / drain section 132b can be made of a structured source / drain conductor material 122.Optionally, the second source / drain section 132b can be wider than the first source / drain section 132a, such that it extends laterally across the upper surface of the dielectric layer. Thus, each source / drain connection 132 could be T-shaped, in the form of an inverted L, etc. For illustrative purposes, the drawings and description depict the first and second source / drain sections (in combination) of each source / drain connection as a single layered structure (i.e., comprising one layer of conductor material). However, it is understood that alternatively, the first and second source / drain sections (in combination) of each source / drain connection can be a multilayered structure (i.e., comprising several sub-layers of different conductor materials).As discussed in more detail above with regard to the method implementations, the source / drain conductor material 122 should be suitable for forming ohmic contact source / drain connections at the metal-semiconductor junction at the bottom of the source / drain openings 112.

[0080] Additionally, it should be noted that, due to some alternative and / or optional process steps within the above described process implementations, certain features of the semiconductor structure implementations, in particular with regard to the structure of the gate terminal 131 and the structure of the source / drain terminals 132, may vary.

[0081] For example, semiconductor structure configurations formed according to the process flow A discussed above (e.g., see semiconductor structures 900A-900C from Fig. 9A-9C, 1000A-1000C from Fig. 10A-10C, 1100A-1100C from Fig. 11A-11C, 1200A-1200C from Fig. 12A-12C, 1300A-1300C from Fig. 13A-13C and 1400A-1400C from Fig. 14A-14C), the source / drain terminals 132 are completely free of the gate conductor material 121, but the gate terminal 131 may or may not be free of the source / drain conductor material 122. In particular, in some of these embodiments formed according to process flow A (e.g., see semiconductor structures 900A-900C of Fig. 9A-9C, 1000A-1000C from Fig. 10A-10C, 1100A-1100C from Fig. 11A-11C and 1200A-1200C from Fig. 12A-12C), the upper surfaces of the gate terminal 131 and the source / drain terminals 132 are essentially coplanar. In the semiconductor structure 900A-900C of Fig. In 9A-9C, the gate terminal 131 is also completely free of source / drain conductor material 122. However, in the semiconductor structure 1000A-1000C, Fig. In semiconductor structure 1100A-1100C, the gate terminal 131 features an additional gate section 131c, which is made of the source / drain conductor material 122 and is positioned laterally immediately adjacent to the side walls of the second gate section 131b. Fig. In semiconductor structures 11A-11C, the gate terminal 131 has an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to the upper surface of the second gate section 131b. This is also the case in semiconductor structures 1200A-1200C. Fig. In 12A-12C, the gate terminal 131 has an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to the upper surface and side walls of the second gate section 131b.

[0082] In other embodiments formed according to the above-mentioned process flow A, the upper surfaces of the gate terminal 131 and the source / drain terminals 132 are not coplanar (e.g., see semiconductor structures 1300A-1300C from Fig. 13A-13C and 1400A-1400C from Fig. 14A-14C). In particular, the top surface of the gate terminal 131 is at a first distance above the level of the top surface of the dielectric layer 105, and the top surfaces of the source / drain terminals are at a second distance, which is less than the first distance, above the level of the top surface of the dielectric layer 105. In the semiconductor structure 1300A-1300C of Fig. In semiconductor structures 13A-13C, the gate terminal 131 has an additional gate section 131c, which is made of the source / drain conductor material 122, is relatively thick, and is positioned immediately adjacent to the upper surface of the second gate section 131b. This is also the case in semiconductor structures 1400A-1400C. Fig. In 14A-14C, the gate terminal 131 can have an additional gate section 131c, which is made of the source / drain conductor material 122 and is immediately adjacent to both the top surface and the side walls of the second gate section 131b.

[0083] In semiconductor structure configurations formed according to the process flow B discussed above (e.g., see semiconductor structures 2200A-2200C from Fig. 22A-22C and 2500A-2500C from Fig.25A-25C) the gate terminal 131 can be completely free of the gate conductor material 121, but the source / drain terminals can be free of the gate conductor material 121 (as shown) or alternatively not free of the gate conductor material 121 (not shown).

[0084] In any case, each of the disclosed semiconductor structure embodiments can further comprise one or more additional dielectric layers 195 (e.g., an optional conformal etch stop layer, an interlayer dielectric layer, etc.) over the dielectric layer 105 and the second gate section 131b and the second source / drain sections 132b thereon. Each of the disclosed semiconductor structure embodiments can further comprise middle-of-line (MOL) contacts extending through the additional dielectric layer(s) 195 to the transistor (e.g., see MOL contact 198 to the gate terminal 131 and MOL contacts 199 to the source / drain terminals 132).

[0085] Additionally, it should be understood that in the process and structures described above, a semiconductor material refers to a material whose conductive properties can be modified by doping with an impurity. Exemplary semiconductor materials include silicon-based semiconductors (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material, and in particular a semiconductor material that is not doped with an impurity for the purpose of increasing conductivity (i.e., an undoped semiconductor material), is referred to in engineering as an intrinsic semiconductor.A semiconductor material doped with an impurity to increase its conductivity (i.e., a doped semiconductor material) is referred to in engineering as an extrinsic semiconductor and is more conductive than an intrinsic semiconductor made from the same base material. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon-germanium is more conductive than intrinsic silicon-germanium; and so on. It should also be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and that the dopants can vary depending on the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon-germanium, etc.)A silicon-based semiconductor material is typically doped with a group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped with a group V dopant, such as arsenic (As), phosphorus (P), or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels depend on the relative concentration levels of the dopant(s) in a given semiconductor region.

[0086] It should be understood that the terminology used herein serves the purpose of describing the disclosed structures and procedures and is not intended to be restrictive. For example, the singular forms "a," "an," "a," and "the," "the," "the," as used herein, are intended to include the plural forms unless the context clearly indicates otherwise. Additionally, the terms "comprises," "comprehensive," "includes," and / or "including," as used herein, specify the presence of specified features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.Furthermore, as used herein, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "upper," "lower," "below," "underneath," "above," "above," "parallel," "perpendicular," etc., are intended to describe relative locations as oriented and illustrated in the drawings (unless otherwise specified). Terms such as "touching," "in direct contact," "adjacent," "directly adjacent to," "immediately adjacent to," etc., are intended to indicate that at least one element is in physical contact with another element (without other elements separating the described elements). The term "lateral" is used herein to describe the relative locations of elements and, in particular, to indicate that an element is positioned on the side of another element, as opposed to above or below the other element, as oriented and illustrated in the drawings.For example, an element positioned laterally adjacent to another element is next to the other element; an element positioned laterally immediately adjacent to another element is directly next to the other element; and an element that laterally surrounds another element is adjacent to and encompassing the outer side walls of the other element. The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or action for performing the function in combination with other claimed elements, as specifically claimed.

Claims

[1] Structure encompassing: comprising a stack of layers: a channel layer (103); a barrier layer (104) on the channel layer (103); and a dielectric layer (105) on the barrier layer (104); Source / drain connections (132); and a gate connection (131) which is positioned laterally between the source / drain connections (132), wherein each source / drain connection (132) comprises: a first source / drain section (132a) within a source / drain opening (112) extending through the dielectric layer (105) and the barrier layer (104) to the channel layer (103); and a second source / drain section (132b) above the first source / drain section (132a) and the dielectric layer (105), wherein the gate terminal (131) comprises: a first gate section (131a) within a gate opening (111) extending through the dielectric layer (105) and having a bottom above the barrier layer (104); and a second gate section (131b) above the first gate section (131a) and the dielectric layer (105), wherein the first source / drain section (132a) and the second source / drain section (132b) comprise a source / drain conductor material (122) and the first gate section (131a) and the second gate section (131b) comprise a gate conductor material (121) that is different from the source / drain conductor material (122), and wherein the upper surfaces of the gate terminal (131) and the source / drain terminals (132) are coplanar and wherein the gate terminal (131) further comprises an additional gate section (131c) comprising the source / drain conductor material (122) which is positioned at least laterally immediately adjacent to the second gate section (131b). [2] Structure encompassing: comprising a stack of layers: a channel layer (103); a barrier layer (104) on the channel layer (103); and a dielectric layer (105) on the barrier layer (104); Source / drain connections (132); and a gate connection (131) which is positioned laterally between the source / drain connections (132), wherein each source / drain connection (132) comprises: a first source / drain section (132a) within a source / drain opening (112) extending through the dielectric layer (105) and the barrier layer (104) to the channel layer (103); and a second source / drain section (132b) above the first source / drain section (132a) and the dielectric layer (105), wherein the gate terminal (131) comprises: a first gate section (131a) within a gate opening (111) extending through the dielectric layer (105) and having a bottom above the barrier layer (104); and a second gate section (131b) above the first gate section (131a) and the dielectric layer (105), wherein the first source / drain section (132a) and the second source / drain section (132b) comprise a source / drain conductor material (122) and the first gate section (131a) and the second gate section (131b) comprise a gate conductor material (121) that is different from the source / drain conductor material (122), and wherein an upper surface of the gate terminal (131) is above a level of upper surfaces of the source / drain terminals (132) and wherein the gate terminal (131) further comprises an additional gate section (131c) comprising the source / drain conductor material (122) immediately adjacent to at least one upper surface of the second gate section (131b). [3] Structure according to claim 1 or claim 2, wherein the first gate section (131a) is immediately adjacent to the barrier layer (104) at a bottom of the gate opening (111). [4] Structure according to one of claims 1 to 2, wherein the stack of layers further comprises a gate dielectric layer (106) between the barrier layer (104) and the dielectric layer (105), wherein the gate opening (111) extends through the dielectric layer (105) to the gate dielectric layer (106), and wherein the first gate section (131a) is immediately adjacent to the gate dielectric layer (106) at the bottom of the gate opening (111). [5] Structure according to one of claims 1 or 2, further comprising: gate dielectric material (108) lining the gate opening (111), wherein the first gate section (131a) is immediately adjacent to the gate dielectric material (108). [6] Structure according to any one of claims 1 to 5, wherein the gate opening (111) is narrower than any source / drain opening (112). [7] Structure according to any one of claims 1 to 6, wherein each source / drain opening (112) has a lower section and an upper section which is wider than the lower section. [8] Structure according to claim 7, further comprising: side wall spacers (114) within the upper section of each source / drain opening (112). [9] Procedure encompassing: Forming a stack of layers comprising: a channel layer (103); a barrier layer (104) on the channel layer (103); and a dielectric layer (105) on the barrier layer (104); and Forming a transistor in the stack such that the transistor comprises: Source / drain connections (132); and a gate connection (131) which is positioned laterally between the source / drain connections (132), wherein each source / drain connection (132) comprises: a first source / drain section (132a) within a source / drain opening (112) extending through the dielectric layer (105) and the barrier layer (104) to the channel layer (103); and a second source / drain section (132b) above the first source / drain section (132a) and the dielectric layer (105), wherein the gate terminal (131) comprises: a first gate section (131a) within a gate opening (111) extending through the dielectric layer (105) and having a bottom above the barrier layer (104); and a second gate section (131b) above the first gate section (131a) and the dielectric layer (105), wherein the first source / drain section (132a) and the second source / drain section (132b) comprise a source / drain conductor material (122) and the first gate section (131a) and the second gate section (131b) comprise a gate conductor material (121) that is different from the source / drain conductor material (122), and wherein the upper surfaces of the gate terminal (131) and the source / drain terminals (132) are coplanar and wherein the gate terminal (131) further comprises an additional gate section (131c) comprising the source / drain conductor material (122) which is positioned at least laterally immediately adjacent to the second gate section (131b), or wherein an upper surface of the gate terminal (131) is above a level of upper surfaces of the source / drain terminals (132) and wherein the gate terminal (131) further comprises an additional gate section (131c) comprising the source / drain conductor material (122) immediately adjacent to at least one upper surface of the second gate section (131b). [10] Method according to claim 9, wherein forming the transistor comprises: forming multiple openings through the dielectric layer (105), wherein the multiple openings comprise source / drain openings (112) and a gate opening (111) positioned laterally between the source / drain openings (112); Deposition of a layer of gate conductor material (121) over the dielectric layer (105) and into the multiple openings; Structuring the layer of gate conductor material (121) to form, for the gate connection (131), the first gate section (131a) inside the gate opening (111) and the second gate section (131b) above the first gate section (131a) and the dielectric layer (105), wherein structuring the layer of gate conductor material (121) exposes the source / drain openings (112); Extending the source / drain openings (112) to the channel layer (103); Deposition of a layer of a source / drain conductor material (122) that is different from the gate conductor material (121); and Structuring the layer of source / drain conductor material (122) to form, for each source / drain connection (132), the first source / drain section (132a) within the source / drain opening (112) and the second source / drain section (132b) above the first source / drain section (132a) and the dielectric layer (105). [11] Method according to claim 10, further comprising, between the deposition of the layer from the source / drain conductor material (122) and the structuring of the layer from the source / drain conductor material (122), making the upper surfaces of the gate terminal (131) and the source / drain terminals (132) coplanar. [12] Method according to claim 10 or 11, wherein the structuring of the layer of the source / drain conductor material (122) is carried out such that the additional gate section (131c) of the gate connector (131) is positioned laterally immediately adjacent to the second gate section (131b). [13] Method according to one of claims 10 to 12, wherein the deposition and structuring of the layer from the source / drain conductor material (122) is carried out such that the source / drain conductor material (122) of the additional gate section (131c) comprises immediately adjacent to at least one upper surface of the second gate section (131b). [14] Method according to any one of claims 10 to 13, wherein the deposition of the layer from the gate conductor material (121) comprises deposition of the layer from the gate conductor material (121) in the gate opening (111) such that the first gate section (131a) is formed immediately adjacent to the barrier layer (104) at a bottom of the gate opening (111). [15] Method according to any one of claims 10 to 13, wherein the stack of layers further comprises a gate dielectric layer (106) between the barrier layer (104) and the dielectric layer (105), wherein each source / drain opening (112) extends through the dielectric layer (105), through the gate dielectric layer (106) and the barrier layer (104) to the channel layer (103), and wherein the gate opening (111) extends through the dielectric layer (105) to the gate dielectric layer (106) such that the first gate section (131a) of the gate terminal (131) is formed within the gate opening (111) immediately adjacent to the gate dielectric layer (106) at a base of the gate opening (111). [16] Method according to any one of claims 10 to 13, further comprising depositing a gate dielectric material (108) to line the multiple openings, wherein the first gate section (131a) of the gate terminal (131) is formed within the gate opening (111) immediately adjacent to the gate dielectric layer (108) and wherein extending the source / drain openings (112) ensures that the first source / drain section (132a) of each source / drain terminal (132) is formed immediately adjacent to the channel layer (103). [17] Method according to any one of claims 10 to 16, wherein the multiple openings in the dielectric layer (105) are formed concurrently such that the gate opening (111) is narrower than any source / drain opening (112). [18] Procedure encompassing: Forming a stack of layers comprising: a channel layer (103); a barrier layer (104) on the channel layer (103); and a dielectric layer (105) on the barrier layer (104); and Forming a transistor in the stack, wherein forming the transistor includes: forming multiple openings through the dielectric layer (105), wherein the multiple openings comprise source / drain openings (112) and a gate opening (111) positioned laterally between the source / drain openings (112), the gate opening (111) being narrower than the source / drain openings (112); Forming a protective plug in the gate opening (111) and sidewall spacers (114) in the source / drain openings (112); Extending the source / drain openings (112) to the channel layer (103); Deposition of a layer of a source / drain conductor material (122); Structuring the layer of source / drain conductor material (122) to form, for each of the two source / drain terminals (132), a first source / drain section (132a) within a source / drain opening (112) and a second source / drain section (132b) above the first source / drain section (132a) and the dielectric layer (105), wherein the structuring of the layer of source / drain conductor material (122) exposes the gate opening (111); Deposition of a layer of a gate conductor material (121) that is different from the source / drain conductor material (122); and Structuring the layer of gate conductor material (121) to form, for a gate connection (131), a first gate section (131a) inside the gate opening (111) and a second gate section (131b) above the first gate section (131a) and the dielectric layer (105), wherein the upper surfaces of the gate terminal (131) and the source / drain terminals (132) are coplanar, and wherein each source / drain terminal (132) further comprises an additional source / drain section comprising the gate conductor material (121) which is positioned at least laterally immediately adjacent to the second source / drain section (132b), or wherein upper surfaces of the source / drain terminals (132) are above a level of the upper surface of the gate terminal (131) and wherein each source / drain terminal (132) further comprises an additional source / drain section comprising the gate conductor material (121) immediately adjacent to at least one upper surface of the second source / drain section (132b).

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