Semiconductor devices with recesses and associated systems and methods

Abstract

A semiconductor assembly (150) comprising:a first semiconductor device (158a) having:a top surface (106a) with a plurality of first metal structures (108a, 108b) at a first lateral edge of the top surface, anda first dielectric layer (112a) over the top surface (106a), the first dielectric layer having a plurality of first recesses (114a, 114b) extending inwardly from the first lateral edge, the plurality of first recesses at least partially exposing the first metal structures (108a, 108b);a second semiconductor device (158b) attached to the first semiconductor device (158a), the second semiconductor device (158b) comprising: a bottom surface (106b) having a plurality of second metal structures (108c, 108d) at a second lateral edge of the bottom surface (106b), each second metal structure (108c, 108d) aligned with a corresponding first metal structure (108a, 108b) of the first semiconductor device (158a), and a second dielectric layer (112b) over the bottom surface (106b), the second dielectric layer having a plurality of second recesses (114c, 114d) extending inwardly from the second lateral edge, the plurality of second recesses at least partially exposing the second metal structures (108c, 108d), the second dielectric layer (112b) being aligned with the first dielectric layer (112a) of the first semiconductor device;anda plurality of plated structures (160) disposed within the first and second recesses (114a, 114b, 114c, 114d), each plated structure electrically coupling a first metal structure (108a, 108b) of the first semiconductor device (158a) to a corresponding second metal structure (108c, 108c) of the second semiconductor device (158b);

Description

TECHNICAL FIELD

[0001] The present technology relates generally to semiconductor devices, and more particularly to semiconductor devices having recessed edges and plated structures therein. BACKGROUND

[0002] Packaged semiconductor devices (semiconductor dies), including memory chips, microprocessor chips, and imager chips, typically comprise a semiconductor device (semiconductor die) mounted on a substrate and enclosed in a protective shell. The semiconductor device may contain functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads may be electrically connected to terminals outside the protective shell to enable the semiconductor device to be connected to higher-level circuitry.

[0003] Market pressures continually drive semiconductor manufacturers to reduce the size of chip packages and / or assemblies to fit the footprints of electronic devices, while simultaneously increasing the functional capacity of each package to meet operating parameters. One approach to increasing the processing power of a semiconductor package without significantly increasing the area covered by the package ("package footprint") is to vertically stack multiple semiconductor chips on top of each other in a single package. The elements (dies) in such vertically stacked assemblies can be interconnected by electrically coupling the bond pads of each element to the bond pads of neighboring elements through silicon vias (TSVs).These connections often contain pillars or bumps that increase the height of a vertical stack and limit the number of elements that can be included in a vertically stacked assembly.

[0004] US 2010 / 0 270 668 A1 concerns a chip package in which low-speed signals are transmitted via edge connectors and high-speed signals are transmitted via silicon vias. The edge connectors are formed in recesses formed in the sidewalls of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Many aspects of this technology can be better understood using the following drawings. The components in the drawings are not necessarily to scale. Instead, the focus is on clearly illustrating the principles of this technology. Fig. 1A is a side cross-sectional view of a semiconductor device configured in accordance with some embodiments of the present technology. Fig. 1B is a plan view of the semiconductor device of Fig. 1A. Fig. 1C is a side cross-sectional view of a semiconductor package at an initial stage of a manufacturing process according to embodiments of the present technology. Fig. 1D is a side cross-sectional view of the semiconductor assembly of Fig. 1C at a later stage of the manufacturing process. Fig. 2A is a side cross-sectional view of a semiconductor device according to embodiments of the present technology. Fig. 2B is a side cross-sectional view of another semiconductor device according to embodiments of the present technology. Fig. 2C is a side cross-sectional view of a semiconductor package at an initial stage of a manufacturing process according to embodiments of the present technology. Fig. 2D is a side cross-sectional view of the semiconductor assembly of Fig. 2C at a later stage of a manufacturing process. Fig. 2E is a side cross-sectional view of a lower device and an upper device according to embodiments of the present technology. Fig. 3A to 3D are side cross-sectional views illustrating various stages of a process or method for fabricating a plurality of semiconductor devices according to embodiments of the present technology. Fig. 4A to 4L are side cross-sectional views illustrating various stages of a process or method for fabricating a plurality of semiconductor devices according to embodiments of the present technology. Fig. 5 is a block diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present technology. Fig. 6 is a schematic view of a system including a semiconductor device or semiconductor package configured in accordance with embodiments of the present technology. DETAILED DESCRIPTION

[0006] Specific details of several embodiments of semiconductor devices, as well as associated systems and methods, are described below. In several of the embodiments described below, a semiconductor package configured according to the present technology may include a first semiconductor device. The first semiconductor device may have a top surface with a plurality of first metal structures at a first side edge of the top surface. The metal structures may be a pad, a bond pad, a contact, a layer, a region, a conductive element, etc., suitable for forming an electrical connection with another semiconductor device.The first semiconductor device may further include a first dielectric layer over the top surface including a plurality of first recesses extending inward from the first side edge and at least partially exposing the first metal structures. The semiconductor assembly may further include a second semiconductor device mounted on the first semiconductor device. The second semiconductor device may have a bottom surface having a plurality of second metal structures at a second side edge of the bottom surface. Each of the second metal structures may be aligned (e.g., vertically) with a corresponding first metal structure on the first semiconductor device. The second semiconductor device may further include a second dielectric layer over the bottom surface including a plurality of second recesses at least partially exposing the second metal structures.The second dielectric layer may be bonded to the first dielectric layer of the first semiconductor device.

[0007] The semiconductor package may further include a plurality of plated structures disposed within the first and second recesses of the first and second semiconductor devices. Each plated structure may electrically couple a first metal structure of the first semiconductor device to a corresponding second metal structure of the second semiconductor device. In some embodiments, the plated structures are deposited in the first and second recesses using an electroless plating process. As a result, the first and second semiconductor devices may be stacked vertically to form a semiconductor package, and the plated structures electrically coupling the first and second devices may add minimal, if any, height to the package.In contrast to conventional hybrid bonding techniques, which typically require very tight planarization tolerances to form high-yield device interconnections, the recesses around the element (die) described herein enable the formation of the plated structures after the elements are stacked, which can lead to larger process margins, since the recesses described herein can also serve as a guide for improved alignment accuracy to neighboring semiconductor devices.

[0008] Those skilled in the art will recognize that suitable stages of the methods described herein may be performed at the wafer level or at the die level. Therefore, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate, depending on the context in which it is used. Unless the context indicates otherwise, the structures disclosed herein may be formed using semiconductor manufacturing techniques, the details of which will be known to those skilled in the art. Materials may be deposited, for example, by chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, by plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0009] Numerous specific details are disclosed herein to provide a thorough and enabling description of embodiments of the present technology. However, one skilled in the art will understand that the technology may have additional embodiments and that the technology may be practiced without several of the details described below with reference to Fig. 1A-6. For example, some details of semiconductor devices and / or assemblies that are well known in the art have been omitted so as not to obscure the present technology. In general, it should be understood that various other devices and systems, in addition to the specific embodiments disclosed herein, may fall within the scope of the present technology.

[0010] As used herein, the terms "vertical," "lateral," "top," "bottom," "above," and "below" may refer to relative directions or positions of features in the semiconductor devices with respect to the orientation illustrated in the figures. For example, "top" or "topmost" may refer to a feature that is closer to the top of a side than another feature. However, these terms should be broadly interpreted to include semiconductor devices with other orientations, such as reversed or skewed orientations, where top / bottom, over / under, top / bottom, up / down, and left / right may be reversed depending on the orientation.

[0011] Fig. 1A is a side cross-sectional view of a semiconductor device 100 ("device 100") configured according to embodiments of the present technology. Device 100 may include a semiconductor element 102 ("semiconductor die") having a semiconductor substrate 104 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.).

[0012] In the illustrated embodiment, the semiconductor substrate 104 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) has a first side or surface 106a and a second side or surface 106b opposite the first side 106a. In some embodiments, the first side 106a may be a top side of the substrate 104, and the second side 106b may be a bottom side of the substrate 104. The first and / or second side 106ab of the semiconductor substrate 104 may be an active side or area containing one or more circuit elements (e.g., wires, traces, interconnects, transistors, etc.) formed in and / or on the respective first and / or second side 106a-b. The circuit elements may be, for example, memory circuits (e.g., dynamic random access memory (DRAM) or other types of memory circuits), control circuits (e.g.,DRAM control circuits), logic circuits, and / or other circuits. In other embodiments, the semiconductor substrate 104 may be a "blank" substrate that does not contain any integrated circuit components and is formed, for example, from crystalline, semi-crystalline, and / or ceramic substrate materials such as silicon, polysilicon, alumina (Al2O3), sapphire, and / or other suitable materials.

[0013] In the illustrated embodiment, the first side 106a of the semiconductor substrate 104 may be electrically connected to a plurality of first side metal structures 108a-b, and the second side 106b of the semiconductor substrate 104 may be electrically connected to a plurality of second side metal structures 108c-d (the first and second side metal structures 108a-d are collectively referred to as "metal structures 108"). Each of the metal structures 108 may be disposed at or near an edge (e.g., lateral edge, periphery, outer perimeter, etc.) of the semiconductor element 102 and / or near a lateral surface 113 of the semiconductor element 102. The metal structures 108 may be configured to electrically couple the device 100 to another semiconductor device, as described in detail below.The first-side metal structures 108a-b may correspond to the second-side metal structures 108c-d, such that each first-side metal structure 106a may be aligned (e.g., vertically) with a second-side metal structure 106b (e.g., 108a with 108c, 108b with 108d). Each of the metal structures 108 may have any suitable dimensions, such as a width and / or diameter of less than or equal to 5 µm, 2 µm, 1 µm, 500 nm, 200 nm, or 100 nm.

[0014] In the illustrated embodiment, the first-side metal structures 108a-b may be electrically connected to the corresponding second-side metal structures 108c-d by a plurality of connectors 110. The connectors 110 may be, for example, or include one or more silicon vias (TSVs) that extend through the semiconductor substrate 104 and electrically connect the first-side metal structures 108a-b to the corresponding second-side metal structures 108c-d. As shown in Fig. 1A, the connectors 110 may be electrically coupled to the metal structures 108 via routing elements 111 (e.g., redistribution layers (RDL), metallization layers, conductive traces, and / or other electrically conductive elements). In some embodiments, the connectors 110 are located at the inner and / or central regions of the semiconductor element 102, and the routing elements 111 may transmit signals from the connector 110 to the metal structures 108 at or near the side surfaces 113 of the semiconductor element 102.

[0015] In some embodiments, the connectors 110 and / or the routing elements 111 may be electrically coupled to one or more circuit elements (not shown) formed in and / or on the first and / or second sides 106a-b of the semiconductor substrate 104. Accordingly, signals generated by the one or more circuit elements may be transmitted from the connectors 110 to the metal structures 108 via the corresponding routing elements 111. The metal structures 108, the connectors 110, and / or the routing elements 111 may be made of any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, or any other suitable material, and combinations thereof.

[0016] The semiconductor element 102 further comprises a first insulating material 112a formed over at least a portion of the first side 106a of the semiconductor substrate 104, and a second insulating material 112b formed over at least a portion of the second side 106b of the semiconductor substrate 104 (collectively referred to as "insulating material 112"). The insulating material 112 may additionally be formed between the semiconductor substrate 104 and the plurality of metal structures 108 on the first and second sides 106a-b of the semiconductor substrate 104. In some embodiments, one or more side surfaces 113 of the substrate 104 may be at least partially or completely covered with a side insulating material 116 (e.g., a passivating material).

[0017] The insulating material 112 and / or the lateral insulating material 116 may each comprise one or more layers of a suitable dielectric material (e.g., a passivation material, a polyimide material, and / or other materials used to cover a surface of a semiconductor device). The insulating material 112 may, for example, include silicon oxide, silicon nitride, polysilicon nitride, polysilicon oxide, tetraethyl orthosilicate (TEOS), etc. In some embodiments, the insulating material 112 and / or the lateral insulating material 116 may at least partially include a dielectric material with a small dielectric constant compared to silicon oxide (a "low-kappa dielectric material").Such low-κ dielectric materials may include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, organic polymeric dielectrics, silicon-based polymeric dielectrics, etc. In some embodiments, the insulating material 112 may be a dielectric material suitable for direct dielectric bonding (e.g., oxide-oxide bonding, nitride-nitride bonding, etc.) to a dielectric material on another semiconductor device, as described further below.

[0018] In the illustrated embodiment, the insulating material 112 includes a plurality of recesses 114a-d (collectively referred to as "recesses 114") extending inwardly from the edges (e.g., side edge, perimeter, outer perimeter, etc.) of the first and second sides 106a-b of the semiconductor substrate 104. The positions and / or geometries of the recesses 114 may correspond to the positions and / or geometries of the metal structures 108, such that each recess 114 may at least partially or completely expose one of the metal structures 108. As described in more detail below, the recesses 114 may provide space for the formation of plated structures to connect the metal structures 108 to another device. The recesses 114 may have any suitable dimension, such as a height H of at least 50 nm, 100 nm, 200 nm, 400 nm, 500 nm, 1 µm, 2 µm, or 5 µm; and / or a depth D of at least 1 µm, 5 µm, 10 µm, 20 µm, or 25 µm.In some embodiments, each of the recesses 114 extends inwardly by the same amount (e.g., from the respective edges of the first and second sides 106a-b).

[0019] Fig. 1B is a plan view of the device 100 of Fig. 1A. Each of the metal structures 108 may be spaced apart and / or electrically insulated by non-recessed regions of insulating material 112. In the illustrated embodiment, the metal structures 108 and recesses 114 are distributed along all four sides of the device 100. In other embodiments, the metal structures 108 and / or recesses 114 may be distributed along one, two, or three of the lateral sides of the device 100. Each of the recesses 114 may have a width W of at least 1 μm, 5 μm, 10 μm, 20 μm, 25 μm, or another suitable width. As shown in Fig. 1B, the recesses 114 may have a square or rectangular shape and expose a correspondingly shaped portion 109 of the metal structures 108. In other embodiments, the recesses 114 and / or the metal structures 108 may have a circular, triangular, pentagonal, hexagonal, or any other suitable shape. Referring to Fig. 1A and Fig. 1B together, in some embodiments, the recesses 114 on the first and second sides 106a-b of the semiconductor substrate 104 (the second side 106b is in Fig. 1B) each have the same geometry (e.g., size and / or shape). In other embodiments, some or all of the recesses 114 on the first and / or second sides 106a-b may have different geometries. While the device 100 is illustrated with eight metal structures 108 and corresponding recesses 114 on each side 106a-b, in other embodiments the device 100 may have fewer or more metal structures 108 and corresponding recesses 114. For example, the device 100 may have one, two, three, four, five, six, seven, nine, ten, or more metal structures 108 and corresponding recesses 114 disposed between the substrate 104 and the insulating material 112.

[0020] Fig. 1C is a side cross-sectional view of a semiconductor package 150 ("package 150") at an initial stage of a manufacturing process according to embodiments of the present technology. The package 150 includes a plurality of semiconductor element stacks ("die stacks") 152a-d (e.g., "first element stack 152a," "second element stack 152b," "third element stack 152c," and "fourth element stack 152d") connected to a package substrate 154. In the illustrated embodiment, each of the element stacks 152a-d includes a corresponding plurality of vertically arranged semiconductor devices (e.g., first semiconductor device 100a, second semiconductor device 100b, third semiconductor device 100c, and fourth semiconductor device 100d—collectively, "devices 100"). Each of the devices 100 in the assembly 150 of Fig. 1C can be used with the Fig. 1A and Fig. 1B. For example, each of the devices 100 may include first and second sides 106a-b, metal structures 108, insulating material 112, and cutouts 114, as previously described in connection with Fig. 1A and Fig. 1B (the reference numerals for these components are shown only for the semiconductor devices 158a-b in the first element stack 152a for clarity).

[0021] For each of the element stacks 152a-d, the devices 100 may be vertically arranged such that the insulating materials 112 on the surfaces of adjacent semiconductor devices 158a-d are in direct contact with each other. For example, in the illustrated embodiment, the first insulating material 112a on the first side 106a of a lower semiconductor device 158a ("lower device 158a") contacts the second insulating material 112b on the second side 106b of an upper semiconductor device 158b ("upper device 158b"), as shown by the dashed line in the inset drawing. The first insulating material 112a on the lower device 158a may be mechanically coupled to the second insulating material 112b on the upper device 158a (e.g., via dielectric-to-dielectric bonding).Accordingly, the lower and upper devices 158a-b may be mechanically coupled to each other via the bond between the first and second insulating materials 112a-b.

[0022] In some embodiments, the devices 100 may be arranged such that the recesses 114 and / or metal structures 108 of adjacent elements are aligned with each other. For example, as shown in Fig. 1C, the recesses 114a and / or metal structures 108a on the first side 106a of the lower device 158a may be vertically aligned with the corresponding recesses 114c and / or metal structures 108c on the second side 106b of the upper device 158b. Each pair of aligned recesses 114a, 114c may form a gap 115 separating the corresponding metal structures 108a, 108c of the lower and upper devices 158a-b. The gap 115 may provide space for the formation of a plated structure to electrically connect the upper and lower devices 158a-b, as described further below.

[0023] In addition, as in Fig. 1C, the bottommost device 100 in each element stack 152a-d may be mechanically and electrically coupled to the package substrate 154. In the illustrated embodiment, for example, the second side 106b and / or the second insulating material 112b of the bottom device 158a may be mechanically coupled to the package substrate 154 (e.g., via an adhesive layer, dielectric-dielectric bonding with an insulating layer on the package substrate 154, etc.), and any metal structures 108 on the second side 106b may be electrically and / or mechanically coupled to the package substrate 154 (e.g., with corresponding metal structures or other electrical contacts on the package substrate 154 - in Fig. 1C). The assembly substrate 154 may be any structure suitable for supporting the element stacks 152a-d, and may be or include a redistribution layer, an interposer, a circuit board, a dielectric spacer, another semiconductor element (e.g., a logic semiconductor element), or another suitable substrate.

[0024] Although the illustrated embodiment shows the assembly 150 with four element stacks 152a-d, with each stack containing four devices 100, in other embodiments the assembly 150 may contain fewer or more element stacks (e.g., one, two, three, five, six, seven, eight, nine, ten, or more element stacks), and each element stack may contain fewer or more devices 100 (e.g., one, two, three, five, six, seven, eight, nine, ten, or more devices).

[0025] Fig. Figure 1D is a side cross-sectional view of assembly 150 of Fig. 1C at a later stage of the manufacturing process. In the illustrated embodiment, the assembly 150 includes a plurality of plated structures 160 that electrically interconnect adjacent semiconductor devices 100 (e.g., devices 158a-b). Each plated structure 160 may be positioned in a respective gap 115 between the correspondingly aligned recesses 114a, 114c to bridge and / or electrically couple the corresponding metal structures 108a of the lower device 158a to the metal structures 108c of the upper device 158b. This configuration of the recesses 114, the gaps 115, and / or the plated structures 160 may advantageously reduce the vertical separation between the individual devices 100.For example, since any plated structure 160 can be formed (e.g., plated) within the aligned recesses 114a, 114c and / or gap 115 formed when the lower device 158a is directly connected to the upper device 158b, the plated structure 160 does not contribute to the overall height of the two connected devices 158a-b.

[0026] The plated structure 160 may be formed from any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof. The plated structures 160 may be formed using any suitable technique, for example, an electroless plating process to deposit the conductive material into the corresponding recesses 114 and / or gaps 115. The electroless plating process may deposit a continuous volume of conductive material on the metal structures 108 and in the recesses 114 and / or gaps 115 to form an electrical connection with few or no voids, seams, gaps, etc. This may be advantageous in embodiments where the dimensions of the metal structures 108, the recesses 114, and / or the gaps 115 are relatively small.Furthermore, the electroless plating process may be performed at or near the end of a manufacturing process (e.g., after the element stacks 152a-d have been assembled) and may form the majority of the coated structures 160 in a single plating process. However, in other embodiments, the conductive material may also be deposited using other methods known to those skilled in the art, such as electroplating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other suitable methods.

[0027] In some embodiments, the method for forming the plated structures 160 may preferably deposit the conductive material on the metal structures 108 and in the corresponding recesses 114 and / or the gap 115, rather than on the side surfaces 113 of the devices 100. Any conductive material deposited on the side surfaces 113 may be removed after completion of the forming process, e.g., by etching or by techniques known to those skilled in the art. Alternatively, the amount of conductive material deposited on the side surfaces 113 may be sufficiently small and / or electrically insulated from each other so that it does not interfere with the electrical coupling of the devices 100 (e.g., does not cause an electrical short circuit of adjacent plated structures 160). However, in other embodiments, the side surfaces 113 of the devices 100 may be at least partially or completely covered with an insulating material (e.g.,the side insulating material 116 made of . Fig. 1A) to at least reduce or prevent the deposition of the conductive material on the side surfaces 113. In such embodiments, the insulating material may be deposited on the side surface 113 using a side surface passivation process prior to the formation of the plated structures 160, as described in more detail below.

[0028] In some embodiments, the assembly 150 includes a plurality of channels 170a-c (collectively referred to as "channels 170") between the element stacks ("die stacks") 152a-d such that each of the element stacks 152a-d is spaced apart from each other. For example, in the illustrated embodiment, the assembly 150 includes a first channel 170a between the first and second element stacks 152a-b, a second channel 170b between the second and third element stacks 152b-c, and a third channel 170c between the third and fourth element stacks 152c-d. The assembly 150 may optionally include one or more bridge structures 180 (shown in dotted lines) within each channel 170. The bridge structures 180 may be made of an electrically conductive material (e.g.,Copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof) configured to electrically couple adjacent element stacks. As shown in . Fig. 1D, the bridge structures 180 may bridge the metal structures 108 of the lowermost devices 100 in adjacent element stacks (e.g., 152a-b, 152b-c, and / or 152c-d) so that the element stacks can communicate directly with each other.

[0029] The bridge structures 180 can be formed before, during, or after the fabrication of the plated structures 160. In some embodiments, the bridge structures 180 are formed using the same or a similar technique as the plated structures 160, for example, using an electroless plating process. In such embodiments, the channels 170 can be dimensioned so small that the bridge structures 180 can be formed between the element stacks. For example, the channels 170 can have a width W that is no more than 500 µm, 400 µm, 300 µm, 250 µm, 200 µm, 150 µm, 100 µm, 50 µm, 20 µm, or 10 µm. Optionally, the regions of the assembly substrate 154 proximate the channels 170 may have grooves, cuts, etc. formed therein (not shown) to provide additional surface area for the deposition of material to form the bridge structures 180.However, in other embodiments, the bridge structures 180 are omitted, and the element stacks may instead communicate with each other via the package substrate 154.

[0030] In some embodiments, after the plated structures 160 are formed, the package 150 may be inserted into a semiconductor package. For example, the package substrate 154 may be bonded to conductive elements (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxies, and / or other suitable electrically conductive elements—not shown) configured to electrically connect the package 150 to an external device. Additionally, the package 150 may be encapsulated in a molding material, such as a resin, epoxy, silicone-based material, polyimide, or other material suitable for protecting the various components of the package 150 from contamination and / or physical damage.

[0031] Fig. 2A and Fig. 2B are cross-sectional views of semiconductor devices 200, 220 according to embodiments of the present technology. The components of the semiconductor devices 200, 220 of Fig. 2A and Fig. 2B can generally be assigned to the components of the device 100 of Fig. 1A and Fig. 1B. Consequently, like numbers (e.g., semiconductor substrate 104 versus semiconductor substrates 204, 224) are used to identify similar or identical components, and the description of the semiconductor devices 200, 220 of Fig. 2A and Fig. 2B is generally limited to the features that differ from the device 100 of the Fig. 1A and Fig. 1B, as well as other similar features necessary for the context. Furthermore, each of the features of the semiconductor devices 200, 220 of the Fig. 2A and Fig. 2B with each other and / or with the device 100 of Fig. 1A and Fig. 1B can be combined.

[0032] The semiconductor device 200 ("device 200") includes a plurality of recesses 214a-b (collectively referred to as "recesses 214") in a first insulating material 212a on a first side or surface 206a (e.g., a top side) of the semiconductor substrate 204, as shown in Fig. 2A. The recesses 214 can be aligned with the recesses 114 in the Fig. 1A and Fig. 1B may be identical or generally similar (e.g., with respect to height, depth, shape, etc.). The positions and / or geometries of the recesses 114 may correspond to the positions and / or geometries of a plurality of metal structures 208a-b (collectively, "metal structures 208"), such that each recess 114 may at least partially or completely expose the metal structures 208.

[0033] The device 200 also includes a plurality of conductive protrusions 218a-b (collectively referred to as "protrusions 218") extending from the second side or surface 206b (e.g., a bottom side) of the semiconductor substrate 204 and / or the second insulating material 212b thereon. Each of the protrusions 218 may be arranged at or near an edge and / or a side surface 213 of the device 200. Each protrusion 218 may be or include a conductive element suitable for forming an electrical connection with another semiconductor device, such that each protrusion 218 may be connected to a corresponding one of the metal structures 208c-d on the second side 206b of the semiconductor substrate 204. For example, in the illustrated embodiment, protrusion 218a is electrically coupled to metal structure 208c, and protrusion 218b is electrically coupled to metal structure 208d.Each of the plurality of protrusions 218a-b may include a conductive region 219a and an insulating region 219b. The conductive region 219a may be electrically connected to the metal structures 208c-d on the second side 206b of the semiconductor substrate. The insulating region 219b may be connected to the second insulating material 212b. In other embodiments, the plurality of protrusions 218a-b may include only the conductive region 219a.

[0034] The positions and / or geometries of the projections 218 may correspond to the positions and / or geometries of the recesses 214, e.g., to facilitate alignment during stack formation, as described below with reference to Fig. 2C. In some embodiments, the recesses 214 have a shape that is complementary to the corresponding projections 218. For example, the recesses 214 may have a shape that corresponds to the recesses 114 of the Fig. 1A-1B (e.g., square, rectangular, circular, triangular, pentagonal, hexagonal, or any other suitable shape), and the protrusions 218 may have a corresponding shape such that the protrusions 218 may at least partially fit into the recesses 214 of another semiconductor device, as described in detail below.

[0035] The recesses 214 may have a height and / or depth selected as previously described with respect to the recesses 114 in the Fig. 1A and Fig. 1B (e.g., height H and depth D), or any other suitable height and / or depth. The protrusions 218 may have similar dimensions to the recesses 214. For example, the protrusions 218 may have a height HP of at least 50 nm, 100 nm, 200 nm, 400 nm, 500 nm, 1 µm, 2 µm, or 5 µm and / or a length L of at least 1 µm, 5 µm, 10 µm, 20 µm, or 25 µm. In some embodiments, the dimensions of the protrusions 218 may be sufficiently smaller than the dimensions of the recesses 214 (e.g., L < D; and / or HP < H) such that the protrusions 218 may be at least partially fitted into the corresponding recesses 214 of another semiconductor device.

[0036] According to Fig. 2B, the semiconductor device 220 (“device 220”) may be substantially similar to the device 200 of Fig. 2A, except that the recesses 234 and projections 238 of the device 220 have inclined (e.g., beveled) surfaces. As in Fig. 2B, the device 220 includes a plurality of recesses 234a-b in a first insulating material 232a on a first side 226a (e.g., a top side) of the semiconductor substrate 224 and exposes a plurality of metal structures 228a-b. The device 220 further comprises a plurality of conductive protrusions 238a-b (collectively, "protrusions 238") extending from the second side 226b of the semiconductor substrate 224 and electrically connected to the respective metal structures 228c-d. Each of the protrusions 238 may include a conductive region 239a corresponding to the conductive region 219a of Fig. 2A, and an insulating region 239b corresponding to the insulating region 219b of Fig. 2A is similar or generally the same. The recesses 234a-b may have similar dimensions (e.g., height, depth) as the recesses 114 in the Fig. 1A and Fig. 1B. The protrusions 238a-b may have similar dimensions to the recesses 234a-b, so that the protrusions 238a-b may at least partially fit into the corresponding recesses 234a-b of another semiconductor device.

[0037] In the illustrated embodiment, the first insulating material 232a further includes a first bevel 240 at an edge of the first insulating material 232a surrounding the recesses 234a-b (e.g., adjacent, contiguous, proximate). Additionally, the device 220 may include a metal structure bevel 244 aligned below and corresponding to the first bevel 240. The metal structure bevel 244 may be part of the metal structure 228 or electrically and / or mechanically connected to the metal structure 228. The insulating region 239b and / or the second insulating material layer 232b may further include a second bevel 242 corresponding to the first bevel 240 in the first insulating material 232a. The positions and / or geometries of the second bevel 242 may match the positions and / or geometries of the first bevel 240, e.g.,to facilitate alignment during element stacking, as described below with reference to . Fig. 2C. The first bevel 240, the second bevel 242, and the metal structure bevel 244 may have any suitable geometry. For example, the first bevel 240 may have an angle A, the metal structure bevel 244 may have an angle B, and the second bevel 242 may have an angle C. The angles A, B, and C may each independently be at least 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, or any other suitable angle. In some embodiments, the angles A, B, and C may each form the same angle, or some or all of the angles A, B, and C may be different angles. Furthermore, the first bevel 240, the second bevel 242 and / or the metal structure bevel 244 may be beveled, conical, concave, convex or any other suitable shape.

[0038] Fig. 2C and Fig. 2D show a side cross-sectional view of a semiconductor package 250 ("package 250") at various stages of a manufacturing process according to embodiments of the present technology. The components of the package of the Fig. 2A and Fig. 2D can essentially be assigned to the components of assembly 150 of the Fig. 1C and Fig. 1D. Consequently, like reference numerals (e.g., assembly 150 versus assembly 250) are used to identify similar or identical components, and the description of assembly 250 of the Fig. 2C and Fig. 2D is limited to the features that differ from assembly 150 of the Fig. 1C and Fig. 1D, as well as other similar features necessary for the context. In addition, each of the features of the assembly 250 of the Fig. 2C and Fig. 2D with each other and / or with the assembly 150 of the Fig. 1C and Fig. 1D can be combined.

[0039] It will initially be Fig. 2C, wherein the assembly 250 in an initial stage of a manufacturing process includes a plurality of semiconductor element stacks 252a-d, and wherein each of the element stacks 252a-d may include a corresponding plurality of semiconductor devices 200a-d (collectively, "devices 200"). Although the devices 200a-d may be identical or similar to the device 200 of Fig. 2A, the devices 200a-d may, in other embodiments, be identical or similar to the device 220 of Fig. 2B. Optionally, at least one of the element stacks 252a-d may include devices that are compatible with the device 200 of Fig. 2A are identical or similar, and at least a second of the element stacks 252a-d may include devices that are compatible with the device 220 of Fig. 2B are identical or similar.

[0040] Each of the devices 200 may include a plurality of metal structures 208, a plurality of recesses 214, and a plurality of conductive protrusions 218 (reference numerals are shown only for the devices 258a-b of the element stack 252a for clarity). The devices 200 may be arranged such that the recesses 214 and protrusions 218 of adjacent elements are aligned with each other. For example, as shown in Fig. 2C, the recesses 214a and / or metal structures 208a of the lower device 158a may be vertically aligned with the corresponding protrusions 218a of the upper device 158b. In some embodiments, the protrusions 218a may occupy at least a portion of the corresponding recesses 214a such that the metal structures 208a remain at least partially exposed. However, in other embodiments, the protrusions 218a may completely fill the corresponding recesses 214a and / or directly contact the metal structures 208a. The complementary positions and / or geometries of the recesses 214 and the protrusions 218 may facilitate the alignment of adjacent (e.g., vertically aligned) devices 200.For example, the projections 218 of the upper device 258b may at least partially fit into the recesses 214 of the lower device 258a so that the upper device 258b may be at least partially mechanically coupled to the lower device 258a.

[0041] With further reference to Fig. 2C, the bottommost devices 200 in each element stack 252a-d may be mechanically and electrically coupled to a package substrate 254. In the illustrated embodiment, for example, the second side 206b and / or the second insulating material 212b of the bottom device 258a may be mechanically coupled to the package substrate 254 (e.g., via an adhesive layer, dielectric-dielectric bonding with an insulating layer on the package substrate 254, etc.), and any metal structures 208 and / or protrusions 218 on the second side 206b may be electrically and / or mechanically coupled to the mounting substrate 254 (e.g., with corresponding metal structures or other electrical contacts on the package substrate 254 - in Fig. 2C not shown).

[0042] As in Fig. 2D, the assembly 250 comprises, in a subsequent phase of a manufacturing process, a plurality of plated structures 260 that are substantially similar to the plated structures 160 of Fig. 1D. The plated structures 260 may electrically connect adjacent semiconductor devices 200. Each plated structure 260 may be positioned between the corresponding recesses 214a and protrusions 218a of the lower and upper devices 258a-b to bridge and / or electrically couple the metal structures 208a of the lower device 258a to the corresponding protrusions 218a of the upper device 258b. The plated structures 260 may be made of any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof. The plated structures 260 may be formed using techniques that are identical or substantially similar to the techniques previously described with respect to Fig. 1C and Fig. 1D and the plated structures 160 were described.

[0043] In some embodiments, the assembly 250 may further include a plurality of channels 270a-c between the element stacks 252a-d such that each of the element stacks 252a-d is spaced apart from each other. The channels 270a-c may be connected to the channels 170a-c of the Fig. 1D may be identical or generally similar. The assembly 250 may optionally include one or more bridge structures 280 (shown in dotted lines) in each channel 270. The bridge structures 280 may be connected to the bridge structures 180 of Fig. 1D be identical or substantially similar.

[0044] Although the Fig. 2C and Fig. 2D comprises projections 218 which, according to the embodiments of Fig. 2A, in other embodiments, the assembly 250 may include conductive protrusions configured according to the embodiments of Fig. 2B are configured. As in Fig. 2E, for example, a lower device 258a has a recess 234a having a first bevel 240, and an upper device 258b has a projection 238a having a second bevel 242. The first bevel 240 of the lower device 258a may be vertically aligned with the second bevel 242 of the upper device. As previously discussed with respect to Fig. 2B, the first bevel 240 and the second bevel 242 may have the same angle. The complementary positions and / or geometries of the first and second bevels 240, 242 may facilitate the alignment of the devices 258a-b. For example, the angled surfaces of the first and second bevels 240, 242 may guide (e.g., direct, steer, etc.) the partially aligned protrusion 238a toward the corresponding recess 234a. This may advantageously facilitate the alignment of the element stack during the manufacturing process. Subsequently, a plated structure (not shown) may be formed in the recess 234a to electrically couple the metal structures 228a, 228c of the devices 258a-b, as previously discussed with reference to Fig. 2D. In still other embodiments, the assembly 250 may include a combination of the conductive protrusions of Fig. 2A and Fig. 2B and additionally conductive projections having any other suitable configuration.

[0045] Fig. 3A to 3D are side cross-sectional views illustrating various stages of a process or method for fabricating a plurality of semiconductor devices according to embodiments of the present technology. The method may be used to fabricate any embodiment of the semiconductor devices described herein and / or one or more components thereof (e.g., the device 100 of Fig. 1A and Fig. 1B, the device 200 from Fig. 2A and the device 220 from Fig. 2B). Although Fig. 3A-3D show a manufacturing process for five semiconductor devices, in practice the process may be scaled or otherwise adapted for any suitable number of semiconductor devices (e.g., a single semiconductor device, tens or hundreds of semiconductor devices, etc.).

[0046] With reference to Fig. 3A, the method comprises forming a plurality of connectors 310 on and / or at least partially through a first side 306a of a semiconductor substrate 304. The connectors 310 may, for example, be or comprise one or more silicon vias (TSVs) extending at least partially through the semiconductor substrate 304. The method may further comprise forming a plurality of metal structures 308a on a first side 306a of a semiconductor substrate 304. The metal structures 308 may be electrically coupled to the connectors 310 via routing elements 311 (e.g., RDLs, metallization layers, traces, and / or other electrically conductive elements). The method may further comprise forming a first insulating material 312a on the first side 306a and / or at least partially over the metal structures 308a, according to semiconductor manufacturing techniques known to those skilled in the art.The method may also include forming a first plurality of recesses 314a in the first insulating material 312a to partially or fully expose the metal structures 308a. For example, the first insulating material 312a may be deposited over parts or all of the metal structures 308a, and then the recesses 314 may be formed by selectively removing part or all of the first insulating material 312a over the metal structures 308a, e.g., by etching or other suitable material removal techniques. Alternatively, the first insulating material 312a may be selectively deposited on the first side 306a at locations away from the metal structures 308a such that the metal structures 308a remain exposed. The first insulating material 312a may be any suitable insulating material, including those discussed herein (e.g., insulating material 112a-b of FIG. Fig. 1A and Fig. 1B), and can be formed using techniques known to those skilled in the art, such as a chemical vapor deposition (CVD) process.

[0047] According to Fig. 3B, the method further includes using an adhesive 380 to bond the first side 306a of the semiconductor substrate 304 and the first insulating material 312a to a first support substrate 382. The adhesive 380 may be any suitable adhesive material known to those skilled in the art. The first support substrate 382 may be a wafer or other structure made of silicon, glass, ceramic, or other suitable material.

[0048] As in Fig. 3C, the method further comprises thinning a second side 306b of the semiconductor substrate 304. Thinning the second side 306b of the semiconductor substrate 304 may be performed using techniques known to those skilled in the art, such as a chemical mechanical planarization (CMP) process. After thinning, the method may then comprise forming a plurality of second metal structures 308b, a plurality of routing elements 311, a second insulating material 312b, and a second plurality of recesses 314b on the second side 306b. The connectors 310 may electrically couple the routing elements 311 and the plurality of second metal structures 308b. The routing elements 311 and / or the plurality of second metal structures 308b may be formed from the same and / or a different conductive material and may be formed using techniques known to those skilled in the art.The second insulating material 312b may be any suitable insulating material, including the materials discussed herein (e.g., the insulating material 112a-b of . Fig. 1A and Fig. 1B), and can be formed using techniques known to those skilled in the art, such as a chemical vapor deposition (CVD) process.

[0049] With reference to Fig. 3D, the method further comprises bonding the second side 306b of the semiconductor substrate 304 and the second insulating material 312b to a second carrier substrate 384 and separating the first side 306a of the semiconductor substrate 304 and the first insulating material 312a from the adhesive 380 and the first carrier substrate 382. Fig. 3C. The first carrier substrate 382 may be separated from the first side 306a and the first insulating material 312a by dissolving, peeling, or otherwise decoupling the adhesive 380, for example, using a suitable stimulator (e.g., heat, light) or agent (e.g., solvent, water). In some embodiments, the second carrier substrate 384 may be a dicing tape mounted on a film frame 386. The semiconductor substrate 304 may then be cut to form a plurality of singulated semiconductor devices (not shown).

[0050] Fig. 4A-4L are side cross-sectional views illustrating various stages of a process or method for fabricating a plurality of semiconductor devices according to embodiments of the present technology. The method may be used to apply a passivation material to a side surface of a semiconductor device (e.g., device 100 of Fig. 1A, device 200 from Fig. 2A and / or device 220 from Fig. 2B). The method may be used during the manufacture of any embodiment of the semiconductor devices described herein and / or one or more components thereof (e.g., the device 100 of Fig. 1A and Fig. 1B, the device 200 from Fig. 2A and / or the device 220 from Fig. 2B). Optionally, some or all of the steps of the method from Fig. 4A-4L with some or all steps of the procedure of Fig. 3A-3D can be combined.

[0051] With reference to Fig. 4A, the method includes forming a plurality of grooves 401 in a first side 406a of a semiconductor substrate 404. The semiconductor substrate 404 may contain functional elements, such as circuit elements, connectors (e.g., vias), etc., as previously described (omitted for clarity). The grooves 401 may be formed in the semiconductor substrate 404 in accordance with techniques known to those skilled in the art. For example, the grooves 401 may be formed by applying a photoresist 402 to the first side 406a, selectively removing portions of the photoresist 402 over the desired locations of the grooves 401, and then selectively removing portions of the semiconductor substrate 404 not covered by the photoresist 402 (e.g., by dry etching) to form the grooves 401. The photoresist 402 can be removed after the grooves 401 are formed.

[0052] As in Fig. 4B, the method further includes forming a first insulating material 412a on the first side 406a and in the grooves 401 of the semiconductor substrate 404. The first insulating material 412a may be any insulating material as previously described and may be deposited using any suitable technique known to those skilled in the art. For example, the first insulating material 412a may be a nitride or oxide material and may be deposited using a chemical vapor deposition (CVD) process.

[0053] As in Fig. 4C, the method further comprises selectively removing the portions of the first insulating material 412a located on the horizontal surfaces of the semiconductor substrate 404 (e.g., first side 406a and / or bottom surfaces 403 of the grooves 401), while preserving the portions of the first insulating material 412a located on the vertical surfaces 405 of the notches 401. This may be achieved using any suitable technique known to those skilled in the art, e.g., by dry etching.

[0054] As in Fig. 4D (the orientation of the semiconductor substrate 404 is different compared to the Fig. 4A-4C (conversely), the method further comprises applying an adhesive 480 to at least partially cover the first side 406a of the semiconductor substrate 404 and to at least partially or completely fill the grooves 401. The adhesive 480 may be a thermosetting adhesive (e.g., a thermosetting adhesive manufactured by Nissan Chemical) or another suitable adhesive. The adhesive 480 may be applied using any suitable technique known to those skilled in the art, such as spin coating, dip coating, spray coating, etc.

[0055] According to Fig. 4E, the method further includes using the adhesive 480 to bond the semiconductor substrate 404 to a support substrate 482. The support substrate 482 may be a wafer or other structure made of silicon, glass, ceramic, or other suitable material.

[0056] As in Fig. 4F, the method further comprises removing at least a portion of the semiconductor substrate 404 from a second side 406b of the semiconductor substrate 404. The portion of the semiconductor substrate 404 may be removed, for example, using a CMP process or other suitable technique known to those skilled in the art. In some embodiments, the amount of the removed semiconductor substrate 404 may be sufficiently small such that the first insulating material 412a and the adhesive 480 are not exposed and remain covered by a portion of the semiconductor substrate 404. However, in other embodiments, the amount of the removed semiconductor substrate 404 may be sufficiently large such that at least a portion of the first insulating material 412a and the adhesive 480 is exposed on the second side 406b of the semiconductor substrate 404.

[0057] Referring to Fig. 4G, the method further comprises selectively removing additional portions of the second side 406b of the semiconductor substrate 404 to expose one or more terminals (e.g., vias) formed in the semiconductor substrate 404 (in Fig. 4G not shown). The portion of the semiconductor substrate 404 may be removed, for example, using a silicon dry etching process or another suitable technique known to those skilled in the art. In the illustrated embodiment, after the removal process, the first insulating material 412a and the adhesive 480 may be exposed and extend beyond the second side 406b of the semiconductor substrate 404. Accordingly, the semiconductor substrate 404 may be divided into a plurality of discrete semiconductor elements ("dies") 400a-g (collectively, "dies 400") by the first insulating material 412a and the adhesive 480.

[0058] As in Fig. 4H, the method further includes applying a second insulating material 412b on the second side 406b of the dies (semiconductor elements) 400 to at least partially cover the dies 400, the first insulating material 412a, and / or the adhesive 480 between the dies 400. The second insulating material 412b may be the same as or different from the first insulating material 412a and may be any suitable insulating material, including the materials discussed previously (e.g., an oxide or nitride material). The second insulating material 412b may be applied using any suitable technique known to those skilled in the art.

[0059] As in Fig. 4l, the method further comprises removing a portion of the second insulating material 412b to expose the vias (not shown) on the second side 406b of the dies 400. In the illustrated embodiment, this also comprises removing the portions of the second insulating material 412b located above the adhesive 480 to at least partially expose the adhesive 480 between the individual dies 400. The portion(s) of the second insulating material 412b may be removed using any suitable technique known to those skilled in the art, e.g., using an oxide CMP process.

[0060] According to Fig. 4J, the method further comprises removing at least a portion of the adhesive 480 between the dies 400 such that the top surfaces of the adhesive 480 are recessed from the top surfaces of the second insulating material 412b. This may be accomplished using a cleaning process based on the chemistry of the adhesive 480 or another suitable method or technique known to those skilled in the art.

[0061] As in Fig. 4K, the method further includes separating the dies 400 from the adhesive 480 and the support substrate 482 and applying the second insulating material 412b to the dies 400 on a second support substrate 486 (e.g., dicing tape or foil mounted in a frame). The adhesive 480 and the support substrate 482 may be removed using any suitable technique known to those skilled in the art. In the illustrated embodiment, portions of the adhesive 480 may remain between the dies 400 after the dies 400 are attached to the second support substrate 486. In other embodiments, the adhesive 480 may be completely removed from between the dies 400 when the dies 400 are attached to the second support substrate 486.

[0062] As in Fig. 4L, the method further comprises removing adhesive residues 480 (not shown) between the dies 400. This may be done using the same method previously described with respect to Fig. 4J, or by any suitable method or technique known to those skilled in the art. In the illustrated embodiment, the dies 400 may have side surfaces 413 that are at least partially covered with the first insulating material 412a (e.g., a side surface passivation material). In some embodiments, the dies 400 may be separated from the second carrier substrate 486 and used in the fabrication of semiconductor devices (e.g., the devices 100, 200, and / or 220 of Fig. 1A-1B, 2A and 2B) according to embodiments of the present technology.

[0063] Fig. 5 is a block diagram illustrating a method 500 for manufacturing a semiconductor package according to embodiments of the present technology. The method 500 may be used to manufacture any embodiment of the semiconductor packages described herein and / or one or more components thereof (e.g., package 150 of the Fig. 1C-1D, assembly 250 of the Fig. 2C-2D) can be used.

[0064] In block 510, the method 500 may include forming a plurality of recesses in a first dielectric layer on a first side or surface of a first semiconductor device. The recesses may expose a plurality of metal structures at an edge (e.g., periphery, outer perimeter, etc.) on the first side of the first semiconductor device (e.g., as previously described with reference to Fig. 1A, Fig. 2A and Fig. 2B). In some embodiments, the plurality of metal structures is a plurality of first metal structures. The recesses may, for example, be formed with the metal structures described above with reference to Fig. 3A-3D.

[0065] In block 520, the method 500 may further include coupling the first dielectric layer of the first semiconductor device to a second dielectric layer on a second side or face of a second semiconductor device. In some embodiments, the first semiconductor device may be a top device, the first side may be a bottom side, the second semiconductor device may be a bottom device, and the second side may be a top side. The second side of the semiconductor device may include a plurality of conductive elements that may be aligned (e.g., vertically aligned) with the metal structures and the recesses of the first semiconductor device (e.g., as previously described with reference to Fig. 1C-1D and 2C-2D). In some embodiments, the plurality of conductive elements comprises a plurality of second metal structures, and the second dielectric layer comprises a plurality of recesses at least partially exposing the plurality of second metal structures (e.g., as previously described with reference to Fig. 1A). In other embodiments, the plurality of conductive elements comprises a plurality of conductive protrusions extending from the second dielectric layer (e.g., as previously described with reference to Fig. 2A and Fig. 2B). In such embodiments, connecting the first and second dielectric layers may include inserting the plurality of conductive protrusions of the second semiconductor device into the corresponding plurality of recesses of the first semiconductor device.

[0066] In block 530, the method 500 may further comprise depositing a conductive material into the recesses to electrically couple the metal structures of the first semiconductor device to the conductive elements of the second semiconductor device (e.g., as previously described with reference to Fig. 1C, Fig. 1D, Fig. 2C and Fig. 2D). As described above, the conductive material may form interconnect structures that electrically connect the first and second semiconductor devices.

[0067] Each of the semiconductor devices and / or assemblies having the features described above with reference to Fig. 1A-5 can be incorporated into a variety of larger and / or more complex systems, a representative example of which is the system shown in Fig. 6 is a schematically illustrated system 600. The system 600 may include a processor 602, a memory 604 (e.g., SRAM, DRAM, Flash, and / or other storage devices), input / output devices 606, and / or other subsystems or components 608. The system 600 described above with reference to Fig. 1A-5, semiconductor devices and / or assemblies may be used in any of the Fig.6. The resulting system 600 may be configured to perform a variety of suitable computing, processing, storage, sensing, and imaging functions and / or other functions. Accordingly, representative examples of the system 600 include, without limitation, computers and / or other computing devices, such as desktop computers, laptop computers, internet devices, handheld devices (e.g., palm-top computers, portable computers, mobile phones or cellular phones, personal digital assistants, music players, etc.), tablets, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative examples of the system 600 include lights, cameras, vehicles, etc. With regard to these and other examples, the system 600 may be housed in a single unit or distributed across multiple interconnected units, e.g.,via a communications network. The components of system 600 may accordingly include local and / or remote storage devices and a plurality of suitable computer-readable media.

Claims

[1] Semiconductor assembly (150) comprising: a first semiconductor device (158a) comprising: an upper surface (106a) having a plurality of first metal structures (108a, 108b) at a first lateral edge of the upper surface, and a first dielectric layer (112a) over the top surface (106a), the first dielectric layer having a plurality of first recesses (114a, 114b) extending inwardly from the first lateral edge, the plurality of first recesses at least partially exposing the first metal structures (108a, 108b); a second semiconductor device (158b) attached to the first semiconductor device (158a), the second semiconductor device (158b) comprising: a lower surface (106b) having a plurality of second metal structures (108c, 108d) at a second lateral edge of the lower surface (106b), each second metal structure (108c, 108d) being aligned with a corresponding first metal structure (108a, 108b) of the first semiconductor device (158a), and a second dielectric layer (112b) over the bottom surface (106b), the second dielectric layer having a plurality of second recesses (114c, 114d) extending inwardly from the second lateral edge, the plurality of second recesses at least partially exposing the second metal structures (108c, 108d), the second dielectric layer (112b) being connected to the first dielectric layer (112a) of the first semiconductor device; and a plurality of plated structures (160) disposed within the first and second recesses (114a, 114b, 114c, 114d), each plated structure electrically coupling a first metal structure (108a, 108b) of the first semiconductor device (158a) to a corresponding second metal structure (108c, 108c) of the second semiconductor device (158b). [2] The semiconductor assembly (150) of claim 1, wherein: each first recess (114a, 114b) and a corresponding second recess (114c, 114d) together form a gap (115), the corresponding first and second metal structures exposed by the first and second recesses, respectively, are spaced apart from each other by the gap (115), and the corresponding plated structure (160) electrically coupling the first and second metal structures bridges the gap. [3] The semiconductor assembly (150) of claim 1, further comprising a passivation material over one or more side surfaces of the first and second semiconductor devices. [4] The semiconductor device (150) of claim 1, wherein an exposed portion of each of the first and second metal structures has a rectangular shape. [5] The semiconductor device (150) of claim 1, wherein the plurality of first and second recesses each have a height in a range of 200 nm to 2 µm and a depth of 25 µm or less. [6] The semiconductor device (150) of claim 1, wherein each plated structure includes copper. [7] The semiconductor package (150) of claim 1, wherein each plated structure does not extend beyond the first and second side edges. [8] The semiconductor device (150, 250) of claim 1, wherein the first recesses (114a, 114b) and the second recesses (114c, 114d) extend inward by the same amount. [9] The semiconductor device (150) of claim 1, wherein the first and second dielectric layers (112a, 112b) each comprise at least one of the following materials: silicon oxide, silicon nitride, polysilicon nitride, polysilicon oxide, and tetraethylorthosilicate (TEOS). [10] Semiconductor assembly (250) comprising: a first semiconductor device (258a) comprising: an upper surface (206a) having a plurality of metal structures (208a, 208b; 228a, 228b) at a first lateral edge of the upper surface, and a first dielectric layer (212a; 232a) over the top surface, the first dielectric layer (212a; 232a) having a plurality of recesses (214a, 214b; 234a, 234b) extending inwardly from the first lateral edge, the plurality of recesses at least partially exposing the metal structures (208a, 208b; 228a, 228b); a second semiconductor device (258b) attached to the first semiconductor device (258a), the second semiconductor device (258b) comprising: a lower surface (206b) having a second dielectric layer (212b; 232b), wherein the second dielectric layer (212b; 232b) is connected to the first dielectric layer (212a; 232a) of the first semiconductor device (258a), and a plurality of conductive protrusions (218a, 218b; 238a, 238b) at a second lateral edge of the lower surface, the plurality of conductive protrusions (218a, 218b; 238a, 238b) extending from the second dielectric layer (212b; 232b), each conductive protrusion aligned with a corresponding metal structure of the first semiconductor device; and a plurality of plated structures (260) disposed within the recesses (214a, 214b; 234a, 234b), each plated structure electrically coupling a metal structure (208a, 208b; 228a, 228b) of the first semiconductor device (258a) to a conductive protrusion of the second semiconductor device (258b). [11] The semiconductor device (250) of claim 10, wherein the first dielectric layer (232a) includes a plurality of first bevels (240), each first bevel (240) being located proximate a corresponding recess (234a, 234b). [12] The semiconductor device (250) of claim 11, wherein each metal structure (228a, 228b) has a metal structure bevel (244) aligned with a corresponding first bevel (240) in the first dielectric (232a) layer. [13] The semiconductor device (250) of claim 11, wherein the second dielectric layer (232b) includes a plurality of second chamfers (242), each second chamfer (242) being proximate a corresponding conductive protrusion (238a). [14] A semiconductor device (250) according to claim 13, wherein: each first bevel (240) is vertically aligned with a corresponding second bevel (242), and each first bevel (240) is configured to receive a corresponding second bevel (242). [15] The semiconductor package (250) of claim 10, wherein each recess (234a, 234b) is configured to receive a corresponding conductive protrusion (238a, 238b). [16] The semiconductor device (250) of claim 15, wherein each recess (234a, 234b) has a shape complementary to the corresponding conductive protrusion (238a, 238b). [17] The semiconductor device (250) of claim 10, wherein the plurality of conductive protrusions (238a, 238b) each include a first region formed from a first conductive material and a second region formed from the second dielectric material layer. [18] A method of manufacturing a semiconductor device (150, 250), the method comprising: Forming a plurality of recesses in a first dielectric layer on a first side of a first semiconductor device (158a; 258a), the semiconductor device having a plurality of metal structures on a first lateral edge of the first side that are at least partially exposed by the recesses; coupling the first dielectric layer of the first semiconductor device to a second dielectric layer on a second side of a second semiconductor device (158b, 258b), the second side of the semiconductor device having a plurality of conductive elements aligned with the metal structures and the recesses of the first semiconductor device; and Plating a conductive material into the recesses to electrically couple the metal structures of the first semiconductor device to the conductive elements of the second semiconductor device. [19] The method of claim 18, wherein: the plurality of metal structures is a plurality of first metal structures; the plurality of conductive elements comprises a plurality of second metal structures; and the second dielectric layer contains a plurality of second recesses that at least partially expose the second metal structures. [20] The method of claim 18, wherein the plurality of conductive elements comprises a plurality of conductive protrusions extending from the second dielectric layer. [21] The method of claim 20, wherein coupling the first and second dielectric layers further comprises inserting the plurality of conductive protrusions of the second semiconductor device into the corresponding plurality of recesses of the first semiconductor device. [22] The method of claim 18, wherein the conductive material comprises copper deposited in the recesses by electroless plating.

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