IMPROVED SEMICONDUCTOR LIGHT SENSOR

Abstract

Photosensitive semiconductor structure (2) comprising the following: a substrate (4); a first doped upper region (8) of the substrate (4) which has a first doping type; a second doped upper region (40) of the substrate (4) which is laterally separated from the first doped upper region (8) and has a second doping type; an isolation structure (20) between the first (8) and the second doped upper region (40); a low-resistance path for current flow between the first (8) and the second doped upper region (40), which is arranged below the insulating structure (20) and around an enclosed region (4') of the substrate (4) having a higher resistance; a first implant region (10) which is arranged below the first doped upper region (8) and which is in direct contact with the first upper region (8), wherein the first implant region (10) has the second doping type, such that a pn junction (6) is arranged between the doped upper region (8) and the first implant region (10), wherein the enclosed region (4') is at least partially enclosed on one side by the first implant region (10) and the low-resistance path passes through the first implant region (10); and a second implant area (32) having a second doping type and located below the first implant area (10) and in direct contact with the first implant area (10), wherein the enclosed area (4') is enclosed on one side by the second implant area (32) and wherein the low-resistance path passes through the second implant area (32).

Description

TECHNICAL AREA

[0001] The present invention relates to semiconductor light sensors, such as avalanche photodiodes (APDs) and single-photon avalanche diodes (SPADs), and methods for manufacturing them. GENERAL STATE OF THE ART

[0002] A single-photon avalanche diode (SPAD) comprises a pn junction across which a high reverse bias is applied to cause an avalanche event to occur when a charge carrier generated by light enters the multiplication region around the pn junction.

[0003] One problem with existing SPADs is that the light detection probability is reduced for either shorter or longer wavelengths and is highly dependent on the excessive bias voltage.

[0004] A well-designed photodiode exhibits stable response over a wide range of reverse bias voltages, and SPADs today require a well-chosen and tightly controlled over-bias to show a similar level of continuity in their response behavior.

[0005] LÓPEZ-MARTÍNEZ, Juan Manuel [et al.]: Limitation of SPADs quantum efficiency due to the dopants concentration gradient. In: 2020 27th IEEE international conference on electronics, circuits and systems, 23-25 ​​November 2020. Glasgow : IEEE, 2020. pp. 1-4. investigates the role of doping concentration gradients in photon collection in single-photon avalanche diodes (SPADs) and how these can be designed to maximize quantum efficiency.

[0006] US 2016 / 0218236A1 discloses an avalanche photodiode operating in Geiger mode. The device comprises a PN junction formed on a substrate, with a first semiconductor region and a second semiconductor region comprising an anode and cathode. The device further comprises a third semiconductor region, which is in physical contact with the second region but not with the first region and has the same semiconductor type as the first semiconductor region. Additionally, the device includes a diode on the second semiconductor region whose turn-on voltage is higher than that of the PN junction. BRIEF SUMMARY OF THE INVENTION

[0007] The invention provides a photosensitive semiconductor structure as claimed in claim 1.

[0008] Preferred embodiments of the invention will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic representation of a previous design of a photosensitive semiconductor structure that includes a p-doped implant region; Fig. Figure 2 shows a graphical representation of the doping profile of the photosensitive semiconductor structure of Fig. 1; Fig. Figure 3 shows a schematic representation of a photosensitive semiconductor structure according to an embodiment that includes two p-doped implant regions; Fig. Figure 4 shows a graphical representation of the doping profile of the photosensitive semiconductor structure of Fig. 3; Fig. Figure 5 shows a schematic representation of a photosensitive semiconductor structure having a low-resistance contact area; Fig. Figure 6 shows a schematic representation of a photosensitive semiconductor structure having an enclosed area; Fig. Figure 7 shows a schematic representation of a photosensitive semiconductor structure according to an embodiment comprising two p-doped implant regions, a low-resistance contact region and an enclosed region; Fig. Figure 8 shows a graphical representation of the doping profile of the photosensitive semiconductor structure of Fig. 7; Fig. Figure 9 shows a schematic representation of a photosensitive semiconductor structure according to another embodiment, comprising two p-doped implant regions; Fig. Figure 10 shows a graphical representation of the doping profile of the photosensitive semiconductor structure of Fig. 9; Fig. 11a shows a first step in a method according to one embodiment; Fig. Figure 11b shows a second step of the procedure, which includes an initial implantation; Fig. Figure 11c shows a third step of the procedure, which includes a second implantation; Fig. 11d shows a fourth step of the procedure; Fig. Figure 12 shows a schematic representation of a manufacturing step of a building block; Fig. Figure 13 shows a schematic representation of a manufacturing step of a component using a photoresist mask with a gap; Fig. 14a shows a photoresist mask before implantation; Fig. 14b shows the photoresist mask after implantation; Fig. Figure 15a shows a different photoresist mask before implantation; and Fig. Figure 15b shows the other photoresist mask after implantation. DETAILED DESCRIPTION

[0009] Fig. Figure 1 shows a schematic cross-section of a light sensor 2, enclosed for illustrative purposes. The light sensor 2 comprises a p-doped substrate 4 with a pn junction 6 between an n-doped region 8 and a p-doped region 10. The multiplication region 12 is arranged around the pn junction 6, where charge is built up to a measurable output current. The n-doped region 8 forms part of a cathode, which is connected via a contact 14 to part of a metal layer 16. The p-doped region 10 and the substrate 4 form part of the anode, which is connected via a contact 18 to part of a metal layer 16. Shallow trench insulation (STI) 20 separates the anode and the cathode at the surface.A bias voltage is applied across the anode and cathode (via contacts 14 and 18) so that when a charge carrier generated by light enters the multiplication area 12, it is accelerated and releases further charge carriers, forming a current that flows between the anode and the cathode. The current flows along the path of least resistance and tends to concentrate just below STI 20.

[0010] Light Sensor 2 is a SPAD. When activated, a large blocking bias is applied across the device, allowing a single charge carrier generated by light to trigger an avalanche and thus be detected. The SPAD is said to operate in Geiger mode. To stop the avalanche current and reset the device to detect another event, the bias must be reduced, which is done by a process called "clearing." Clearing can be passive, by allowing the current to dissipate through a resistor (not shown), or active, by changing the bias in response to the detection of the event (i.e., the detection of the avalanche current).

[0011] Fig. Figure 2 shows the doping profile 22 as a function of the depth of the light sensor 2. The doping profile 22 is shown along the dashed line in Fig. The profile 22 comprises a high concentration of n-doping 24 near the surface (in the n-doped region 8) and a high concentration of p-doping 26 below (in the p-doped region 10), followed by a low, essentially constant concentration of p-doping 26 (in the substrate 4). The doping profile 22 transitions from n-doping 24 to p-doping 26 at a depth 28, which is the depth of the pn junction 6. There is a so-called "doping peak" 30 in the doping profile 22, which corresponds to the peak doping concentration of the p-doped region 10 near the pn junction 6. The doping peak 30 generates an electrostatic self-potential, and the bias voltage must be sufficient to drive charge carriers across the peak 30 towards the transition 6 in order to capture light that is absorbed below the peak concentration.

[0012] One problem with existing light sensors, such as APD and SPAD, is the doping peak located near the sensor's multiplication area. Since longer wavelengths tend to penetrate deeper into the semiconductor structure of the light sensor, while shorter wavelengths tend to be absorbed closer to the surface, the position of the doping peak affects the detection probability of different wavelengths. The bias voltage must be very precisely controlled to ensure correct sensor performance.

[0013] To overcome this problem at least partially, at least some of the embodiments described herein provide a semiconductor light sensor without a doping bump near the multiplication region.

[0014] Fig. Figure 3 shows a schematic cross-sectional view of a light sensor 2, such as a SPAD, according to one embodiment. Similar or equivalent features in different figures have been given the same reference numerals for ease of understanding, and these reference numerals are not intended to limit the illustrated embodiments. The sensor 2 comprises a silicon substrate 4 with a pn junction 6 between an n-doped region 8 and a p-doped region 10. The multiplication region 12 is arranged around the pn junction 6. A second p-doped region 32 is provided below the first p-doped region 10. The first and second p-doped regions 10 and 32 can also be referred to as implant regions, since they are formed by two (or more) implantations.

[0015] By having two p-doped regions 10 and 32 (two or more implantations) instead of just one (as in, for example, in Fig. 1) exhibits the doping peak 30 can be moved away from the first p-doped region 10, as the peak concentration is driven deeper into the light sensor 2. The dashed line 34, which runs through the second p-doped region 32, indicates the position of a peak at the doping concentration.

[0016] The light sensor 2 includes an optional plasma shielding structure 44 to protect the pn junction 6 from plasma damage during fabrication. The shielding structure 44 comprises polysilicon 46 and a portion of the first metal layer 16, which overlaps the edge of the pn junction 6. By reducing plasma damage at or near the pn junction 6, the dark count rate (DCR) can be reduced. Furthermore, the shallow trench insulation (STI) 20 is arranged such that the edge of the pn junction 6 is recessed beneath a portion of the STI 30, providing additional protection against plasma damage.

[0017] Fig. Figure 4 illustrates the doping profile 22 of the light sensor 2 in Fig. 3. Near the surface, there is a high concentration of n-type doping 24, which decreases sharply towards the depth of the pn junction 6. The doping at the pn junction 6 can be adjusted to provide a target breakdown voltage. The p-type doping 26 provides two regions 48 and 50, which are separated by the intrinsic electric field. In the first region 48, between the pn junction 6 and the peak 52 in the doping profile 22, the doping concentration decreases essentially linearly towards the pn junction 6. Importantly, there is no doping peak in this region 48, and all charge carriers in this region are driven towards the multiplication region 12 around the pn junction 6.

[0018] In two specific embodiments of the light sensor 2, the tip 52 is positioned in the doping profile 22 at a depth of 3 µm and 4 µm, respectively. A greater depth can provide a useful increase in the area (or volume in 3D) in which generated charge carriers can be detected. The maximum achievable depth depends on the manufacturing process and the equipment used. With current manufacturing techniques, it is difficult to achieve a depth greater than 5 µm. The implantation depth can be controlled by the implantation energy.

[0019] The n-doped region 8 is part of a cathode, which is connected to the first metal layer 16 (metal 1) in the backend stack of the sensor 2 via a metal contact 14. The first p-doped region 10 and the second p-doped region 32 are part of the anode, which is connected to the first metal layer 16 via a metal contact 18. In operation, the bias voltage is applied between the cathode and the anode via contacts 14 and 18.

[0020] Another insight of the inventors is that a component can be improved by reducing the resistance along the current path from the anode to the cathode in the component's substrate. For example, in a SPAD, such as the SPAD from Fig. 1. The current through the p-doped substrate 4 is below the STI range 20. However, substrate 4 exhibits a relatively high resistance, which limits the current flowing during an avalanche (i.e., an event). A larger avalanche current can ensure improved photodetection.

[0021] To at least partially solve this problem, a low-resistance area can be provided. For example, another implant area can be provided below a contact to reduce the resistance in that area where the avalanche current flows when an event occurs.

[0022] Fig. Figure 5 shows a schematic representation of a cross-section of a light sensor 2 according to one embodiment. Similar to the one in Fig. As illustrated in Figure 3, the sensor 2 comprises a silicon substrate 4 with a pn junction 6 between an n-doped region 8 and a p-doped region 10. The multiplication region 12 is arranged around the pn junction 6. The n-doped region 8 is part of a cathode, which is connected to the first metal layer 16 (metal 1) in the back-end stack of the sensor 2 via a metal contact 14. The p-doped region 10 is part of the anode, which is connected via a rear-side metal contact 18. In application, the bias voltage is applied between the cathode and the anode via contacts 14 and 18. The anode contact 18 is in direct contact with the p-doped implant region 10 via a low-resistance region (a region with a higher doping concentration than the surrounding substrate 4). This provides a low-resistance path (without interrupting the low-doped substrate 4) between the anode and the cathode.

[0023] To further reduce the resistance between the metal contact 18 and the silicon, a heavily doped p+ region 40 is formed below the contact 18, and a p-well 42 is formed between the heavily p-doped region 40 and the p-doped region 10. In operation, the current will follow the path of least resistance from the anode contact 18, through the heavily p-doped region 40, the p-well 42, and the p-doped region 10, to the cathode.

[0024] Due to the reduced resistivity of the p-doped regions 40, 42, and 10 compared to the surrounding substrate 4, a larger avalanche current can be achieved for a given bias voltage compared to conventional devices where the current path passes through the substrate 4. A larger avalanche current, in turn, allows for faster extinguishing when the device discharges following an event, which can increase the dynamic range (maximum intensity) of the light sensor 2.

[0025] Fig. Figure 6 shows a schematic cross-section of a light sensor 2 according to another embodiment. The sensor 2 comprises a silicon substrate 4 with a pn junction 6 between an n-doped region 8 and a p-doped region 10. The multiplication region 12 is arranged around the pn junction 6. The n-doped region 8 is part of a cathode, which is connected to the first metal layer 16 (metal 1) in the backend stack of the sensor 2 by a metal contact 14. The p-doped region 10 is part of the anode, which is connected to the first metal layer 16 by the metal contact 18. In operation, the bias voltage is applied between the cathode and the anode via the contacts 14 and 18.

[0026] Importantly, the device includes an enclosed region 4' of the substrate 4. This enclosed region 4' is located below the STI region 20 and is enclosed by a p-doped region 12 and the p-well 42 of the anode contact structure. The enclosed region 4' forms a three-dimensional ring around the p-doped region 10 and prevents the current from taking the shortest path directly below the STI 20 between the cathode and the anode. Instead, due to the lower resistivity of the p-doped region 10 (compared to the resistivity of the substrate 4), the current flows around the enclosed region 4'. Consequently, the structure provides a low-resistance path around region 4' so that the current flows directly below the STI from the anode to the cathode.This can also cause the current to flow more homogeneously to the multiplication region 12 (instead of concentrating at the edge near the pn junction 6) and between the contacts 14 and 18. The enclosed region 4' preferably extends 500 nm downwards into the substrate 4.

[0027] While the in Fig. In embodiments 3 to 6 illustrated, an upper n-doped region 8 and a p-doped implant region 10 below it to form the pn junction 6 may be included. Other embodiments of this disclosure may have the doping type reversed, such that the upper doped region is p-doped and the implant region below it is n-doped.

[0028] In a particularly advantageous embodiment, the features of Fig. 3, Fig. 5 and Fig. 6 combined, as in Fig. 7, which is described below, is illustrated.

[0029] Fig. Figure 7 shows a schematic cross-sectional view of a light sensor 2, which is a SPAD according to one embodiment. The sensor 2 comprises a silicon substrate 4 with a pn junction 6 between an n-doped region 8 and a p-doped region 10. The multiplication region 12 is arranged around the pn junction 6. A second p-doped region 32 is provided below and in direct contact with the first p-doped region 10. The first and second p-doped regions 10 and 32 can also be referred to as implant regions, since they are formed by two (or more) implantations. In other embodiments, one or more further implant regions can be arranged between the first and second implant regions 10 and 32.

[0030] By having two p-doped regions 10 and 32 (two or more implantations) instead of just one (as in, for example, in Fig. 1) exhibits, the doping peak 30 can be moved away from the first p-doped region 10, as the peak concentration is driven deeper into the light sensor 2. The dashed line 34, which runs through the second p-doped region 32, indicates the position of a peak at the doping concentration that defines a collection volume 36 from which charge carriers are "collected" (driven by the electrostatic self-potential towards the pn junction 6). Charge carriers generated outside the collection volume 36 will be blocked by the doping profile (unless the excessive bias is high enough to overcome the electrostatic self-potential, as discussed later), thus providing isolation.

[0031] The collection volume 36 is well-defined, with only charge carriers generated within the collection volume capable of inducing an event. The range of transit times for charge carriers to move to the pn junction is therefore also well-defined. This can reduce the uncertainty of the arrival time and thus ensure more accurate measurements, for example, when the light sensor 2 is used in a time-of-flight (TOF) distance measurement device.

[0032] The collection volume can be significantly larger compared to conventional devices that only have one implant area. The increased collection volume 36 can ensure a higher photodetection probability (PDP) and consequently a higher output power for a given light intensity. In particular, for light with longer wavelengths (e.g., IR) that penetrate deeper into the device, the light sensor 2 can exhibit a higher PDP compared to conventional devices.

[0033] The n-doped region 8 is part of a cathode, which is connected to the first metal layer 16 (metal 1) in the backend stack of the sensor 2 via a metal contact 14. The first p-doped region 10 and the second p-doped region 32 are part of the anode, which is connected to the first metal layer 16 via the metal contact 18. During operation, the bias voltage is applied between the cathode and the anode via contacts 14 and 18.

[0034] During the implantation of the first p-doped region 10, a peripheral p-doped region 10' is also formed adjacent to and laterally spaced from the first p-doped region 10. An implantation mask can be used to provide the gap between the p-doped region 10 and the peripheral p-doped region 10'.

[0035] The first and second p-doped regions 10 and 32, and the peripheral p-doped region 10' together define / enclose a region 4' of the substrate 4. Region 4' forms a three-dimensional ring around the first p-doped region 10 and above the second p-doped region 32. The enclosed region 4' can provide an additional advantage by preventing the current from taking the shortest path directly below the STI 30 between the cathode and the anode. Instead, due to the lower resistivity of the peripheral p-doped region 10' and the second p-doped region 32, the current flows more homogeneously to the multiplication region 12 and between contacts 14 and 18.

[0036] To further reduce the resistance between the metal contact 18 and the silicon, a heavily doped p+ region 40 is formed on the surface below the contact 18, and a p-well 42 is formed between the heavily p-doped region 40 and the peripheral p-doped region 10'. In operation, the current follows the path of least resistance from the anode contact 18, through the heavily p-doped region 40, the p-well 42, the peripheral p-doped region 10', into the second p-doped region 32, up to the multiplication region 12, into the n-doped region 8, and to the cathode contact 14. The current flows around the enclosed region 4' of the substrate 4, which has a light doping concentration and therefore a higher resistivity.

[0037] Furthermore, due to the reduced resistivity of the p-doped regions 10, 10', and 32 compared to the surrounding substrate 4, a larger avalanche current can be achieved for a given bias voltage compared to conventional devices. A larger avalanche current, in turn, allows for faster clearing when the device discharges following an event, which can increase the dynamic range (maximum intensity) of the light sensor 2. This can also facilitate clearing, as there is no need for transistor-based clearing, since the discharge of the over-biased SPAD by the SPAD itself can occur quickly enough without any transistor assistance.

[0038] The light sensor 2 includes an optional plasma shielding structure 44 to protect the pn junction 6 from plasma damage during fabrication. The shielding structure 44 comprises polysilicon 46 and a portion of the first metal layer 16, which overlaps the edge of the pn junction 6. By reducing plasma damage at or near the pn junction 6, the dark count rate (DCR) can be reduced. Furthermore, the shallow trench insulation (STI) 20 is arranged such that the edge of the pn junction 6 is recessed beneath a portion of the STI 30, providing additional protection against plasma damage.

[0039] Sensor 2 further comprises an n-tub protective ring 45. The protective ring 45 can be useful for absorbing charge carriers generated in the substrate 4, which would otherwise be trapped in the substrate 4. The protective ring 45 acts as a sink and prevents a build-up of charge carriers in the substrate 4.

[0040] Fig. Figure 8 illustrates the doping profile 22 of the light sensor 2 in Fig. 7, which is essentially the same as the doping profile of the embodiment of Fig. 3, as in Fig. Figure 4 illustrates this. Near the surface, there is a high concentration of n-type doping 24, which decreases sharply towards the depth of the pn junction 6. The doping at the pn junction 6 can be adjusted to provide a target breakdown voltage. The p-type doping 26 provides two regions 48 and 50, which are separated by the electric intrinsic field. In the first region 48, between the pn junction 6 and the peak 52 in the doping profile 22, the doping concentration decreases essentially linearly towards the pn junction 6. Importantly, there is no doping peak in this region 48, and all charge carriers in this region are driven towards the multiplication region 12 around the pn junction 6. Region 48 corresponds to the collection volume 36, as shown in Figure 4. Fig. Figure 7 illustrates that charge carriers generated in the second region 50, on the other side of the tip 52, away from the pn junction 6, are blocked by the intrinsic electric field (unless the excessive bias voltage is high enough to overcome the intrinsic field and drive charge carriers over the tip 52 and into the other region 48).

[0041] In two specific embodiments of the light sensor 2, the tip 52 is positioned in the doping profile 22 at a depth of 3 µm and 4 µm, respectively. A greater depth is associated with a larger collection volume 36 and an increased PDP (photon penetration depth). The maximum achievable depth depends on the manufacturing process and the equipment used. With current manufacturing techniques, it is difficult to achieve a depth greater than 5 µm. The implantation depth can be controlled by the implantation energy.

[0042] The light sensor 2 can be operated in two different modes depending on the level of the applied bias relative to the tip doping concentration in the second implant region 32. In the first (normal) mode, the doping profile 22 provides intrinsic insulation, and the bias is insufficient to drive charge carriers over the tip 34 and into the collection volume 36. In the second mode, the bias is higher, so charge carriers generated deeper in the substrate 4 (below the tip 34) will tend to flow towards the pn junction 6. In this second mode, there is no insulation and therefore no well-defined collection volume. Charge carriers generated anywhere in the substrate 4 can be detected, which increases the PDP of the device. However, the range of transit times for charge carriers is larger, which increases the uncertainty of transit-time measurements.

[0043] Fig. Figure 9 shows a different embodiment of a light sensor 2, which has active isolation comprising a second pn junction 54. The sensor 2 comprises a p-doped substrate 4, a first pn junction 6 between a p-doped region 56 and an n-doped region 58 below the p-doped region 56. A second n-doped region 60 is arranged below the first n-doped region 58. The first and second n-doped regions 58 and 60 (also referred to as implant regions) enclose / define the region 4' of the substrate 4. Consequently, the Fig. 9 illustrated light sensor 2 similar to the one from Fig. 7, but the doping type of the implants has been exchanged. This creates a second pn junction 54 between the implanted n-regions 58 and 60 and the substrate 4. The p-doped region 56 on the surface forms part of a first anode, while the substrate 4 is part of a second anode. The n-doped regions 58 and 60 are part of a cathode. The second pn junction 54 provides isolation by preventing charge carriers in the substrate 4 from reaching the multiplication region 12. A guard ring is not necessary because charge carriers in the substrate 4 eventually reach the second pn junction 54 and are collected there.

[0044] Fig. Figure 10 illustrates the doping profile 22 of the light sensor 2 in Fig. 9. The doping profile 22 is recorded vertically through the structure along the central line of symmetry. Near the surface, there is a high concentration of p-type doping 62, which decreases sharply towards the depth of the pn junction 6. The doping at the pn junction 6 can be adjusted to provide a target breakdown voltage. The n-type doping 64 provides two regions 48 and 50, which are separated by the intrinsic electric field. In the first region 48, between the pn junction 6 and the peak 52 in the doping profile 22, the doping concentration decreases essentially linearly towards the pn junction 6. Importantly, there is no doping peak in this region 48, and all charge carriers in this region 48 are driven towards the multiplication region 12 around the pn junction 6. Region 48 corresponds to the collection volume 36, as shown in Fig. Figure 9 illustrates this. Charge carriers generated in the second region 50, on the other side of the tip 52, away from the pn junction 6, are blocked by the intrinsic electric field (unless the excessive bias voltage is high enough to overcome the intrinsic field and drive charge carriers over the tip 52 and into the other region 48). A second pn junction 54 is arranged between region 50 and substrate 4. Charge carriers generated in substrate 4 can be collected at this pn junction 54.

[0045] It may be more difficult to implant an n-type doping substance at greater depths, and therefore the tip doping 34 in the second implant area 60 may be located, for example, at a depth between 1 µm and 2.5 µm.

[0046] The absence of a doping peak can significantly improve the collection efficiency, as more charge carriers reach the multiplication region. This can ensure a SPAD with a significantly higher red / infrared (IR) PDP compared to conventional SPADs.

[0047] Furthermore, the embodiments described herein can be less dependent on the excessive bias voltage. This allows for good PDP at very low bias values, which remain constant up to a certain limit. Beyond this limit, the light sensor can still be used, but in a second operating mode. In this mode, the lack of isolation increases the PDP, but the larger range of propagation times required for charge carriers to reach the multiplication region can also cause flickering. If the isolation in the light sensor is provided not by a pn junction, but by the doping profile, it is possible to operate it in these two modes. For lower excessive bias voltages (e.g., < 5 V), there is intrinsic isolation due to the doping profile. Beyond this, the electric field is modified in such a way that the device will exhibit no isolation.Consequently, the sensor can be operated at high, excessive bias voltages to collect all charge carriers. The transition voltage (where the sensor mode changes) can be adjusted by the peak doping of the second (deeper) p-doped region.

[0048] Furthermore, the enhanced multiplication implant design can create isolation that can give the light sensor a lower dark count rate (DCR) and improved flicker (due to a smaller volume from which free carriers can originate). Crosstalk between adjacent SPADs can also be drastically reduced by the described embodiments.

[0049] Fig. Figures 11a to 11d illustrate part of a process for forming a light-sensitive semiconductor structure, such as the semiconductor structure of the [document / device] in Fig. 7 illustrated sensors 2.

[0050] In Fig. 11a A substrate 4 is provided, which is typically a silicon substrate.

[0051] In Fig. In step 11b, a mask 66 is applied to the substrate 4, and a first dopant 68 (e.g., boron) is implanted to form an implant area 32. During implantation, an ion beam illuminates the substrate and the mask. The implant depth can be adjusted by the implantation energy.

[0052] In Fig. In step 11c, a second mask 70 is applied to the substrate 4, and a second implantation is performed using the same type of doping substance 68 to form another implant area 10 and a peripheral doped area 10'. The mask 70 is positioned to separate the first implant area 10 from the peripheral area 10' by an area 4' of the substrate 4.

[0053] In Fig. 11d After the provision of an STI 20, a third implantation is performed to form a doped surface area 8 over the first implant area 10. The third implantation uses a different dopant 72 (e.g., phosphorus) to provide a pn junction 6 between the doped surface area 8 and the first implant area 10.

[0054] After forming the doped surface area, the process can further include steps such as providing contact structures to complete the component.

[0055] During the fabrication of a photosensitive semiconductor structure, such as a SPAD, the breakdown voltage must be set and a suitable avalanche region defined to meet application requirements. The multiplication region is the area where impact ionization occurs. Therefore, high-dose and / or high-energy implantation may be necessary. The size of the optically active region is particularly important for SPAD devices. Inappropriate implantation in these regions can lead to premature edge breakdown, which degrades device performance.

[0056] Ion implantation with relatively high energy requires a thick photoresist mask (e.g., with a thickness in the range of 2 to 10 µm). Unfortunately, with such a thick photoresist, the geometry at the edge of the photoresist opening changes during the implantation process, resulting in a beveled / sloping photoresist edge. A sloping edge, in turn, can lead to a blurred implantation profile beneath the photoresist edge, potentially resulting in premature edge failure in the finished building block.

[0057] Fig. Figure 12 shows a schematic cross-section of a photosensitive semiconductor structure 2 of a SPAD in a manufacturing snapshot after implantation to form an implant area 10 in the optically active area 74 of the SPAD. A thick photoresist mask 76 with a central opening 78 over the optically active area 74 is used during implantation to form the implant area 10. The photoresist mask 76 covers a contact area 80 outside the optically active area 74.

[0058] The implantation (i.e., the "baking" of the photoresist and exposure with an ion beam) alters the shape of the photoresist mask 76 and, in particular, changes the angle of the edge 82. The baking step of the photoresist is performed to allow the photoresist to outgas, but it also causes the photoresist to shrink, which in turn causes the beveling of the edge 82. Wider sections of the photoresist exhibit more pronounced beveling because there is more stress due to the higher area-to-perimeter ratio. The mask will typically have a substantially perpendicular angle to the substrate 4 when placed on the substrate 4. After baking, the angle has decreased, and the edge 82 slopes down towards the central opening 78.

[0059] The sloping edge 82 of the photoresist mask can influence the shape of the implant area 10 and can, in particular, increase the doping around the edges of the optically active area, forming a U-shape, as shown in Fig. 12 can be seen.

[0060] To solve this problem, the inventors realized that the implantation area could be improved by providing a gap in the photoresist mask outside the optically active area. Accordingly, implantation occurs within the active area of ​​the device and in a ring spaced a specific distance outside the active area (corresponding to the gap in the photoresist). Ion implantation just outside the active area of ​​the device is blocked by a narrow strip of photoresist, which, compared to a conventional mask, better retains its original geometry during the baking process. The additional area implanted outside the optically active area has a positive effect on the device's performance, as it reduces resistance along the current path.

[0061] The photoresist shape is maintained by the design of the device itself during ion implantation. The additional implant outside the optically active area has no impact on device performance. This approach can lead to significant improvements in the performance of SPAD devices by preventing premature edge breakthrough and can also be applied to other devices where the shape of the implantation profile at the device edge plays a critical role. Compared to conventional approaches to addressing the problem, the disclosed solution does not require the additional deposition of sacrificial layers or other technical means that need to be introduced into the processing steps or equipment.

[0062] Fig. Figure 13 shows a schematic cross-section of a photosensitive semiconductor structure 2 of a SPAD during fabrication, where the described solution is applied to provide an improved implant area 10. Specifically, the photoresist mask 76 has a gap 84 (forming a ring in three dimensions) outside the optically active area 74 and above the contact area 80. Due to the gap 84, the inner part 76a of the photoresist mask 76 substantially retains its shape after implantation to form the implant area 10. In particular, the inner edge 82 of the photoresist mask 76 remains substantially perpendicular to the underlying substrate 4, which in turn reduces implant blurring at the edge / circumference of the optically active area 74 below the edge 82. To maintain this geometry, the inner part 76a of the photoresist mask 76 can have a width in the range of 0.7 to 5 µm.

[0063] An additional implant area 10', which can be referred to as a peripheral implant area 10', is formed below the gap 84 in the contact area 80. The peripheral implant area 10' does not significantly affect the component performance but can be advantageously used to form structures such as those described above. For example, the peripheral implant area 10' can be used to reduce the resistance in the contact area 80 to support a larger avalanche current for a given preload.

[0064] Experiments were conducted to determine how the design of the photoresist mask influenced the shape change of the mask due to implantation. Fig. 14a and Fig. Figure 14b schematically shows the observed shape of a single opening 86 (i.e., no gap outside) in a photoresist mask 76 before and after photoresist baking, respectively. The opening 86 forms a line through the photoresist in three dimensions. The opening 86 had an approximate width of 1 µm. The thickness of the photoresist was approximately 3 µm. After the baking step, as shown in Figure 14b, the opening 86 was approximately 1 µm wide. Fig. 14b shows the edge 82 of the opening 86 beveled / inclined at an angle θ of approximately 10° to the normal.

[0065] Fig. 15a and Fig. Figure 15b shows the results for a photoresist mask 76 having a grouping of 1 µm apertures 86 (three shown). Implantation was performed using the same setup with the same implantation energy, dose, etc., as for the single-aperture mask, as in Fig. 14a shown, performed. After implantation, as shown in 14a, the following were as follows: Fig.Figure 15b shows that the edges 82 of the openings are beveled / inclined at an angle θ of approximately 1° to the normal. Consequently, it has been shown that a relatively narrow piece of photoresist may be better at retaining its shape before implantation during baking.

[0066] In general, embodiments described herein provide a photosensitive semiconductor structure (e.g., a SPAD) comprising a substrate (typically silicon), a doped surface region on the surface of the substrate having a first doping type (e.g., n-type), a first implant region located below and in direct contact with the doped surface region, wherein the first implant region has a second doping type (e.g., p-type) such that a pn junction is arranged between the doped surface region and the first implant region. The structure further comprises a second implant region located below the first implant region and having the second doping type, wherein a peak in a doping profile of the second doping type is arranged in the second implant region.

[0067] The multiplication implant (i.e., the first implant region) is not only used to increase the doping according to the required breakdown voltage level, as in a conventional component, but is also extended to provide a collection volume from which the sensor obtains its carriers. The second implant region can be located at a depth in the range of 1 µm to 5 µm. For example, if the second doping type is p-type doping, the second implant region can preferably be located at a depth between 3 µm and 4 µm. If the second doping type is n-type doping, the second implant region can be located at a shallower depth between 1 µm and 2 µm.

[0068] The doping profile can exhibit a continuously decreasing doping concentration from the tip to the pn junction. For example, the doping profile towards the pn junction in the first implant region, or the entire distance from the tip to the pn junction, can exhibit a substantially linear decrease in doping concentration. The collection volume towards the multiplication region and the pn junction is defined by the continuously decreasing doping profile, surrounding the tip at the doping concentration. Carriers from outside this collection volume are repelled / blocked by the structure within the doping profile, which generates an intrinsic electric field.

[0069] The structure preferably comprises a peripheral doped region having the same doping concentration as the first implant region and positioned at the same depth (because it is formed by the same implantation step). The peripheral doped region is arranged around the first implant region and is laterally separated from it by an enclosed region of the substrate. The second implant region extends laterally beneath the enclosed region of the substrate and at least partially beneath the peripheral doped region. The arrangement of the doped regions and the enclosed substrate region provides a current path (a path with lower resistivity) around the enclosed region.This current path also allows the current to flow more homogeneously from the multiplication area of ​​the component and can also support a higher avalanche current for a given pre-voltage.

[0070] The structure can include a first and a second contact for applying a bias across the pn junction of the semiconductor structure, with the peripheral doped region positioned beneath the second contact such that any current flowing to or from the second contact passes through the peripheral doped region. Consequently, the first implant region, the second implant region, and the peripheral doped region can be arranged such that the current does not flow through the enclosed area of ​​the substrate. This can prevent the current from concentrating at the edge of the peripheral doped region closest to the other contact.

[0071] For example, the first contact can be the cathode contact (the first doping type of the doped surface area is n-doping), and the second contact is an anode contact (the second doping type in the first and second implant areas is p-doping), and the photosensitive semiconductor structure can be arranged such that the current flowing between the first and second contacts flows from the anode contact to the peripheral doped area, from the peripheral doped area to the second implant area, from the second implant area to the first implant area, from the first implant area to the doped surface area, and from the doped surface area to the cathode contact.

[0072] The photosensitive semiconductor structure can have a tip positioned at a depth of 2 µm to 5 µm (below the substrate surface). A greater depth increases the collection volume and can also provide a deeper enclosed area of ​​the substrate (between the first implant area and the doped peripheral area). The enclosed area should preferably have a depth of at least 500 nm. The tip can be positioned at a depth of 3 µm to 4 µm, which ensures good results.

[0073] The embodiments described herein also provide a method for forming a photosensitive semiconductor structure. The method comprises providing a substrate, providing a doped surface region on the surface of the substrate having a first doping type, providing a first implant region located below and in direct contact with the doped surface region, wherein the first implant region has a second doping type, such that a pn junction is provided between the doped surface region and the first implant region. The method further comprises providing a second implant region located below the first implant region and having the second doping type, and wherein a peak in a doping profile of the second doping type is provided in the second implant region.

[0074] The step of preparing the first implant area may involve using a mask and implanting a first dopant into the substrate to form the first implant area and to create a peripheral doped area around the first implant area, separated from it laterally by a region of the substrate. The mask shields the area of ​​the substrate between the first implant area and the doped peripheral area. The step of preparing the second implant area may then involve using a different mask and implanting the first dopant into the substrate to form the second implant area.

[0075] Other embodiments provide a photosensitive semiconductor structure comprising a substrate, a doped upper region of the substrate having a first doping type, an implant region located below and in direct contact with the doped upper region, the implant region having a second doping type such that a pn junction is arranged between the doped upper region and the implant region, and a first and a second contact structure configured to apply a voltage across the pn junction, the first contact structure being directly connected to the doped upper region and the second contact structure being directly connected to a low-resistance region of the substrate. The low-resistance region is in direct contact with the implant region, thereby providing a low-resistance path between the anode and cathode.The low-resistance contact structure allows a larger avalanche current to flow between the contacts for a given preload.

[0076] The low-resistance region can comprise at least three vertically arranged doped regions. A first of the at least three vertically arranged doped regions can be a heavily doped region (e.g., p+) directly connected to the second contact structure, a second of the at least three vertically arranged doped regions can be the doped well region (e.g., a p-well) in the substrate, and a third of the at least three vertically arranged doped regions can be another implant region.

[0077] The implant areas can have the same doping composition and can be laterally separated, extending to the same depth in the substrate. Typically, the two implant areas are formed in a single implantation step.

[0078] Another embodiment provides a photosensitive semiconductor structure comprising a substrate, a first doped upper region of the substrate having a first doping type, and a second doped upper region of the substrate, separated laterally from the first doped upper region and having a second doping type. An insulating structure (typically STI) is arranged between the first and second doped upper regions. The structure further comprises a low-resistance path for current flow between the first and second doped upper regions, located below the insulating structure and around an enclosed region of the substrate having a higher resistance. The enclosed region is typically a low-doped region directly below the insulating structure.The enclosed area preferably extends to a depth of at least 500 nm below the surface.

[0079] The structure can further include an implant region located below and in direct contact with the first doped upper section, wherein the implant region has the second doping type, such that a pn junction is arranged between the doped upper region and the implant region. The enclosed region can be at least partially enclosed on one side by the implant region, and the low-resistance path can pass through the implant region.

[0080] Preferably, the implant area is a first implant area, and the structure further comprises a second implant area having a second doping type and arranged below the first implant area and in direct contact with it, wherein the enclosed area is enclosed on one side by the second implant area and the low-resistance path passes through the implant area. The inclusion of multiple implant areas allows the doping cusp to be moved away from the pn junction.

[0081] Another embodiment provides a photosensitive semiconductor structure comprising a substrate, a pn junction for collecting light-generated charge carriers, and a collection volume surrounding the pn junction, defined by a peak doping concentration in the substrate. An intrinsic electric field, generated by a doping profile, prevents charge carriers outside the collection volume from reaching the pn junction. The doping profile can drive charge carriers within the collection volume toward the pn junction. Typically, the doping profile slopes substantially linearly from the peak to the pn junction. Charge carriers outside the collection volume must overcome the intrinsic electric field to enter the collection volume. Consequently, the doping profile provides passive isolation.

[0082] The structure can further comprise an upper doped region having a first doping type and one or more implant regions having a second doping type, such that the pn junction is located between the upper doped region and the one or more implant regions. The peak doping concentration is located in at least one of the one or more implant regions.

[0083] A method for forming a photosensitive semiconductor structure includes providing a substrate (typically a silicon substrate) and a photoresist mask on the substrate, the photoresist mask having a central opening and a gap around the central opening. The method further includes irradiating the substrate and the photoresist mask with an ion beam (e.g., phosphorus or boron ions), thereby forming an implant region in an optically active area of ​​the substrate below the central opening and a peripheral implant region in a contact area of ​​the substrate below the gap in the photoresist mask. As part of the implantation process, the photoresist mask is typically baked prior to the irradiation step.

[0084] The photoresist mask includes a first edge extending towards the central opening, and this edge is typically substantially perpendicular to the substrate when the photoresist mask is prepared (i.e., prior to implantation). A perpendicular edge can ensure a better implant area with less blurring around the edge of the optically active region. The width of the gap is not critical but can range, for example, from 1 µm to 10 µm. The thickness of the photoresist mask can range from 2 to 10 µm. The relatively thin portion of the photoresist mask (between the central opening and the gap) can have a width ranging from 0.7 to 5 µm.

[0085] The method can further include the formation of an isolation structure, such as STI, in the substrate between the optically active area and the contact area.

[0086] Any feature disclosed or illustrated in the present description may be included in the invention, either alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

[1] Light-sensitive semiconductor structure (2) comprising: a substrate (4); a first doped upper region (8) of the substrate (4) which has a first doping type; a second doped upper region (40) of the substrate (4) which is laterally separated from the first doped upper region (8) and has a second doping type; an isolation structure (20) between the first (8) and the second doped upper region (40); a low-resistance path for current flow between the first (8) and the second doped upper region (40), which is arranged below the insulating structure (20) and around an enclosed region (4') of the substrate (4) having a higher resistance; a first implant region (10) which is arranged below the first doped upper region (8) and which is in direct contact with the first upper region (8), wherein the first implant region (10) has the second doping type, such that a pn junction (6) is arranged between the doped upper region (8) and the first implant region (10), wherein the enclosed region (4') is at least partially enclosed on one side by the first implant region (10) and the low-resistance path passes through the first implant region (10); and a second implant area (32) having a second doping type and located below the first implant area (10) and in direct contact with the first implant area (10), wherein the enclosed area (4') is enclosed on one side by the second implant area (32) and wherein the low-resistance path passes through the second implant area (32).

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