Contact formation method with reduced dopant loss and larger dimensions

Abstract

Process comprising: forming a first source / drain region (142); Forming a dielectric layer (46) over the first source / drain region (142); Etching the dielectric layer (46) to form a first contact opening (162), wherein the first source / drain region (142) is exposed through the first contact opening (162); depositing a dielectric spacer layer (66) extending into the first contact opening (162); etching the dielectric spacer layer (66) to form a first contact spacer (166) in the first contact opening; after depositing the dielectric spacer layer (66), implanting a dopant into the first source / drain region (142) through the first contact opening (162); and Forming a first contact plug (186) to fill the first contact opening (162), wherein the dopant penetrates a lower portion of the dielectric spacer layer (66) to reach the first source / drain region (142).

Description

BACKGROUND

[0001] As integrated circuits become increasingly smaller, their formation processes become increasingly difficult, and problems may arise where previously they were not. For example, in the formation of fin-field-effect transistors (FinFETs), the source / drain regions become increasingly smaller, causing contact resistance to continually increase.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2021 / 0 043 502 A1, US 9 852 947 B1, US 2016 / 0 336 412 A1 and US 2018 / 0 047 623 A1.

[0003] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that various elements are not drawn to scale, as is common practice in the industry. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for the sake of clarity of explanation. The Fig. 1 to 6, 7A, 7B, 8A, 8B and 9 to 15 illustrate cross-sectional views and perspective views of intermediate stages in forming fin-field effect transistors (FinFETs) and contact plugs according to some embodiments. The Fig. 16 and Fig. 17 illustrate cross-sectional views of intermediate stages in forming FinFETs and contact plugs according to some embodiments. Fig. 18 illustrate the distribution of an implanted dopant in a FinFET according to some embodiments. Fig. 19 illustrates a process flow for forming FinFETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various elements of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. For example, in the following description, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or devices discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0007] A method for forming contact plugs for transistors and the methods for forming the same are provided according to various embodiments. According to some embodiments, a transistor is formed. Then, a contact opening is formed exposing the source / drain region of the transistor. Then, a conformal dielectric spacer layer is formed, extending into the contact opening and then etched to form a contact spacer. Then, an implantation process is performed to implant a dopant into the source / drain region and the contact spacer. A silicide region and a contact plug are then formed in the contact opening. By performing the implantation process after forming the contact spacer, the lateral dimension of the contact plug is not significantly reduced by the implantation. Furthermore, dopant loss in the source / drain region is reduced.The intermediate steps in forming transistors are illustrated according to some embodiments. In some illustrated embodiments, the formation of fin-field-effect transistors (FinFETs) is used as an example to explain the concept of this disclosure. Other transistors, such as planar transistors, gate-all-around transistors (GAA transistors), etc., may also adopt the concept of this disclosure. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments.

[0008] The Fig. 1 to 6, 7A, 7B, 8A, 8B, and 9 to 15 illustrate cross-sectional and perspective views of intermediate stages in forming transistors (which may be, for example, FinFETs) according to some embodiments of this disclosure. The processes are also schematically illustrated in process flow 300 of Fig. 19 reflected.

[0009] Fig. 1 illustrates a perspective view of a starting structure. The starting structure includes wafer 10, which further includes substrate 20. Wafer 10 includes a device region 100 and a device region 200, each forming a transistor. According to some embodiments of this disclosure, the transistors formed in device regions 100 and 200 are of opposite types. For example, the transistor formed in device region 100 may be a p-type transistor, and the transistor in device region 200 may be an n-type transistor. According to other embodiments, the transistor formed in device region 100 may be an n-type transistor, and the transistor formed in device region 200 may be a p-type transistor. According to other embodiments, the transistors formed in device regions 100 and 200 are of the same conductivity type, such as p or n.

[0010] Substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed from other semiconductor materials. According to some embodiments, substrate 20 includes a bulk silicon substrate and an epitaxial layer of silicon germanium (SiGe) or a germanium layer (without silicon therein) over the bulk silicon substrate. Substrate 20 may be doped with a p-type or n-type impurity. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed to extend into substrate 20. The portions of substrate 20 between adjacent STI regions 22 are referred to as semiconductor stripes 124 and 224, which are located in device regions 100 and 200, respectively.

[0011] The STI regions 22 may include a liner oxide (not shown). The liner oxide may be formed from a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 22 may also include a dielectric over the liner oxide, where the dielectric may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0012] With reference to Fig. 2, the STI regions 22 are cut out so that the upper portions of the semiconductor stripes 124 and 224 protrude higher than the upper surfaces 122A and 222A of the adjacent STI regions 22 to form protruding fins 124' and 224', respectively. The respective process is shown as process 302 in process flow 300 of Fig. 19. The etching may be performed using a dry etching process using, for example, NH3 and NF3 as etching gases. During the etching process, plasma may be generated for etching. Argon may also be included. According to alternative embodiments of this disclosure, the excision of STI regions 22 is performed using a wet etching process. The etching chemical may, for example, comprise dilute HF solution.

[0013] In embodiments illustrated above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing the creation of structures having, for example, pitches smaller than would otherwise be possible using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to pattern the fins.

[0014] With reference to Fig. 3, dummy gate stacks 130 and 230 are formed on the upper surfaces and side walls of the projecting fins 124' and 224', respectively. The respective process is shown as process 304 in process flow 300 of Fig. 19. The dummy gate stack 130 may include dummy gate dielectrics 132 and dummy gate electrodes 134 over the dummy gate dielectrics 132. The dummy gate stack 230 may include dummy gate dielectrics 232 and dummy gate electrodes 234 over the dummy gate dielectrics 232. The dummy gate dielectrics 132 and 232 may be formed by thermal oxidation, chemical oxidation, or a deposition process and may be formed from or include, for example, silicon oxide. Fig. 3 illustrates the deposited gate dielectrics 132 and 232, which include horizontal sections extending across the STI regions 22. Otherwise, if the dummy gate dielectrics 132 and 232 are formed by oxidation, the dummy gate dielectrics 132 and 232 are formed on the surfaces of the protruding fins 124' and 224' and do not include horizontal sections on the STI regions 22.

[0015] The dummy gate electrodes 134 and 234 may be formed from amorphous silicon or polysilicon, for example, but other materials such as amorphous carbon may also be used. The dummy gate stacks 130 and 230 may also include hard mask layers 136 and 236, respectively. The hard mask layers 136 and 236 may be formed from silicon nitride, silicon carbonitride, or the like, or from multiple layers thereof. Each of the dummy gate stacks 130 and 230 traverses a single or multiple protruding fins 124' and 224', respectively.

[0016] Then, gate spacers 138 and 238 are formed on the sidewalls of the dummy gate stacks 130 and 230, respectively. Meanwhile, fin spacers (not shown) may also be formed on the sidewalls of the protruding fins 124' and 224'. According to some embodiments of this disclosure, the gate spacers 138 and 238 are formed from one or more dielectrics such as silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon nitride, or the like, and may have a single-layer structure or a multi-layer structure with multiple dielectric layers. For example, the gate spacers 138 and 238 may include a low-k dielectric underlayer and a non-low-k dielectric underlayer. Forming the gate spacers 138 and 238 may include one or more conformal deposition processes followed by one or more anisotropic etch processes.The conformal deposition processes can be carried out using ALD, CVD or the like.

[0017] Then, an etching process is performed to etch the portions of the protruding fins 124' and 224' that are not covered by the corresponding dummy gate stacks 130 and 230 and the gate spacers 138 and 238, resulting in the Fig. 4. The respective process is shown as process 306 in process flow 300 of Fig. 19. The etch process may be anisotropic, such that the portions of the fins 124' and 224' that lie directly beneath the respective dummy gate stack 130 / 230 and the gate spacers 138 / 238 are protected and not etched. The upper surfaces of the excised semiconductor stripes 124 and 224 may, according to some embodiments, be lower than the upper surfaces of the adjacent STI regions 22. Accordingly, cutouts 140 and 240 may be formed between the STI regions 22. The excision in the device regions 100 and 200 may be performed in a common etch process or in separate processes, and the depths of the cutouts 140 may be the same as or different from the depths of the cutouts 240.

[0018] Then, epitaxial regions (source / drain regions) are formed by selectively building up semiconductor materials in the cutouts 140 and 240, resulting in the Fig. 5. The respective process is shown as process 308 in process flow 300 of Fig. 19. The material of the epitaxial regions depends on whether the respective device region is for forming a p-type transistor or an n-type transistor. According to some embodiments, when the respective transistor is a p-type transistor, the respective epitaxial regions 142 or 242 may comprise boron-doped silicon germanium (SiGeB), silicon boron (SiB), or the like, or multiple layers thereof that are p-type layers. According to some embodiments, when the respective transistor is an n-type transistor, the respective epitaxial regions 142 or 242 may be formed of or comprise silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), silicon arsenic (SiAs), or the like, or multiple layers thereof that are n-type layers.If the epitaxial regions 142 and 242 have opposite conductivity types, the epitaxial regions 142 and 242 are performed in separate processes and formed using different masks (not shown).

[0019] After cutouts 140 and 240 are filled with the epitaxial semiconductor material, further epitaxial growth of epitaxial regions 142 and 242 results in a horizontal expansion of epitaxial regions 142 and 242, and facets may be formed. The epitaxial regions constructed from adjacent cutouts may be merged into one large epitaxial region or may remain as individual epitaxial regions if not merged. Epitaxial regions 142 and 242 form the source / drain regions of the respective transistors and may also be referred to as source / drain regions 142 and 242, respectively.

[0020] Fig. 6 illustrates a perspective view for the deposition of the contact etch stop layer (CESL) 46 and the interlayer dielectric (ILD) 48. The respective process is shown as process 310 in process flow 300 of Fig. 19. According to some embodiments of this disclosure, CESL 46 is formed from silicon nitride, silicon carbonitride, or the like. CESL 46 may be formed by a conformal deposition process such as ALD or CVD. ILD 48 is formed over CESL 46 and may be formed, for example, by FCVD, spin coating, CVD, or the like. ILD 48 may be formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethylorthosilicate oxide (TEOS), or the like. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to flatten the top surfaces of CESL 46, ILD 48, dummy gate stacks 130 and 230, and gate spacers 138 and 238 relative to one another.

[0021] After the Fig. 6 has been formed, the dummy gate stacks 130 and 230, including the hard mask layers 136 and 236, the dummy gate electrodes 134 and 234, and the dummy gate dielectrics 132 and 232, are replaced with metal gates and replacement gate dielectrics that form replacement gate stacks. The respective process is shown as process 312 in process flow 300 of Fig. 19. To form the replacement gates, the Fig. 6 are removed by etching processes, creating trenches between the gate spacers 138 and between the gate spacers 238, respectively. The top surfaces and sidewalls of the protruding fins 124' and 224' are exposed by the resulting trenches.

[0022] The replacement gate stacks 150 and 250 are then formed in the trenches as shown in the Fig. 7A and Fig. 7B, which show a perspective view and a cross-sectional view of portions of the wafer 10. According to some embodiments of this disclosure, replacement gate stacks 150 include gate dielectrics 152 and gate electrodes 158 over the corresponding gate dielectrics 152. Replacement gate stacks 250 include gate dielectrics 252 and gate electrodes 258 over the corresponding gate dielectrics 252. The gate dielectrics 152 and 252 include the interface layers (ILs) 154 and 254 and the overlying high-k dielectrics 156 and 256, respectively, as shown in Fig. 7B. ILs 154 and 254 are formed on the exposed surfaces of protruding fins 124' and 224', respectively. Each of ILs 154 and 254 may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the surface layers of protruding fins 124' and 224', a chemical oxidation process, or a deposition process.

[0023] In Fig. 7B are the Fig. 7A shown cross sections 7B to 7B. As in Fig. 7B, the gate dielectrics 152 and 252 may further include high-k dielectric layers 156 and 256 formed over the ILs 154 and 254, respectively. The high-k dielectric layers 156 and 256 may be formed from or include a high-k dielectric such as hafnium oxide, lanthanum oxide, alumina, zirconium oxide, silicon nitride, or the like. The dielectric constant (k value) of the high-k dielectric is greater than 3.9 and may be greater than approximately 7.0. The high-k dielectric layers 156 and 256 are formed as conformal layers and extend on the sidewalls of the protruding fins 124' and 224' and the sidewalls of the gate spacers 138 and 238. According to some embodiments of this disclosure, the high-k dielectric layers 156 and 256 are formed using ALD or CVD.

[0024] It should be noted that although Fig. 7B illustrates the top surfaces of epitaxial regions 142 and 242 as coplanar with the top surfaces of protruding fins 124' and 224', however, the top surfaces of epitaxial regions 142 and 242 may be higher than the top surfaces of the corresponding protruding fins 124' and 224'.

[0025] The gate electrodes 158 and 258 ( Fig. 7B) may include multiple stacked conductive sublayers. Forming the gate electrodes 158 and 258 may include conformal deposition processes such as ALD or CVD, such that the thicknesses of the vertical portions and the thickness of the horizontal portions of the stacked conductive sublayers are substantially equal.

[0026] The gate electrodes 158 and 258 may include a metal layer 158A and 258A, respectively, each comprising a diffusion barrier layer and one or more work function layers (not shown separately) above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (but need not be) doped with silicon. The work function layer determines the work function of the corresponding gate and includes at least one or more layers formed of different materials. The material of the work function layer is selected depending on whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, if a device region 100 is a p-type device region, the work function layer in the metal layer 158A may include a TiN layer.If device region 200 is an n-type device region, the corresponding work function layer in metal layer 258A may comprise an aluminum-containing metal layer (such as TiAl, TiAlC, TiAlN, or the like). After deposition of the work function layer(s), a barrier layer, which may be another TiN layer, is formed.

[0027] The gate electrodes 158 and 258 may also include respective fill metals 158B and 258B, which fill the remaining trenches if the trenches have not been completely filled by the respective metal layer 158A and 258A. The fill metal may be formed of tungsten or cobalt, for example. After forming the fill material, a planarization process, such as a CMP process or a mechanical grinding process, is performed so that the portions of the deposited layers above ILD 48 are removed. The remaining portion of the gate dielectrics 152 / 252 and the gate electrodes 158 / 258 are hereinafter referred to as replacement gate stacks 150 and 250.

[0028] According to some embodiments, self-aligned gate masks 160 and 260 are then formed. The respective process is also shown as process 312 in process flow 300 of Fig. 19. The self-aligned gate masks 160 and 260 are self-aligned to the underlying replacement gate stacks 150 and 250. They are formed from one or more dielectrics such as ZrO2, Al2O3, SiON, SiCN, SiO2, or the like. The formation process may include cutting out the replacement gate stacks 150 and 250 by etching to form cutouts, filling the dielectric into the cutouts, and performing a planarization process to remove excess portions of the dielectric. Here, the top surfaces of the gate masks 160 and 260, the gate spacers 138 and 238, the CESL 46, and the ILD 48 may be substantially coplanar.

[0029] With reference to the Fig. 8A and Fig. 8B, ILD 48 and CESL 46 are etched to form source / drain contact openings 162 and 262. The respective process is shown as process 314 in process flow 300 of Fig. 19 illustrated. Fig. Figure 8B illustrates the cross section 8B to 8B as in Fig. 8A. The CESL 46 is used as an etch stop layer during the etching of the ILD 48, and then the CESL 46 is etched, exposing the underlying source / drain regions 142 and 242. The contact openings 162 and 262 may be formed simultaneously or separately. Due to the overetch, the openings 162 and 262 may extend slightly into the source / drain regions 142 and 242, as shown in Fig. 8B is shown.

[0030] With reference to Fig. 8B, after forming contact openings 162 and 262, some portions of CESL 46 and ILD 48 remain on one side or both sides of the respective contact openings 162 and 262 according to some embodiments. The corresponding remaining portions of CESL 46 and ILD 48 are also used as portions of the spacers in the subsequent dopant implantation and silicidation processes. Accordingly, the remaining portions of CESL 46 and ILD 48 on the opposite sides of contact openings 162 and 262 are referred to as spacers 163 and 263. According to alternative embodiments, the portions of CESL 46 and ILD 48 between adjacent gate spacers 138 and between adjacent gate spacers 238 are completely removed. Therefore, the sidewalls of gate spacers 138 and 238 are exposed at the corresponding contact openings 162 and 262, respectively.

[0031] The exposed surfaces of the source / drain regions 142 and 242 may be oxidized, for example, when exposed to open air or other oxygen-containing gases and / or moisture-containing gases. The oxidation may also be caused by a cleaning process performed after the formation of the contact vias 162 and 262, in which the cleaning solution may include water. The oxidation results in the formation of oxide layers 164 and 264 on the exposed surfaces of the source / drain regions 142 and 242, respectively. The oxide layers 164 and 264 may comprise silicon oxide, silicon germanium oxide, or the like, depending on the material of the underlying source / drain regions 142 and 242. According to some embodiments, the oxide layers 164 and 264 have thicknesses ranging between about 2 nm and about 4 nm.

[0032] According to some embodiments, contact openings 162 and 262 have the same lateral dimensions, such as the same lengths, widths, diameters, etc. For example, the width W1 of contact opening 162 may be equal to the width W2 of contact opening 262. The widths W1 and W2 may be measured at the mid-heights of the gate stacks 150 and 250, respectively. Furthermore, contact opening 162 may be formed midway between adjacent gate spacers 138, and contact opening 262 may be formed midway between adjacent gate spacers 238. Accordingly, the thickness T1 of spacer 163 may be equal to the thickness T2 of spacer 263, wherein the thicknesses T1 and T2 are also measured at the mid-heights of the corresponding gate stacks 150 and 250, respectively.

[0033] With reference to Fig. 9, the dielectric spacer layer 66 is formed to extend into the contact openings 162 and 262, respectively, and onto the sidewalls of CESL 46 and ILD 48. The respective process is shown as process 316 in process flow 300 of Fig. 19. The dielectric spacer layer 66 also extends onto the sidewalls of the source / drain regions 142 and 242, as can be seen from the shape of the source / drain regions 142 and 242 in Fig. 8A. According to some embodiments of this disclosure, the dielectric spacer layer 66 is formed by a conformal deposition process such as CVD or ALD. The dielectric spacer layer 66 may be a high-k dielectric layer of greater than 3.9, thus providing good insulating properties. Candidate materials include SiN, SiOCN, Al x O y, HfO2, or the like. The thickness of the dielectric spacer layer 66 may, for example, range between about 2 nm and about 6 nm.

[0034] With reference to Fig. 10, an anisotropic etching process is performed such that the horizontal portions of the dielectric spacer layer 66 are removed and the vertical portions of the dielectric spacer layer 66 remain within the contact openings 162 and 262 to form contact spacers 166 and 266, respectively. The respective process is shown as process 318 in process flow 300 of Fig. 19. Each of the contact spacers 166 and 266 may form a ring when viewed from the top surface of the wafer 10. Since the portions of the dielectric layer 66 in the contact openings 162 and 262 have the same thickness and furthermore, the widths W1 and W2 (the widths of the contact openings 162 and 262 without the contact spacers 166 and 266) are equal, the width W3 of the contact opening 162 may be equal to the width W4 of the contact opening 262. The widths W3 and W4 may be measured at the mid-heights of the gate stacks 150 and 250, respectively.

[0035] With reference to Fig. 11, the implantation mask 270 is formed. The implantation mask 270 may comprise a photoresist and may be a single-layer mask, a three-layer mask, a four-layer mask, or the like. The respective process is shown as process 320 in process flow 300 of Fig. 19. The implantation mask 270 is patterned, with a remaining portion covering the pattern in the device region 200 while the pattern remains exposed in Figure 100.

[0036] Next, an implantation process 172 is performed to implant a dopant into the device region 100. The respective process is shown as process 322 in process flow 300 of Fig. 19. The dopant is of the same conductivity type as the transistor formed in device region 100. For example, if a p-type transistor is to be formed in device region 100 (and source / drain regions 142 are p-type), the implanted dopant is also p-type and may include boron, BF2, gallium, indium, or the like, or combinations thereof. If an n-type transistor is to be formed in device region 100 (and source / drain regions 142 are n-type), the implanted dopant may include arsenic, phosphorus, antimony, or combinations thereof. By selectively masking device region 200 and implanting into source / drain regions 142, the devices in device regions 100 and 200 can be treated differently. For example, if a p-type transistor and an n-type transistor are formed in the device regions 100 and 102, respectively.200 are to be formed, the p-type dopant may be implanted to increase the p-type dopant concentration in the source / drain region 142 (so that the source / drain resistance can be reduced), while leaving the n-type dopant concentration in the source / drain regions 242 unchanged. If the devices in the device regions 100 and 200 are of the same conductivity type, such as p or n, the selective implantation may also be used to fine-tune the device performance of the transistors in the device regions 100 and 200, so that the transistors may have different performance.

[0037] The implantation energy of the implantation process 172 may range between approximately 0.3 keV and approximately 50 keV. The implantation process 172 results in the upper portion of the source / drain region 142 being implanted to include the dopant therein, while the lower portion of the source / drain region 142 is not implanted. The implantation dose may range between approximately 5E13 / cm 2 and about 1E16 / cm 2 The implantation can be performed vertically or at an inclination angle of less than approximately 60 degrees. During implantation, the temperature of the wafer can be increased, for example, in a range between approximately 100°C and approximately 500°C.

[0038] Fig. 11 schematically illustrates the implanted regions, which are labeled with the corresponding notation of the implanted regions followed by the character "'". For example, the implanted upper portion of source / drain 142, the contact spacers 166, and the gate masks 160 may alternatively be referred to as 142', 166', and 160', respectively. Spacers 163 may also be implanted. Upon implantation, the volume of the implanted portions increases due to the implantation damage and the addition of the implanted dopant. The thicknesses of the spacers 163 and 166 are referred to as T1' and T3', respectively, where the thickness T1' is greater than the thickness T1 ( Fig. 10) and the thickness T3' is greater than the thickness T3 ( Fig. 10). Thicknesses T1 and T3 are the thicknesses of spacers 163 and 166, respectively, before the implantation process is performed. Furthermore, thickness T1' may be greater than thickness T2 of spacers 263, and thickness T3' may be greater than thickness T4 of spacers 266.

[0039] According to some embodiments, the total thickness (T1' + T3') is greater than the total thickness (T1 + T3) by a difference in the range between about 0.2 nm and about 1 nm ( Fig. 10, before the implantation process). In addition, the spacers 263 and 266 have a total thickness (T2 + T4) that may be equal to the total thickness (T1 + T3). Accordingly, the total thickness (T1' + T3') of the contact spacers 163' and 166' is greater than the total thickness (T2 + T4) of the contact spacers 263 and 266. The expansion of the contact spacers 163' and 166' may lead to an unfavorable reduction in the width of the subsequently formed contact plugs and to an unfavorable increase in the contact resistance.

[0040] Due to the masking of the device region 200 during the implantation process 172, the contact spacers 266 and the spacers 263 (and the ILD 48 and CESL 46 in the spacers 263) may be free of the implanted dopant such as boron, gallium, indium, or the like, depending on the dopant used in the implantation process 172. Furthermore, no dopant having the same conductivity type as the source / drain regions 242 may be implanted in the device region 200. For example, if the source / drain regions 242 are n-type regions, the contact spacers 266 and the spacers 263 may be present in the resulting FinFET 290 ( Fig. 15) be free from phosphorus, arsenic, antimony or the like.

[0041] After the implantation process, the implantation mask 270 is removed. The resulting structure is shown in Fig. 12. The respective process is shown as process 324 in process flow 300 of Fig. 19. The two oxide layers 164 and 264 are exposed. Due to the implantation, the contact spacers 163 and 166' expand laterally, while the contact spacers 263 and 266 do not expand, so that W3' of the contact opening 162 is smaller than W4 of the contact opening 262.

[0042] In a subsequent process, a cleaning process is performed to remove the oxide layers 164 and 264 and to expose the source / drain regions 142 and 242. The respective process is shown as process 326 in process flow 300 of Fig. 19. The resulting structure is shown in Fig. 13. According to some embodiments, the cleaning process may be performed using a mixture of NF3 and NH3, a mixture of HF and NH3, or the like when dry cleaning is used. The cleaning process may also be performed with diluted HF solution when wet cleaning is used. During the cleaning process, the two contact spacers 166' and 266 are exposed to the cleaning chemical and are also thinned, although the contact spacers 166' and 266 are thinned at a lower etch rate than the corresponding oxide layers 164 and 264. The resulting thicknesses of the contact spacers 166' and 266 are referred to as thicknesses T3" and T4", respectively, which are smaller than the thicknesses T3' and T4, respectively, in Fig. 11. According to some embodiments, the thicknesses of the spacers 166' and 266 may be reduced by values ​​in the range between about 0.5 nm and about 2 nm.

[0043] The implanted contact spacers 166' have a higher etch rate than the contact spacer 266. Accordingly, the increased thickness of the contact spacers 166' (due to the implantation) is compensated (reduced more) by the higher etch rate of the contact spacers 166' compared to the contact spacers 266. By performing the implantation process after rather than before the formation of the contact spacers 166' (166), the effect of the implantation on the thickness of the contact spacers 166' is at least reduced or substantially eliminated. For example, the thickness T3" is smaller than the thickness T3' ( Fig. 11) and can be equal to, smaller or larger than the thickness T3 ( Fig. 10).

[0044] In addition, by performing the implantation process after forming contact spacers 166 (166'), the thickness difference ((T1' + T3") - (T2 + T4")) is reduced and can be eliminated, where (T1' + T3") is the total thickness of contact spacers 163 and 166' and (T2 + T4") is the total thickness of contact spacers 263 and 266. For example, the thickness difference can be less than about 0.5 nm and less than about 0.2 nm. In addition, in Fig. 13 W3" of contact opening 162 may be equal to, less than, or greater than W4" of contact opening 262. Alternatively, the width of opening 162 may be reduced by a first amount by the implantation, and the cleaning and thinning process may increase the width of opening 162 by a second amount. The second amount may be equal to, greater than, or less than the first amount. According to some embodiments, the cleaning process (such as the chemical and / or the duration) is adjusted so that width W3" is equal to width W4" and the width of the resulting contact plug is maximized while not compromising the protection provided by contact spacer 166. Additionally, thickness T1' may be greater than thickness T2, and thickness T3" will be less than thickness T4".

[0045] The Fig. 14 and Fig. 15 illustrate the formation of source / drain silicide regions. With reference to Fig. 14, the metal layer 76 (such as a titanium layer or a cobalt layer) is deposited, for example, using physical vapor deposition (PVD). The barrier layer 78, which may be a metal nitride layer such as a titanium nitride layer or a tantalum nitride layer, is then deposited over the metal layer 76. The respective process is shown as process 328 in process flow 300 of Fig. 19. The barrier layer 78 may be formed by nitriding an upper layer of the metal layer 76, leaving the lower layer of the metal layer 76 unnitrided. Alternatively, the barrier layer 78 may be formed by a deposition process such as a CVD process or an ALD process. The metal layer 76 and the barrier layer 78 may both be uniform and extend into the contact openings 162 and 262.

[0046] Then, an annealing process is performed to react the metal layer 76 with the silicon (and optionally germanium) in the source / drain regions 142 and 242. Thus, the source / drain silicide regions 180 and 280 are formed, as shown in Fig. 15. The respective process is shown as process 330 in process flow 300 of Fig. 19. The annealing process can be performed by rapid thermal annealing (RTA), furnace annealing, or the like. Some sidewall portions of the metal layer 76 remain after the silicidation process.

[0047] According to some embodiments, the barrier layer 78 and the remaining metal layer 76 are removed. Then, additional barrier layers 182 and 282 are formed, as shown in Fig. 15. According to some embodiments, barrier layers 182 and 282 are also formed of titanium nitride, tantalum nitride, or the like. A metallic material is then deposited over and in contact with barrier layers 182 and 282. The metallic material may include tungsten, cobalt, or the like. A planarization process, such as a CMP process or a mechanical grinding process, is then performed to remove excess portions of barrier layers 182 and 282 and the metallic material. The remaining metallic material portions are referred to as metal regions 184 and 284. Diffusion barrier 182 and metal region 184 together form source / drain contact plug 186, and diffusion barrier 282 and metal region 284 together form source / drain contact plug 286. The respective process is shown as process 332 in process flow 300 of Fig. 19. FinFETs 190 and 290 are formed in this way.

[0048] According to alternative embodiments, the barrier layer 78 and the remaining metal layers 76 may not be removed, but rather the barrier layer 78 may be retracted by etching so that its upper surface is lower than the upper surface of the ILD 48, and the opening therefore has wider upper portions to facilitate gap filling. Additional barrier layers 182 and 282 are formed on the retracted barrier layer 78 (not shown) and the remaining portions of the metal layer 76. Metal regions 184 and 284 are further formed on the additional barrier layers 182 and 282.

[0049] The Fig. 16 and Fig. 17 illustrate cross-sectional views of intermediate stages in the formation of FinFETs and the corresponding contact plugs according to alternative embodiments of this disclosure. These embodiments are similar to the previous embodiments, except that the implantation is performed before, rather than after, the anisotropic etching of the spacer layer to form contact spacers. Unless otherwise specified, the materials and formation processes of the components in these embodiments are substantially the same as their like components, which are denoted by like reference numerals in the previous embodiments shown in the previous figures. The details of the formation process and materials of the components from the Fig. 16 and Fig. 17 can therefore be found in the explanation of the previous embodiments.

[0050] The initial processes of these embodiments are the same as in Fig. 1 to 6, 7A, 7B, 8A, 8B and 9. Instead of etching the spacer layer 66 to form contact spacers, the Fig. 16 is applied. The implantation mask 270 is formed, and the implantation process 172 is performed to dope dopant into the device region 100. During the implantation, the unremoved horizontal portions of the spacer layer 66 may help reduce implantation damage to the underlying source / drain region 142. After the implantation process 172, the implantation mask 270 is removed, followed by the anisotropic etching of the spacer layer 66, so that the contact spacers 166' and 266 are formed. The resulting structure is shown in Fig. 17. The following processes are essentially the same as in the Fig. 13 to 15 and are not repeated here. The resulting FinFETs 190 and 290 are also essentially identical to those shown in Fig. 15 shown.

[0051] Fig. Figure 18 schematically illustrates the distribution of the implanted dopant in the spacer 163, the contact spacer 166', and the contact plug 186 according to some embodiments. The distribution is obtained in the middle height of the gate stack 150. Line 191 represents a likely distribution. Due to the etching of the spacer 166' during the cleaning process, as shown in Fig. 13, the peak concentration of the dopant, which is present in the Fig. 11, after the cleaning process, are located on the exposed sidewall. Therefore, the peak dopant concentration in the final structure ( Fig.15) due to subsequent diffusion at the interface between the contact spacer 166' and the contact plug 186. If a tilt implant is performed and the dopant is implanted deeper into the contact spacer 166' and the spacer 163, the peak dopant concentration may be at the positions shown by lines 192, 193, or 194.

[0052] The embodiments of this disclosure have several advantageous elements. By applying the embodiments of this disclosure, the dopant loss from the source / drain regions due to the various processes for forming contact plugs is reduced compared to conventional processes. In conventional processes, the dopant implantation is performed after the contact opening is formed and before the deposition and anisotropic etching of the spacer layer to form contact spacers. Since the anisotropic etching of the spacer layer leads to dopant losses in the already implanted dopant, the dopant loss is correspondingly high. Since the implantation is performed after the anisotropic etching, there is no dopant loss caused by the anisotropic etching in the embodiments of this disclosure.Dopant loss in the embodiments of this disclosure is therefore lower than in conventional processes. For example, several experimental samples have shown that the final dopant concentration in the source / drain regions of samples fabricated according to the embodiments of this disclosure is approximately 6 percent higher than in the source / drain regions of samples formed using conventional processes.

[0053] Furthermore, because the implanted contact spacers have a higher etch rate during the cleaning processes than the non-implanted contact spacers, the expansion of the contact spacers caused by the implantation process is compensated for, and the thickness of the expanded contact spacers can be reduced more than when they are not implanted. The widths (critical dimension) of the resulting contact plugs 186 can thus be returned to the same values ​​as the contact plugs (e.g., contact plug 286), and the uniformity of the width of the contact plugs within the wafers is improved. For example, some example wafers are formed adopting the embodiments of this disclosure. The average difference between the widths of the contact plugs 186 and 286 is less than about 0.2 nm (or less than about 0.1 nm) and is less than about 2 percent or 1 percent of the average widths.For comparison, using conventional processes, the average width of contact plugs 186 is smaller than the average width of contact plug 286, with the average difference being about 1 nm and can amount to up to about 7% of the average widths.

[0054] According to some embodiments of this disclosure, a method comprises the steps of: forming a first source / drain region; forming a dielectric layer over the first source / drain region; etching the dielectric layer to form a first contact opening, wherein the first source / drain region is exposed through the first contact opening; depositing a dielectric spacer layer extending into the first contact opening; etching the dielectric spacer layer to form a first contact spacer in the first contact opening; after depositing the dielectric spacer layer, implanting a dopant into the first source / drain region through the first contact opening; and forming a first contact plug to fill the first contact opening.

[0055] In one embodiment, the dopant is implanted onto the first contact spacer. In one embodiment, the dopant penetrates a lower portion of the dielectric spacer layer to reach the first source / drain region. In one embodiment, forming the first source / drain region comprises in-situ doping of a p-type dopant, wherein the dopant introduced by the implantation is also p-type.In one embodiment, implanting the dopant results in the width of the first contact opening being reduced by a first amount, and the method comprises, at a time after implanting the dopant into the first source / drain region and before forming the first contact plug to fill the first contact opening, performing a cleaning process to remove an oxide layer on the first source / drain region, wherein in the cleaning process the width of the first contact opening is increased by a second amount that is equal to or greater than the first amount.

[0056] In one embodiment, the second amount is greater than the first amount. In one embodiment, etching the dielectric layer comprises etching an interlayer dielectric and etching a contact etch stop layer underlying the interlayer dielectric. In one embodiment, after etching the dielectric layer to form the first contact opening, a portion of the dielectric layer is left on opposite sides of the first contact opening to form additional spacers.In one embodiment, the method further comprises forming a second source / drain region; etching the dielectric layer to form a second contact opening, wherein the second source / drain region is exposed through the second contact opening; etching the dielectric spacer layer to form a second contact spacer in the second contact opening, wherein the second contact spacer is masked during implantation of the dopant prior to the implantation; and forming a second contact plug to fill the second contact opening. In one embodiment, the first source / drain region is p-type and the second source / drain region is n-type.

[0057] According to some embodiments of this disclosure, a method comprises etching an interlayer dielectric and a contact etch stop layer underlying the interlayer dielectric to form a first contact opening and a second contact opening, wherein a first source / drain region and a second source / drain region are underlying and exposed through the first contact opening and the second contact opening, respectively; depositing a dielectric spacer layer extending into the first contact opening and the second contact opening; etching the dielectric spacer layer to form a first contact spacer in the first contact opening and a second contact spacer in the second contact opening; forming an implantation mask over the second contact spacer and the second source / drain region; implanting a dopant into the first source / drain region through the first contact opening; and removing the implantation mask.

[0058] In one embodiment, the method further comprises performing an etching process after removing the implantation mask to remove a first oxide layer on the first source / drain region and a second oxide layer on the second source / drain region. In one embodiment, the first contact spacer has a first thickness before implantation, and after implantation, the first contact spacer has a second thickness greater than the first thickness, wherein after the etching process, the first contact spacer has a third thickness equal to or less than the first thickness. In one embodiment, the first source / drain region and the second source / drain region are of opposite conductivity types. In one embodiment, the first source / drain region and the second source / drain region are of the same conductivity type.In one embodiment, the dopant implanted by the implantation has the same conductivity type as the first source / drain region. In one embodiment, the dopant implanted by the implantation has a conductivity type opposite to that of the second source / drain region.

[0059] According to some embodiments of this disclosure, a structure comprises a first semiconductor region; a first gate stack on the first semiconductor region; a first source / drain region on one side of the first gate stack, the first source / drain region having a first conductivity type; a first silicide region over the first source / drain region; a first contact plug over the first silicide region; a first contact spacer surrounding and contacting the first contact plug; and a dopant of the first conductivity type in the first contact plug and the first contact spacer, the dopant having a peak concentration located either in the first contact spacer or at an interface between the first contact spacer and the first contact plug.

[0060] In one embodiment, the peak concentration is at the interface. In one embodiment, the structure further comprises a second semiconductor region; a second gate stack on the second semiconductor region; a second source / drain region on one side of the second gate stack, the second source / drain region having a second conductivity type opposite the first conductivity type; a second silicide region over the second source / drain region; a second contact plug over the second silicide region, the first contact plug and the second contact plug having substantially the same width; and a second contact spacer surrounding and contacting the second contact plug, the first contact spacer and the second contact spacer being formed of the same dielectric, and the second contact spacer being thinner than the first contact spacer.

Claims

[1] Method comprising: forming a first source / drain region (142); Forming a dielectric layer (46) over the first source / drain region (142); Etching the dielectric layer (46) to form a first contact opening (162), wherein the first source / drain region (142) is exposed through the first contact opening (162); depositing a dielectric spacer layer (66) extending into the first contact opening (162); etching the dielectric spacer layer (66) to form a first contact spacer (166) in the first contact opening; after depositing the dielectric spacer layer (66), implanting a dopant into the first source / drain region (142) through the first contact opening (162); and Forming a first contact plug (186) to fill the first contact opening (162), wherein the dopant penetrates a lower portion of the dielectric spacer layer (66) to reach the first source / drain region (142). [2] The method of claim 1, wherein the dopant is implanted on the first contact spacer (166). [3] The method of any preceding claim, wherein forming the first source / drain region (142) comprises in-situ doping of a p-type dopant, and wherein the dopant introduced by the implantation is also p-type. [4] The method of any preceding claim, wherein implanting the dopant results in the width of the first contact opening (162) being reduced by a first amount, and the method comprises: at a time after implanting the dopant into the first source / drain region (142) and before forming the first contact plug (186) to fill the first contact opening (162), performing a cleaning process to remove an oxide layer (164) on the first source / drain region (142), the cleaning process resulting in the width of the first contact opening (162) being increased by a second amount that is equal to or greater than the first amount. [5] The method of claim 4, wherein the second amount is greater than the first amount. [6] The method of any preceding claim, wherein etching the dielectric layer (46) comprises etching an interlayer dielectric (48) and etching a contact etch stop layer (46) underlying the interlayer dielectric (48). [7] A method according to any one of the preceding claims, wherein after etching the dielectric layer (46) to form the first contact opening (162), a portion of the dielectric layer (46) remains on opposite sides of the first contact opening (162) to form additional spacers (163). [8] Method according to one of the preceding claims, further comprising: forming a second source / drain region (242); etching the dielectric layer (46) to form a second contact opening (262), wherein the second source / drain region (242) is exposed through the second contact opening (262); Etching the dielectric spacer layer (66) to form a second contact spacer (266) in the second contact opening (262), wherein the second contact spacer (266) is masked during implantation of the dopant prior to implantation; and Forming a second contact plug (286) to fill the second contact opening (262). [9] The method of claim 8, wherein the first source / drain region (142) is p-type and the second source / drain region (242) is n-type. [10] Method comprising: Etching an interlayer dielectric (48) and a contact etch stop layer (46) underlying the interlayer dielectric (48) to form a first contact opening (162) and a second contact opening (262), wherein a first source / drain region (142) and a second source / drain region (242) are located beneath and exposed through the first contact opening (162) and the second contact opening (262); depositing a dielectric spacer layer (66) extending into the first contact opening (162) and the second contact opening (262); etching the dielectric spacer layer (66) to form a first contact spacer (166) in the first contact opening (162) and a second contact spacer (266) in the second contact opening (262); Forming an implantation mask (270) over the second contact spacer (266) and the second source / drain region (242); implanting a dopant into the first source / drain region (142) through the first contact opening (162); and Removing the implantation mask (270), wherein the dopant penetrates a lower portion of the dielectric spacer layer (66) to reach the first source / drain region (142). [11] The method of claim 10, further comprising performing an etching process after removing the implantation mask (270) to remove a first oxide layer (164) on the first source / drain region (142) and a second oxide layer (264) on the second source / drain region (242). [12] The method of claim 11, wherein the first contact spacer (166) has a first thickness before implantation and the first contact spacer (166) has a second thickness greater than the first thickness after implantation, wherein after the etching process the first contact spacer (166) has a third thickness equal to or less than the first thickness. [13] The method of any one of the preceding claims 10 to 12, wherein the first source / drain region (142) and the second source / drain region (242) have opposite conductivity types. [14] The method of any one of the preceding claims 10 to 12, wherein the first source / drain region (142) and the second source / drain region (242) have a same conductivity type. [15] The method of any one of the preceding claims 10 to 14, wherein the dopant implanted by the implantation has a same conductivity type as the first source / drain region (142). [16] The method of claim 15, wherein the dopant implanted by the implantation has an opposite conductivity type to the second source / drain region (242).

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