Integrated chip structures with diffusion barrier to reduce creep loss due to direct short circuit in conductive bridging ram (CBRAM) manufacturing process

Abstract

Featuring an integrated chip structure: a lower electrode arranged in a dielectric structure on a substrate; an upper electrode that is positioned above the lower electrode in the dielectric structure; a switching layer between the lower electrode and the upper electrode; an ion source layer positioned between the lower electrode and the upper electrode; and a barrier structure located between the lower electrode and the upper electrode, wherein the barrier structure contains a metal nitride designed to restrict thermal diffusion of metal during a high-temperature manufacturing process, wherein the barrier structure has a first non-zero atomic percentage of nitrogen of over about 50%, and the ion source layer has a second non-zero atomic percentage of nitrogen of under about 20%.

Description

BACKGROUND

[0001] Many modern electronic devices contain memory designed to digitally store data. Memory in electronic devices can be either volatile or non-volatile. Volatile memory stores data when power is applied, while non-volatile memory can store data when the power is turned off. Conductive-bridging random-access memory (CBRAM) is considered a promising candidate for a new generation of non-volatile memory technology because of its high-speed, low-power capability, and the ability to be manufactured using a process compatible with existing CMOS manufacturing processes.

[0002] The prior art relating to the subject matter of the invention can be found, for example, in the patent specifications DE 10 2019 116 329 A1, DE 10 2020 107 107 A1, US 2017 / 0 133 434 A1 and US 2015 / 0 123 065 A1.

[0003] The task is to improve corresponding CBRAM memories.

[0004] The object is achieved by the integrated chip structures according to claims 1 and 10 and the method according to claim 18. Further embodiments are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure can best be understood by studying the following detailed description in conjunction with the accompanying figures. It should be noted that, consistent with industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be exaggerated or decreased for purposes of illustration. Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip structure including a conductive bridging random access memory (CBRAM) device with a barrier structure configured to reduce metal diffusion caused by high-temperature manufacturing processes. The Fig. 2A and Fig. 2B illustrate some additional embodiments of an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion. The Fig. 3A and Fig. 3B illustrate cross-sectional views of some embodiments showing the operation of a CBRAM device with a barrier structure designed to reduce metal diffusion. The Fig. 4A and Fig. 4B illustrate some additional embodiments of an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion. The Fig. 5 to 7D illustrate some additional embodiments of integrated chip structures including a CBRAM device with a barrier structure configured to reduce metal diffusion. The Fig. 8A and Fig. 8B illustrate some additional embodiments of an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion. Fig. 9 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including a logic region and an embedded memory region with a CBRAM device having a barrier structure configured to reduce metal diffusion. The Fig. 10 to 19 illustrate cross-sectional views showing some embodiments of a method for forming an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion. Fig. 20 illustrates a flow diagram for some embodiments of a method of forming an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples of implementing various features of the subject matter. Certain example components and arrangements are described below to simplify the present disclosure. In the following description, forming a first feature on or at a second feature may include, for example, embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, throughout the present disclosure, reference numbers and / or reference characters may be repeated throughout the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various embodiments and / or configurations explained.

[0007] Spatially relatable terms such as "beneath," "under," "lower," "above," "above," "above," "upper," and the like may also be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relatable terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relatable descriptors used herein may also be interpreted accordingly.

[0008] A conductive bridging random access memory (CBRAM) device typically comprises an ion source layer (ISL) and a switching layer (SL) disposed between first and second electrodes. The CBRAM device operates by selectively forming and dissolving a conductive filament of metal ions in the switching layer, switching between conduction states. When the conductive filament is present in the switching layer, the CBRAM device has a first resistance corresponding to a first data state (e.g., a logical "1"). When the conductive filament is absent from the switching layer, the CBRAM device has a second resistance corresponding to a second data state (e.g., a logical "0").

[0009] During a set mode, for example, a first bias voltage applied to the first and / or second electrode causes metal ions to migrate from the ion source layer into the switching layer, forming a conductive filament that passes through the switching layer and imparts a first resistance to the CBRAM device (e.g., placing it in a low-resistance state). During a reset mode, a polarity of the bias voltage is changed, and metal ions are driven back from the switching layer into the ion source layer, dissolving the conductive filament and switching the CBRAM device from the first resistance to a second resistance (e.g., placing it in a high-resistance state).

[0010] A CBRAM device may be subjected to high-temperature processes (e.g., bonding processes, soldering processes, or the like) during manufacturing. It is understood that metal (e.g., metal ions and / or metal atoms) in the ion source layer may thermally diffuse into the switching layer during such high-temperature processes. Thermal diffusion of metal into the switching layer may result in unwanted metal being present in the switching layer without a bias voltage being applied to the CBRAM device. The unwanted metal may cause leakage between the top and bottom electrodes and / or even lead to failure of the CBRAM device (e.g., the unwanted metal may form an undesirable conductive bridge in the switching layer, preventing switching between conduction states).

[0011] The present disclosure relates to an integrated chip structure comprising a CBRAM device with a barrier structure designed to prevent thermal diffusion of metal into a switching layer during high-temperature manufacturing processes (the barrier structure may, for example, prevent a short-circuit current problem caused by ion migration during the thermal wiring process (BEOL - Back-End-of-Line)). In some embodiments, the integrated chip structure may comprise a bottom and an top electrode arranged in a dielectric structure on a substrate. A switching layer and an ion source layer are located between the bottom electrode and the top electrode. A barrier structure is arranged between the switching layer and the ion source layer.The barrier structure is designed to limit thermal diffusion of metal (e.g., metal ions) between the ion source layer and the switching layer during high-temperature processes that can occur during the fabrication of the integrated chip structure. By limiting thermal diffusion of metal during high-temperature fabrication processes, the barrier structure can prevent unwanted metal in the switching layer and improve the performance and / or yield of the CBRAM device. According to a wafer quality test (WAT - Wafer Acceptance Test), the barrier structure can, for example, prevent and / or reduce leakage currents between the bottom electrode and the top electrode.

[0012] Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip structure 100 including a conductive bridging random access memory (CBRAM) device with a barrier structure configured to reduce metal diffusion caused by high-temperature manufacturing processes.

[0013] The integrated chip structure 100 includes a conductive bridging random access memory (CBRAM) device 108 disposed within a dielectric structure 104 on a substrate 102. The dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers. In some embodiments, the plurality of stacked ILD layers may include a lower ILD structure 104L disposed between the CBRAM device 108 and the substrate 102 and an upper ILD structure 104U surrounding the CBRAM device 108. In some embodiments, the lower ILD structure 104L includes one or more lower ILD layers surrounding one or more lower interconnects 106 disposed beneath the CBRAM device 108.

[0014] The CBRAM device 108 includes a switching layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. During operation, a bias voltage causes metal (e.g., metal ions such as silver, copper, aluminum ions, etc.) to move between the ion source layer 116 and the switching layer 112, selectively forming and / or dissolving a conductive filament (e.g., a conductive bridge) in the switching layer 112. For example, when a first bias voltage is applied to the CBRAM device 108, metal ions move from the ion source layer 116 into the switching layer 112, forming a conductive filament in the switching layer 112 and imparting a first resistance to the CBRAM device 108 (e.g., placing it in a low-ohmic state corresponding to a first data state).Alternatively, when a second bias voltage is applied to the CBRAM device 108, metal ions move from the switching layer 112 back into the ion source layer 116, imparting a second resistance to the CBRAM device 108 (e.g., placing it in a high-resistance state corresponding to a second data state).

[0015] The CBRAM device 108 also includes a barrier structure 114 disposed between the bottom electrode 110 and the top electrode 118. The barrier structure 114 is configured to contain the thermal diffusion of metal (e.g., metal ions). In some embodiments, the barrier structure 114 may be disposed between the switching layer 112 and the ion source layer 116. In such embodiments, the barrier structure 114 may be configured to contain the thermal diffusion of metal from the ion source layer 116 into the switching layer 112 during high-temperature processes (e.g., manufacturing processes performed at a temperature of at least about 300°C, about 400°C, about 500°C, or other similar temperatures) employed in the fabrication of an integrated chip structure (e.g., an integrated chip).By limiting the thermal diffusion of metal from the ion source layer 116 into the switching layer 112 during high-temperature processes, the formation of unwanted metal (e.g., an unwanted conductive filament) in the switching layer 112 can be avoided, thereby improving the performance and / or yield of the CBRAM device 108.

[0016] Fig. 2A illustrates a cross-sectional view of some additional embodiments of an integrated chip 200 including a CBRAM device with a barrier structure configured to reduce metal diffusion.

[0017] The integrated chip 200 includes a CBRAM device 108 arranged in a dielectric structure 104 on a substrate 102. In some embodiments, the dielectric structure 104 includes a lower ILD structure 104L and an upper ILD structure 104U on the lower ILD structure 104L. The lower ILD structure 104L includes one or more lower ILD layers 104a and 104b laterally surrounding one or more lower interconnects 106. In some embodiments, the lower ILD structure 104L may include a first lower ILD layer 104a and a second lower ILD layer 104b. In some embodiments, the one or more interconnects 106 may include conductive contacts, interconnect traces, and / or interconnect vias. The upper ILD structure 104U laterally surrounds the CBRAM device 108.In some embodiments, the lower ILD structure 104L and / or the upper ILD structure 104U may comprise silicon dioxide, carbon-doped silicon oxide (SiCOH), phosphosilicate glass (PSG), boron-phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or / and the like. In some embodiments, the one or more lower interconnects 106 may comprise copper, aluminum, tungsten, ruthenium, or / and the like.

[0018] In some embodiments, the one or more interconnects 106 are configured to connect the CBRAM device 108 to an access device 202 disposed in the substrate 102. In some embodiments, the access device 202 may comprise a MOSFET device having a gate structure 202c disposed laterally between a source region 202a and a drain region 202b. In some embodiments, the gate structure 202c may comprise a gate electrode separated from the substrate 102 by a gate dielectric. In some of these embodiments, the source region 202a is connected to a source line SL, and the gate structure 202c is connected to a word line. In various embodiments, the MOSFET device may comprise a planar FET, a FinFET, a gate all-around (GAA) device, or the like.In other embodiments, the access device 202 may comprise a HEMT (high-electron-mobility transistor), a BJT (bipolar junction transistor), a JFET (junction-gate field-effect transistor), or the like.

[0019] A lower isolation structure 204 is disposed on the lower ILD structure 104. The lower isolation structure 204 includes sidewalls that define an opening extending through the lower isolation structure 204. In some embodiments, the lower isolation structure 204 may include a first dielectric layer 204a and a second dielectric layer 204b on top of the first dielectric layer 204a. In some embodiments, the first dielectric layer 204a may include a different material than the second dielectric layer 204b. In various embodiments, the first dielectric layer 204a may include silicon-rich oxide, silicon carbide, silicon dioxide, silicon nitride, or the like, while the second dielectric layer 204b may include silicon carbide, silicon nitride, silicon dioxide, or the like.

[0020] A bottom electrode via 206 is disposed between the sidewalls of the bottom insulating structure 204. The bottom electrode via 206 extends from one of the bottom interconnects 106 to the top of the bottom insulating structure 204. In some embodiments, the bottom electrode via 206 may include a barrier layer 206a and a conductive core 206b surrounded by the barrier layer 206a. In some embodiments, the barrier layer 206a may include titanium, titanium nitride, tantalum, tantalum nitride, or / and the like. In some embodiments, the conductive core 206b may include aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or / and the like.

[0021] The CBRAM device 108 is disposed on the bottom electrode via 206. In some embodiments, the CBRAM device 108 includes a bottom electrode 110 separated from a top electrode 118 by a switching layer 112 and an ion source layer 116. In some embodiments, the bottom electrode 110 and the top electrode 118 may comprise a metal such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. In some embodiments, the bottom electrode 110 may have a first work function (e.g., about 4.2 eV) and the top electrode 118 may have a second work function (e.g., about 4.15 eV) lower than the first work function. In some embodiments, the switching layer 112 may comprise an oxide, a nitride, or the like.For example, in some embodiments, the switching layer 112 may comprise a metal oxide, a chalcogenide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon oxide, or the like. In some embodiments, the ion source layer 116 may comprise copper, silver, aluminum, or the like.

[0022] The CBRAM device 108 further includes a barrier structure 114 disposed between the bottom electrode 110 and the top electrode 118. In some embodiments, the barrier structure 114 has a bottom surface in contact with the switching layer 112 and a top surface in contact with the ion source layer 116. In some embodiments, the barrier structure 114 comprises a nitride and / or a metal nitride. In various embodiments, the barrier structure 114 may comprise, for example, titanium nitride, amorphous titanium nitride, tantalum nitride, tungsten nitride, aluminum nitride, silicon nitride, tungsten nitride, ceramic aluminum nitride, or the like. In some embodiments, the barrier structure 114 may have a thickness 208 of a maximum of about 7.5 nm, a maximum of about 5.0 nm, a maximum of about 4.0 nm, or other similar values. If the thickness 208 of the barrier structure 114 is too large (e.g.more than about 7.5 nm, more than about 5.0 nm, or other similar values), the barrier structure 114 may hinder movement of metal ions during operation of the CBRAM device 108 and thereby adversely affect the operation of the CBRAM device 108.

[0023] A first conductive filament 210 (e.g., a conductive bridge) extends through the barrier structure 114. The first conductive filament 210 comprises a plurality of metal ions (e.g., gold ions, copper ions, aluminum ions, or the like) that extend continuously from an upper surface of the barrier structure 114 to a lower surface of the barrier structure 114. In some embodiments, the first conductive filament 210 extends through the barrier structure 114 when storing a first and a second data state, while a second conductive filament (not shown) is present in the switching layer 112 when storing the first or second data state.

[0024] An upper interconnect structure 120 is arranged in the upper ILD structure 104U and connected to the upper electrode 118. The upper interconnect structure 120 may include an interconnect via 120a and / or an interconnect trace 120b. In some embodiments, the upper interconnect structure 120 may include aluminum, copper, tungsten, or the like. In some embodiments, the upper interconnect structure 120 is further connected to a bit line BL.

[0025] Fig. 2B illustrates a circuit diagram for some embodiments of a memory circuit 212 including a disclosed CBRAM device.

[0026] The memory circuit 212 comprises a memory array 214 with a plurality of CBRAM memory cells 216 1,1 up to 216 n,m . The multiple CBRAM memory cells 216 1,1 up to 216 n,mare arranged in rows and / or columns in the memory array 214. The plurality of CBRAM memory cells 216 x,1 up to 216 x,m in a row are with word lines WL x (x=1-m) are operatively connected. The multiple CBRAM memory cells 216 1,x up to 216 n,x in one column are bit lines BL x (x=1-n) and source lines SL x (x=1-n) effectively connected.

[0027] The word lines WL1 to WL m , the bit lines BL1 to BL n and the source lines SL1 to SL n are connected to control circuits 218. In some embodiments, the control circuits 218 include a word line WL1 to WL m connected word line decoder 220, one connected to the bit lines BL1 to BL n connected bit line decoder 222 and one connected to the source lines SL1 to SL nconnected source line decoder 224. In some embodiments, the control circuits 218 further include a source line decoder 224 connected to the bit lines BL1 to BL n or the source lines SL1 to SL n connected sense amplifier 226. In some embodiments, the control circuits 218 further comprise a control unit 228 configured to receive address information S ADR to the word line decoder 220, the bit line decoder 222 and / or the source line decoder 224, thus enabling the control circuits 218 to selectively access one or more of the plurality of CBRAM memory cells 216 1,1 up to 216 n,m to access.

[0028] The control circuits 218 are designed, for example, to provide address information S ADRfor the word line decoder 220, the bit line decoder 222 and the source line decoder 224. The word line decoder 220 is designed to operate on the basis of the address information S ADR specifically applies a bias voltage to one of the word lines WL1 to WL m At the same time, the bit line decoder 222 is designed to selectively apply a bias voltage to one of the bit lines BL1 to BL n and / or the source line decoder 224 is designed to selectively apply a bias voltage to one of the source lines SL1 to SL n By applying a bias voltage to selected word lines WL1 to WL m , bit lines BL1 to BL n and / or source lines SL1 to SL n the memory circuit 212 can be operated to store different data states into the plurality of CBRAM memory cells 216 1,1 up to 216 n,m writes or reads from them.

[0029] The Fig. 3A and Fig. 3B illustrate cross-sectional views of some embodiments showing the operation of a CBRAM device with a barrier structure designed to reduce metal diffusion.

[0030] Fig. 3A illustrates a cross-sectional view 300 of a CBRAM device 108 during a tuning operation. During the tuning operation, a tuning voltage V is applied to a lower electrode 110 and an upper electrode 118 of the CBRAM device 108 (e.g., via a lower electrode via 206 and an upper interconnect structure 120). S A first conductive filament 210 (e.g., a first conductive bridge) is present in a barrier structure 114, which is arranged between a switching layer 112 and an ion source layer 116. The setting voltage V Scauses metal ions to migrate from the ion source layer 116 into the switching layer 112, thereby forming the second conductive filament 302 (e.g., a second conductive bridge) in the switching layer 112. The first conductive filament 210 and the second conductive filament 302 extend together between an upper surface of the barrier structure 114 and a lower surface of the switching layer 112. Because the first conductive filament 210 and the second conductive filament 302 extend together through the barrier structure 114 and the switching layer 112, a conduction path is present in the barrier structure 114 and the switching layer 112, thereby imparting a first resistance to the CBRAM device 108 corresponding to a first data state (e.g., a logic "1").

[0031] Fig. 3B illustrates a cross-sectional view 304 of a CBRAM device 108 during a reset operation. During the reset operation, a reset voltage V R The reset voltage V R ensures that metal ions migrate from the switching layer 112 into the ion source layer 116, causing the second conductive filament (302 in Fig. 3A) in the switching layer 112 without removing the first conductive filament 210. Since at least a portion of the second conductive filament 302 is removed, no conduction path is present in the barrier structure 114 and the switching layer 112, thereby imparting a second resistance to the CBRAM device 108 corresponding to a second data state (e.g., a logic "0").

[0032] The Fig. 4A and Fig. 4B illustrate some additional embodiments of an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion.

[0033] Fig. 4A illustrates a cross-sectional view of an integrated chip 200 including a CBRAM device 108 disposed in a dielectric structure 104 on a substrate 102. The CBRAM device 108 includes a switching layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. A barrier structure 114 is disposed between the switching layer 112 and the ion source layer 116. The barrier structure 114 includes a metal nitride configured to restrict thermal diffusion of metal (e.g., metal ions) between the switching layer 112 and the ion source layer 116. In some embodiments, the barrier structure 114 may have a nitrogen to metal ratio that is less than 1, less than about 70%, between about 70% and about 40%, or similar values.For example, the barrier structure 114 may have an atomic percentage ratio of nitrogen to aluminum that is between about 40% and about 70%.

[0034] In some embodiments, the barrier structure 114 has a nitrogen content gradient (e.g., dopant concentration, atomic percentage, or the like) that changes continuously across its height. Fig. For example, Figure 4B illustrates a graph 402 showing an atomic percentage of nitrogen in the barrier structure (on the y-axis) as a function of the location within the CBRAM device (x-axis). As shown in the graph 402 (along line AA' in Fig. 4A), the barrier structure 114 has a first nitrogen content N1 along a lower surface and a second nitrogen content N2 along a top surface. In some embodiments, the first nitrogen content N1 is less than the second nitrogen content N2. In some embodiments, the nitrogen content changes continuously (e.g., increases) between the first nitrogen content N1 and the second nitrogen content N2.

[0035] Fig. 5 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 500 including a CBRAM device with a multi-layer barrier structure.

[0036] The integrated chip structure 500 includes a CBRAM device 108 disposed in a dielectric structure 104 on a substrate 102. The CBRAM device 108 includes a switching layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. A barrier structure 114 is disposed between the switching layer 112 and the ion source layer 116. In some embodiments, the barrier structure 114 includes a plurality of stacked barrier layers 114a and 114b. The plurality of barrier layers 114a and 114b have different nitrogen contents (e.g., dopant concentration, atomic percentage, or the like) such that the barrier structure 114 has a plurality of discrete (e.g., discontinuous) nitrogen contents throughout its height.In some embodiments, the first barrier layer 114a along a lower surface of the barrier structure 114 has a first nitrogen content that is higher than a second nitrogen content of a second barrier layer 114b along a top surface of the barrier structure 114. In some embodiments, the plurality of barrier layers 114a and 114b may have content gradients that are discontinuous with each other at an interface between adjacent ones of the plurality of barrier layers 114a and 114b.

[0037] The Fig. 6A and Fig. 6B illustrate some additional embodiments of an integrated chip structure including a CBRAM device with a barrier structure.

[0038] Fig. 6A illustrates a cross-sectional view 600 of the integrated chip structure. As shown in cross-sectional view 600, the integrated chip structure includes a CBRAM device 108 disposed within a dielectric structure 104 on a substrate 102. The CBRAM device 108 includes a switching layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. A barrier structure 114 is disposed between the switching layer 112 and the ion source layer 116. One or more sidewall spacers 602 extend along outer sidewalls of the switching layer 112, the barrier structure 114, the ion source layer 116, and / or the top electrode 118. The one or more sidewall spacers 602 comprise a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, or the like).

[0039] Fig. 6B illustrates a top view 604 of the integrated chip structure along line AA' in cross-sectional view 600. Cross-sectional view 600 extends along line BB' in top view 604. As shown in top view 604, one or more sidewall spacers 602 extend around an outer edge of barrier structure 114 and separate it from dielectric structure 104.

[0040] The Fig. While Figures 1 to 6B illustrate CBRAM devices having a single barrier structure disposed between a switching layer and an ion source layer, it should be understood that in various additional embodiments, the barrier structure may be located at different locations in the disclosed CBRAM device and / or one or more additional barrier structures may be disposed in the CBRAM device. Fig. 7A to 7C illustrate cross-sectional views of some additional embodiments of integrated chip structures including a CBRAM device with one or more barrier structures between a top and a bottom electrode.

[0041] Fig. 7A illustrates a cross-sectional view of an integrated chip 700 with a CBRAM device 108 having a barrier structure 114 disposed between a top electrode 118 and an upper surface of an ion source layer 116 facing the top electrode 118. Without the barrier structure 114, metal (e.g., metal atoms and / or metal ions) may thermally diffuse between the ion source layer 116 and the top electrode 118, increasing leakage in the CBRAM device 108. The barrier structure 114 is designed to prevent thermal diffusion of metal between the ion source layer 116 and the top electrode 118, thereby mitigating the risk of leakage and / or CBRAM failure. In some embodiments, the barrier structure 114 may have a thickness 208 of less than about 7.5 nm, less than about 5.0 nm, less than about 4.0 nm, or other similar values.

[0042] Fig. 7B illustrates a cross-sectional view of an integrated chip 702 with a CBRAM device 108 having a barrier structure 114 disposed between a bottom electrode 110 and a bottom surface of a switching layer 112 facing the bottom electrode 110. Without the barrier structure 114, metal (e.g., metal atoms and / or metal ions) may thermally diffuse between the ion source layer 116 and the bottom electrode 110, thereby increasing leakage in the CBRAM device 108. The barrier structure 114 is designed to prevent thermal diffusion of metal between the ion source layer 116 and the bottom electrode 110, thereby reducing the risk of leakage and / or failure of the CBRAM device.

[0043] Fig. 7C illustrates a cross-sectional view of an integrated chip 704 with a CBRAM device 108 having a barrier structure 114 disposed between a bottom electrode 110 and a bottom surface of a switching layer 112 facing the bottom electrode 110. In some embodiments, a first additional barrier structure 706 is disposed between an top electrode 118 and an top surface of an ion source layer 116 facing the top electrode 118. The first additional barrier structure 706 is configured to contain thermal diffusion of metal (e.g., metal atoms and / or metal ions) between the ion source layer 116 and the top electrode 118.

[0044] Fig. 7D illustrates a cross-sectional view of an integrated chip 708 with a CBRAM device 108 having a barrier structure 114 disposed between a switching layer 112 and an ion source layer 116. In some embodiments, a first additional barrier structure 706 is disposed between the bottom electrode 110 and the switching layer 112. The first additional barrier structure 706 is configured to contain thermal diffusion of metal (e.g., metal atoms and / or metal ions) between the ion source layer 116 and the bottom electrode 110. In some embodiments, a second additional barrier structure 710 is disposed between the ion source layer 116 and the top electrode 118. The second additional barrier structure 114 is configured to contain thermal diffusion of metal between the ion source layer 116 and the top electrode 118.In some alternative embodiments (not shown), the integrated chip may include the barrier structure 114 between the switching layer 112 and the ion source layer 116, and the second additional barrier structure 710 between the ion source layer 116 and the top electrode 118, but no first additional barrier structure between the bottom electrode 110 and the switching layer 112. In some additional alternative embodiments, the integrated chip may include the barrier structure 114 between the switching layer 112 and the ion source layer 116, and the first additional barrier structure 706 between the bottom electrode 110 and the switching layer 112, but no second additional barrier structure between the ion source layer 116 and the top electrode 118.

[0045] In some embodiments, the barrier structure 114, the first additional barrier structure 706, and the second additional barrier structure 710 may comprise a metal nitride. In some embodiments, the barrier structure 114 may comprise a first metal nitride (e.g., aluminum nitride, silicon nitride, tungsten nitride, or the like) and the first additional barrier structure 706 and / or the second additional barrier structure 710 may comprise an additional metal nitride different from the first metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, or the like). In some embodiments, the barrier structure 114 and the first additional barrier structure 706 and / or the second additional barrier structure 710 may have a different nitrogen content.In some embodiments, the barrier structure 114 may have a different maximum nitrogen content than the first additional barrier structure 706 and / or the second additional barrier structure 710. For example, the barrier structure 114 may have a lower maximum nitrogen content than the first additional barrier structure 706 and / or the second additional barrier structure 710. In some embodiments, the barrier structure 114 has a first nitrogen-to-metal ratio, the first additional barrier structure 706 has a second nitrogen-to-metal ratio different from the first, and the second additional barrier structure 710 has a third nitrogen-to-metal ratio different from the first. In some embodiments, the first ratio is less than 1 and the second and / or third ratio is greater than 1.

[0046] In some embodiments, the barrier structure 114, the first additional barrier structure 706, and / or the second additional barrier structure 710 may comprise two-layer structures (e.g., structures with more than one layer). In some embodiments, the first additional barrier structure 706 may comprise a first layer closer to the bottom electrode and a second layer closer to the switching layer 112. In some embodiments, the first layer may have a lower resistivity than the second layer. In some embodiments, the second layer may comprise or be a nitride. In some embodiments, the second additional barrier structure 710 may comprise a third layer closer to the top electrode 118 and a fourth layer closer to the ion source layer 116.In some embodiments, the third layer may have a lower resistivity than the fourth layer. In some embodiments, the fourth layer may comprise or be a nitride.

[0047] The Fig. 8A and Fig. 8B illustrate some additional embodiments of an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion.

[0048] Fig. 8A illustrates a cross-sectional view 800 of an integrated chip including a CBRAM device 108 disposed in a dielectric structure 104 on a substrate 102. The CBRAM device 108 includes a switching layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. A barrier structure 114 is disposed between the switching layer 112 and the ion source layer 116.

[0049] Fig. 8A further illustrates a graph 802 showing the atomic percentage of various elements in the CBRAM device 108 as a function of a location in the CBRAM device 108 (along line AA' in the cross-sectional view 800). The graph 802 shows an atomic percentage of nitrogen 804, an atomic percentage of titanium 806, an atomic percentage of aluminum 808, an atomic percentage of tungsten 810, and an atomic percentage of oxygen 812 across a height of the CBRAM device 108. As shown in the graph 802, the atomic percentage of nitrogen 804 in the barrier structure 114 changes as a function of location. In some embodiments, the atomic percentage of nitrogen 804 in the barrier structure 114 is higher at a top surface facing the ion source layer 116 than at a bottom surface facing the switching layer 112.

[0050] In some embodiments, the atomic percentage of nitrogen 804 in the barrier structure 114 is higher than in the ion source layer 116. In some embodiments, the atomic percentage of nitrogen 804 in the barrier structure 114 may be at least about 40%, while the atomic percentage of nitrogen 804 in the ion source layer 116 may be less than about 40% and in the switching layer 112 may be less than about 10%, less than about 5%, or another similar value. In some embodiments, the barrier structure 114 has a maximum nitrogen content separated by a non-zero distance from a top and a bottom of the barrier structure 114. In some embodiments, the barrier structure 114 has a nitrogen content that is maximum between a top and a bottom of the barrier structure 114 and that is asymmetric about a center of the barrier structure 114.In some embodiments, the ratio of the atomic percentage of nitrogen 804 to the atomic percentage of aluminum 808 in the barrier structure 114 is less than 1.

[0051] Fig. 8B illustrates a cross-sectional view 814 of an integrated chip including a CBRAM device 108 disposed in a dielectric structure 104 on a substrate 102. The CBRAM device 108 includes a switching layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. A barrier structure 114 is disposed between the ion source layer 116 and the top electrode 118.

[0052] Fig. 8B further illustrates a graph 816 showing the atomic percentage of various elements in the CBRAM device 108 as a function of a location in the CBRAM device 108 (along line BB' in the cross-sectional view 814). The graph 816 shows an atomic percentage of nitrogen 818, an atomic percentage of titanium 820, and an atomic percentage of aluminum 822 across a height of the CBRAM device 108. As shown in the graph 816, the atomic percentage of nitrogen 818 in the barrier structure 114 changes as a function of location. In some embodiments, the atomic percentage of nitrogen 818 in the barrier structure 114 is higher at an interface with the top electrode 118 than at an interface with the ion source layer 116.In some embodiments, the atomic percentage of nitrogen 818 at the interface between the barrier structure 114 and the top electrode 118 is at least about 10% greater than at the interface between the barrier structure 114 and the ion source layer 116.

[0053] In some embodiments, the atomic percentage of nitrogen 818 in the barrier structure 114 is higher than in the top electrode 118 or the ion source layer 116. In some embodiments, the atomic percentage of nitrogen 818 in the barrier structure 114 may be higher than about 50%, while it may be less than about 50% in the top electrode 118 and less than about 20% in the ion source layer 116. In some embodiments, the ratio of the atomic percentage of nitrogen 818 to the atomic percentage of titanium 820 in the barrier structure 114 is greater than 1.

[0054] Fig. 9 illustrates a cross-sectional view of some additional embodiments of an integrated chip 900 including a CBRAM device with a disclosed barrier structure.

[0055] The integrated chip 900 includes a substrate 102 with an embedded memory region 902 and a logic region 904. A dielectric structure 104 is disposed on the substrate 102. The dielectric structure 104 includes a bottom ILD structure 104L comprising a plurality of bottom ILD layers 104a and 104b. In some embodiments, two or more adjacent ones of the plurality of bottom ILD layers 104a and 104b may be separated by an etch stop layer (not shown). In various embodiments, the etch stop layer may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0056] The embedded memory region 902 includes an access device 202 arranged on and / or in the substrate 102. The access device 202 is connected to a plurality of lower interconnects 106 arranged in a plurality of lower ILD layers 104a and 104b. A lower isolation structure 204 is arranged on the plurality of lower ILD layers 104a and 104b. In some embodiments, the lower isolation structure 204 may comprise two or more stacked dielectric layers 204a and 204b.

[0057] A bottom electrode via 206 extends through the bottom isolation structure 204 between one of the plurality of bottom interconnects 106 and a CBRAM device 108 lying on the bottom isolation structure 204. The CBRAM device 108 is arranged in an upper ILD structure 104U on the bottom isolation structure 204. In some embodiments, one or more sidewall spacers 602 are arranged on opposite sides of the CBRAM device 108. An etch stop layer 908 is arranged on the bottom isolation structure 204 and runs along opposite sides of the CBRAM device 108 and the one or more sidewall spacers 602. In some embodiments, a hard mask 906 may be arranged between the top electrode 118 and a bottom surface of the etch stop layer 908.

[0058] The logic region 904 includes a transistor device 910 arranged on and / or in the substrate 102. The transistor device 910 is connected to a plurality of interconnects 912-918 surrounded by the dielectric structure 104. In some embodiments, the plurality of interconnects 912-918 include a conductive contact 912 and a first interconnect trace 914 surrounded by the lower ILD structure 104L, and an interconnect via 916 and a second interconnect trace 918 surrounded by the upper ILD structure 104U. In some such embodiments, the interconnect via 916 is laterally separated from the CBRAM device 108, and the second interconnect trace 918 is laterally separated from the upper interconnect structure 120. In some embodiments, the plurality of interconnects 912 to 918 may comprise copper, tungsten, aluminum, and / or the like.

[0059] The Fig. 10 to 19 illustrate cross-sectional views 1000 to 1900 showing some embodiments of a method for forming an integrated chip structure including a CBRAM device with a barrier structure configured to reduce thermal diffusion of metal. Fig. Although paragraphs 10 to 19 are described with regard to a method, it is understood that the Fig. 10 to 19 are not limited to such a process, but can exist as structures independent of the process.

[0060] As shown in the cross-sectional view 1000 of Fig. 10, a substrate 102 is provided. In various embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith.

[0061] In some embodiments, one or more of the lower interconnects 106 may be formed in a lower ILD structure 104L formed on the substrate 102. In some embodiments, the one or more interconnects 106 may include a conductive contact, an interconnect trace, and / or an interconnect via. The one or more lower interconnects 106 may be formed by forming the lower ILD structure 104L on the substrate 102, selectively etching the lower ILD structure 104L to define a hole and / or trench, forming a conductive material (e.g., copper, aluminum, etc.) in the hole and / or trench, and performing a planarization process (e.g., chemical mechanical) to remove excess conductive material on the lower ILD structure 104L.

[0062] As shown in cross-sectional view 1100 in Fig. 11, a lower isolation structure 204 is formed on the lower ILD structure 104L. In some embodiments, the lower isolation structure 204 may comprise a plurality of superimposed dielectric layers 204a and 204b. In some embodiments, the lower isolation structure 204 may comprise, for example, a first dielectric layer 204a and a second dielectric layer 204b on top of the first dielectric layer 204a. In some embodiments, the first dielectric layer 204a may comprise silicon-rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, the second dielectric layer 204b may comprise silicon carbide, silicon nitride, or the like. In some embodiments, the lower isolation structure 204 may be formed by one or more deposition processes (e.g.,a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PE-CVD) process, or the like).

[0063] As shown in the cross-sectional view 1200 in Fig. 12, the lower insulating structure 204 is selectively patterned to form an opening 1202 extending through the lower insulating structure 204 and exposing a top surface of the plurality of lower interconnects 106. Thereafter, one or more conductive materials 1204-1206 are formed in the opening 1202 and on a top surface of the lower insulating structure 204. In some embodiments, the one or more conductive materials 1204-1206 may include a diffusion barrier layer 1204 and a metal layer 1206 on the diffusion barrier layer 1204. In some embodiments, the diffusion barrier layer 1204 and the metal layer 1206 may be formed via deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like).

[0064] As shown in the cross-sectional view 1300 in Fig. 13, parts of the one or more conductive materials (1204 to 1206 in Fig. 12) is removed so that a bottom electrode via 206 is formed with a barrier layer 206a and a conductive core 206b surrounded by the barrier layer 206a. In some embodiments, the portions of the one or more conductive materials (1204 to 1206 in Fig. 12) using a planarization process (e.g., a chemical mechanical planarization (CMP) process) in which an excess of the one or more conductive materials (1204 to 1206 in Fig. 12) on the lower insulating structure 204 along line 1302. In other embodiments, the portions of the one or more conductive materials (1204 to 1206 in Fig. 12) using an etch-back process.

[0065] As shown in the cross-sectional view 1400 in Fig. 14, a CBRAM stack 1401 is formed on the lower isolation structure 204 and the lower electrode via 206. In some embodiments, the CBRAM stack 1401 includes a bottom electrode layer 1402, a switching interlayer 1404 on the bottom electrode layer 1402, a barrier interlayer 1406 on the switching interlayer 1404, an ion source interlayer 1408 on the barrier interlayer 1406, and a top electrode layer 1410 on the ion source interlayer 1408. In some embodiments, the bottom electrode layer 1402, the switching interlayer 1404, the barrier interlayer 1406, the ion source interlayer 1408, and the top electrode layer 1410 may be formed via deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like).

[0066] In other embodiments (not shown), the CBRAM stack 1401 includes a bottom electrode layer, a switching interlayer on the bottom electrode layer, an ion source interlayer 1408 on the switching interlayer, a barrier interlayer on the ion source layer, and a top electrode layer on the barrier interlayer. In further embodiments (not shown), the CBRAM stack 1401 includes a bottom electrode layer, a barrier interlayer on the bottom electrode layer, a switching interlayer 1404 on the barrier interlayer, an ion source interlayer on the switching interlayer, and a top electrode layer on the ion source interlayer. In further embodiments, the CBRAM stack 1401 may include any combination of the above CBRAM stacks (e.g., barrier interlayers at two or more of the locations disclosed above).

[0067] In some embodiments, the bottom electrode layer 1402 and / or the top electrode layer 1410 may comprise a metal such as titanium, tantalum, titanium nitride, tantalum nitride, or the like. In some embodiments, the switching interlayer 1404 may comprise an oxide, a nitride, or the like. In some embodiments, the switching interlayer 1404 may comprise, for example, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon oxide, or the like. In some embodiments, the barrier interlayer 1406 comprises a metal nitride. In various embodiments, the barrier interlayer 1406 may comprise, for example, titanium nitride, amorphous titanium nitride, tantalum nitride, tungsten nitride, silicon nitride, aluminum nitride, tungsten nitride, or the like. In some embodiments, the ion source interlayer 1408 may comprise copper, silver, aluminum, or the like.In some embodiments, the ion source intermediate layer 1408 may comprise cobalt, iron, boron, nickel, ruthenium, iridium, platinum, or the like.

[0068] As shown in the cross-sectional view 1500 in Fig. As shown in Figure 15, a mask 1502 is formed on the CBRAM stack 1401 and directly over the bottom electrode via 206. In some embodiments, the mask 1502 may include a photosensitive material (e.g., photoresist). In some embodiments, the photosensitive material may be applied using a spin-coating process. In other embodiments, the mask 1502 may include a hard mask (e.g., titanium, titanium nitride, tantalum, silicon nitride, silicon carbide, etc.).

[0069] As shown in the cross-sectional view 1600 in Fig. 16 is used for the targeted structuring of the CBRAM stack (1401 in Fig. 15), an etching process is performed corresponding to the mask 1502 to form a CBRAM device 108. In some embodiments, the CBRAM device 108 includes a switching layer 112, a barrier structure 114, and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118. In some embodiments, the patterning process of the mask 1502 selectively exposes the CBRAM stack to a first etchant 1602. In some embodiments, the first etchant 1602 may include a dry etchant (e.g., with a fluorine- or chlorine-based etch chemistry).

[0070] As shown in the cross-sectional view 1700 in Fig. As shown in Figure 17, a top ILD structure 104U is formed on the CBRAM device 108. In some embodiments, the top ILD structure 104U may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In some embodiments, the top ILD structure 104U may comprise a nitride, a carbide, an oxide, or the like.

[0071] An upper interconnect structure 120 is formed in the upper ILD structure 104U. In some embodiments, the upper interconnect structure 120 may be formed by performing a patterning process in which one or more openings 1702 (e.g., a via hole and / or trench) are formed in the upper ILD structure 104U. The one or more openings 1702 extend through the upper ILD structure 104U, thus exposing the upper electrode 118. One or more conductive materials are disposed in the one or more openings 1702. Thereafter, a planarization process (e.g., a CMP process) is performed to remove excess of the one or more conductive materials and to form the upper interconnect structure 120 in the upper ILD structure 104U. In some embodiments, the one or more conductive materials may include aluminum, copper, tungsten, or the like.

[0072] As shown in the cross-sectional view 1800 in Fig. 18, a high-temperature process 1802 (e.g., at a temperature of at least about 300°C, at least about 400°C, greater than about 500°C, at least about 750°C, or other similar values) is performed. In some embodiments, a high-temperature process 1802 may be performed for a period of time that is at least about 30 minutes, at least about 60 minutes, about 60 minutes, or other similar values. The barrier structure 114 is configured to contain the thermal diffusion of metal (e.g., metal ions) from the ion source layer 116 into the switching layer 112 during the high-temperature process 1802, thereby containing undesirable creepage between the ion source layer 116 and the switching layer 112.In some embodiments, a high-temperature process 1802 may include a manufacturing process used in the fabrication of a BEOL interconnect, a far-back-end-of-the-line (FBEOL) structure, or the like. In some embodiments, the high-temperature process may include a bonding process, a reliability test process, a solder contact process, or other similar processes. In some embodiments, the high-temperature process 1802 may be performed after forming a passivation layer on a bond pad configured to bond an integrated chip to an external integrated chip structure (e.g., another die, a circuit board, a package, or the like).

[0073] As shown in the cross-sectional view 1900 in Fig. 19, a formation process is performed on the CBRAM device 108. During the formation process, a first conductive filament 210 is formed in the barrier structure 114 and a second conductive filament 302 is formed in the switching layer 112. In some embodiments, the formation process may be performed by applying a bias voltage to the CBRAM device 108. The bias voltage may be higher than a bias voltage applied to the CBRAM device 108 during the set and / or reset operation.

[0074] Fig. 20 illustrates a flow diagram for some embodiments of a method 2000 for forming an integrated chip structure including a CBRAM device with a barrier structure configured to reduce metal diffusion.

[0075] While the method 2000 is illustrated and described herein as a series of steps or acts, it should be understood that the illustrated order of such steps or acts is not intended to be limiting. Thus, some steps may be performed in a different order and / or concurrently with other steps or acts than those illustrated and / or described herein. Furthermore, not all of the illustrated steps may be required to practice one or more aspects or embodiments of the present description. Moreover, one or more of the steps illustrated herein may be performed in one or more separate steps and / or stages.

[0076] At 2002, a lower interconnect is formed in a lower ILD structure on a substrate. Fig. 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to step 2002.

[0077] At 2004, a lower isolation structure is formed on the lower interconnect and the lower ILD structure 104. Fig. 11 illustrates a cross-sectional view 1100 of some embodiments corresponding to step 2004.

[0078] At 2006, a lower electrode via is formed in the lower insulation structure. Fig. 12 and Fig. 13 illustrate cross-sectional views 1200 and 1300 of some embodiments corresponding to step 2006.

[0079] At 2008, a CBRAM stack is formed on the bottom electrode via, comprising an intermediate barrier structure between a top and a bottom electrode layer. Fig. 14 illustrates a cross-sectional view 1400 of some embodiments corresponding to step 2008. In some embodiments, the CBRAM stack may be formed according to steps 2010 through 2018.

[0080] At 2010, a lower electrode layer is formed on the lower electrode via.

[0081] At 2012, a switching intermediate layer is formed on the lower electrode layer.

[0082] At 2014, a barrier intermediate structure is formed on the switching intermediate layer.

[0083] At 2016, an ion source intermediate layer is formed on the barrier intermediate structure.

[0084] At 2018, an upper electrode layer is formed on the ion source intermediate layer.

[0085] At 2020, the CBRAM stack is patterned to form a CBRAM device. The CBRAM device includes a barrier structure disposed between a bottom and a top electrode. The Fig. 15 to 16 illustrate cross-sectional views 1500 to 1600 of some embodiments corresponding to step 2020.

[0086] At 2022, an upper interconnect structure is formed in an upper ILD structure formed on the CBRAM device. Fig. 17 illustrates a cross-sectional view 1700 of some embodiments corresponding to step 2022.

[0087] At 2024, a high-temperature process is performed. In some embodiments, the high-temperature process may include a manufacturing process performed at a temperature greater than about 400°C. Fig. 18 illustrates a cross-sectional view 1800 of some embodiments corresponding to step 2024.

[0088] At 2026, conductive filaments (e.g. conductive bridges) are formed in the barrier structure and the switching layer. Fig. 19 illustrates a cross-sectional view 1900 of some embodiments corresponding to step 2026.

[0089] Accordingly, in some embodiments, the present disclosure relates to an integrated chip structure comprising a conductive bridging random access memory (CBRAM) device having a barrier structure configured to reduce thermal diffusion of metal (e.g., metal ions) caused by high-temperature manufacturing processes.

[0090] In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure comprises: a bottom electrode arranged in a dielectric structure on a substrate, an top electrode arranged in the dielectric structure on the bottom electrode, a switching layer between the bottom electrode and the top electrode, an ion source layer arranged between the bottom electrode and the top electrode, and a barrier structure arranged between the bottom electrode and the top electrode, wherein the barrier structure comprises a metal nitride configured to restrict thermal diffusion of metal during a high-temperature manufacturing process. In some embodiments, the barrier structure is arranged between the switching layer and the ion source layer.In some embodiments, the integrated chip structure further comprises: a first additional barrier structure arranged between a bottom surface of the switching layer and a top surface of the bottom electrode, and a second additional barrier structure arranged between a top surface of the ion source layer and a bottom surface of the top electrode. In some embodiments, the barrier structure has a nitrogen content gradient that continuously changes between a first nitrogen content at a bottom surface of the barrier structure and a second nitrogen content at an top surface of the barrier structure, wherein the second nitrogen content is higher than the first. In some embodiments, the barrier structure has a maximum nitrogen content separated by a non-zero distance from the top surface and the bottom surface of the barrier structure.In some embodiments, the barrier structure comprises a first barrier layer having a first nitrogen content on a lower surface and a second barrier layer having a second nitrogen content on an upper surface, wherein the second nitrogen content is discontinuous with the first nitrogen content. In some embodiments, the barrier structure comprises titanium nitride, tantalum nitride, aluminum nitride, silicon nitride, or tungsten nitride. In some embodiments, the barrier structure is arranged between a top surface of the ion source layer and a bottom surface of the top electrode. In some embodiments, the integrated chip structure further comprises an additional barrier structure having an additional metal nitride arranged between the ion source layer and the top electrode, wherein the barrier structure and the additional barrier structure have different nitrogen contents.

[0091] In other embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure comprises: a conductive bridging random access memory (CBRAM) device disposed on a substrate, the CBRAM device comprising: a switching layer disposed between first and second electrodes, an ion source layer disposed between the switching layer and the second electrode, and a barrier structure disposed between the switching layer and the ion source layer, the barrier structure configured to contain thermal diffusion of metal between the switching layer and the ion source layer.In some embodiments, a first conductive filament extends through the barrier structure when storing a first and a second data state, and a second conductive filament is configured to extend through the switching layer when storing the first data state but not when storing the second data state. In some embodiments, the barrier structure has a nitrogen to aluminum ratio between about 40% and about 70%. In some embodiments, the barrier structure has a nitrogen content that is maximum between a top and a bottom of the barrier structure and that is asymmetric about a center of the barrier structure.In some embodiments, the integrated chip structure further comprises a first additional barrier structure disposed between a bottom surface of the switching layer and a top surface of the first electrode, the barrier structure having a first nitrogen to metal ratio that is less than 1, and the first additional barrier structure having a second nitrogen to metal ratio that is greater than 1. In some embodiments, the barrier structure comprises silicon nitride, aluminum nitride, or tungsten nitride. In some embodiments, the barrier structure has a thickness that is less than about 5.0 nm. In some embodiments, the barrier structure comprises a first barrier layer having a first nitrogen content gradient and a second barrier layer having a second nitrogen content gradient that is discontinuous with the first nitrogen content gradient.In some embodiments, the barrier structure has a first non-zero atomic percentage of nitrogen that is greater than about 50%, and the ion source layer has a second non-zero atomic percentage of nitrogen that is less than about 20%.

[0092] In further embodiments, the present disclosure relates to a method of forming an integrated chip structure. The method includes forming a bottom interconnect in a bottom interlayer dielectric (ILD) structure on a substrate, forming a conductive bridging random access memory (CBRAM) stack on the bottom ILD structure and the bottom interconnect, patterning the CBRAM stack according to a mask to form a CBRAM device having a switching layer and an ion source layer between first and second electrodes, wherein a barrier structure is also arranged between the first and second electrodes, and forming a top interconnect in an top ILD structure on the CBRAM device, wherein the top interconnect is connected to the second electrode.In some embodiments, the method further comprises, after patterning the CBRAM stack, performing a high-temperature process at a temperature of more than 400°C, wherein the barrier structure is configured to restrict thermal diffusion of metal ions from the ion source layer into the switching layer during the high-temperature process.

Claims

[1] Integrated chip structure comprising: a lower electrode arranged in a dielectric structure on a substrate; an upper electrode disposed in the dielectric structure above the lower electrode; a switching layer between the lower electrode and the upper electrode; an ion source layer disposed between the lower electrode and the upper electrode; and a barrier structure arranged between the lower electrode and the upper electrode, wherein the barrier structure contains a metal nitride configured to restrict thermal diffusion of metal during a high-temperature manufacturing process, wherein the barrier structure has a first non-zero atomic percent of nitrogen of greater than about 50%, and the ion source layer has a second non-zero atomic percent of nitrogen of less than about 20%. [2] The integrated chip structure according to claim 1, wherein the barrier structure is arranged between the switching layer and the ion source layer. [3] Integrated chip structure according to claim 1 or 2, further comprising: a first additional barrier structure arranged between a bottom side of the switching layer and a top side of the lower electrode; and a second additional barrier structure arranged between a top surface of the ion source layer and a bottom surface of the upper electrode. [4] The integrated chip structure according to any one of claims 1 to 3, wherein the barrier structure has a nitrogen content gradient that continuously changes between a first nitrogen content at a lower surface of the barrier structure and a second nitrogen content at an upper surface of the barrier structure, the second nitrogen content being higher than the first nitrogen content. [5] The integrated chip structure of claim 4, wherein the barrier structure has a maximum nitrogen content separated by a non-zero distance from the top surface and the bottom surface of the barrier structure. [6] The integrated chip structure of any one of claims 1 to 3, wherein the barrier structure comprises a first barrier layer having a first nitrogen content at a lower surface of the barrier structure and a second barrier layer having a second nitrogen content at an upper surface of the barrier structure, the second nitrogen content being discontinuous with the first nitrogen content. [7] Integrated chip structure according to one of claims 1 to 6, wherein the barrier structure contains titanium nitride, tantalum nitride, aluminum nitride, silicon nitride or tungsten nitride. [8] The integrated chip structure according to any one of claims 1 to 7, wherein the barrier structure is arranged between a top surface of the ion source layer and a bottom surface of the upper electrode. [9] Integrated chip structure according to one of claims 1 to 8, further comprising: an additional barrier structure containing an additional metal nitride arranged between the ion source layer and the upper electrode, wherein the barrier structure and the additional barrier structure have different nitrogen contents. [10] Integrated chip structure comprising: a CBRAM device arranged on a substrate, wherein the CBRAM device comprises: - a switching layer arranged between a first electrode and a second electrode; - an ion source layer arranged between the switching layer and the second electrode; and - a barrier structure arranged between the switching layer and the ion source layer, wherein the barrier structure is configured to restrict thermal diffusion of metal between the switching layer and the ion source layer, wherein the barrier structure has a first non-zero atomic percent of nitrogen of greater than about 50%, and the ion source layer has a second non-zero atomic percent of nitrogen of less than about 20%. [11] The integrated chip structure of claim 10, wherein a first conductive filament extends through the barrier structure while storing a first data state and a second data state, wherein a second conductive filament is configured to extend through the switching layer during storage of the first data state, but not during storage of the second data state. [12] The integrated chip structure of claim 10 or 11, wherein the barrier structure has a nitrogen to aluminum ratio of about 40% to about 70%. [13] The integrated chip structure according to any one of claims 10 to 12, wherein the barrier structure has a nitrogen content whose maximum lies between a top and a bottom of the barrier structure and which is asymmetric about a center of the barrier structure. [14] Integrated chip structure according to one of claims 10 to 13, further comprising: a first additional barrier structure arranged between a bottom side of the switching layer and a top side of the first electrode, wherein the barrier structure has a first nitrogen to metal ratio that is less than 1, and the first additional barrier structure has a second nitrogen to metal ratio that is greater than 1. [15] Integrated chip structure according to one of claims 10 to 14, wherein the barrier structure contains silicon nitride, aluminum nitride or tungsten nitride. [16] The integrated chip structure of any one of claims 10 to 15, wherein the barrier structure has a thickness of less than about 5.0 nm. [17] The integrated chip structure of any one of claims 10 to 16, wherein the barrier structure comprises a first barrier layer having a first nitrogen content gradient and a second barrier layer having a second nitrogen content gradient that is discontinuous with the first nitrogen content gradient. [18] A method of forming an integrated chip structure, comprising: Forming a bottom interconnect in a bottom ILD structure on a substrate; Forming a CBRAM stack on the lower ILD structure and the lower interconnect; Patterning the CBRAM stack according to a mask to define a CBRAM device comprising a switching layer and an ion source layer between a first electrode and a second electrode, further comprising a barrier structure disposed between the first electrode and the second electrode; and Forming an upper interconnect in an upper ILD structure on the CBRAM device, wherein the upper interconnect is coupled to the second electrode, wherein the barrier structure has a first non-zero atomic percent of nitrogen of greater than about 50%, and the ion source layer has a second non-zero atomic percent of nitrogen of less than about 20%. [19] The method of claim 18, further comprising: after patterning the CBRAM stack, performing a high-temperature process at a temperature of more than about 400 °C, wherein the barrier structure is configured to restrict thermal diffusion of metal ions from the ion source layer into the switching layer during the high-temperature process.

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