TRANSMISSION OF ADMINISTRATIVE TRAFFIC BETWEEN BASEBOARD MANAGEMENT CONTROLLERS AND NETWORK INTERFACE CONTROLLERS

Abstract

One process involves a bridge port supplying a reference clock signal to the first end of an intermediate link extending between the first port and a network interface controller. The reference clock signal propagates along the intermediate link to provide a delayed reference clock signal to the network interface controller at a second end of the intermediate link. As part of the process, the bridge detects the timing of the delayed reference clock signal. The process includes management traffic communication between a network interface of a baseboard management controller and the network interface controller over the intermediate link. This management traffic communication involves the port synchronizing data communication with the first end of the link to the delayed reference clock signal in response to its detection of the timing.

Description

BACKGROUND

[0001] A computing platform (such as a server) may contain a specialized service processor called a baseboard management controller, or BMC, which is used to monitor and manage the platform. As part of this monitoring and management, the BMC may oversee one or more of the computing platform's network interface controllers (also called network interface cards), or NICs. A NIC provides network connectivity for the computing platform's components. Computer technology is constantly evolving, and newer computing platforms may feature intelligent NICs. In addition to providing network connections, an intelligent NIC can also offload processing traditionally performed by general-purpose central processing units (CPUs) on older computing platforms.

[0002] From US 2018 / 0 239 730 A1 a method is known, wherein in the network interface controller a path is established between the host interface and the BMC via the sideband interface of the network interface controller in order to route data selectively between the management network and either the host central unit and the or internally in the network interface controller.

[0003] US 2016 / 0 323 148 A1 describes systems and methods that can be implemented using memory as a common interface between a BMC and a network controller of an information processing system (e.g., a server) to achieve a relatively high-speed data path between a network and the management controller without requiring the use and / or presence of a physical high-speed connection to and / or from a sideband interface of the network controller.

[0004] US 2017 / 0 359 139 A1 relates to a bridge element for establishing clock synchronization between network elements, including a first network element using a first clock synchronization transport protocol and a second network element using a second clock synchronization transport protocol that is different from the first clock synchronization transport protocol, and from US 4 831 338 A a synchronizing clock signal generator is known which, in combination with a PLL circuit, comprises a signal delay circuit for delaying a reference input signal by a prescribed time and outputting a reference signal, and a shift register which receives the reference input signal and a clock signal to output a comparison signal synchronously with a clock signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a schematic diagram of a computer platform having a sideband communication bridge for communicating sideband management traffic between a baseboard management controller (BMC) and network interface controllers (NICs), according to an example implementation. Fig. is a schematic representation of the sideband communication bridge of Fig. according to an embodiment. Fig. is a schematic diagram of the first-in-first-out (FIFO) buffers of the sideband communication bridge port interfaces according to an example implementation. Fig. is a schematic diagram of the sideband communication bridge circuit to delay the communication of arbitration signals according to an example implementation. Fig. is a flowchart showing a process for communicating management traffic between a BMC and a network interface controller according to an example implementation. Fig. is a schematic diagram of a bridge for communicating with a system management controller and a network interface controller according to an example implementation. Fig. is a schematic diagram of a computing platform including network interface controllers, a BMC, and a bridge for communicating management traffic between the network interface controllers and the BMC, according to an example implementation. DETAILED DESCRIPTION

[0005] Examples of tasks a BMC can perform for a computing platform include powering on the computing platform, powering off the computing platform, monitoring sensors (e.g., temperature sensors, fan speed sensors), monitoring the operating system status, monitoring the power status, logging events on the computing platform, controlling boot paths, controlling the use of virtual media, controlling security checks, updating firmware, validating software, validating hardware, enabling boot functionality, performing recovery operations after an operating system failure or other catastrophic error, and so on. The BMC can provide management functions that can be controlled by a remote management server.In addition, the BMC can be powered independently of other parts of the computing platform, allowing the remote management server to manage operations for the computing platform even when other subsystems of the computing platform are powered off.

[0006] The BMC can manage computing platform peripherals, such as network interface controllers (NICs). A NIC provides network connectivity for computing platform components. The NIC can communicate with the computing platform components through an in-band main connection, and the NIC can be connected to the network fabric (switches, gateways, etc.) through network cabling (e.g., an Ethernet cable). In this context, an "in-band connection" (also called an "inline connection") refers to a main communication interface for the NIC, such as a Peripheral Component Interconnect Express (PCIe) connection or an Open Compute (OCP) interface.

[0007] The NIC can be a "smart NIC," meaning that in addition to network connectivity, the NIC also provides backend input / output (I / O) services for the computing platform. I / O services can include, for example, network virtualization services (e.g., overlay network services, virtual switching services, virtual routing services, and network function virtualization services), network storage services, network monitoring services, storage acceleration services (e.g., NVMe-based services), security services (e.g., cryptography services and network firewall services), and so on.

[0008] The BMC can be mounted on a computer platform's motherboard, and for the purpose of managing a network card, the BMC can be connected to the network card via a sideband connection. The term "sideband connection" refers to a secondary, restricted-access communication interface for the NIC that is separate from the NIC's in-band connection and used for a specific purpose. The specific purpose can be, for example, the transfer of management data or traffic between the NIC and the BMC. The BMC can communicate management data with a specific NIC for a variety of different purposes, such as:monitoring NIC events, monitoring NIC sensors, configuring the NIC, turning off the NIC, turning on the NIC, updating the NIC firmware, performing an integrity test on the NIC software, validating the NIC software, validating the NIC hardware, setting a boot path for the NIC, performing a recovery operation on the NIC, and so on.

[0009] The sideband connection for a particular NIC can take one of many different possible forms. For example, the sideband connection can be a wired connection (e.g., a connection using a cable), or the sideband connection can be wireless (e.g., consisting of traces on the motherboard). As a more specific example, the BMC can communicate management traffic with a particular NIC using a multi-conductor ribbon cable or a ribbon cable that connects (at one end of the cable) to a corresponding connector on the NIC and (at the other end of the cable) to a connector on the computer platform's motherboard.Another example is that the BMC may communicate management traffic with a particular NIC via electrically conductive traces formed on or in a multilayer motherboard circuit substrate, where these traces may, for example, be connected to terminals of a connector for the NIC.

[0010] The sideband link can enable full-duplex communication between its two endpoints (or "ends"). To this end, the sideband link carries a clock signal; one or more data signals corresponding to a first channel for communication in one direction over the link; and one or more data signals corresponding to a second channel for communication over the link in the other direction. The communication of the sideband link's data signals can be synchronized with active edges of the clock signal. Here, the "active edge" (or "active clock edge") refers to a specific clock edge, such as a positive or rising edge of the clock signal.

[0011] As a more specific example, a transmitter at one end of the sideband connection can change the states of the data signals of a channel (corresponding to a sequence of data bits) synchronously with the rising edges of the clock signal (i.e., the rising edge is the "active clock edge"). To transmit a specific data bit, for example, the transmitter can drive the data signal to the logic level corresponding to the data bit, and the driving of the data signal is triggered by the active clock edge. Therefore, to transmit a sequence of data bits, the transmitter drives the data signal in response to temporally successive active clock edges. The receiver at the other end of the sideband connection captures the data bits of the channel synchronously with the active clock edges. To receive a specific data bit, the receiver samples the data bit signal, and this sampling is triggered by an active clock edge.To receive a sequence of data bits, the receiver therefore samples the data signal in response to successive active clock edges.

[0012] Due to signal propagation delays introduced by the sideband connection, the clock and data signals at one end of the sideband connection may be delayed relative to the clock and data signals at the other end of the sideband connection. Because the rate at which the logic levels of the data bits change may differ from the clock frequency, the delay for a given data signal may be different from the delay for the clock signal. If this is ignored, the signal propagation delays can lead to metastability problems in data transmission, causing receivers to detect incorrect data bits.

[0013] To avoid metastability problems, a standard for the sideband link may specify timing metrics that define limits on the timing relationship between the data signal and the active clock edge. For example, the timing metrics may include a minimum setup time and a minimum hold time that specify a minimum time window of stability for the data signal around the active clock edge. The minimum setup time refers to a minimum time that the data signal must be stable before the active clock edge, and the minimum hold time refers to a minimum time that the data signal must be stable after the active clock edge. As further described herein, a first endpoint at one end of a sideband link synchronizes its communication with the sideband link with a clock signal appearing at a second endpoint at the other end of the sideband link.According to example implementations, this synchronization provides the advantage of maximizing the time required for a data signal transmitted over the sideband connection to stabilize before the data signal is detected by the first or second endpoint (depending on the transmission direction).

[0014] Due to the signal propagation delays caused by the sideband connection, timing metric violations may occur if appropriate compensation is not provided. For example, a data signal arriving at the receiver may be so distorted (relative to the clock signal) that the data signal is not stable for the minimum setup time before the active clock edge. For a specific sideband connection, measures can be taken to resolve timing metric violations. For example, a delay can be added to the clock signal for a specific sideband connection to resolve minimum setup time violations.

[0015] The sideband connection can carry signals based on the Reduced Media Independent Interface (RMII) specification published by the RMII Interface Consortium (1997), according to example implementations. In addition, according to some implementations, the BMC can communicate with multiple NICs of the computing platform over multiple sideband connections. In these example implementations, the communication of signals over the sideband connections can be based on the Network Controller-Sideband Interface (NC-SI) specification published by the Distributed Management Task Force (2009). The NC-SI specification is based on the RMII specification and includes modifications (such as the addition of arbitration signaling and a protocol) to support communication between a single BMC and multiple NICs.

[0016] The computing platform may have multiple NICs, and the physical characteristics of the sideband connections for the NICs may vary. For example, a sideband connection for one NIC may be a cable-based connection; a sideband connection for another NIC may be a non-cable, printed circuit board-based connection; cable-based sideband connections for different NICs may have different physical lengths; printed circuit board-based sideband connections may have different lengths, and so on. Furthermore, for a given computing platform, different NICs from different manufacturers and with sideband connections with different physical characteristics may be installed in the computing platform during the lifetime of the platform.Due to these differences in the physical properties of the sideband links, the signal propagation characteristics between the sideband links may be so different that measures taken to meet the timing metrics for one sideband link may not be sufficient to meet the timing metrics for another sideband link.

[0017] According to the example implementations described herein, a computing platform (e.g., a server such as a blade server) includes a sideband communication bridge that transmits management traffic between a BMC and multiple NICs in a manner that allows for sideband connections with different physical characteristics. In particular, according to example implementations, the NICs and the BMC may be connected to different respective ports of the sideband communication bridge. According to example implementations, the BMC may transmit management traffic to the NICs via the sideband communication bridge over the transmit channels of the sideband connections. In addition, the NICs may (individually) transmit management data to the BMC via receive channels of the sideband connections over the sideband communication bridge.

[0018] According to example implementations, each NIC can communicate with a NIC port of the sideband communication bridge over an associated sideband link. According to example implementations, the sideband communication bridge synchronizes data communication between each NIC port and the associated sideband link to adapt to the physical characteristics of the sideband link and to meet timing metrics. Data communication synchronization in this context refers to the NIC port synchronizing the transmission of data signals to the sideband link synchronously with the active edges of a customized clock signal (also referred to herein as a "feedback clock signal"). Data communication synchronization further includes the NIC port synchronizing the reception of data signals from the sideband link synchronously with active edges of the customized clock signal.The timing of the adjusted clock signals (or "feedback clock signals") can vary between NIC ports, as described here, to account for variations in the physical properties of the sideband connections.

[0019] Specifically, according to example implementations, the NIC ports of the sideband communication bridge may provide reference clock signals (i.e., a set of synchronized clock signals) to the NIC port ends (or "endpoints") of the associated sideband links. Each reference clock signal propagates across the sideband link and is received by the associated NIC at the other end of the sideband link. The sideband link introduces a propagation delay for the reference clock signal such that the version of the reference clock signal (referred to herein as a "delayed reference clock signal") received at the NIC end of the sideband link is delayed relative to the reference clock signal provided to the NIC port end of the sideband link.According to example implementations, the NIC synchronizes its data communication with the sideband interconnect with active edges of the delayed reference clock signal, and the NIC port of the sideband communication bridge also synchronizes its data communication with the sideband interconnect with the active edges of the delayed reference clock signal. In other words, according to example implementations, each NIC port outputs data signals to the sideband interconnect synchronously with the active edges of the delayed reference clock signal (i.e., the clock signal received by the NIC), and each NIC port receives data signals from the sideband interconnect synchronously with the active edges of the delayed reference clock signal.

[0020] According to example implementations, the sideband communication bridge captures the delayed reference clock signals to provide corresponding feedback clock signals that are replicas or near replicas of the corresponding delayed reference clock signals. Furthermore, according to example implementations, each NIC port synchronizes data communication with the sideband connection with the active edges of the associated feedback clock signal. Therefore, according to example implementations, the sideband communication bridge aligns the timing of the active edges of the clock signal at the NIC port end of the sideband connection with the timing of the active clock edge at the NIC end of the sideband connection.According to example implementations, due to the adjustment of the clock signals at the opposite ends of the sideband link, the data signals at the receiving end of the link are given maximum time to stabilize before the states of the data signals are captured.

[0021] In accordance with some implementations, the sideband interconnect includes two clock communication lines: a first clock communication line to convey the reference clock signal to the NIC, and a second clock communication line (referred to herein as the "clock feedback path") to provide a feedback clock signal to the sideband communication bridge. The first clock communication line has a first end at the NIC port (for receiving the reference clock signal) and a second end at the NIC (for providing the delayed reference clock signal). Unlike the first clock communication line, the clock feedback path loops so that both ends of the clock feedback path terminate at the NIC port. The sideband communication bridge provides the reference clock signal to one end of the clock feedback path.The clock feedback path has a physical length close to or equal to the physical length of the first clock communication line, and the reference clock signal propagates across the clock feedback path to provide a feedback clock signal at the other end of the clock feedback path that is identical to, or at least close to, the delayed reference clock signal received by the NIC. Therefore, according to example implementations, both the NIC port and the NIC effectively synchronize their respective communications with the sideband connection to the same clock signal for a particular sideband connection.

[0022] Referring to Fig. As a more specific example, in accordance with some implementations, a computing platform 100 may include a host 102 and a BMC 130 that manages the host 102. In accordance with at least some implementations, the host 102 may include one or more NICs 134. A blade server is an example of a computing platform 100 according to one example implementation. However, the computing platform 100 may be a platform other than a blade server, such as a rack server, a client, a desktop computer, a smartphone, a laptop computer, a tablet computer, and so on, according to further implementations. The NICs 134 may be one or more of the following NICs, as well as other NICs, according to example implementations: a smart NIC, a non-smart NIC, a PCIe card-based NIC, or an Open Compute Project (OCP) card-based NIC.

[0023] Regardless of the particular form of the computing platform 100, the host 102, in accordance with example implementations, may include components that can generally provide one or more operating system instances (e.g., operating system instances as part of virtual machines and non-virtual machine-based operating system instances). As an example, in accordance with some implementations, the host 102 may include actual physical hardware, such as hardware processors or hardware processing cores 120 (e.g., CPU cores, GPU cores, etc.), system memory 128, bus infrastructure, I / O devices, etc. In addition to the hardware components, the host 102, in accordance with example implementations, may include software components, i.e., components formed in whole or in part from one or more processing cores 120 that execute machine-executable instructions (or "software"). In Fig. Example software components are shown, such as an operating system 145 and applications 144.

[0024] According to example implementations, the software components may be formed by one or more compute cores 120 that execute machine-executable instructions 124 stored in a system memory 128 of the computing platform 100. Furthermore, the execution of the instructions 124 may include storing data 125 in the system memory 128. According to example implementations, the system memory 128 and other memories discussed herein are non-transitory storage media, which may be formed from semiconductor memory devices, memristor-based memory devices, magnetic memory devices, phase-change memory devices, a combination of devices from one or more of these memory technologies, etc. The system memory 128 may be comprised of both volatile and non-volatile memory devices.

[0025] In accordance with example implementations, the computing platform 100 may be one of a plurality of computing resources 190 that are part of a cloud computing system. In these example implementations, the computing platform 100 may have a cloud-centric architecture, and one or more NICs 134 may be intelligent NICs. For example, the intelligent NICs may provide various I / O services to the software of the computing platform 100, such as network virtualization services (e.g., overlay network services, virtual switch services, virtual routing services, and network function virtualization services), network storage services, network monitoring services, storage acceleration services, security services (e.g., cryptography services and network firewall services), etc. In accordance with some implementations, the compute cores 120 may execute various instances of the applications 144 (e.g.,Application instances running in virtual machines, in specific containers, etc.) connected to tenant-associated clients 192 of the cloud computing system. Execution of such tenant software may utilize one or more of the I / O services provided by the Smart NIC. Communication between the components of the host 102 and the NICs 134 may occur via inline connections 133 (or "in-band connections 133").

[0026] As in Fig. As shown, the NICs 134, the computing resources 190, and the clients 192 of the cloud computing system may be coupled via the network fabric 155. In general, the network fabric 155 may be connected to one or more types of communications networks, such as (as examples) Fibre Channel networks, Gen-Z fabrics, dedicated management networks, local area networks (LANs), wide area networks (WANs), global networks (e.g., the Internet), wireless networks, or any combination thereof.

[0027] Regardless of the particular use of the computing platform 100, the BMC 130 can manage the NICs 134, and to this end, the BMC 130 can communicate with the NICs 134 via corresponding associated sideband connections 160. To this end, according to example implementations, the BMC 130 has a network interface that communicates via a sideband communication connection 154 (also referred to herein as "BMC sideband connection 154") with a corresponding port of a sideband communication bridge 150. The sideband communication bridge 150 has ports (referred to herein as "NIC ports") that are coupled to corresponding sideband connections 160 for the NICs 134. At least some of the management functions of the BMC 130 may be controlled by a remote management server 197 that, according to example implementations, communicates with the BMC 130 via a NIC (not shown) of the BMC 130.

[0028] As examples of various management actions that the BMC 130 can perform for a particular NIC 134, the BMC 130 can, via communications made over the corresponding sideband connection 160, change a power state of the NIC 134 (e.g., turn off the NIC 134, reset the NIC 134, turn on the NIC 134, etc.); select a boot path to boot and load an operating system of the NIC 134; select and configure virtual media for use by the NIC 134; update the firmware of the NIC 134, etc. In addition, via communications made over the sideband connection 160, the BMC 130 can monitor sensors of the NIC 134; collect information about environmental conditions and events related to the NIC 134 so that the conditions and events can be reported from the BMC 130 to the remote management server 197; Carry out corrective actions on NIC 134, e.g.Take corrective action following an operating system failure or other failure of the NIC 134; and so on. As examples of other management functions, the BMC 130 may, in accordance with some implementations, communicate over the sideband links 160 to validate the software of the NICs 134, detect hardware failures on the NICs 134, perform software measurements related to the NICs 134, etc.

[0029] A "BMC," or "Baseboard Management Controller," is a specialized service processor that monitors the physical state of a server or other hardware using sensors and communicates with a management system over a management network. The Baseboard Management Controller can also communicate with applications running at the operating system level through an input / output controller (IOCTL) interface driver, a REST application program interface (API), or another system software proxy that facilitates communication between the Baseboard Management Controller and applications. The Baseboard Management Controller can access hardware devices located within a server chassis, including system memory, at the hardware level. The Baseboard Management Controller may be able to directly modify the hardware devices.The baseboard management controller can operate independently of the operating system of the system in which the baseboard management controller is located. The baseboard management controller can be located on the motherboard or mainboard of the server or other device to be monitored. The fact that a baseboard management controller is mounted on the motherboard of the server / hardware to be monitored or is otherwise connected or attached to the server / hardware to be monitored does not prevent the baseboard management controller from being considered "separate" from the server / hardware to be monitored. As used herein, a baseboard management controller has management functions for subsystems of a computing device and is separate from a processing resource executing an operating system of a computing device. The baseboard management controller is separate from a processor, e.g.,a central processing unit that runs a high-level operating system or hypervisor on a system.

[0030] One or more NICs 134 may be installed in corresponding connectors 132 (e.g., connectors 132 mounted on a motherboard or other circuit substrate of the computing platform 100). For example, in accordance with some implementations, the connectors 132 may include one or more PCIe card connectors, one or more OCP connectors, etc.

[0031] The physical properties of the sideband connections 160 may vary. For example, according to some implementations, a sideband connection 160 may be a cable-based connection, that is, a connection with a cable (e.g., a ribbon cable or flat cable) that extends between a cable connector on the motherboard and a cable connector on the circuit substrate of the NIC. As another example, according to example implementations, a particular NIC 134 may include a sideband connection 160 formed from electrically conductive traces on a circuit board substrate, such as the motherboard. As another example, a particular connector 132 connected to the NIC 134 may, according to some implementations, carry both in-band signals and sideband signals connected to the sideband connection 160.

[0032] Among other features of the computing platform 100, a bus infrastructure of the computing platform 100 may, in accordance with some implementations, include one or more input / output I / O bridges 129 that may be coupled to the system memory 128, one or more expansion buses (e.g., PCIe links), and so on. In general, the I / O bridge(s) 129 may include interfaces to various buses of the computing platform 100, such as PCIe links, a Serial Peripheral Interconnect (SPI) bus, an enhanced SPI bus (eSPI), a Low Pin Count (LPC) bus, an inter-integrated bus (I 2 C), an improved inter-integrated bus (I 3 C) and possibly one or more other buses or communication links associated with other standards.

[0033] In accordance with some implementations, the I / O bridge(s) 129 may include a north I / O bridge 129 and a separate south I / O bridge 129. Thus, in accordance with some implementations, the processing core 120 may include one or more semiconductor packages (or "chips"), and the processing core 120 may include the north I / O bridge 129, which includes a memory controller and PCIe root ports. The south I / O bridge 129 may provide I / O ports, such as Serial Advanced Technology Attachment (SATA) ports, Universal Serial Bus (USB) ports, LPC ports, SPI ports, eSPI ports, and so on. In accordance with some implementations, the north I / O bridge 129 may not be part of the processing core 120.According to further implementations, the north and south I / O bridges may be combined into a single I / O bridge 129; and according to some implementations, this single I / O bridge 129 may be part of a multi-core CPU semiconductor package (or "chip") that includes multiple processing cores 120.

[0034] According to Fig. combined with Fig. In example implementations, the sideband connections 154 and 160 conform to the NC-SI specification, although according to further implementations, the sideband connections 154 and 160 may communicate management traffic using signaling and protocols according to a different standard or specification. According to example implementations, each connection 154, 160 comprises multiple bit data transmission channels (in Fig. designated "TX") to transmit the management traffic transmitted by the BMC 130; several bit data receive channels (in Fig. denoted by "RX") to convey the data transmitted from the NICs 134 to the BMC 130; a clock signal; and optional arbitration-related signals.

[0035] In general, the sideband communication bridge 150 handles communication synchronization so that sideband connections 160 of different types and lengths can be used with the NICs 134. Although in Fig. four NICs 134-1, 134-2, 134-3, and 134-4 are illustrated, the computing platform 100 may include more than four NICs 134 or fewer than four NICs 134 according to further example implementations.

[0036] Given the single receive channel of the sideband connection 154 between the BMC 130 and the sideband communication bridge 150, only a single NIC 134 transmits data to the BMC 130 at a time. As described further herein, in accordance with some implementations, the NICs 134 use serial token-based arbitration to determine which NIC 134 has the right to transmit data to the BMC 130 at a given time. This data transmission by the NIC 134 occurs over the RX channel of the corresponding sideband connection 160 and the RX channel of the sideband connection 154.In accordance with example implementations, the NICs 134 serially communicate an ownership token such that the NIC 134 having ownership of the token can assert a token ownership signal, and the sideband communication bridge 150 is responsive to the assertion of the token ownership signal to receive the transmission data from the NIC 134 having the token ownership and to convey that data to the BMC 130.

[0037] Such arbitration cannot be used for the transmission of management data from the BMC 130. Thus, according to example implementations, the sideband communication bridge 150 may, for example, send the data transmitted over the TX transmit channel of link 154 to the TX transmit channels of all sideband links 160, with each individual NIC 134 determining whether the transmitted data is targeted to the NIC 134.

[0038] In accordance with some implementations, management traffic between the BMC 130 and the NICs 134 may be communicated in the form of data packets. The data packet may include, for example, a header (containing data representing a source address, a destination address, etc.) and payload data. In accordance with some implementations, the packets may include control packets communicated between the BMC 130 and the NICs 134, and the packets may include pass-through packets communicated between the BMC 130 and remote devices, such as the Remote Management Server 197 ( Fig. ), communicated.

[0039] According to example implementations, the sideband communication bridge 150 includes NIC port interfaces 220, such as NIC port interfaces 220-1, 220-2, 220-3, and 220-4, which communicate with the NICs 134-1, 134-2, 134-3, and 134-4, respectively, via corresponding sideband connections 160. According to example implementations, the sideband communication bridge 150 includes a clock buffer 230 that provides a leader reference clock (in Fig. referred to as “LEADER_REF_CLK” clock signal) to generate corresponding reference clock signals (in Fig. referred to as "REF_CLK" clock signals). In accordance with example implementations, the reference clock signals and the leader reference clock signal may be identical. According to example implementations, the sideband communication bridge 150 provides the REF_CLK reference clock signals to the clock signal line of each of the interconnects 154 and 160. According to example implementations, the REF_CLK reference clock signal propagates from the sideband communication bridge 150 via the clock signal line of each respective sideband interconnect 160 to arrive at each NIC 134. Furthermore, according to example implementations, the REF_CLK reference clock signal propagates from the sideband communication bridge 150 via the sideband interconnect line 154 to arrive at the BMC 130.

[0040] The NIC 134 receives a delayed version of the REF_CLK reference clock from the clock signal line of the sideband interconnect 160 at a clock input 290 of the NIC 134, and the NIC 134 synchronizes communication with the sideband interconnect 160 in synchronism with the received, delayed version of the REF_CLK reference clock signal. In other words, the NIC 134 sends data to the RX receive channel of the sideband interconnect 160 in synchronism with active edges of the received, delayed version of the REF_CLK reference clock signal, and the NIC 134 receives data from the TX channel of the sideband interconnect 160 in synchronism with the received, delayed version of the REF_CLK reference clock signal.

[0041] In accordance with example implementations, clock buffer 230 also provides one or more REF_CLK reference clock signals to one or more clock feedback paths connected to sideband interconnects 160. Note that a particular clock feedback path may be connected to one or more sideband interconnects 160. For example, in accordance with some implementations, sideband communication bridge 150 provides a REF_CLK reference clock signal to a clock feedback path 260 connected to sideband interconnects 160 for NICs 134-1 and 134-2. Clock feedback path 260, in accordance with example implementations, has a physical length that is exactly or nearly exactly the same length as each of the clock lines of these sideband interconnects 160.Since the sideband connections 160 for the NICs 134-1 and 134-2 are assumed to be identical in this example, the clock feedback path 260 can be part of either of the sideband connections 160. In the embodiment shown in . Fig. In the example implementation shown, the clock return path 260 is part of the sideband interconnect 160 that is connected to the NIC 134-1.

[0042] In accordance with further implementations, the clock feedback path may not be part of a specific sideband interconnect 160, but may have a length corresponding to the length of the clock line of the sideband interconnect 160. Furthermore, in accordance with further implementations, the length of the clock feedback path may not be identical or nearly identical to the length of the clock line of the sideband interconnect 106, but rather the length of the clock feedback path may have a predetermined length ratio to the clock line (e.g., the length of the clock feedback path may be one-quarter or one-half the length of the clock feedback path), and based on this predetermined length ratio, the sideband communication bridge 150 may provide a clock signal at the NIC port 220 that matches the clock signal at the NIC 134.

[0043] The REF_CLK reference clock signal is received at a first end 263 of the feedback clock signal path 260, and the REF_CLK reference clock signal propagates through the clock feedback path 260 to generate a feedback clock signal at a second end 265 of the clock feedback path 260 (in Fig. referred to as "FB_CLK_P1,2"). The NIC port interfaces 220-1 and 220-2 clock or synchronize communication with the respective sideband links 160 to the FB_CLK_P1,2 clock signal (rather than, for example, the NIC port interfaces 220-1 and 220-2 synchronizing communication to the reference clock signal REF_CLK). In this example, the sideband links 160 for the NICs 134-1 and 134-2 have similar physical characteristics. For example, the NICs 134-1 and 134-2 may each be PCIe-based NICs with similar sideband links 160. Thus, the sideband communication bridge 150 may apply the same feedback clock signal to multiple sideband links 160, according to some implementations.

[0044] Similarly, according to some implementations, connections 160-3 and 160-4 may have similar physical characteristics. For example, NICs 134-3 and 134-4 may be OCP-based NICs. This allows sideband communication bridge 150 to use a single clock feedback path 264 to provide a feedback clock signal (in Fig. designated “FB_CLK_P3,4”) for clocking sideband link communication over NIC port interfaces 220-3 and 220-4.

[0045] In accordance with further example implementations, each of the NIC port interfaces 220-1, 220-2, 220-3, and 220-4 may have their own respective feedback clock paths to derive a feedback clock signal for clocking those port interfaces; three of the NIC port interfaces 220 may have an associated clock feedback path; four of the NIC port interfaces 220 may have their own individual clock feedback paths; and so on.

[0046] As also in Fig. As shown, in accordance with some implementations, the clock buffer 230 may also provide the REF_CLK reference clock signal to a clock line of the BMC sideband interconnect 154 and provide a REF_CLK reference clock signal to a clock feedback path 207 coupled to the BMC sideband interconnect 154. In this manner, according to example implementations, the sideband communication bridge 150 includes a BMC port interface 210 communicating with the BMC sideband interconnect 154; and a clock input 211 of the BMC port interface 210 receives a feedback clock signal (in Fig. denoted by "FB_CLK_BMC"). The FB_CLK_BMC feedback clock signal, in accordance with example implementations, corresponds to a delayed version of the REF_CLK reference clock received from a clock input 201 of a network interface 204 of the BMC 130 and used by the network interface 204 to synchronize communication with the BMC sideband interconnect 154.

[0047] According to other example implementations, clock feedback-based adjustment may not be used by the BMC port interface 210. Accordingly, in these example implementations, the clock input 211 of the BMC port interface 210 may receive the instantaneous reference clock signal REF_CLK and synchronize communication with the BMC sideband interconnect 154 to this clock signal.

[0048] Among other features, in accordance with some implementations, the sideband communication bridge 150 may include an arbitration retiming circuit 280. The arbitration retiming circuit 280 resynchronizes the arbitration-related communication between the NICs 134-1, 134-2, 134-3, and 134-4, as described further below in connection with Fig. described.

[0049] Fig. shows a transmit and receive path architecture 300 of the sideband communication bridge 150 in accordance with example implementations. According to Fig. in connection with the Fig. The architecture 300 includes FIFO buffers 304, 308, 312, and 316 connected to the RX channels. Thus, the input sides of FIFO buffers 304, 308, 312, and 316 are connected to the RX channels of the sideband interconnect for NIC port interfaces 220-1, 220-2, 220-3, and 220-4, respectively. The output sides of FIFO buffers 304, 308, 312, and 316 are connected to the RX channel for BMC sideband interconnect 154 (i.e., connected to the RX channel for BMC port interface 210). The architecture 300 also includes transmit FIFO buffers 320 and 324. The output side of FIFO buffer 320 is connected to the TX channels of the sideband interconnect for the NIC port interfaces 220-1 and 220-2. The output side of FIFO buffer 324 is connected to the TX channels of the sideband interconnect for the NIC port interfaces 220-3 and 220-4. The input sides of FIFO buffers 320 and 324 are connected to the TX channel for the BMC sideband interconnect 154 (ieconnected to the TX channel for the BMC connection interface 210).

[0050] Regarding the FIFO receive buffers, FIFO buffer 304 has an input side that receives data (represented by a two-bit data signal labeled "RCD[1:0]_PORT1") from the RX channel of sideband interconnect 160 connected to NIC 134-1. The input side of FIFO buffer 304 has a clock input 351 that receives the feedback clock signal FB_CLK_P1,2. FIFO buffer 304 receives an arbitration token ownership signal labeled "CRS_DV_PORT1," which NIC 134-1 asserts (e.g., sets high or to a logic one) to indicate that NIC 134-1 is in possession of the ownership token. In other words, in accordance with example implementations, in response to the assertion of the CRS_DV_PORT1 token ownership signal, the FIFO buffer 304 receives data from the NIC 134-1 in synchronization with the FB_CLK_P1,2 feedback clock signal.

[0051] The output side of the FIFO buffer 304 is connected to the RX channel of the BMC sideband interconnect 154 according to example implementations. The output side of the FIFO buffer 304 has a clock input 305 that receives the FB_CLK_BMC feedback clock signal, according to example implementations. Furthermore, as shown in Fig. As shown, an output 305 of the FIFO buffer 304 is coupled to a multiplexer or selector 302. The selector 302 couples the output 305 to the RX channel of the BMC sideband link 154 when the NIC 134-1 asserts the CRS_DV_PORT1 token ownership signal. As shown in Fig. As shown, the selector 302 may output a signal labeled “CRS_DV_BMC” which, when output, is applied to the network interface 204 of the BMC ( Fig. ) indicates that NIC data (represented by a two-bit data signal labeled "RCD[1:0]_BMC") is being transferred from the sideband communication bridge 150b to the BMC 130. Therefore, in accordance with example implementations, when the NIC 134-1 possesses the ownership token, it communicates data through the FIFO buffer 304 to the BMC 130; and this communication includes synchronizing the communication from the NIC 134 with the FB_CLK_P1,2 feedback clock signal and includes the sideband communication bridge 150 resynchronizing or resynchronizing the data with the FB_CLK_BMC feedback clock signal.

[0052] Similarly, according to example implementations, the other receive FIFO buffers 308, 312, and 316 have clock inputs 351, 353, 355, and 356 for their respective input sections, which receive the feedback clock signals FB_CLK_P1,2, FB_CLK_P3,4, and FB_CLK_P3,4, respectively. The input sections of FIFO buffers 308, 312, and 316 receive data via two bit data signals labeled "RCD[1:0]_PORT2," "RCD[1:0]_PORT3," and "RCD[1:0]_PORT4." In addition, FIFO buffers 308, 312, and 316 receive corresponding token ownership signals labeled "CRS_DV_PORT2," "CRS_DV_PORT3," and "CRS_DV_PORT4" from NIC 134-2, NIC 134-3, and NIC 134-4, respectively, so that the input section receives data from NIC 134 when the corresponding NIC 134 asserts the token ownership signal. Furthermore, similar to FIFO buffer 304 according to the example implementations, FIFO buffers 308, 312, and 316 have clock inputs 305, 309, 313, and 317, respectively, which receive the FB_CLK_BMC clock signal.The output sections of FIFO buffers 308, 312, and 316 provide outputs 361, 363, and 365, respectively, to selector 302, so that selector 302 forwards the corresponding output to the RX channel of BMC sideband interconnect 154 when the corresponding token ownership signal is asserted.

[0053] Regarding the transmit FIFO buffers, in accordance with example implementations, FIFO buffer architecture 300 further includes FIFO buffers 320 and 324 that forward transmit data from the TX channel of sideband interconnect 154 to sideband interconnects 160. More specifically, in accordance with example implementations, FIFO buffer 320 has an input section clocked by the FB_CLK_BMC clock signal and receiving data (represented by a two-bit data signal labeled "TXD[1:0]_BMC") from the TX channel of interconnect 154. That is, the input section of FIFO buffer 320 clocks the incoming data synchronously with the edges of the FB_CLK_BMC clock signal. The FIFO buffer 320 also has an output section that supplies data to the connection lines 160 connected to the NICs 134-1 and 134-2. In this way, as shown in Fig. As shown, data directed to either NIC 134-1 or 134-2 is transmitted to both NICs via respective two-bit data signals labeled "TXD[1:0]_PORT1" and "TXD[1:0]_PORT2," respectively, in synchronization with the FB_CLK_P1,2 clock signal. Similarly, FIFO buffer 324 has an input section that receives data from the TX channel of interconnect 154, and FIFO buffer 324 has an output section that provides data to NICs 134-1 and 134-4 via respective two-bit data signals labeled "TXD[1:0]_PORT3" and "TXD[1:0]_PORT4," respectively, in synchronization with the FB_CLK_P3,4 clock signal.

[0054] In Fig. , a retiming circuit architecture 400 of the sideband communication bridge 150 is illustrated according to example implementations. Referring to Fig. in connection with the Fig. According to some implementations, the NICs 134 communicate an arbitration ownership token in a serial arbitration communication chain. The retiming architecture 400 includes the arbitration retiming circuit 280, which delays the serial communication of the arbitration ownership token between the NICs 134-1, 134-2, 134-3, and 134-4 to account for the different respective NIC clock domains. In accordance with example implementations, one of the NICs 134 owns the ownership token at a time; and possession of the ownership token authorizes the NIC 134 (to the exclusion of the other NICs 134) to transmit data to the RX channel of its associated sideband interconnect 160.

[0055] According to example implementations, the arbitration retiming circuit 280 includes retiming circuits 412 (specifically, retiming circuits 412-1, 412-2, 412-3, and 412-4), with each retiming circuit 412 retiming an arbitration output signal provided at an arbitration signal output 408 of a particular NIC 134 to provide a retimed arbitration input signal to an arbitration signal input 404 of another NIC 134. The NICs 134 may serially transmit an ownership token using the arbitration input and output signals. For example, according to example implementations, a NIC 134 may assert its output arbitration signal (e.g.,switch to "high" or to a logic state of one) to indicate that the NIC is relinquishing ownership of the ownership token, and an input arbitration signal may be asserted to indicate that the receiving NIC 134 is taking ownership of the ownership token. In accordance with some implementations, a NIC 134 may retain ownership of the ownership token for a predetermined number of clock pulses, after which the NIC 134 passes the ownership token to the next NIC 134 in the serial arbitration communication chain. When a NIC 134 is in possession of the ownership token, the NIC 134 may assert its CRS_DV PORT signal (see . Fig. ) and transmit data to the RX channel of their corresponding sideband connection 160.

[0056] As in Fig. As shown, in accordance with example implementations, the retiming circuit 412-1 receives an arbitration output signal (in Fig. (labeled "ARB_OUT4") from NIC 134-4. NIC 134-4 asserts the ARB_OUT4 signal to indicate that NIC 134-4 is relinquishing ownership of the ownership token, i.e., NIC 134-4 is passing the ownership token to the next NIC 134 in the serial arbitration communication chain (here, NIC 134-1). Retiming circuit 412-1 delays the ARB_OUT4 signal with the edges of the FB_CLK_P1,2 feedback clock signal to provide NIC 134-1 with an arbitration input signal labeled "ARB_IN1." In response to the NIC 134-4 asserting the arbitration output signal ARB_OUT4 to relinquish ownership of the property token, the NIC 134-1 acquires ownership of the property token due to the assertion of the ARB_IN1 signal.

[0057] According to example implementations, the retiming circuit 412 may have a clock input 413 and receive the corresponding feedback clock signal; and the retiming circuit 412 may include a chain of two D flip-flops. According to example implementations, for example, a non-inverting input of a first D flip-flop receives the arbitration output signal. A non-inverting output of the first D flip-flop is coupled to the non-inverting input of a second D flip-flop. A non-inverting output of the second D flip-flop provides the retimed arbitration output signal. The first and second D flip-flops may each be clocked by the feedback clock signal FB_CLK_P1,2.

[0058] Similarly, in accordance with example implementations, retiming circuits 412-2, 412-3, and 412-4 delay arbitration output signals provided by corresponding NICs 134 to provide arbitration input signals to other NICs 134 in the serial arbitration communication chain.

[0059] As also in Fig. As shown, in accordance with example implementations, the retiming architecture 400 may include a bypass circuit 420 for each slot port because a particular NIC 134 may not be installed in a corresponding slot port. More specifically, in accordance with example implementations, the bypass circuit 410 receives a corresponding presence or installation signal (i.e., an INSTALL1, INSTALL2, INSTALL3, or INSTALL4 signal) for the associated NIC slot. In accordance with example implementations, the bypass circuit 420 is responsive to the installation signal being deasserted (e.g., to a low value or a logic zero state) to couple the arbitration input 404 and the output 408 of the associated NIC 134 together to bypass the NIC 134 in the serial arbitration communication chain.

[0060] According to Fig. and in accordance with example implementations, a process 500 includes a port of a bridge providing a reference clock signal to a first end of an interconnect (block 504) extending between the first port and a network interface controller. The reference clock signal propagates across the interconnect to provide a delayed reference clock signal to the network interface controller at a second end of the interconnect. According to the process 500, the bridge detects (block 508) a timing of the delayed reference clock signal. The process 500 includes communicating (block 512) management traffic between a network interface of a baseboard management controller and the network interface controller over the interconnect.Communication of management traffic involves the port, in response to detecting the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the link with the delayed reference clock signal.

[0061] As in Fig. As shown, a bridge 600 includes, according to example implementations, a first port interface 604 and a second port interface 608. The first port interface 604 communicates first data with a first interconnect coupled between the first port interface 604 and a system management controller. The second port interface 608 communicates second data with a second interconnect coupled between the second port interface 608 and a network interface controller. The second port interface 608 provides a reference clock signal to the second interconnect. The reference clock signal propagates across the second interconnect from a first end of the second interconnect to a second end of the second interconnect to provide a delayed reference clock signal to the network interface controller at the second end of the second interconnect.The second connection interface 608 transmits the second data synchronously with the delayed reference clock signal.

[0062] As in Fig.As shown, a computing platform 700 includes, according to example implementations, network interface controllers 704, a baseboard management controller 708, main processing cores 712, sideband interconnects 720, and a bridge 730. The network interface controllers 704 provide a plurality of input / output (I / O) services, and the main processing cores 712 utilize the plurality of I / O services. The sideband interconnect 720 is coupled to the network interface controller 704. The bridge 730 is coupled to the sideband interconnects 720 to carry management traffic between the network interface controller 704 and the baseboard management controller 708. The bridge 730 includes a first port interface 734 and a second port interface 738. The first port interface 734 is coupled to the baseboard management controller 708.The second connection interface 738 is connected to a first network interface controller 704-1 via a first sideband connection 720-1. The second connection interface 738 provides a reference clock signal to a first end of the first sideband connection 720-1. The reference signal propagates across the first sideband connection 720-1 to provide a second clock signal to the first network interface controller 704-1 at a second end of the first sideband connection 720-1. The second connection interface 738 synchronizes data communication with the first sideband connection 720-1 with the second clock signal.

[0063] In accordance with example implementations, the bridge includes a second port that provides the reference clock signal to a first end of a second interconnect extending between the second port and the network interface of the baseboard management controller. The reference clock propagates across the second interconnect to provide a second delayed reference clock signal to the network interface of the baseboard management controller at a second end of the second interconnect. The bridge detects a timing of the second delayed reference clock signal. Communicating the management traffic further comprises communicating the management traffic across the second interconnect, and the second port, in response to detecting the timing of the second blade reference clock signal, synchronizes data communication with the first end of the second interconnect with the second delayed reference clock signal.A particular advantage is that baseboard management controller connections with different timing characteristics can be considered.

[0064] In accordance with example implementations, the first port provides the reference clock signal to a first end of a feedback clock path. The reference clock signal propagates across the feedback clock path to provide a feedback clock signal at a second end of the feedback clock path. The feedback clock path has a length between the first end and the second end that corresponds to a length of the connection over which the reference clock signal propagates. The bridge that detects the timing of the delayed reference clock signal includes the bridge that receives the feedback clock signal. Synchronizing data transmission to the first end of the connection with the delayed reference clock signal comprises at least one of the following steps: the first port receiving data from the first connection synchronously with the feedback clock signal or transmitting data to the first connection synchronously with the feedback clock signal.A particular advantage is that connections with different time characteristics are taken into account.

[0065] According to example implementations, a second port of the bridge provides the reference clock signal to a first end of a second interconnect extending between the second port and a second network interface controller. Management traffic is transmitted between the network interface of the baseboard management controller and the second network interface controller over the second interconnect, and this communication includes the second port synchronizing data communication with the first end of the second interconnect to the first delayed reference clock signal. A particular advantage is that interconnects with different timing characteristics are accommodated.

[0066] In accordance with example implementations, a second port of the bridge provides the reference clock signal to a first end of a second interconnect extending between the second port and a second network interface controller. The reference clock signal propagates across the second interconnect to provide a second delayed reference clock signal to the second network interface controller at a second unit of the second interconnect. The bridge detects the timing of the second delayed reference clock signal.Management traffic is transmitted between the network interface of the baseboard management controller and the second network interface controller over the second connection. This communication includes the second port responsive to detecting the second delayed reference clock signal and synchronizing data communication with the first end of the second connection with the second delayed reference clock signal. A particular advantage is that connections with different timing characteristics are accommodated.

[0067] In accordance with example implementations, the first connection comprises a wired connection and the second connection a wireless connection. A particular advantage is that connections with different timing characteristics can be considered.

[0068] According to example implementations, the bridge receives an arbitration output signal provided by the second network interface controller. The arbitration output signal indicates that the second network interface controller is relinquishing ownership of a token. The bridge synchronizes the arbitration output signal with the first delayed reference clock signal to provide a retimed arbitration signal indicating whether ownership of the token is transferred to the first network interface controller. The bridge provides the retimed arbitration signal to a first network interface controller. A particular advantage is that connections with different timing characteristics can be accommodated.

[0069] According to example implementations, the bridge includes a third port connected to the network interface of the baseboard management controller. The method includes, in response to the first network controller asserting an ownership signal indicating that the first network controller owns a token, the bridge coupling the first port to the third port to allow the first network interface controller to transmit data over the first connection to the network interface of the baseboard management controller.In response to the second network controller asserting an ownership signal, indicating that the second network controller owns the token, the bridge couples the second port to the third port, allowing the second network interface controller to transmit data over the second connection to the network interface of the baseboard management controller. A particular advantage is that connections with different timing characteristics are accommodated.

[0070] According to example implementations, the bridge includes a third port connected to the network interface of the baseboard management controller. The third port receives the transmit data transmitted by the baseboard management controller. The first port transmits the transmitted data to the first interconnect line synchronously with the first delayed reference clock signal. The second port transmits the transmit data to the second interconnect line synchronously with the second delayed reference clock signal. A particular advantage is that connections with different timing characteristics can be accommodated.

[0071] According to example implementations, the bridge includes a third port coupled to the network interface of the baseboard management controller via a third interconnect, and the third interconnect is connected to a specific clock signal. In response to the first interconnect controller granting the first network interface controller an exclusive right to transmit data to the baseboard management controller via the third interconnect, the first port receives, from the first end of the first interconnect, first receive data transmitted by the first network interface controller synchronously with the first delayed clock signal, and the third port transmits the first data to the third interconnect synchronously with the given clock signal. A particular advantage is that interconnects with different timing characteristics are accommodated.

[0072] According to example implementations, in response to the second network interface controller asserting its exclusive right to transmit data to the baseboard management controller via the third interconnect, the second port receives second receive data from the first end of the second interconnect, which second port transmits the second received data synchronously with the second delayed clock signal, and the third port transmits the second received data to the third interconnect synchronously with the given clock signal. A particular advantage is that connections with different timing characteristics are considered.

[0073] In accordance with example implementations, the third port provides the reference clock signal to a first end of the third interconnect. The reference clock signal propagates across the third interconnect to provide a third delayed reference clock signal to the network interface of the baseboard management controller at a second end of the second interconnect. The bridge uses a feedback clock path to provide the given clock signal, wherein using the feedback clock path comprises providing the reference clock signal at one end of the feedback clock path to provide the given clock signal at a second end of the feedback clock path. The feedback clock path has a length corresponding to a length of the third interconnect over which the reference clock signal propagates.A particular advantage is that connections with different timing properties can be taken into account.

[0074] Although the present disclosure has been described with respect to a limited number of implementations, those skilled in the art, having the benefit of this disclosure, will recognize numerous modifications and variations thereof. The appended claims are intended to cover all such modifications and variations.

Claims

[1] Procedure comprising: Providing a reference clock signal through a first port of a bridge to a first end of a first interconnect extending between the first port and a first network interface controller, the reference clock signal propagating across the first interconnect to provide a first delayed reference clock signal to the first network interface controller at a second end of the first interconnect; detecting a time of the first delayed reference clock signal by the bridge; Communicating management traffic between a network interface of a baseboard management controller and the first network interface controller over the first connection, wherein communicating the management traffic comprises the first port, in response to detecting the timing of the first delayed reference clock signal, synchronizing communication of data with the first end of the first connection with the first delayed reference clock signal; Providing the reference clock signal through a second port of the bridge to a first end of a second interconnect extending between the second port and the network interface of the baseboard management controller; and Communicating management traffic between the network interface of the baseboard management controller and the second network interface controller over the second connection, comprising synchronizing, through the second port, the data communication with the first end of the second connection to the first delayed reference clock signal. [2] Procedure comprising: Providing a reference clock signal through a first port of a bridge to a first end of a first interconnect extending between the first port and a first network interface controller, the reference clock signal propagating across the first interconnect to provide a first delayed reference clock signal to the first network interface controller at a second end of the first interconnect; detecting a time of the first delayed reference clock signal by the bridge; Communicating management traffic between a network interface of a baseboard management controller and the first network interface controller over the first connection, wherein communicating the management traffic comprises the first port, in response to detecting the timing of the first delayed reference clock signal, synchronizing communication of data with the first end of the first connection with the first delayed reference clock signal; Providing the reference clock signal through a second port of the bridge to a first end of a second interconnect extending between the second port and the network interface of the baseboard management controller, wherein the reference clock signal propagates over the second interconnect to provide a second delayed reference clock signal to the network interface of the baseboard management controller at a second end of the second interconnect; and detecting a timing of the second delayed reference clock signal by the bridge; whereby the transmission of management traffic further includes: Transmission of management traffic over the second connection line; and in response to detecting the timing of the second delayed reference clock signal, synchronizing communication of data to the first end of the second connection through the second port with the second delayed reference clock signal. [3] Procedure which includes: Providing a reference clock signal through a first port of a bridge to a first end of a first interconnect extending between the first port and a first network interface controller, the reference clock signal propagating across the first interconnect to provide a first delayed reference clock signal to the first network interface controller at a second end of the first interconnect; detecting a time of the first delayed reference clock signal by the bridge; Communicating management traffic between a network interface of a baseboard management controller and the first network interface controller over the first connection, wherein communicating the management traffic comprises the first port, in response to detecting the timing of the first delayed reference clock signal, synchronizing communication of data with the first end of the first connection with the first delayed reference clock signal; Providing the reference clock signal through a second port of the bridge to a first end of a second interconnect extending between the second port and a second network interface controller, the reference clock signal propagating across the second interconnect to provide a second delayed reference clock signal to the second network interface controller at a second end of the second interconnect; detecting a timing of the second delayed reference clock signal by the bridge; and Communicating management traffic between the network interface of the baseboard management controller and the second network interface controller over the second interconnect, wherein the second port, in response to detecting the second delayed reference clock signal, synchronizes communication of data with the first end of the second interconnect with the second delayed reference clock signal. [4] The method of claim 3, wherein the first connection comprises a wired connection and the second connection comprises a wireless connection. [5] The method of claim 3, further comprising: receiving, by the bridge, an arbitration output signal provided by the second network interface controller, the arbitration output signal indicating that the second network interface controller relinquishes ownership of a token; Synchronizing the arbitration output signal with the first delayed reference clock signal by the bridge to provide a re-timed arbitration signal indicating whether ownership of the token is transferred to the first network interface controller; and Provision of the re-timed arbitration signal by the bridge to the first network interface controller. [6] The method of claim 3, wherein the bridge comprises a third port connected to the network interface of the base board management controller, the method further comprising: coupling the first port to the third port through the bridge to enable the first network interface controller to transmit data over the first connection to the network interface of the baseboard management controller when the first network controller asserts an ownership signal representing possession of a token by the first network controller; and Coupling the second port to the third port through the bridge to enable the second network interface controller to transmit data over the second connection to the network interface of the baseboard management controller when the second network controller asserts an ownership signal indicating that the second network controller is the owner of the token. [7] The method of claim 3, wherein the bridge comprises a third port connected to the network interface of the base board management controller, the method further comprising: Receiving transmission data transmitted from the base board management controller via the third port; Sending the transmit data via the first terminal to the first connection in synchronization with the first delayed reference clock signal; and Sending the transmit data via the second port to the second connection in synchronization with the second delayed reference clock signal. [8] The method of claim 3, wherein the bridge comprises a third port coupled to the network interface of the base board management controller via a third connection, and wherein the third connection is connected to a given clock signal, the method further comprising: in response to the first network interface controller asserting an exclusive right to transmit data to the baseboard management controller over the third connection: Receiving first receive data transmitted by the first network interface controller synchronously with the first delayed clock signal via the first port from the first end of the first connection; and Transmitting the first receive data via the third port to the third connection in synchronization with the given clock signal. [9] The method of claim 8, further comprising: in response to the second network interface controller asserting the exclusive right to transmit data to the base board management controller over the third connection: Receiving second receive data transmitted by the second network interface controller synchronously with the second delayed clock signal via the second port from the first end of the second connection; and Transmitting the second receive data via the third port to the third connection in synchronization with the given clock signal. [10] The method of claim 8, further comprising: Providing the reference clock signal through the third terminal to a first end of the third interconnect, wherein the reference clock signal propagates across the third interconnect to provide a third delayed reference clock signal to the network interface of the base board management controller at a second end of the second interconnect; and Using a feedback clock path through the bridge to provide the given clock signal, comprising providing the reference clock signal at one end of the feedback clock path to provide the given clock signal at a second end of the feedback clock path, the feedback clock path having a length corresponding to a length of the third interconnection over which the reference clock signal propagates. [11] Bridge, comprising: a first connection interface for transmitting first data with a first interconnect coupled between the first connection interface and a system management controller; a FIFO (first-in-first-out) buffer with a first FIFO port and a second FIFO port; a second port interface to: transmit second data with a second connection between the second connection interface and a first network interface controller; provide a reference clock signal to the second interconnect, the reference clock signal propagating across the second interconnect from a first end of the second interconnect to a second end of the second interconnect to provide a first delayed reference clock signal to the first network interface controller at the second end of the second interconnect; and Transmission of the second data in synchronization with the first delayed reference clock signal, where: the first connection interface communicates the first data with the first interface in synchronization with a given clock signal; the first FIFO port is clocked by the given clock signal; and the second FIFO port is clocked by the first delayed reference clock signal. [12] A bridge according to claim 11, further comprising: a third port interface for communicating third data with a third interconnect coupled between the second port and a second network interface controller, the third port interface being connected to: Providing a reference clock signal to the third interconnect, the reference clock signal propagating across the third interconnect from a first end of the third interconnect to a second end of the third interconnect to provide a second delayed reference clock signal to the second network interface controller at the second end of the third interconnect; and Transmission of the third data in synchronization with the second delayed reference clock signal. [13] The bridge of claim 11, wherein the first terminal interface transmits the first data in accordance with a Network Controller-Sideband Interface (NC-SI) standard and the second terminal interface transmits the second data in accordance with the NC-SI standard. [14] Computer platform comprising: a plurality of network interface controllers to provide a plurality of input / output (I / O) services; a baseboard management controller; a plurality of main processing cores for utilizing the plurality of I / O services; a plurality of sideband connections coupled to the plurality of network interface controllers; and a bridge coupled to the plurality of sideband connections for communicating management traffic between the plurality of network interface controllers and the baseboard management controller, the bridge comprising: a first port interface coupled to the baseboard management controller; a second port interface coupled to a first network interface controller of the plurality of network interface controllers via a first sideband connection of the plurality of sideband connections, the second port interface being configured to: Providing a reference clock signal at a first end of the first sideband connection, the reference clock signal propagating across the first sideband connection to provide a second clock signal at a second end of the first sideband connection to the first network interface controller; and synchronize the communication of data with the first sideband connection with the second clock signal. [15] The computer platform of claim 14, wherein the bridge further comprises: a third port interface to communicate data with a second network interface controller of the plurality of network interface controllers over a third sideband connection of the plurality of sideband connections in synchronization with a third clock signal that is asynchronous to the second clock signal. [16] The computing platform of claim 15, wherein the first sideband connection comprises a wired connection and the second sideband connection comprises a wireless connection.

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