Semiconductor devices and their manufacturing processes

Abstract

Semiconductor device (200), comprising: an insulating layer (212) with an upper surface; a first epitaxial source / drain feature (234, 234n, 234p) extending from the insulating layer (212) across its upper surface; a second epitaxial source / drain feature (234, 234n, 234p) extending from the insulating layer (212) across its upper surface; a hybrid fin (218, 218p, 218n, 218pn) arranged between the first epitaxial source / drain feature (234, 234n, 234p) and the second epitaxial source / drain feature (234, 234n, 234p), wherein the hybrid fin (218, 218p, 218n, 218pn) has a first end embedded in the insulating layer (212) and a second end extending over the upper surface of the insulating layer (212); a source / drain contact feature (260) in electrical contact on a lower surface with the first and second epitaxial source / drain features (234, 234n, 234p), wherein the lower surface of the source / drain contact feature (260) lies above the second end of the hybrid fin (218, 218p, 218n, 218pn); and a gate structure located next to the first epitaxial source / drain feature (234, 234n, 234p) and the second epitaxial source / drain feature (234, 234n, 234p), wherein the hybrid fin (218, 218p, 218n, 218pn) extends under the gate structure and an upper surface of a section of the hybrid fin (218, 218p, 218n, 218pn) under the gate structure is higher than an upper surface of the second end of the hybrid fin (218, 218p, 218n, 218pn).

Description

BACKGROUND

[0001] The integrated semiconductor circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. As IC development progresses, functional density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This downscaling process generally offers advantages by increasing production efficiency and reducing associated costs. However, such downscaling has also increased the complexity of processing and manufacturing ICs. US 2021 / 0202714A1 describes a semiconductor device with a wall fin and a method for manufacturing it.

[0002] Therefore, there is a need to improve the processing and manufacturing of ICs. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. Fig. Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to embodiments of the present disclosure. The Fig. Figures 2-28 schematically show different stages of the manufacture of a semiconductor device according to embodiments of the present disclosure. The Fig. 29, Fig. 29A, Fig. 29B, Fig. Figure 29C shows various views of a semiconductor device according to embodiments of the present disclosure. The Fig. Figures 30-33 show different stages of a semiconductor device according to embodiments of the present disclosure. The Fig. Figures 34-40 show various stages of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "above," "uppermost," "superior," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0006] The foregoing broadly outlines some aspects of embodiments described in this disclosure. While some embodiments described herein are in the context of nanostructured FETs (e.g., nanowire transistors, nanosheet transistors, gate all-around transistors, etc.), implementations of some aspects of this disclosure may be used in other processes and / or in other devices, such as planar FETs, FinFETs, and other suitable devices. Those skilled in the art will readily understand that further modifications that may be made are considered within the scope of this disclosure. Although embodiments of the method may be described in a particular sequence, various other implementations of the method may be carried out in any logical order and may include fewer or more steps than described herein.In the present disclosure, Source / Drain denotes a source and / or a drain. Source and drain are used interchangeably.

[0007] The present disclosure relates to a semiconductor device with source / drain contacts featuring improved RC delay and reduced resistance. In particular, semiconductor devices according to the present disclosure have height-varying hybrid fins between the edges of the p-type and n-type device regions.

[0008] Fig. Figure 1 is a flowchart of a method 100 for manufacturing a semiconductor device according to embodiments of the present disclosure. Fig. Figures 2-28 schematically show various stages of the fabrication of a semiconductor device 200 according to embodiments of the present disclosure. In particular, the semiconductor device 200 can be fabricated according to method 100 of the Fig. 1. They will be produced. Fig. Figures 2-28 are schematic perspective views of the semiconductor device 200.

[0009] In process 102 of method 100, semiconductor fins 204 are formed on a substrate 202, as shown in Fig. 2 shown. Fig. Figure 2 is a schematic perspective view of the semiconductor device 200 according to the present disclosure. The substrate 202 can be a bulk silicon substrate. Alternatively, the substrate 202 can contain an elemental semiconductor such as silicon (Si) or germanium (Ge) in a crystal structure; a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or combinations thereof. The substrate 202 can also be a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods.

[0010] Depending on the circuit design, the substrate 202 can have various doping configurations. For example, the substrate 202 can have one or more p-doped regions and one or more n-doped regions. The p-doped regions can be doped with p-type dopants such as boron or BF₂. The n-doped regions can be doped with n-type dopants such as phosphorus or arsenic. The doped regions can be formed directly on the substrate 202 in a p-well structure, an n-well structure, a dual-well structure, and / or using a raised structure. The substrate 202 can further include various active regions, such as regions configured for an n-metal-oxide-semiconductor transistor device and regions configured for a p-metal-oxide-semiconductor transistor device.The semiconductor fins 204n and 204p (together 204) can be formed by suitable structuring and etching processes. The n-type devices are subsequently formed from the semiconductor fins 204n, while the p-type devices are subsequently formed from the semiconductor fins 204p. The semiconductor fins 204n are formed over an n-type device area 200n, and the semiconductor fins 204p are formed over a p-type device area 200p.

[0011] In some embodiments, a buffer layer (pad layer) 206 and a mask layer 208 are deposited on the substrate 202, then patterned and used as a mask for forming the semiconductor fins 204. The buffer layer 206 and the mask layer 208 can be formed over the substrate 202 by opaque deposition. A patterned photosensitive layer (not shown) can then be formed over the mask layer 208. The buffer layer 206 and the mask layer 208 can be patterned with the patterned photosensitive layer using one or more photolithographic processes. In some embodiments, dual or multiple patterning processes can be used to pattern the buffer layer 206 and the mask layer 208. The patterned buffer layer 206 and mask layer 208 are then used as a mask to etch the substrate 202 to form the semiconductor fins 204.In some embodiments, the buffer layer 206 can be a thin film containing silicon oxide, which is formed, for example, using a thermal oxidation process. The buffer layer 206 can act as an adhesive layer between the substrate 202 and the mask layer 208. In some embodiments, the mask layer 208 contains silicon nitride, for example, silicon nitride formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0012] As in Fig. As shown in Figure 2, the semiconductor fins 204p, 204n extend along the x-direction from the substrate 202. Trenches 210 (210s, 210l) are formed between adjacent semiconductor fins 204p, 204n. The trenches 210 are formed along the x-direction. As shown in Fig. As shown in Figure 2, the trenches 210 can have different widths along the y-direction according to the circuit design. In some embodiments, hybrid fins or dielectric fins are formed in some of the trenches 210. In some embodiments, the hybrid fins can serve to provide electrical insulation between active areas of the different devices. In other embodiments, the hybrid fins serve to support subsequently formed gate structures, particularly when sacrificial gate structures are to be supported between the wider trenches 210l. Trenches 21ol denote wider trenches in which hybrid fins are subsequently formed, and trenches 210s denote narrow trenches in which no hybrid fins are formed.

[0013] In process 104 of method 100, an insulating layer 212 is deposited over the semiconductor fins 204, as shown in Fig. Figure 3 shows that in some embodiments, the mask layer 208 and the buffer layer 206 can remain on the semiconductor fins 204 during the deposition of the insulating layer 212. In some embodiments, the insulating layer 212 can be deposited to a target thickness such that the narrow grooves 210n are filled with the insulating layer 212, while a groove 210r remains in the wider grooves 210l. The grooves 210r can be dimensioned to accommodate a hybrid fin to be formed therein. The insulating layer 212 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), continuous vapor deposition (CVD), atomic layer deposition (ALD), or another suitable deposition process. In some embodiments, the insulating layer 212 can contain silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or combinations thereof.

[0014] In process 106 of method 100, a dielectric fin layer 214 is deposited over the substrate 202, as shown in Fig. Figure 4 shows that the dielectric fin layer 214 fills the grooves 210r, forming a dielectric fin or hybrid fin in the grooves 210r. In some embodiments, the dielectric fin layer 214 is formed by a suitable deposition process to fill the grooves 210r.

[0015] The dielectric fin layer 214 can contain a single layer of a dielectric or two or more layers of dielectrics deposited sequentially therein. In some embodiments, the dielectric fin layer 214 can contain a dielectric exhibiting etch selectivity with respect to the insulating layer 212. In some embodiments, the dielectric fin layer 214 can consist of silicon nitride (SiN), an oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), an oxide, SiO2, Si3N4, SiOCN, and the like. The dielectric fin layer 214 can be formed by processes used to form such a layer, for example, CVD, plasma-assisted CVD, sputtering, or other suitable methods.

[0016] In some embodiments, the dielectric fin layer 214 can be a high-k dielectric such as a metal oxide like HfO2, ZrO2, HfAlO x , HfSiOx and the like. The dielectric fin layer 214 can be formed by CVD, plasma-assisted CVD, sputtering, and other suitable methods. In some embodiments, the dielectric fin layer 214 can be made of high-k materials other than metallic dielectrics.

[0017] In some embodiments, the dielectric fin layer 214 comprises an outer dielectric layer and an inner dielectric layer. The outer dielectric layer can be deposited first to cover the sidewalls of the grooves 210r, and the inner dielectric layer is then deposited over the outer dielectric layer. In some embodiments, the outer dielectric layer can consist of silicon nitride (SiN), an oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), an oxide, SiO2, Si3N4, SiOCN, or a metal oxide layer. The inner dielectric layer can be a low-k dielectric layer, for example, a silicon oxide layer.

[0018] In some embodiments, the dielectric fin layer 214 can have air gaps 216 formed therein. In some embodiments, the air gaps 216 can form because the trenches 210r have a high aspect ratio. During deposition, the opening of the trenches 210r is tightly closed before the trenches 210r are completely filled, thereby forming the air gaps 216. The air gaps 216 can be desirable because they lower the dielectric constant of the dielectric fin layer 214 and thus reduce the RC delay. Fig. Figure 4 shows an air gap 216 with an oval cross-section, which is formed in each trench 210r. However, depending on the dimensions of the trench 210r and the processes used in the deposition of the dielectric fin layer 214, more air gaps with different dimensions and shapes may be present at different locations. In some embodiments, the air gap 216 in the dielectric fin layer 214 may extend along the x-direction.

[0019] In step 108 of process 100, hybrid fins 218p, 218pn and 218n (together 218) are formed adjacent to the semiconductor fins 204, as shown in the Fig. 5 and Fig. Figure 6 shows that after filling the trenches 210r, a planarization process can be carried out to expose the semiconductor fins 204 and the insulating layer 212, as shown in Figure 6. Fig. 5 shown. Then a back-etching process is carried out to expose parts of the hybrid fins 218 and the semiconductor fins 204, as shown in Fig. 6 shown. The etching process can be carried out using a suitable anisotropic etching process to etch back the insulating layer 212 and expose parts of the semiconductor fins 204 and the hybrid fins 218.

[0020] After process 108, the semiconductor fins 204 and the hybrid fins 218 extend from the insulating layer 212. In some embodiments, after etching, the semiconductor fins 204 and the hybrid fins 218 have substantially the same height above an upper surface 212t of the insulating layer 212. In some embodiments, the semiconductor fins 204 and the hybrid fins 218 have a projecting fin height H1 above the insulating layer 212. For example, the projecting fin height H1 can be defined by the distance between an upper surface 214t of the hybrid fins 218 and the upper surface 212t of the insulating layer 212. The projecting fin height H1 can vary depending on the circuit design. In some embodiments, the height H1 of the projecting fin is in a range between about 20 nm and about 100 nm. Portions of the hybrid fins 218 are embedded in the insulating layer 212.In some embodiments, the embedded fin height Ho of the hybrid fins 218 is embedded in the insulating layer 212. For example, the embedded fin height Ho can be defined by the distance between a lower surface 214b of the hybrid fins 218 and the upper surface 212t of the insulating layer 212. The hybrid fins 218 can have a width W1 along the y-direction. The width W1 of the hybrid fins 218 can vary depending on the circuit design. In some embodiments, the width W1 lies in a range between approximately 10 nm and approximately 20 nm.

[0021] The hybrid fins 218 are essentially bar-shaped and extend along the x-direction. The hybrid fins 218 have one or more dielectric fin layers 214. One or more air gaps 216 can be formed in the hybrid fin 218. In some embodiments, the air gaps 216 are arranged in an inner volume of the hybrid fin 218 and extend along the x-direction.

[0022] The hybrid fins 218p are arranged in the p-device region 200p. The hybrid fins 218p can be arranged between two semiconductor fins 204p or adjacent to a semiconductor fin 204p. The hybrid fins 218n are arranged in the n-device region 200n. The hybrid fins 218n can be arranged between two semiconductor fins 204n or adjacent to a semiconductor fin 204n. The hybrid fin 218pn is arranged at a boundary between the n-device region 200n and the p-device region 200p. The hybrid fin 218pn is arranged between a semiconductor fin 204n and a semiconductor fin 204p.

[0023] In process 110 of procedure 100, sacrificial gate structures 226 are formed over the semiconductor fins 204, the hybrid fins 218 and the insulating layer 212, as shown in the Fig. 7 and Fig. Figure 8 shows a sacrificial gate dielectric layer 220 being conformally deposited over the semiconductor fins 204, the hybrid fins 218, and the insulating layer 212. The sacrificial gate dielectric layer 220 can contain silicon oxide, silicon nitride, a combination thereof, or the like. The sacrificial gate dielectric layer 220 can be deposited or thermally grown using suitable techniques such as thermal CVD, ALD, and other suitable methods.

[0024] A sacrificial gate electrode layer 222 is deposited on the sacrificial gate dielectric layer 220. The sacrificial gate electrode layer 222 contains silicon, for example, polycrystalline silicon, amorphous silicon, polycrystalline silicon germanium (Poly-SiGe), or the like. The sacrificial gate electrode layer 222 can be deposited using CVD, for example, LPCVD and PECVD, PVD, ALD, or other suitable processes. In some embodiments, a planarization process can be performed after the deposition of the sacrificial gate electrode layer 222.

[0025] A mask layer 224 is sequentially deposited over the sacrificial gate electrode layer 222. In some embodiments, a buffer layer (not shown) can be deposited between the mask layer 224 and the sacrificial gate electrode layer 222. The buffer layer can contain silicon nitride. The mask layer 224 can contain silicon oxide. A structuring process using one or more etching processes, such as one or more plasma etching processes or one or more wet etching processes, is performed on the mask layer 224, the buffer layer (if present), the sacrificial gate electrode layer 222, and the sacrificial gate dielectric layer 220 to form the sacrificial gate structures 226. In some embodiments, the mask layer 224 can first be structured using a structuring process. The sacrificial gate electrode layer 222 is then structured using the structured mask layer 224 as an etching mask.In some embodiments, the sacrificial gate electrode layer 222 can be etched by anisotropic etching, such as a reactive ion etching (RIE) process. Anisotropic etching exhibits a higher etch rate along the z-direction than the etch rate along the x- and y-directions. During etching of the sacrificial gate electrode layer 222, the sacrificial gate dielectric layer 220 on the semiconductor fins 204 can act as an etch stop to prevent the etchant from removing the semiconductor fins 204.

[0026] In some embodiments, after structuring the sacrificial gate electrode layer 222, any exposed portion of the remaining sacrificial gate dielectric layer 220 is removed by a suitable etching process. In some embodiments, the remaining sacrificial gate dielectric layer 220 can be etched by adjusting one or more parameters, such as the etchant, the etching temperature, the etching solution concentration, the etching pressure, the source power, the radio frequency bias (RF bias), the etchant flow rate, or the etching process for etching the sacrificial gate electrode layer 222. As described in Fig. As shown in Figure 8, the sacrificial gate structure 226 covers a section of the semiconductor fins 204 and the hybrid fins 218. The section of the semiconductor fins 204 covered by the sacrificial gate structures 226 ultimately forms a channel region in a transistor.

[0027] In process 112 of procedure 100, side wall spacers 228 are formed on side walls of the victim gate structures 226, as shown in the Fig. 8, Fig. 8A and Fig. 8B shown. Fig. 8A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 8. Fig. Figure 8B is a schematic sectional view of the semiconductor device 200 along line BB in Fig. 8.

[0028] The sidewall spacers 228 are formed on the sidewalls of each sacrificial gate structure 226. After the sacrificial gate structures 226 are formed, the sidewall spacers 228 are formed by depositing one or more layers of insulating material. After deposition of the insulating material, anisotropic etching is performed to remove portions of the insulating material from horizontal surfaces. In some embodiments, the insulating material can also be removed from the sidewalls of the semiconductor fins 204. In some embodiments, portions of the sidewall spacers 228 may remain on the sidewalls of the semiconductor fins 204 (not shown). In some embodiments, the insulating material of the sidewall spacers 228 is a silicon nitride-based material, for example, SiN, SiON, SiOCN, or SiCN, and combinations thereof. The sidewall spacers 228 can have a thickness in the range of about 4 nm to about 7 nm.

[0029] Fig. Figure 8A schematically shows a cross-sectional view of the sacrificial gate structure 226. Fig. Figure 8B schematically shows a sectional view of the hybrid fin 218pn. Fig. Figure 8B shows two additional victim gate structures 226 to illustrate the arrangement of the victim gate structures 226. As in Fig. As shown in Figure 8B, the air gap 216 in the hybrid fin 218 can extend along the x-direction through the hybrid fin 218.

[0030] In step 114 of method 100, a sacrificial spacer layer 230 is arranged over the semiconductor device 200, as shown in Fig. Figure 9 shows that the sacrificial spacer layer 230 can be a dielectric layer used to protect areas that are not processed during the subsequent source / drain formation. The sacrificial spacer layer 230 can be selected from any material with etch selectivity towards the materials of the semiconductor fins 204 and the hybrid fins 218. In some embodiments, the sacrificial spacer layer 230 comprises silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the sacrificial spacer layer 230 is formed by CVD, ALD, and / or other suitable techniques.

[0031] In step 116 of method 100, the sacrificial spacer layer 230 is structured such that the hybrid fin 218pn, which separates the n-device area 200n and the p-device area 200p, and a device area of ​​a certain type, such as the n-device area 200n or the p-device area 200p, are exposed, as shown in the Fig. 10 and Fig. Figure 11 shows that a photoresist layer 232 can be formed over the sacrificial spacer layer 230. The photoresist layer 232 is then structured and used as a mask to remove the sacrificial spacer layer 230 over the hybrid fin 218pn and a device area of ​​a specific type that is connected to the hybrid fin 218pn.

[0032] According to embodiments of the present disclosure, the hybrid fins, which are arranged between the device areas to be processed and the device areas to be covered, are exposed and etched back during the etching process of the semiconductor fins. In some embodiments, the device areas to be processed and the device areas to be covered can be device areas of different types. In other embodiments, the device areas to be processed and the device areas to be covered can be device areas of the same type. As in Fig. As shown in Figure 10A, the photoresist layer 232 is structured such that the sacrificial spacer layer 230 is exposed above the hybrid fin 218pn and the n-device area 200n. In some embodiments, the photoresist layer 232 can be structured such that part of the unmachined device area is exposed. In the Fig. 10 and Fig. 10A a small section of the unmachined fixture area, the p-fixture area 200p, is exposed through the structured photoresist layer 232. Fig. 10A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 10. In some embodiments, the exposed portion of the unmachined device area may have a width W2 along the y-direction, or a direction perpendicular to the length of the hybrid fins 218. In some embodiments, the width W2 may be in a range between approximately 0 nm and 20 nm. In some embodiments, the width W1 may be in a range between approximately 6 nm and 20 nm.

[0033] After the photoresist layer 232 is structured, the sacrificial spacer layer 230 is structured such that the n-device region 200n, the hybrid fin 218pn and part of the p-device region 200p are exposed, as shown in the Fig. 11 and Fig. Shown in 11A. Fig. 11A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 11.

[0034] In step 118 of process 100, one or more etching processes are carried out to re-etch sections of the semiconductor fins 204 and the hybrid fins 218 that are exposed by the sacrificial spacer layer 230, as shown in the Fig. 12, Fig. 12A and Fig. 12B shown. Fig. 12A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 12. Fig. Figure 12B is a schematic sectional view of the semiconductor device 200 along line BB in Fig. 12.

[0035] In some embodiments, the semiconductor fins 204n are etched to a desired depth in order to subsequently form source / drain features. In some embodiments, the semiconductor fins 204n can be recessed to a level below the upper surface 212t of the insulating layer 212, as shown in Fig. 12A shown.

[0036] The exposed hybrid fins 218n, 218pn are further etched to a depth below an upper surface 204t of the semiconductor fins 204, as originally configured. In some embodiments, the exposed hybrid fins 218n, 218pn can be etched back. As a result of the etching to deepen the surface, the hybrid fins 218n, 218pn have an upper cut surface 218nt or 218pnt and a vertical cut surface 218v. The vertical cut surface 218v is substantially flush with the sidewall spacer 228. The upper cut surface 218nt, 218pnt can be located at a projecting fin height H2 above the upper surface 212t of the insulating layer 212. The aforementioned fin height H2 can be chosen to provide a suitable height to prevent the hybrid fins 218n, 218pn from being exposed to a landing area of ​​source / drain contact features.In some embodiments, the air gaps 216 formed in the hybrid fins 218n, 218pn can be opened and exposed at the upper cut surface 218nt, 218pnt and / or the vertical cut surface 218v.

[0037] The etching can be carried out by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, etchants such as tetramethylammonium hydroxide (TMAH), CF4, CHF3, O2, H3, CH4, CH3F, HBr, He, or combinations thereof can be used to etch the materials. For example, combinations such as CH4 and Ar, Ch3F and O2, CH4, or HBr and He can be used to etch the materials. The etchant is selected so that different materials exhibit different etch rates. For example, the semiconductor material of the semiconductor fins 204n can exhibit a first etch rate by the etchant, and the hybrid fins 218pn, 218n can exhibit a second etch rate by the etchant. The composition of the etchant can be selected to achieve the target height of the semiconductor fins 204n and the hybrid fins 218n, 218pn.

[0038] In some embodiments, the sidewall spacers 228 can remain on the semiconductor fins 204 after process 112. In some embodiments, parts of the sidewall spacers 228 can remain on the insulating layer 212 after etching to recess the semiconductor fins 204. The height of the sidewall spacers 228 can be used to control the shape of the source / drain features to be formed.

[0039] In process 120, epitaxial source / drain features 234n are formed by the semiconductor fins 204n, as shown in the Fig. 13 and Fig. 13A shown. Fig. 13A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 13.

[0040] In some embodiments, a pre-cleaning process can be performed to remove all unwanted silicon oxide that has formed as a result of the oxidation of the exposed surfaces. In some embodiments, the pre-cleaning process can be performed using inductively coupled plasma of a cleaning agent. In some embodiments, the cleaning agent contains Ar, NF3, and NH3. The pre-cleaning process can be performed in a temperature range between approximately 25°C and approximately 74°C for a duration between 80 seconds and approximately 400 seconds. Alternatively, the pre-cleaning process can be performed using an RF-based gas or a SiCoNi-based gas.

[0041] The epitaxial source / drain features 234n can be formed by any suitable method, for example, by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. The epitaxial source / drain features 234n can have one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain features 234n also contain n-type dopants, for example, phosphorus (P), arsenic (As), etc. In some embodiments, the epitaxial source / drain features 234n can consist of a single Si layer containing phosphorus dopants. In some embodiments, the epitaxial source / drain features 234n have a dopant concentration of approximately 1 × 10²⁰ atoms / cm². 3 and approximately 5E21 atoms / cm² 3 on.

[0042] The shape and dimensions of the epitaxial source / drain features 234n can be controlled by adjusting processing parameters and / or the height of the sidewall spacers, if present. In some embodiments, the cross-section of the epitaxial source / drain features 234n can have a wider central section and narrower upper and lower sections, for example, an oval or hexagonal shape. In some embodiments, the widest central section can have a center height H3 along the y-direction above the upper surface 212t of the insulating layer 212. In some embodiments, the center height H3 can be greater than the height of the projecting fin H2 of the hybrid fin 218.

[0043] In process 122, the sacrificial spacer layer 230 is removed, as shown in Fig. Figure 14 shows the semiconductor fins 204p in the p-device area 200p being exposed for processing. The sacrificial spacer layer 230 can be removed by any suitable etching process.

[0044] In process 124, a sacrificial spacer layer 236 is deposited by an opaque deposition, as in Fig. Figure 15 shows that the sacrificial spacer layer 236 can be a dielectric layer used to protect areas that are not processed during subsequent machining operations. For example, the sacrificial spacer layer 236 protects the epitaxial source / drain features 234n. Similar to the sacrificial spacer layer 230, the sacrificial spacer layer 236 can be selected from silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the sacrificial spacer layer 236 is formed by CVD, ALD, and / or other suitable techniques.

[0045] In step 126 of procedure 100, the sacrificial spacer layer 236 is structured such that the p-device area 200p is exposed, as shown in the Fig. 16 and Fig. Figure 17 shows that a photoresist layer 238 is formed over the sacrificial spacer layer 236. The photoresist layer 238 is then patterned and used as a mask to remove the sacrificial spacer layer 236 over parts of the p-device region 200p, exposing the semiconductor fins 204p and the hybrid fins 218p. After the photoresist layer 238 is patterned, the pattern is transferred to the sacrificial spacer layer 236 by a suitable etching process.

[0046] In some embodiments, the hybrid fin 218pn remains covered by the sacrificial spacer layer 236 between the p-device region 200p and the n-device region 200n, as shown in Fig. 17 shown. Covering the hybrid fin 218pn ensures that the epitaxial source / drain features 234n are protected by the sacrificial spacer layer 236, especially when parts of the epitaxial source / drain features 234n extend over the hybrid fins 218pn.

[0047] In step 128 of process 100, one or more etching processes are carried out to re-etch sections of the semiconductor fins 204 and the hybrid fins 218 that are exposed by the sacrificial spacer layer 236, as shown in Fig. 18 shown.

[0048] In some embodiments, the semiconductor fins 204p are etched to a desired depth to subsequently form source / drain features. In some embodiments, the semiconductor fins 204p can be etched to a level below the upper surface 212t of the insulating layer 212. The exposed hybrid fins 218p are also etched to a depth below an upper surface 204t of the semiconductor fins 204, as originally formed. The etching can be carried out by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, the exposed hybrid fins 218p can be etched to a projecting fin height H4 above the upper surface 212t of the insulating layer 212. For example, the protruding fin height H4 can be defined by the distance between an upper cut surface 218pt of the hybrid fins 218p and the upper surface 212t of the insulating layer 212.In some embodiments, the etching for deepening may be similar to the etching process used in process 118.

[0049] In process 130 of procedure 100, epitaxial source / drain features 234p are formed by the semiconductor fins 204p, as shown in Fig. Figure 19 shows that in some embodiments, a pre-cleaning process can be performed to remove any unwanted silicon oxide that has formed as a result of the oxidation of the exposed surfaces. The epitaxial source / drain features 234p can be formed by any suitable method, for example, by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. The epitaxial source / drain features 234p can have one or more layers of Si, SiGe, or Ge with p-type dopants such as boron (B) for a p-type device such as a pFET. In some embodiments, the epitaxial source / drain features 234p can consist of SiGeB material, with boron being a dopant. In some embodiments, the epitaxial source / drain features 234p consist of a SiGeB layer with a boron concentration of about 5 × 10¹⁸ atoms / cm². 3 and about 1E21 atoms / cm² 3 .

[0050] The shape and dimensions of the epitaxial source / drain features 234p can be controlled by adjusting processing parameters and / or the height of the sidewall spacers, if present. In some embodiments, the cross-section of the epitaxial source / drain features 234p can have a wider central section and narrower upper and lower sections, for example, a hexagonal or oval shape. In some embodiments, the widest central section can have a center height H5 along the y-direction from the upper surface 212t of the insulating layer 212. In some embodiments, the widest central section occurs near the center of the semiconductor fins 204. The center height H5 is approximately 50% of the projecting fin height H1. In some embodiments, the center height H5 can be greater than the projecting fin height H4 of the hybrid fin 218p and the projecting fin height H2 of the hybrid fin 218pn.

[0051] In step 132 of procedure 100, the sacrificial spacer layer 236 is removed, as shown in Fig. Figure 20 shows the hybrid fins 218n, 218pn and 218n and the epitaxial source / drain features 234n, 234p, which are exposed for subsequent processing. The sacrificial spacer layer 236 can be removed by any suitable etching method.

[0052] In step 134 of process 100, a contact etch stop layer (CESL) 240 is deposited over the semiconductor device 200, as shown in the Fig. 21, Fig. 21A, Fig. 21B and Fig. 21C shown. Fig. 21A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 21. Fig. Figure 21B is a schematic sectional view of the semiconductor device 200 along line BB in Fig. 21. Fig. 21C is a schematic sectional view of the semiconductor device 200 along line CC in Fig. 21. The CESL 240 is conformally formed over exposed surfaces of the semiconductor device 200. As in Fig. As shown in Figure 21, the CESL 240 covers exposed surfaces of the epitaxial source / drain features 234n, 234p, the hybrid fins 218n, 218p, 218pn, the insulating layer 212, and the sidewall spacers 228. The CESL 240 can contain SiN, SiON, SiCN, or any other suitable material and can be formed by CVD, PVD, or ALD.

[0053] In some embodiments, the CESL 240 can have a thickness T1 on the exposed surfaces of the epitaxial source / drain features 234n, 234p. In some embodiments, the thickness T1 of the CESL 240 on the epitaxial source / drain features 234n, 234p can be maintained at a sufficient value to protect the epitaxial source / drain features 234n, 234p during the contact hole etching process. In some embodiments, the thickness T1 can be in a range between approximately 1 nm and approximately 10 nm.

[0054] As in the Fig. 21A and Fig. As shown in Figure 21B, air spaces or gaps 242 can form between the epitaxial source / drain features 234n, 234p and the hybrid fin 218n, 218p, 218pn, which is located adjacent to the epitaxial source / drain features 234n, 234p. The air spaces 242 are formed during the deposition of the CESL layer 240 when access to the space between the epitaxial source / drain features 234n, 234p and the hybrid fin 218n, 218p, 218pn is closed. Depending on the dimensions and shape of the epitaxial source / drain features 234n, 234p and the adjacent hybrid fins 218n, 218p and 218pn, the CESL 240 around the air spaces 242 can be thinner than the thickness T1. Alternatively, the CESL 240 can fill the space between the epitaxial source / drain features 234n, 234p and the adjacent hybrid fins 218 without forming any air spaces between them.In some embodiments, the air spaces 242 can be formed during the formation of the epitaxial source / drain features 234n, 234p, and thus no CESL material is arranged in the air spaces 242.

[0055] As in the Fig. 21A and Fig. As shown in Figure 21B, the CESL 240 can be deposited on the upper cut surface 218nt, 218pnt, 218pt and the vertical cut surface 218v of the hybrid fins 218n, 218pn, 218p. The CESL 240 can seal all air gaps 216 that are exposed on the upper cut surface 218nt, 218pnt, 218pt and the vertical cut surface 218v. Since the upper cut surfaces 218nt, 218pnt, 218pt of the hybrid fins 218 are located at a level below the widest part of the epitaxial source / drain features 234n, 234p, the portion of CESL 240 deposited on the widest part of the epitaxial source / drain features 234n is also located above the upper cut surface 218h of the hybrid fins 218. Thus, the recessed hybrid fins 218 can have additional layers (not shown) of CESL 240 for protection. In other words, the portion of CESL 240 located above the upper cut surfaces 218nt, 218pnt, 218pt can have a greater thickness than the thickness T1.For example, the CESL 240 can have a thickness T2 across the upper cut surface 218nt, 218pt, 218pt. In some embodiments, the ratio between thickness T2 and thickness T1 can range from 1.5 to 6.0. At a ratio of less than 2.0, the CESL 240 does not need to seal the air gaps 216 in the underlying hybrid fin 218 during the etching of the CESL 240 when forming the contact hole. A ratio greater than 4.0 can increase the RC delay without providing any additional benefit for sealing protection.

[0056] In some embodiments, an airspace or gap 244 can form in the area of ​​the CESL 240 above the CESL 240, depending on the dimensions and geometry of the space between the epitaxial source / drain features 234n, 234p and the hybrid fin 218pn and the deposition parameters of the CESL 240. Alternatively, an airspace 244 can be present in the CESL 240 above the hybrid fin 218.

[0057] In step 136 of process 100, an intermediate dielectric layer (ILD layer) 246 is formed over the CESL 240, as shown in Fig. Figure 22 shows that the materials for the ILD layer 246 contain compounds containing Si, O, C, and / or H, for example, silicon dioxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 246. In some embodiments, the ILD layer 246 can be formed by flowable CVD (FCVD). The ILD layer 246 protects the epitaxial source / drain features 234n and 234p during the removal of the sacrificial gate structures 226. After deposition of the ILD layer 246, a planarization process can be performed to expose the sacrificial gate structure 226 for the subsequent replacement gate process.

[0058] In step 138 of procedure 100, the sacrificial gate structure 226 is removed, thereby forming a gate cavity 226v between the side wall spacers 228, as shown in Fig. Figure 23 shows that the sacrificial gate dielectric layer 220 and the sacrificial gate electrode layer 222 are removed by one or more suitable processes such as dry etching, wet etching, or a combination thereof, so that the semiconductor fins 204 are exposed. In some embodiments, a wet etching agent such as a tetramethylammonium hydroxide (TMAH) solution is used. Fig. 23A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 23. As in Fig. As shown in 23A, the hybrid fins 218p, 218pn, 218n remain essentially with the protruding fin height H1 in the gate cavity 226v.

[0059] In process 140 of procedure 100, a replacement gate structure 252 is formed, as described in the Fig. 24, Fig. 24A, Fig. 24B and Fig. 24C shown. Fig. 24A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 24. Fig. Figure 24B is a schematic sectional view of the semiconductor device 200 along line BB in Fig. 24. Fig. 24C is a schematic sectional view of the semiconductor device 200 along line CC in Fig. 24. The replacement gate structure 252 can have a gate dielectric layer 248 and a gate electrode layer 250.

[0060] The gate dielectric layer 248 can be conformally deposited on exposed surfaces in the gate cavity 226v. The gate dielectric layer 248 can have different compositions and dimensions for n-type and p-type devices and is formed separately using structured mask layers and different deposition recipes. The gate dielectric layer 248 can comprise one or more layers of a dielectric such as silicon oxide or silicon nitride, or a high-k dielectric, other suitable dielectrics, and / or combinations thereof. Examples of high-k dielectrics include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), other suitable high-k dielectrics, and / or combinations thereof. The gate dielectric layer 248 can be formed by CVD, ALD or any suitable method.

[0061] The gate electrode layer 250 is then formed on the gate dielectric layer 248 such that the gate cavities 226v are filled. The gate electrode layer 250 can comprise one or more layers of conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 250 can be formed by CVD, ALD, electroplating, or other suitable processes. After the formation of the gate electrode layer 250, a planarization process, such as a CMP process, is performed to remove excess deposited gate electrode material and expose the top surface of the ILD layer 246.

[0062] In process 142 of procedure 100, dielectric structures 254 are formed in the substitute gate structure 252, as shown in the Fig. 25 and Fig. 25A shown. Fig. 25A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 25. The dielectric structure 254 contains a dielectric and serves to divide the gate electrode layer 250 into electrically isolated sections. In some embodiments, the dielectric structure 254 is connected to one of the hybrid fins 218, and the gate electrode layer 250 is divided into electrically isolated sections by the dielectric structure 254 and the hybrid fin 218 connected to the dielectric structure 254, as shown in Fig. 25A shown. Alternatively, the dielectric structure 254 can extend the upper surface 212t of the insulating layer 212 to the top of the replacement gate structure 252.

[0063] One or more etching processes are performed to remove portions of the gate dielectric layer 248 and the gate electrode layer 250 such that the replacement gate structure 252 is divided into two or more sections along the y-direction. The etching process can be a plasma etching process using one or more etchants such as a chlorine-containing gas, a bromine-containing gas, and / or a fluorine-containing gas. The etching process allows the gate dielectric layer 248 and the gate electrode layer 250 to be etched selectively relative to the ILD layer 246 and the CESL 240. The gate dielectric layer 248 and the gate electrode layer 250 are etched back to a level lower than the top surface 218t of the hybrid fins 218 parallel to the semiconductor fins 204.

[0064] The dielectric structure 254 is formed by filling the trenches in the substitute gate structure 252 by one or more deposition processes, followed by a planarization process that exposes the gate electrode layer 250. The dielectric structure 254 may comprise one or more layers of dielectrics. In some embodiments, the dielectric structure 254 may include silicon nitride, silicon oxynitride, silicon carbide, and the like, formed by PVD, CVD, ALD, or other suitable deposition methods.

[0065] In process 144 of method 100, contact holes 255, 256 for the epitaxial source / drain contact features 234n and / or the epitaxial source / drain contact features 234p are formed by one or more suitable structuring and etching processes, as shown in Fig. Figure 26 shows that in process 144, the contact holes 255, 256 are formed by one or more structuring and etching processes such that portions of the ILD layer 246 are removed and the CESL 240 is exposed, which covers the epitaxial source / drain features 234n, 234p to be connected. The contact holes 255, 256 can be designed to form a contact feature to a single source / drain feature or a common contact feature to connect two or more epitaxial source / drain features.

[0066] In Fig. 26 The contact hole 256 is intended to form a common contact feature for connecting the epitaxial source / drain feature 234n and the epitaxial source / drain feature 234p, which are arranged on opposite sides of the hybrid fin 218pn. In some embodiments, after process 144, parts of the CESL 240 are exposed above the epitaxial source / drain features 234n, 234p and the hybrid fin 218pn opposite the contact hole 256.

[0067] In step 146 of procedure 100, CESL 240 is removed and the epitaxial source / drain features 234n, 234p are etched back, creating a contact landing surface as shown in Fig. 27 shown.

[0068] In some embodiments, the CESL 240 can first be removed using a suitable etching process. In some embodiments, the CESL 240 can be etched by anisotropic etching. Since the hybrid fin 218pn, as described above, was etched back to a level below the widest sections of the epitaxial source / drain features 234n, 234p, the CESL 240 over the upper cut surface 218pnt of the hybrid fin 218pn has a greater thickness than the CESL 240 on other sections of the epitaxial source / drain features 234n, 234p. The thicker CESL 240 over the hybrid fin 218pn ensures that the hybrid fin 218pn remains covered by the CESL 240 after the epitaxial source / drain features 234n, 234p opposite the contact hole 256 have been exposed.

[0069] After the CESL 240 has been removed from the epitaxial source / drain features 234n, 234p, a portion of the epitaxial source / drain features 234n, 234p is removed such that contact surfaces are created in the epitaxial source / drain features 234n, 234p. In some embodiments, the epitaxial source / drain features 234n, 234p can be etched by an anisotropic etching process along the z-direction. The contact surfaces in each of the epitaxial source / drain features 234n, 234p can have a horizontal section 234nl, 234pl that is essentially parallel to the xy-plane, and various non-horizontal surfaces, depending on the location and shape of the contact hole 256 and the shape of the epitaxial source / drain features 234n, 234p. The horizontal sections 234nl, 234pl can be referred to as landing surfaces.The horizontal sections 234nl, 234pl of the epitaxial source / drain features 234n, 234p can be substantially at the same level in the z-direction. The level of the horizontal sections 234nl, 234pl can be selected to obtain enlarged contact areas. In some embodiments, the horizontal sections 234nl, 234pl, i.e., the landing surface, can be located at a landing height H6 above the upper surface 212t of the insulating layer 212. In some embodiments, the landing height H6 of the landing surface is higher than the projecting fin height H4 of the recessed hybrid fin 218pn, 218p, 218n. In some embodiments, the landing height H6 of the landing surface can be higher than the midpoint height H5 of the widest section of the epitaxial source / drain features 234n, 234p.

[0070] In process 148 of procedure 100, source / drain contact features 260, 262 are formed in the contact holes 255, 256, as shown in the Fig. 28, Fig. 28A, Fig. 28B and Fig. 28C shown. Fig. 28A is a schematic sectional view of the semiconductor device 200 along line AA in Fig. 28. Fig. Figure 28B is a schematic sectional view of the semiconductor device 200 along line BB in Fig. 28. Fig. 28C is a schematic sectional view of the semiconductor device 200 along line CC in Fig. 28.

[0071] In some embodiments, a silicide layer 258 is selectively formed over an exposed surface of the epitaxial source / drain features 234n, 234p, which is exposed through the source / drain contact holes. In some embodiments, the silicide layer 258 is formed on the contact surfaces. In some embodiments, the silicide layer 258 contains WSi, CoSi, NiSi, TiSi, MoSi and / or TaSi.

[0072] The source / drain contact features 260, 262 are then formed by filling the contact holes 255, 256 with a conductive material. In some embodiments, the conductive material layer for the gate contact can be formed by CVD, PVD, plating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact features 260, 262 comprises TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, or the like. Subsequently, a CMP process is performed to remove a portion of the conductive material layer above an upper surface of the ILD layer 246.

[0073] As in Fig. As shown in Figure 28A, the source / drain contact feature 260, which is associated with the epitaxial source / drain features 234p and 234n, can have a lower surface 260b having at least three sections 260bn, 260bp, and 260bh. Section 260bn is in contact with the epitaxial source / drain feature 234n, section 260bp is in contact with the epitaxial source / drain feature 234p, and section 260bh is located above the hybrid fin 218pn. Section 260bh can be in contact with a section of the CESL 240 located between section 260bp and the hybrid fin 218pn. In some embodiments, section 260bh is located at a level below sections 260bn and 260bp.

[0074] As in Fig. As shown in Figure 28B, the hybrid fin 218pn, which is located between the epitaxial p-source / drain feature 234p and the epitaxial n-source / drain feature 234n, has two height levels. In some embodiments, the hybrid fin 218pn below the gate has a first projecting fin height H1 from the upper surface 212t of the insulating layer 212. Outside the gate structure, the hybrid fin 218pn has a second projecting height H4 from the upper surface 212t of the insulating layer 212. The hybrid fin 218pn is taller below the gate structure and shorter outside the gate structure, or the first projecting height is greater than the second projecting height. In some embodiments, the upper cut surface 218pnt is lower than the center point of the semiconductor fin 204 or the widest section of the epitaxial source / drain feature 234. In some embodiments, the second height is less than 50% of the first height.Since the upper cut surface 218pnt of the hybrid fin 218pn is lower than the center point of the semiconductor fin 204, the contact hole for the source / drain contact feature, for example, the source / drain contact feature 260, does not expose the hybrid fin 218pn. As a result, conductive material cannot fill air gaps in the hybrid fin 218pn when the contact hole is filled with conductive material.

[0075] The section of the hybrid fin 218 below the gate structure and the section of the hybrid fin 218 outside the gate structure are connected via the vertical cut surfaces 218v. The vertical cut surfaces 218v of the hybrid fin 218 are in contact with the CESL 240. The hybrid fin 218pn outside the gate structure is defined by the upper cut surface 218pnt. In some embodiments, the upper cut surface 218pnt is in contact with the CESL 240. In some embodiments, the section of the CESL 240 on the hybrid fin 218pn has a thickness greater than that of the CESL 240 on the epitaxial source / drain features 234n, 234p. In some embodiments, as in Fig. 28B shows an airspace in CESL 240 above the hybrid fins 218pn.

[0076] The Fig. 29, Fig. 29A, Fig. 29B and Fig. Figure 29C schematically shows a semiconductor device 200a according to the present disclosure. The semiconductor device 200a is essentially similar to the semiconductor device 200 of the Fig. 28, except that there is no airspace in CESL 240. The semiconductor device 200a can be manufactured similarly to the semiconductor device 200 using method 100.

[0077] The Fig. Figures 30-33 show various stages of a semiconductor device 200b according to embodiments of the present disclosure. The semiconductor device 200b can be fabricated using the method 100 described above. The semiconductor device 200b resembles the semiconductor device 200 with epitaxial source / drain features but a different shape. Fig. Figure 30 is a schematic perspective view of the semiconductor device 200b after procedure 132. As in Fig. As shown in Figure 30, the epitaxial source / drain features 234p, 234n are not extended over the hybrid fin 218. Fig. Figure 31 is a schematic perspective view of the semiconductor device 200b after process 134, in which the CESL 240 is deposited. Since the epitaxial source / drain features 234p, 234n are located further away from the upper cut surface 218pnt of the hybrid fin 218pn, the CESL 240 formed thereon has only a single thickness T1.

[0078] Fig. Figure 32 is a schematic perspective view of the semiconductor device 200b after process 144, in which the ILD layer 246 is removed to form the contact holes 255, 256. The ILD layer 246 is removed to a level 246h at a height H7 above the upper cut surface 218pnt of the hybrid fin 218pn. The height H7 is a thickness sufficient to protect the CESL 240 during process 148. In some embodiments, the height H7 is in a range between approximately 10 nm and 30 nm.

[0079] Fig. Figure 33 is a schematic perspective view of the semiconductor device 200b after process 148, in which the source / drain contact features 260 and 262 are formed. Fig. 33A is a sectional view of the semiconductor device 200b along line AA of Fig. 33. Fig. Figure 33B is a sectional view of the semiconductor device 200b along line BB of Fig. 33.

[0080] As in Fig. As shown in Figure 33, section 260bh of the lower surface 260b of the source / drain contact feature 260 is located above the hybrid fin 218pn. Section 260bh is in contact with the section of the ILD layer 246 that is located between section 260bp and the hybrid fin 218pn.

[0081] As in Fig. As shown in Figure 33A, the hybrid fin 218pn, which is located between the epitaxial p-source / drain feature 234p and the epitaxial n-source / drain feature 234n, has two height levels. In some embodiments, the hybrid fin 218pn is longer or taller below the gate structure and shorter outside the gate structure. The vertical cut surfaces 218v of the hybrid fin 218 are in contact with the CESL 240. In some embodiments, the upper cut surface 218pnt is in contact with the CESL 240. In some embodiments, the section of the CESL 240 on the hybrid fin 218pn has substantially the same thickness as the CESL 240 on the epitaxial source / drain features 234n and 234p.

[0082] The Fig. Figures 34-40 show various stages of a semiconductor device 200c according to an embodiment of the present disclosure. The semiconductor device 200c can be fabricated without the use of back-etching the hybrid fin 218pn, which is arranged between the n-device region 200n and the p-device region 200p, during the formation of the epitaxial source / drain features 234n, 234p.

[0083] Fig. Figure 34 is a schematic perspective view of the semiconductor device 200c during process 116, in which the photoresist layer 232 is structured to expose the n-device area 200n for further processing. As shown in Fig. As shown in Figure 34, the photoresist layer 232 is structured such that the sacrificial spacer layer 230 is exposed over the n-device region 200n, while the hybrid fin 218pn is not exposed.

[0084] Fig. Figure 35 is a schematic perspective view of the semiconductor device 200c after procedure 132. The hybrid fin 218pn retains the original protruding fin height H1. Fig. Figure 36 is a schematic perspective view of the semiconductor device 200c after process 134, in which the CESL 240 is positioned over the exposed surfaces. The hybrid fin 218pn is covered by the CESL 240.

[0085] Fig. Figure 37 is a schematic perspective view of the semiconductor device 200b after process 144, in which the ILD layer 246 is removed to form the contact holes 255, 256. The ILD layer 246 is etched back to level 246h. The hybrid fin 218pn, together with the CESL 240, extends partially beyond level 246h.

[0086] Fig. Figure 38 is a schematic perspective view of the semiconductor device 200c after process 146, in which an etching process is carried out such that the exposed CESL 240 is removed, thus exposing the epitaxial source / drain features 234n, 234p. During the removal of the CESL 240, the hybrid fin 218pn can also be partially etched down to an upper cut surface 218pnt', thereby exposing the air gaps 216.

[0087] According to embodiments of the present disclosure, a deposition process followed by a etching process can be carried out after process 146 and before process 148 to fill the air gap 216 in the hybrid fin 218pn with a dielectric filling material 264, as shown in Fig. Figure 39 shows. In some embodiments, the dielectric filling material 264 can consist of silicon nitride (SiN), an oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), an oxide, SiO2, Si3N4, SiOCN, and the like. In some embodiments, the dielectric filling material 264 can contain a high-k dielectric, for example, a metal oxide such as HfO2, ZrO2, or HfAlO. x , HfSiO x and the like. The dielectric filling material 264 can be formed by processes used to form such a layer, for example CVD, plasma-assisted CVD, sputtering or other suitable processes for filling or at least partially filling the air gaps 216.

[0088] Following the deposition process, an etching process is performed to remove excess dielectric filler material 264 from outside the air gaps 216. Any suitable etching method can be used to remove the excess dielectric filler material 264.

[0089] In some embodiments, an over-etching process can be carried out on the epitaxial source / drain features 234n, 234p to produce contact surfaces in the epitaxial source / drain features 234n, 234 for the processes in operation 148.

[0090] Fig. Figure 40 is a schematic perspective view of the semiconductor device 200c after process 148, in which the source / drain contact features 260 and 262 are formed. Fig. 40A is a sectional view of the semiconductor device 200b along line AA of Fig. 40. Fig. 40B is a sectional view of the semiconductor device 200b along line BB of Fig. 40.

[0091] As in Fig. As shown in Figure 40, an upper section of the hybrid fin 218pn extends from section 260bh of the lower surface 260b into the source / drain contact feature 260. The exposed air gaps in the hybrid fin 218pn are filled with the dielectric filler material 264. The upper section of the hybrid fin 218pn is in direct contact with the source / drain contact feature 260. Since the air gaps on the surfaces of the hybrid fin 218pn are filled with the dielectric filler material 264, the dielectric filler material 264 prevents the conductive material from entering the interior of the hybrid fin 218pn, particularly the inner section beneath the gate structures.

[0092] By deepening sections of hybrid fins located between two different epitaxial source / drain features, embodiments of the present disclosure prevent conductive material from entering internal air gaps of the hybrid fin, thereby preventing a short circuit between source / drain contacts and gate electrodes. Deepening the hybrid fins can be achieved by enlarging the mask during the back-etching of the semiconductor fins, without increasing production costs.

[0093] It is understood that not all advantages have necessarily been described herein; no particular advantage is required in all embodiments or examples, and other embodiments or examples may offer other advantages.

[0094] Some embodiments of the present disclosure provide a semiconductor device comprising an insulating layer with an upper surface; a first epitaxial source / drain feature extending from the insulating layer across its upper surface, the first epitaxial source / drain feature serving an n-type device; a second epitaxial source / drain feature extending from the insulating layer across its upper surface, the second epitaxial source / drain feature serving a p-type device; a hybrid fin arranged between the first epitaxial source / drain feature and the second epitaxial source / drain feature, the hybrid fin having a first end embedded in the insulating layer and a second end extending across the upper surface of the insulating layer;and a source / drain contact feature that is in contact with the first and second epitaxial source / drain features on a lower surface, the lower surface of the source / drain contact feature being located above the second end of the hybrid fin.

[0095] Some embodiments of the present disclosure provide a semiconductor device comprising a first semiconductor fin; a second semiconductor fin; a first epitaxial source / drain feature in electrical contact with the first semiconductor fin, wherein the first epitaxial source / drain feature is doped with n-type dopants; a second epitaxial source / drain feature in electrical contact with the second semiconductor fin, wherein the second epitaxial source / drain feature is doped with p-type dopants; a hybrid fin arranged between the first and second semiconductor fins and the first and second epitaxial source / drain features;and a gate structure arranged above the first semiconductor fin, the second semiconductor fin and the hybrid fin, wherein the hybrid fin has a first upper surface below the gate structure and a second upper surface between the first and the second epitaxial source / drain feature, and wherein the second upper surface is lower than the first upper surface.

[0096] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising forming a first semiconductor fin, a second semiconductor fin, and a hybrid fin between the first and second semiconductor fins; etching to deepen the first semiconductor fin and the hybrid fin while the second semiconductor fin is covered with a first mask; forming a first epitaxial source / drain feature associated with the first semiconductor fin and doping the first epitaxial source / drain feature with n-type dopants; etching to deepen the second semiconductor fin while the hybrid fin and the second semiconductor fin are covered with a second mask; and forming a second epitaxial source / drain feature associated with the second semiconductor fin and doping the second epitaxial source / drain feature with p-type dopants.

Claims

[1] Semiconductor device (200), comprising: an insulating layer (212) with an upper surface; a first epitaxial source / drain feature (234, 234n, 234p) extending from the insulating layer (212) across its upper surface; a second epitaxial source / drain feature (234, 234n, 234p) extending from the insulating layer (212) across its upper surface; a hybrid fin (218, 218p, 218n, 218pn) arranged between the first epitaxial source / drain feature (234, 234n, 234p) and the second epitaxial source / drain feature (234, 234n, 234p), wherein the hybrid fin (218, 218p, 218n, 218pn) has a first end embedded in the insulating layer (212) and a second end extending over the upper surface of the insulating layer (212); a source / drain contact feature (260) in electrical contact on a lower surface with the first and second epitaxial source / drain features (234, 234n, 234p), wherein the lower surface of the source / drain contact feature (260) lies above the second end of the hybrid fin (218, 218p, 218n, 218pn); and a gate structure located next to the first epitaxial source / drain feature (234, 234n, 234p) and the second epitaxial source / drain feature (234, 234n, 234p), wherein the hybrid fin (218, 218p, 218n, 218pn) extends under the gate structure and an upper surface of a section of the hybrid fin (218, 218p, 218n, 218pn) under the gate structure is higher than an upper surface of the second end of the hybrid fin (218, 218p, 218n, 218pn). [2] Semiconductor device (200) according to claim 1, further comprising: a contact etch stop layer (240) that is arranged between the lower surface of the source / drain contact feature (260) and the second end of the hybrid fin (218, 218p, 218n, 218pn). [3] Semiconductor device (200) according to claim 2, wherein the contact etch stop layer (240) is in contact with the second end of the hybrid fin (218, 218p, 218n, 218pn). [4] Semiconductor device (200) according to claim 3, wherein the contact etch stop layer (240) is in contact with the lower surface of the source / drain contact feature (260). [5] Semiconductor device (200) according to claim 3, which further comprises an intermediate dielectric layer (246) between the lower surface of the source / drain contact feature (260) and the contact etch stop layer (240). [6] Semiconductor device (200) according to one of the preceding claims, wherein the first epitaxial source / drain feature (234, 234n, 234p) has a first height from the top surface of the insulating layer (212), the second end of the hybrid fin (218, 218p, 218n, 218pn) has a second height from the top surface of the insulating layer (212) and the second height is less than 50% of the first height. [7] Semiconductor device (200) according to one of the preceding claims, wherein the first epitaxial source / drain feature (234, 234n, 234p) serves for an n device and the second epitaxial source / drain feature (234, 234n, 234p) serves for a p device. [8] Semiconductor device (200), comprising: a first semiconductor fin (204, 204n, 204p); a second semiconductor fin (204, 204n, 204p); a first epitaxial source / drain feature (234, 234n, 234p) associated with the first semiconductor fin (204, 204n, 204p); a second epitaxial source / drain feature (234, 234n, 234p) connected to the second semiconductor fin (204, 204n, 204p); a hybrid fin (218, 218p, 218n, 218pn) positioned between the first and second semiconductor fins (204, 204n, 204p) and the first and second epitaxial source / drain feature (234, 234n, 234p); and a gate structure arranged above the first semiconductor fin (204, 204n, 204p), the second semiconductor fin (204, 204n, 204p) and the hybrid fin (218, 218p, 218n, 218pn), wherein the hybrid fin (218, 218p, 218n, 218pn) has a first upper surface below the gate structure and a second upper surface between the first and second epitaxial source / drain feature (234, 234n, 234p), and wherein the second upper surface is lower than the first upper surface. [9] Semiconductor device (200) according to claim 8, wherein the first upper surface is arranged at a first height of an upper surface of an insulating layer (212), the second upper surface is arranged at a second height of the upper surface of the insulating layer (212) and the second height is less than 50% of the first height. [10] Semiconductor device (200) according to claim 8 or 9, comprising a contact etch stop layer (240) arranged on the first and second epitaxial source / drain feature (234, 234n, 234p) and the hybrid fin (218, 218p, 218n, 218pn) between the first and second epitaxial source / drain feature (234, 234n, 234p). [11] Semiconductor device (200) according to claim 10, further comprising a source / drain contact feature (260) arranged on the first and second epitaxial source / drain features (234, 234n, 234p), wherein a section of the contact etch stop layer (240) is arranged between the source / drain contact feature (260) and the hybrid fin (218, 218p, 218n, 218pn). [12] Semiconductor device (200) according to claim 11, which further comprises an interlayer dielectric layer (246), wherein a section of the interlayer dielectric layer (246) is arranged over the contact etch stop layer (240) and the source / drain contact. [13] Semiconductor device (200) according to any one of claims 8 to 12, wherein the hybrid fin (218, 218p, 218n, 218pn) comprises: a dielectric fin layer (214) with one or more air gaps (216); and a dielectric filling layer arranged in one or more air gaps (216). [14] Method (100) for manufacturing a semiconductor device (200), comprising: Forming a first semiconductor fin (204, 204n, 204p), a second semiconductor fin (204, 204n, 204p) and a hybrid fin (218, 218p, 218n, 218pn) between the first and second semiconductor fin (204, 204n, 204p); Covering (110) the hybrid fin (218, 218p, 218n, 218pn) in a first area with a sacrificial gate structure (226); Etching to deepen (118) the first semiconductor fin (204, 204n, 204p) and the hybrid fin (218, 218p, 218n, 218pn) in a second region, while the second semiconductor fin (204, 204n, 204p) is covered with a first mask, so that the hybrid fin (218, 218p, 218n, 218pn) has a first top surface in the first region and a second top surface in the second region, wherein the second top surface is lower than the first top surface; Forming (120) a first epitaxial source / drain feature (234, 234n, 234p) that is connected to the first semiconductor fin (204, 204n, 204p); Etching to deepen the second semiconductor fin (204, 204n, 204p), while the hybrid fin (218, 218p, 218n, 218pn) and the second semiconductor fin (204, 204n, 204p) are covered with a second mask; and Forming a second epitaxial source / drain feature (234, 234n, 234p) that is connected to the second semiconductor fin (204, 204n, 204p). [15] Method (100) according to claim 14, further comprising: Deposition of a contact etch stop layer (240) over the first and second epitaxial source / drain feature (234, 234n, 234p) and the hybrid fin (218, 218p, 218n, 218pn); and Deposition of an intermediate dielectric layer (246) over the contact etch stop layer (240). [16] Method (100) according to claim 15, further comprising: Formation of a contact hole (256) in the interlayer dielectric layer (246) over the first and second epitaxial source / drain feature (234, 234n, 234P). [17] Method (100) according to claim 16, further comprising: Etching of the contact etch stop layer (240) from the first and second epitaxial source / drain feature (234, 234n, 234P). [18] Method (100) according to any one of claims 14 to 17, wherein forming the first semiconductor fin (204, 204n, 204p), the second semiconductor fin (204, 204n, 204p) and the hybrid fin (218, 218p, 218n, 218pn) comprises forming the first semiconductor fin (204, 204n, 204p), the second semiconductor fin (204, 204n, 204p) and the hybrid fin (218, 218p, 218n, 218pn) to a first projecting height from an upper surface of an insulating layer (212). [19] Method (100) according to claim 18, further comprising: forming a gate structure over the first semiconductor fin (204, 204n, 204p), the second semiconductor fin (204, 204n, 204p) and the hybrid fin (218, 218p, 218n, 218pn). [20] Method (100) according to claim 18 or 19, wherein the deep etching of the first semiconductor fin (204, 204n, 204p) and the hybrid fin (218, 218p, 218n, 218pn) comprises deepening the hybrid fin (218, 218p, 218n, 218pn) to a second projecting height from the upper surface of the insulating layer (212), wherein the second projecting height is less than 50% of the first projecting height.

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