USE OF DATALATCHES TO COMPRESS SOFTBIT DATA IN NON-VULNERABLE STORAGE

Abstract

Non-volatile storage device comprising: a control circuit configured to connect to a plurality of bit lines, each of which is connected to a corresponding plurality of memory cells, wherein the control circuit comprises the following: a plurality of sensing amplifiers (230), each configured to read data from the memory cells connected by one or more corresponding bit lines; a plurality of sets of internal data latches (340, 342, 344, 346), each set of internal data latches (340, 342, 344, 346) being configured to store data connected to a corresponding sensing amplifier (230); and an input / output interface configured to provide data for an external data bus (334), the control circuit is set up to: to perform a read operation through each of the sensing amplifiers (230) on a plurality of memory cells; to store the results of the reading operation by each of the sensing amplifiers (230) in the corresponding set of internal data latches (340, 342, 344, 346); to compress the results of the reading operation by each of the sensing amplifiers (230) within the corresponding set of internal data latches (340, 342, 344, 346); and to transfer the compressed results of the read operation via the input / output interface to the external data bus (334); and a cache buffer (1507) which has a plurality of sets of transfer data latches, each corresponding to one of the sets of internal data latches (340, 342, 344, 346), wherein, in order to transmit the compressed results of the reading operation via the input-output interface to the external data bus (334), the control circuit is further configured to: to transfer the compressed results of the read operation from each of the sets of internal data latches (340, 342, 344, 346) to a corresponding set of transfer data latches; to compress the results of the read operation from the sets of transfer data latches into a smaller number of sets of transfer latches; and to transfer the compressed results of the read operation to the input-output interface before transferring the compressed results of the read operation to the external data bus (334).

Description

PRIORITY CLAIM

[0001] The present application is a partial continuation of US patent application No. 17 / 557,236 entitled “Efficient sensing of Soft Bit Data for Non-Volatile Memory” by Hsu, filed on December 21, 2021, which in turn claims priority over preliminary US patent application No. 63 / 244,951 entitled “Plane Level Vertical Compression Scheme” by Hsu et al., filed on September 16, 2021. BACKGROUND

[0002] The present disclosure relates to non-volatile storage.

[0003] The use of semiconductor memory in various electronic devices such as mobile phones, digital cameras, PDAs, medical electronics, mobile computing devices, servers, solid-state drives, stationary computing devices, and other equipment is widespread. Semiconductor memory can be either non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when the memory is not connected to a power source (such as a battery). An example of non-volatile memory is flash memory (e.g., NAND and NOR flash memory).

[0004] Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back. For example, a digital camera can take a photo and store it in non-volatile memory. Later, a user of the digital camera can view the photo by reading it from the non-volatile memory. Because users often rely on the stored data, it is important for users of non-volatile memory that the data can be stored reliably so that it can be successfully retrieved.

[0005] Publication US 2017 / 0046220A1 relates to data storage devices and, in particular, to the use of soft bits during the operation of data storage devices.

[0006] Publication US 2005 / 0114600A1 relates to computer systems and, in particular, to buses used for data transmission in a processor chip.

[0007] Document US 2020 / 0366314A1 relates to a device and method for compressing compressed and uncompressed data blocks into an output buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Elements with the same number refer to common components in the different figures. Fig. Figure 1 is a block diagram showing one embodiment of a storage system. Fig. 2A is a block diagram of an embodiment of a memory chip. Fig. 2B is a block diagram of an embodiment of an integrated memory assembly. Fig. 3 represents a switching logic used to sensing data from non-volatile memory. Fig. Figure 4 is a perspective view of a section of an embodiment of a monolithic three-dimensional storage structure. Fig. 4A is a block diagram of an embodiment of a two-level memory structure. Fig. Figures 4B-4G show further details of the embodiment of Fig. 4. Fig. 5A-5F represent examples of threshold voltage distributions. Fig. Figure 6 is a flowchart that describes one embodiment of a process for programming non-volatile memory. Fig. Figure 7 illustrates the overlap of the distribution of two adjacent data states and a set of read values ​​that can be used to determine the data state of a cell and the reliability of such a read operation. Fig. Figure 8 illustrates the concept of hard bits and soft bits. Fig. 9A and Fig. Figure 9B illustrates the read levels for calculating hard bit and soft bit values ​​for the lower side of the data in an embodiment with three data bits per memory cell. Fig. Figure 10 illustrates the mapping of hard bit and soft bit values ​​and the reading levels used in one embodiment for efficient soft sensing. Fig. Figure 11 illustrates the application of the efficient soft-sensing mode to lower page data in an embodiment with three data bits per memory cell using the encoding of Table 2. Fig. Figure 12 illustrates an embodiment for the sensing operations for the reading of the lower page data in an efficient soft-sensing read operation, according to the one described in Fig. 11 illustrated reading points. Fig. Figure 13 illustrates an embodiment of a sensing amplifier circuit that can be used to determine the hard bit and soft bit values ​​of a memory cell. Fig. Figure 14 is a flowchart for one embodiment of an efficient soft-sensing process. Fig. Figure 15 is a block diagram of an embodiment for some of the control circuit elements of a storage device, including a soft bit compression element. Fig. 16, Fig. 17A and Fig. Section 17B provides further details of the embodiments for the data latches that can be used in the soft bit data compression process. Fig. 18 and Fig. 19 illustrate two embodiments for compressing the original softbit data from one set of internal data latches to another set of data latches. Fig. Figure 20 illustrates a rearrangement of the compressed soft bit data within the internal data latches. Fig. Figure 21 illustrates a transfer within the transfer latches for the compression of the compressed data. Fig. Figure 22 is a schematic representation of the rearrangement of the compressed data bits into a logical sequence. Fig. Figure 23 is a block diagram of an alternative embodiment for some of the elements of the control circuit of a storage device that includes a soft bit compression element. Fig. 24A and Fig. Figure 24B is a schematic representation of an alternative embodiment of rearranging the compressed data bits into a logical sequence using the embodiment of Fig. 23. Fig. Figure 25 is a flowchart for an embodiment of carrying out data compression with the data latches connected to the sensing amplifiers of a non-volatile storage device. DETAILED DESCRIPTION

[0009] Some storage systems employ error correction procedures that include "soft bit" data. Soft bit data provides information about the reliability of the standard, or "hard bit," data values ​​used to distinguish between data states. For example, if the data values ​​are based on memory cell threshold voltages, a hard bit read would determine whether a memory cell's threshold voltage is above or below a data read value to differentiate between stored data states. For memory cells with a threshold voltage that is only slightly above or below this reference value, this hard bit might be incorrect because the memory cell should actually be in the other data state.To identify memory cells whose threshold voltage is close to the hard bit read level, and which consequently have less reliable hard bit values, a pair of additional read operations can be performed, shifted slightly above and slightly below the hard bit read level, to generate soft bit values ​​for the hard bit values. Using soft bits can be a powerful tool for extracting the data contents of memory cells. However, because additional read operations are required to obtain the soft bit data, which then needs to be transferred to the error correction switching logic, it is generally only used when the data cannot be accurately determined from the hard bit values ​​alone.

[0010] The following describes an efficient soft-sensing read mode that requires fewer read operations to generate soft-bit data and produces less soft-bit data overall. This reduces the performance and power consumption losses typically associated with using soft-bit data, allowing the efficient soft-sensing mode to be used as the standard read mode. Compared to a conventional hard-bit-soft-bit arrangement, the hard-bit read point is shifted so that the hard-bit value is reliable for one of the memory cell's data states, while the hard-bit for the other data state contains a larger number of unreliable hard-bit values. A single soft-bit read operation is performed to provide reliability information for the less reliable hard-bit value, but not for the more reliable one, thus reducing both the number of read operations and the amount of resulting data.To further improve performance, both hard bit sensing and soft bit sensing can be combined in a single sensing process, such as by preloading a node of a sensing amplifier and discharging it once through a selected memory cell, with the resulting stage for the single discharge being measured twice at the node, once for a hard bit value and once for a soft bit value.

[0011] To further reduce the amount of data that needs to be transferred from storage to the controller and to improve the performance of the storage system, the soft bit data can be compressed before transmission. After the soft bit data is read and stored in the internal data latches connected to the sensing amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transmission data latches of a cache buffer, where the compressed soft bit data is consolidated and output via an input / output interface. Within the input / output interface, the compressed data can be reordered, if necessary, to bring it into the logical order of the user data.

[0012] The components of the in Fig. The storage system 100 shown in Figure 1 consists of electrical circuits. The storage system 100 includes a memory controller 120, which is connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The local high-speed volatile memory 140 is used by the memory controller 120 to perform certain functions. For example, the local high-speed volatile memory 140 stores tables for translating logical addresses to physical addresses (“L2P tables”).

[0013] The storage controller 120 has a host interface 152 that is connected to and communicates with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) over PCI Express (PCle). Other interfaces, such as SCSI, SATA, etc., can also be used. The host interface 152 is also connected to a network-on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit. NOCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies network theory and techniques to on-chip communications, providing significant improvements over traditional bus and crossbar connections. An NOC improves the scalability of systems-on-a-chip (SoCs) and the power efficiency of complex SoCs compared to other designs.The wires and connections of the NOC are shared by many signals. High parallelism is achieved because all connections in the NOC can work on different data packets simultaneously. Therefore, as the complexity of integrated subsystems increases, an NOC provides improved performance (such as throughput) and scalability compared to earlier communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The processor 156, the ECC engine 158, the memory interface 160, and the DRAM controller 164 are connected to and communicate with the NOC 154. The DRAM controller 164 is used to work with and communicate with a local high-speed volatile memory 140 (e.g., DRAM).In other embodiments, the local high-speed volatile memory 140 can be an SRAM or another type of volatile memory.

[0014] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technique. In one embodiment, the ECC engine 158 is an electrical circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a custom and dedicated hardware circuit without any software. In yet another embodiment, the function of the ECC engine 158 is implemented by the processor 156.

[0015] The Processor 156 performs various control memory operations such as programming, erasing, reading, and memory management processes. In one embodiment, the Processor 156 is programmed by firmware. In other embodiments, the Processor 156 is a custom, dedicated hardware circuit without any software. The Processor 156 also implements a translation module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory within the storage system is addressed using physical addresses associated with one or more memory chips. However, the host system uses logical addresses to address the different memory locations. This allows the host to assign data to consecutive logical addresses, while the storage system can freely store the data at any location on the one or more memory chips.To implement this system, the memory controller 120 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory chips. One example implementation involves maintaining tables (i.e., the L2P tables mentioned above) that identify the current translation between logical and physical addresses. An entry in the L2P table can include an identification of a logical address and its corresponding physical address. Although tables containing a logical address-to-physical address mapping (or L2P tables) include the word "tables," they need not actually be tables. Rather, the tables containing a logical address-to-physical address mapping (or L2P tables) can be any type of data structure.In some examples, the storage capacity of a storage system is so large that the local memory 140 cannot hold all the L2P tables. In such a case, the entire set of L2P tables is stored in a memory chip 130, and a subset of the L2P tables is cached in the local volatile high-speed memory 140 (L2P cache).

[0016] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a toggle-mode interface. Other interfaces can also be used. In some exemplary implementations, the memory interface 160 (or another section of the controller 120) implements a scheduler and buffer for transferring data to and receiving data from one or more memory chips.

[0017] In one embodiment, the non-volatile memory 130 comprises one or more memory chips. Fig. Figure 2A is a functional block diagram of an embodiment of a memory chip 200 comprising a non-volatile memory 130. Each of the one or more memory chips of the non-volatile memory 130 can be designated as a memory chip 200. Fig. 2A will be implemented. The in Fig. The components shown in Figure 2A are electrical circuits. The memory chip 200 includes a memory array 202, which can have non-volatile memory cells, as described in more detail below. The array connection lines of the memory array 202 include the various layer(s) of word lines, organized as rows, and the various layer(s) of bit lines, organized as columns. However, other orientations can also be implemented. The memory chip 200 includes a row control logic 220, the outputs 208 of which are connected to the respective word lines of the memory array 202.The line control logic 220 receives a group of M line address signals and one or more different control signals from the system control logic circuit 260 and can typically include such circuits as line decoders 222, array connection drivers 224, and block selection logic 226 for both read and write (programming) operations. The line control logic 220 can also include read / write logic. The memory chip 200 also includes column control logic 210, including sensing amplifier(s) 230, whose inputs / outputs 206 are connected to corresponding bit lines of the memory array 202. Although only a single block for the array 202 is shown, a memory chip can include multiple arrays that can be accessed individually.The column control switching logic 210 receives a group of N column address signals and one or more different control signals from the system control logic 260 and can typically include such circuits as column decoders 212, array connection receivers or driver circuits 214, block selection switching logic 216, as well as read / write switching logic and I / O multiplexers.

[0018] The system control logic 260 receives data and instructions from the memory controller 120 and provides output data and a status to the host. In some embodiments, the system control logic 260 (which comprises one or more electrical circuits) includes a state machine 262, which provides chip-level control of memory operations. In one embodiment, the state machine 262 is software-programmable. In other embodiments, the state machine 262 does not use software and is fully implemented in hardware (e.g., electrical circuits). In yet another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor, either on or off the memory chip.The system control logic 260 can also include a power control module 264, which controls the power and voltages supplied to the rows and columns of the memory structure 202 during memory operations, and can include charge pumps and a control circuit for generating control voltages. The system control logic 260 includes a memory 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for the operation of the memory array 202.

[0019] Commands and data are transferred between the memory controller 120 and the memory chip 200 via the memory controller interface 268 (also referred to as the "communication interface"). The memory controller interface 268 is an electrical interface for communication with the memory controller 120. Examples of the memory controller interface 268 include a toggle-mode interface and an Open NAND Flash (ONFI) interface. Other I / O interfaces may also be used.

[0020] In some embodiments, all elements of the memory chip 200, including the system control logic 360, can be configured as part of a single chip. In other embodiments, part or all of the system control logic 260 can be configured on a separate chip.

[0021] In one embodiment, the memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory layers are formed on a single substrate, such as a wafer. The memory structure can incorporate any type of non-volatile memory monolithically formed in one or more physical layers of memory cells, each with an active region arranged on a silicon (or other type) substrate. In one example, the non-volatile memory cells comprise vertical NAND chains with charge-trapping layers.

[0022] In another embodiment, the memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

[0023] The precise type of memory array architecture or memory cell enclosed in memory structure 202 is not limited to the preceding examples. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No specific non-volatile memory technology is required for the purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM (resistive random-access memory), magnetoresistive memory (e.g., MRAM, spin-transfer-torque MRAM, spin-orbit-torque MRAM), FeRAM, phase-change memory (e.g., PCM), and the like.Examples of suitable technologies for the memory cell architectures of memory structure 202 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0024] An example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in crosspoint arrays, accessed via X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element can be used as a state-change element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes.As the temperature increases, so does the mobility of the ions, which causes the programming threshold for the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element can exhibit a wide range of programming thresholds across a range of temperatures.

[0025] Another example is magnetoresistive random-access memory (MRAM), which stores data using magnetic memory elements. The elements are formed from two ferromagnetic layers separated by a thin insulating layer, each capable of holding a magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match that of an external field for storing data. A memory device is constructed from a grid of such memory cells. In one programmable embodiment, each memory cell is situated between a pair of write lines arranged parallel to the cell at right angles to each other, one above and one below the cell. When current flows through them, an induction magnetic field is generated. MRAM-based memory implementations are discussed in more detail below.

[0026] Phase-change memory (PCM) devices exploit the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve non-thermal phase changes by simply altering the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). Therefore, the programming doses are laser pulses. The memory cells can be locked by preventing them from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes any (continuous or non-continuous) oscillation or pulse of sound, current, voltage light, or other wave.These memory elements within the individual selectable memory cells or bits may include another row element that is a selector, such as an ovonic threshold switch or a metal insulator substrate.

[0027] The average person skilled in the art will recognize that the technology described herein is not limited to a single specific storage structure, storage design or material composition, but covers many relevant storage structures in accordance with the spirit and scope of the technology as described herein and as known to a person skilled in the art.

[0028] The elements of Fig. 2A can be grouped into two parts: (1) the memory structure 202 and (2) the peripheral switching logic, all of which are in Fig. The components shown in Figure 2A, with the exception of the memory structure 202, are included. An important property of a memory circuit is its capacity, which can be increased by enlarging the area of ​​the memory chip of the storage system 100 allocated to the memory structure 202; however, this reduces the area available on the memory chip for peripheral switching logic. This can impose significant limitations on these peripheral switching logic elements. For example, the need to fit sensing amplifier circuits into the available area can be a significant constraint on sensing amplifier design architectures. With respect to the system control logic 260, reduced area availability can limit the functionalities that can be implemented on the chip.Consequently, a fundamental compromise in the design of a memory chip for the storage system 100 is the size of the area allocated for the memory structure 202 and the size of the area allocated for the peripheral switching logic.

[0029] Another area where the memory structure 202 and the peripheral switching logic often conflict is the processing involved in creating these regions, as these regions often involve different processing technologies and the trade-off of having different technologies on a single chip. For example, if the memory structure 202 is NAND flash, it is an NMOS structure, while the peripheral switching logic is often CMOS-based. For instance, elements such as sensing amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral switching logic in the system control logic 260 often use PMOS devices. Processing operations for manufacturing a CMOS chip will differ in many aspects from processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0030] To improve upon these limitations, the embodiments described below can modify the elements of Fig. 2A can be divided across separately manufactured chips, which are then interconnected. More precisely, the memory structure 202 can be implemented on one chip (referred to as the memory chip), and some or all of the peripheral switching logic elements, including one or more control circuits, can be enclosed on a separate chip (referred to as the control chip). For example, a memory chip can consist only of the memory elements, such as the array of memory cells of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or another type of memory. Some or all of the peripheral switching logic, even including elements such as decoders and sensing amplifiers, can then be placed on a separate control chip. This allows each of the memory chips to be individually optimized according to its technology.For example, a NAND memory chip can be optimized for an NMOS-based memory array structure without having to worry about the CMOS elements, which are now moved to a controller chip that can be optimized for CMOS processing. This frees up more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily accommodated if they were confined to the edges of the same chip containing the memory cell array. The two chips can then be bonded together in a bonded multi-chip memory circuit, with the array on one chip connected to the peripheral elements on the other. Although the following focuses on a bonded memory circuit with one memory chip and one controller chip, other embodiments can use more chips, such as two memory chips and one controller chip.

[0031] Fig. 2B shows an alternative arrangement to that of Fig. 2A, which can be implemented by wafer-to-wafer bonding to provide a bonded chip pair. Fig. Figure 2B shows a functional block diagram of an embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 can be used to implement the non-volatile memory 130 of the storage system 100. The integrated memory assembly 307 includes two types of semiconductor chips (or, more simply, "chips"). The memory chip 201 includes the memory structure 202. The memory structure 202 includes non-volatile memory cells. The control chip 211 includes control switching logic 260, 210, and 220 (as described above). In some embodiments, the control chip 211 is configured to communicate with the memory structure 202 in the memory chip 201. In some embodiments, the memory chip 201 and the control chip 211 are interconnected.

[0032] Fig. Figure 2B shows an example of peripheral switching logic, including control circuits, formed in a peripheral circuit or control chip 311, which is coupled to the memory structure 202 formed in the memory chip 201. Common components are similar to those in Fig. 2A. The system control logic 260, the row control switching logic 220, and the column control switching logic 210 are located in the control chip 211. In some embodiments, all or part of the column control switching logic 210 and all or part of the row control switching logic 220 are located on the memory chip 201. In some embodiments, part of the switching logic in the system control logic 260 is located on the memory chip 201.

[0033] The system control logic 260, the row control switching logic 220, and the column control switching logic 210 can be formed by a common process (e.g., a CMOS process), so that adding elements and functionalities, such as ECC, which are actually more commonly found on a memory controller 120, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 can also be used to manufacture the system control logic 260, the row control switching logic 220, and the column control switching logic 210). While moving such circuits from a chip, such as the memory 2 chip 201, can reduce the number of steps required to manufacture such a chip, adding such circuits to a chip, such as the controller chip 311, does not require many additional process steps.The control chip 211 can also be called a CMOS chip, since CMOS technology is used to implement some or all of the control switching logics 260, 210, 220.

[0034] Fig. Figure 2B shows a column control switching logic 210, which includes one or more sensing amplifiers 230 on the control chip 211, connected via electrical paths 206 to the memory structure 202 on the memory chip 201. For example, the electrical paths 206 can provide an electrical connection between the column decoder 212, the driver switching logic 214, and the block selector 216 and the bit lines of the memory structure 202. Electrical paths can extend from the column control switching logic 210 on the control chip 211 through pads on the control chip 211 that are bonded to corresponding pads on the memory chip 201, which are connected to bit lines of the memory structure 202. Each bit line of the memory structure 202 can have a corresponding electrical path in the electrical paths 206, including a pair of bonded pads connected to the column control switching logic 210.Similarly, the line control switching logic 220, including the line decoder 222, the array driver 224, and the block selector 226, is connected to the memory structure 202 via electrical paths 208. Each of the electrical paths 208 can correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths can also be provided between the control chip 211 and the memory chip 201.

[0035] For the purposes of this document, the terms "a control circuit" or "one or more control circuits" may include any or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control switching logic 220, all or a portion of column control switching logic 210, a microcontroller, a microprocessor, and / or other circuits with similar functions. The control circuit may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, integrated circuit, or any other type of circuit.In some embodiments, there is more than one control chip 211 and more than one memory chip 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control chips 211 and multiple memory chips 201.

[0036] Fig. Figure 3 is a block diagram showing an embodiment of a section of the column control switching logic 210, which is subdivided into a plurality of sensing amplifiers 230, and a common section called the management circuit 302. In one embodiment, each sensing amplifier 230 is connected to a corresponding bit line, which in turn is connected to one or more NAND gates. In one exemplary implementation, each bit line is connected to six NAND gates, with one NAND gate per subblock. The management circuit 302 is connected to a set of several (e.g., four, eight, etc.) sensing amplifiers 230. Each of the sensing amplifiers 230 in a group communicates with the associated management circuit via the data bus 304.

[0037] Each sensing amplifier 230 provides voltages for the bit lines (see BL0, BL1, BL2, BL3) during the programming, verifying, erasing, and reading operations. Sensing amplifiers are also used to detect the state (e.g., the data state) of a memory cell in a NAND flash memory array connected to the bit line connected to the respective sensing amplifier.

[0038] Each sensing amplifier 230 includes a selector 306 or switch connected to a transistor 308 (e.g., an NMOS). Based on the voltages at the control gate 310 and drain 312 of transistor 308, the transistor can operate as a pass-through gate or as a bit line terminal. If the control gate voltage is sufficiently higher than the drain voltage, the transistor operates as a pass-through gate, passing the drain voltage to the bit line (BL) at the transistor's source 314. For example, when pre-charging and inhibiting an unselected NAND chain, a program inhibit voltage of 1–2 V can be passed through. Or, a program enable voltage, such as 0 V, can be passed through to allow programming in a selected NAND chain. The selector 306 can pass a supply voltage Vdd (e.g., 3–4 V) to the control gate of transistor 308 so that it operates as a pass-through gate.

[0039] If the voltage at the control gate is lower than the voltage at the drain, transistor 308 operates as a source follower to set or clamp the bit line voltage to Vcg-Vth, where Vcg is the voltage at control gate 310 and Vth, for example, 0.7 V, is the threshold voltage of transistor 308. This assumes the source line is at 0 V. If Vcelsrc is not zero, the bit line voltage is clamped at Vcg-Vcelsrc-Vth. The transistor is therefore sometimes called a bit line clamping transistor (BLC), and the voltage Vcg at control gate 310 is called the bit line clamping voltage Vblc. This mode can be used in sensing operations such as read and verification. Thus, the bit line voltage is set by transistor 308 based on the voltage output by selector 306. For example, selector 306 can forward Vsense+Vth, e.g. 1.5 V, to the control gate of transistor 308 to set Vsense, e.g.0.8 V is provided on the bit line. A Vbl selector 316 can supply a relatively high voltage, such as Vdd, to the drain 312, which is higher than the control gate voltage at transistor 308, in order to provide source follower mode during sensing operations. Vbl refers to the bit line voltage.

[0040] The Vbl selector 316 can pass one of several voltage signals. For example, the Vbl selector can pass a program inhibit voltage signal that rises from an initial voltage, e.g., 0 V, to a program inhibit voltage, e.g., Vbl_inh, for the respective bit lines of the unselected NAND gate during a program loop. The Vbl selector 316 can also pass a program enable voltage signal, such as 0 V, for the respective bit lines of the selected NAND gates during a program loop.

[0041] In one approach, the selector 306 of each sensing circuit can be controlled separately from the selectors of the other sensing circuits. The Vbl selector 316 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0042] During sensing, a sensing node 318 is charged to an initial voltage, Vsense_init, such as 3 V. The sensing node is then connected to the bit line via transistor 308, and the decay rate of the sensing node determines whether a memory cell is in a conducting or non-conducting state. The decay rate of the sensing node also indicates whether a current Icell in the memory cell exceeds a reference current, Iref. A greater decay rate corresponds to a larger current. If Icell ≤ Iref, the memory cell is in a non-conducting state, and if Icell > Iref, the memory cell is in a conducting state.

[0043] In particular, the comparator circuit 320 determines the decay rate by comparing the voltage of the sensing node with a trigger voltage at a sensing time. If the voltage of the sensing node drops below the trigger voltage, Vtrip, the memory cell is in a conducting state and its Vth is at or below the verification voltage. If the voltage of the sensing node does not drop below Vtrip, the memory cell is in a non-conducting state and its Vth is above the verification voltage. A sensing node latch 322, for example, is set to 0 or 1 by the comparator circuit 320, depending on whether the memory cell is in a conducting or non-conducting state. In a program verification test, for example, a 0 can represent a failure and a 1 a pass.The bit in the sensing node latch can be read in a scan of the status bit or switched from 0 to 1 in a fill operation. The bit in the sensing node latch 322 can also be used in a lock scan to decide whether a bit line voltage should be set to a blocking or programming level in the next program loop. L.

[0044] The management circuit 302 includes a processor 330, four exemplary sets of data latches 340, 342, 344 and 346 and an I / O interface 332 which is connected between the sets of data latches and the data bus 334. Fig. Figure 3 shows four example sets of data latches 340, 342, 344, and 346; however, in other embodiments, more or fewer than four can be implemented. In one embodiment, there is one set of latches for each sensing amplifier 230. For each sensing circuit, a set of three data latches, e.g., comprising individual latches ADL, BDL, CDL, and XDL, can be provided. In some cases, a different number of data latches can be used. In an embodiment with three bits per memory cell, ADL stores one bit for a lower side of data, BDL stores one bit for a middle side of data, CDL stores one bit for an upper side of data, and XDL serves as an interface latch for storing / latching data from the memory controller.

[0045] The processor 330 performs calculations to determine the data stored in the detected memory cell and to store this data in the set of data latches. Each set of data latches 340-346 is used to store data bits determined by the processor 330 during a read operation and to store data bits imported from the data bus 334 during a programming operation, representing write data to be programmed into memory. The I / O interface 332 provides an interface between the data latches 340-346 and the data bus 334.

[0046] During the read operation, the system's operation is controlled by the state machine 262, which regulates the supply of various control gate voltages to the addressed memory cell. As the system cycles through the different predefined control gate voltages, corresponding to the various memory states supported by the memory, the sensing circuit can trigger at one of these voltages, and a corresponding output is provided by the sensing amplifier to the processor 330 via the data bus 304. At this point, the processor 330 determines the resulting memory state, taking into account the trigger events of the sensing circuit and the information about the applied control gate voltage from the state machine via the input lines 348. It then calculates a binary code for the memory state and stores the resulting data bits in the data latches 340-346.

[0047] Some implementations can include multiple 330 processors. In one embodiment, each 330 processor includes an output line (not shown), such that each of the output lines is connected via a wired OR connection. A wired OR connection or line can be provided by connecting multiple wires together at a node, each wire carrying a high or low input signal from a corresponding processor, and an output from the node being high when either of the input signals is high. In some embodiments, the output lines are inverted before being connected to the wired OR line. This configuration allows for rapid determination during a program verification test of when the programming process is complete because the state machine receiving the wired OR can determine when all programmed bits have reached the desired state.For example, when each bit reaches its desired level, a logic zero for that bit is sent to the wired OR line (or a data one is inverted). When all bits output a data zero (or an inverted data one), the state machine knows to terminate the programming procedure. Since each processor communicates with eight sensing circuits, the state machine must either read the wired OR line eight times, or logic is added to processor 330 to accumulate the results of the associated bit lines, so the state machine only needs to read the wired OR line once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and modify the algorithms accordingly.

[0048] During programming or verification operations for memory cells, the data to be programmed (write data) is stored in the set of data latches 340-346 from the data bus 334. During reprogramming, a corresponding set of data latches for a memory cell can store data specifying when the memory cell should be activated for reprogramming based on the programming pulse size.

[0049] Under the control of the state machine 262, the programming process applies a series of programming voltage pulses to the control gates of the addressed memory cells. Each voltage pulse can be incremented by one step size, on the order of a previous programming pulse, in a process known as incremental step-pulse programming. Each programming voltage is followed by a verification process to determine whether the memory cells have been programmed to the desired memory state. In some cases, the processor 330 monitors the state of the read-back memory relative to the desired memory state. If the two match, the processor 330 puts the bit line into a program-inhibiting mode, for example, by updating its latches.This prevents the memory cell, which is coupled to the bit line, from being programmed further, even if additional programming pulses are applied to its control gate.

[0050] Fig. Figure 4 is a perspective view of a section of an exemplary embodiment of a monolithic three-dimensional memory array / structure which may include a memory structure 202 that incorporates a plurality of non-volatile memory cells arranged as vertical NAND chains. Fig. Figure 4, for example, shows section 400 of a memory block. The structure shown includes a set of bit lines BL that lie above a stack 401 of alternating dielectric and conductive layers. As an example, one of the dielectric layers is labeled D and one of the conductive layers (also called word line layers) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. As further explained below, in one embodiment, the alternating dielectric and conductive layers are subdivided into six (or another number of) regions (e.g., subblocks) by isolation regions IR. Fig. Figure 4 shows an isolation region IR separating two subblocks. Below the alternating dielectric and conduction layers is a source conduction layer SL. Storage holes are formed in the stack of alternating dielectric and conduction layers. For example, one of the storage holes is labeled MH. It should be noted that in Fig. 4. The dielectric layers are shown transparently so that the reader can see the memory holes positioned in the stack of alternating dielectric and conductive layers. In one embodiment, NAND chains are formed by filling the memory hole with materials that enclose a charge-swapping material to create a vertical column of memory cells. Each memory cell can store one or more data bits. Further details of the three-dimensional monolithic memory array comprising memory structure 202 are provided below.

[0051] Fig. Figure 4A is a block diagram illustrating an exemplary organization of the memory structure 202, which is divided into two levels 402 and 404. Each level is then subdivided into M blocks. In one example, each level has approximately 2000 blocks. However, other numbers of blocks and levels can be used. In one embodiment, a memory cell block is a single erasing unit. That is, all memory cells of a block are erased together. In other embodiments, blocks can be subdivided into subblocks, and the subblocks can be the erasing unit. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuitry. In some embodiments, a block represents a group of interconnected memory cells because the memory cells of a block share a common set of word lines.For example, the word leads of a block are all connected to all vertical NAND chains of that block. Although... Fig. Figure 4A shows two levels 402 / 404; however, more or fewer than two levels can also be implemented. In some embodiments, the memory structure 202 includes eight levels.

[0052] Fig. 4B-4G show an example of a three-dimensional (“3D”) NAND structure, which resembles the structure of Fig. 4 corresponds and for the implementation of the storage structure 202 of Fig. 2A and Fig. 2B can be used. Fig. 4B is a block diagram showing a top view of section 406 of block 2 of level 402. As shown in Fig. As can be seen in 4B, the route runs in Fig. Block 4B is shown in the direction of 432. In one embodiment, the memory array has many layers; however, it shows Fig. 4B only the top layer.

[0053] Fig. 4B represents a multitude of circles that constitute the vertical columns corresponding to the memory holes. Each vertical column contains multiple selection transistors (also called selection gates) and multiple memory cells. In one embodiment, each vertical column implements a NAN D chain. Fig. For example, 4B labels a subset of the vertical columns / NAND chains 426, 432, 436, 446, 456, 462, 466, 472, 474 and 476.

[0054] Fig. 4B also represents a set of bit lines 415 including bit lines 411, 412, 413, 414, ... 419. Fig. Figure 4B shows twenty-four bit lines, as only a section of the block is depicted. It is conceivable that more than twenty-four bit lines are connected to the vertical columns of the block. Each of the circles representing vertical columns has an "x" to indicate its connection to one bit line. For example, bit line 411 is connected to vertical columns 426, 436, 446, 456, 466, and 476.

[0055] The in Fig. The block shown in Figure 4B includes a set of insulating regions 480, 482, 484, 486, and 488 formed from SiO2; however, other dielectric materials can also be used. The insulating regions 480, 482, 484, 486, and 488 serve to divide the upper layers of the block into six regions; for example, the one shown in Fig. The upper layer shown in Figure 4B is subdivided into regions 420, 430, 440, 450, 460, and 470, all referred to as subblocks. In one embodiment, the isolation regions subdivide only the layers used to implement selection gates, allowing NAND chains in different subblocks to be selected independently. In one exemplary implementation, a bit line is connected to only one vertical column / NAND chain in each of the regions (subblocks) 420, 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to six rows in each block. In another embodiment, all six vertical columns / NAND chains connected to a common bit line are connected to the same word line (or set of word lines).Therefore, the system uses the drain-side selection lines to choose one (or another subset) of the six to be subjected to a storage operation (programming, verifying, reading and / or erasing).

[0056] Although Fig. Figure 4B shows that each region 420, 430, 440, 450, 460, and 470 has four rows of vertical columns, and six regions have twenty-four rows of vertical columns in a block. These exact figures are an exemplary implementation. Other embodiments may include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block. Fig. Figure 4B also shows that the vertical columns are staggered. Different staggering patterns can be used in other embodiments. In some embodiments, the vertical columns are not staggered.

[0057] Fig. Figure 4C represents a section of an embodiment of a three-dimensional storage structure 202, which shows a cross-sectional view along line AA of Fig. 4B shows this cross-sectional view, which cuts through the vertical columns (NAND chains) 472 and 474 of region 470 (see Fig. 4B). The structure in Fig. 4C includes the following: three drain-side selector layers SGD0, SGD1, and SGD2; three source-side selector layers SGS0, SGS1, and SGS2; three dummy word line layers DD0, DD1, and DDS; two hundred and forty word line layers WL0-WL239 for interconnection with data storage cells; and two hundred and fifty dielectric layers DI0-DL249. Other embodiments may include more or fewer than those above. Fig. Implement the numbers described in 4C. In one embodiment, SGD0, SGD1 and SGD2 are interconnected, and SGDS0, SGS1 and SGS2 are interconnected.

[0058] Vertical columns 472 and 474 are shown protruding through the drain-side select layers, source-side select layers, dummy word line layers, and word line layers. In one embodiment, each vertical column has a vertical NAND chain. Below the vertical columns and layers are the substrate 453, an insulating film 454 on the substrate, and the source line SL. The NAND chain of vertical column 442 has a source end at the bottom of the stack and a drain end at the top of the stack. As shown in Fig. 4B shows Fig. 4C the vertical column 472, which is connected to the bit line 414 via connector 417.

[0059] For simplicity, the drain-side selection layers, source-side selection layers, dummy word line layers, and data word line layers are collectively referred to as conductive layers. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metals like tungsten, or metal silicides. In some embodiments, different conductive layers can be formed from different materials. Between the conductive layers are the dielectric layers DL0-DL249. For example, dielectric layer DL240 is located above word line layer WL235 and below word line layer WL236. In one embodiment, the dielectric layers are made of SiO2.In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0060] The non-volatile memory cells are arranged along vertical columns that run through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND chains. The word line layers WL0-W239 are connected to memory cells (also called data storage cells). The dummy word line layers DD0, DD1, and DS are connected to dummy memory cells. A dummy memory cell does not store, nor is authorized to store, host data (data provided by the host or an entity outside of Storage System 100, for example, data from a user of the host), whereas a data storage cell is authorized to store host data. Host data can be compared to system data generated by Storage System 100 (e.g., L2P tables).In some embodiments, data storage cells and dummy storage cells can have the same structure. The drain-side selection layers SGD0, SGD1, and SGD2 are used to electrically connect or disconnect the NAND chains from the bit lines. The source-side selection layers SGS0, SGS1, and SGS2 are used to electrically connect or disconnect the NAND chains from the source line SL.

[0061] It should be noted that the stack of word lines WL0-WL239 includes two marginal word lines at the edges of the stack, including the upper marginal word line WL239 and the lower marginal word line WL0. The word lines WL1-WL238 are word lines without a margin.

[0062] Fig. Figure 4D represents a section of an embodiment of a three-dimensional storage structure 202, which shows a cross-sectional view along line BB of Fig. 4B shows this cross-sectional view cutting through the vertical columns (NAND chains) 432 and 434 of region 430 (see Fig. 4B). Fig. 4D shows the same alternating conductive and dielectric layers as in Fig. 4C. Fig. 4D also shows isolation region 482. Isolation regions 480, 482, 484, 486, and 488 occupy the space that would have been used for a section of the memory holes / vertical columns / NAND chains. For example, isolation region 482 occupies the space that would have been used for a section of vertical column 434. More precisely, a section (e.g., half the diameter) of vertical column 434 in layers SDG0, SGD1, SGD2, and DD0 was removed to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (with a circular cross-section), the section of vertical column 434 in layers SDG0, SGD1, SGD2, and DD0 has a semicircular cross-section. In one embodiment, after the formation of the stack of alternating conductive and dielectric layers, the stack is etched to create space for the insulation region, and this space is then filled with SiO2.

[0063] Fig. Figure 4E represents a section of an embodiment of a three-dimensional storage structure 202, which shows a cross-sectional view along line CC of Fig. 4B shows this cross-sectional view, which cuts through vertical columns (NAND chains) 452 and 462 (see Fig. 4B). Fig. 4E shows the same alternating conductive and dielectric layers as in Fig. 4C. Fig. 4E also shows the isolation region 486, which intersects the vertical columns (NAND chain) 452.

[0064] Fig. Figure 4F shows a cross-sectional view of region 429 of Fig. 4C, which encloses a section of the vertical column 472. In one embodiment, the vertical columns are round; however, in other embodiments, other shapes may be used. In one embodiment, the vertical column 472 encloses an inner core layer 490 made of a dielectric, such as SiO2. Other materials may also be used. The surrounding inner core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. It should be noted that the channel 491 is connected to the bit line and the source line. The surrounding channel 491 is a tunnel dielectric 492. In one embodiment, the tunnel dielectric 492 has an ONO structure. The surrounding tunnel dielectric 492 is a charge-trapping layer 493, such as (for example) silicon nitride. Other storage materials and structures may also be used.The technology described herein is not limited to a specific material or structure.

[0065] Fig. Figure 4D shows the dielectric layers DLL239, DLL240, DLL241, DLL242, and DLL243, as well as the word conduction layers WLL234, WLL235, WLL236, WLL237, and WLL238. Each of the word conduction layers encloses a word conduction region 496, which is surrounded by an aluminum oxide layer 497, which in turn is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel to and adjacent to the charge-snatch layer 493. The physical interaction of the word conduction layers with the vertical gap forms the memory cells. Thus, in one embodiment, a memory cell comprises channel 491, tunnel dielectric 492, charge-snatch layer 493, blocking oxide layer 498, aluminum oxide layer 497, and word conduction region 496. For example, the word line layer WLL238 and a section of the vertical column 472 contain a memory cell MC1.Word layer WL237 and a section of vertical column 472 contain a memory cell MC2. Word layer WLL236 and a section of vertical column 472 contain a memory cell MC3. Word layer WLL235 and a section of vertical column 472 contain a memory cell MC4. Word layer WLL234 and a section of vertical column 472 contain a memory cell MC5. In other architectures, a memory cell may have a different structure, but the memory cell would still be the storage unit.

[0066] When a memory cell is programmed, electrons are stored in a section of the charge-trapping layer 493 that is connected to (e.g., within) the memory cell. These electrons are drawn into the charge-trapping layer 493 from the channel 491, through the tunneling dielectric 492, in response to a corresponding voltage in the word-line region 496. The threshold voltage (Vth) of a memory cell is increased proportionally to the amount of stored charge. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of the electrons into the charge-trapping layer. During an erasure operation, the electrons return to the channel, or holes are injected into the charge-trapping layer to recombine with electrons. In another embodiment, erasure by hole injection into the charge-trapping layer is achieved via a physical mechanism such as GIDL.

[0067] Fig. 4G is a schematic diagram of a section of the [unclear] in the Fig. 4-4F shown memory arrays 202. Fig. 4G shows the physical data word lines WL0-WL239, which run across the entire block. The structure of Fig. 4G corresponds to section 306 in block 2 of Fig. 4A, including bit line 411. Within the block, in one embodiment, each bit line is connected to six NAND chains. Thus, it shows Fig. 4G is a bit line connected to the NAND chain NS0 (corresponding to vertical column 426), the NAND chain NS1 (corresponding to vertical column 436), the NAND chain NS2 (corresponding to vertical column 446), the NAND chain NS3 (corresponding to vertical column 456), the NAND chain NS4 (corresponding to vertical column 466) and the NAND chain NS5 (corresponding to vertical column 476). As mentioned previously, in one embodiment SGD0, SGD1, and SGD2 are interconnected to operate as a single logical select gate for each subblock separated by isolation regions (480, 482, 484, 486, and 486) to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5. SGD0, SGD1, and SGD2 are also interconnected to operate as a single logical select gate, which is configured in Fig. 4E is represented as SGS. Although the selection gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4 and SGD-s5 are isolated from each other by the isolation regions, the data word lines WL0-WL239 of each subblock are interconnected.

[0068] The isolation regions (480, 482, 484, 486, and 486) are used to allow separate control of subblocks. The first subblock corresponds to the vertical NAND chains controlled by SGD-s0. The second subblock corresponds to the vertical NAND chains controlled by SGD-s1. The third subblock corresponds to the vertical NAND chains controlled by SGD-s2. The fourth subblock corresponds to the vertical NAND chains controlled by SGD-s3. The fifth subblock corresponds to the vertical NAND chains controlled by SGD-s4. The sixth subblock corresponds to the vertical NAND chains controlled by SGD-s5.

[0069] Fig. Figure 4G only shows the NAND chains connected to bit line 411. However, a complete schematic of the block would show each bit line and six vertical NAND chains connected to each bit line.

[0070] Although the exemplary storage devices are from Fig. Although 4-4G refers to three-dimensional memory structures that include vertical NAND chains with charge-capture material, other (2D and 3D) memory structures can also be used with the technology described herein.

[0071] The storage systems discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltages of the memory cells should lie within one or more distributions of threshold voltages for programmed memory cells, or, if applicable, within a distribution of threshold voltages for erased memory cells. Fig. Figure 5A is a graph of the threshold voltage as a function of the number of memory cells and illustrates exemplary threshold voltage distributions for the memory array when each memory cell stores one data bit per cell. Memory cells that store one data bit per cell are called single-level cells (SLC). The data stored in SLC memory cells is called SLC data; therefore, SLC data has one bit per cell. Data stored as one bit per cell is SLC data. Fig. Figure 5A shows two threshold voltage distributions: E and P. The threshold voltage distribution E corresponds to a cleared data state. The threshold voltage distribution P corresponds to a programmed data state. Memory cells exhibiting threshold voltages in the threshold voltage distribution E are therefore in the cleared data state (e.g., they are erased). Memory cells exhibiting threshold voltages in the threshold voltage distribution P are therefore in the programmed data state (e.g., they are programmed). In one embodiment, cleared memory cells store data "1" and programmed memory cells store data "0". Fig. 5A represents the read reference voltage Vr. By testing (e.g., performing one or more sensing operations) whether the threshold voltage of a specific memory cell is above or below Vr, the system can determine whether a memory cell is erased (state E) or programmed (state P). Fig. 5A also represents the verification reference voltage Vv. In some embodiments, when memory cells are programmed to the data state P, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv.

[0072] Fig. Figures 5B-F illustrate exemplary threshold voltage distributions for the memory array when each memory cell stores data with multiple bits per cell. Memory cells that store multiple data bits per cell are called multilevel cells (MLCs). The data stored in MLC memory cells is called MLC data; therefore, MLC data has multiple bits per cell. Data stored as multiple data bits per cell is MLC data. In the exemplary embodiment of Fig. In the 5B form factor, each memory cell stores two data bits. Other embodiments can use different data capacities per memory cell (e.g., three, four, five, or six data bits per memory cell).

[0073] Fig. Figure 5B shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B, and C for programmed memory cells are also shown. In one embodiment, the threshold voltages in distribution E are negative, and the threshold voltages in distributions A, B, and C are positive. Each different threshold voltage distribution in Fig. 5B corresponds to predetermined values ​​for the set of data bits. In one embodiment, each data bit of the two data bits stored in a memory cell is located on different logical sides, referred to as the lower side (LP) and upper side (UP). In other embodiments, all data bits stored in a memory cell are located on a common logical side. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage levels depends on the data encoding scheme used for the cells. Table 1 provides an example of an encoding scheme. Table 1 E A B C LP 1 0 0 1 UP 1 1 0 0

[0074] In one embodiment, referred to as full sequence programming, memory cells can be directly programmed from the erased data state E into one of the programmed data states A, B, or C, using the process of Fig. 6 (see below). For example, a population of memory cells to be programmed can first be erased so that all memory cells in the population are in the erased data state E. Then, a programming process is used to program memory cells directly into data states A, B, and / or C. For example, while some memory cells are programmed from data state E to data state A, other memory cells are programmed from data state E to data state B and / or from data state E to data state C. The arrows of Fig. 5B represents the full sequence programming. In some embodiments, the data states AC can overlap, with the memory controller 120 (or the control chip 211) relying on error correction to identify the correct data to be stored.

[0075] Fig. 5C presents exemplary threshold voltage distributions for memory cells where each memory cell stores three data bits per memory cell (which is another example of MLC data). Fig. Figure 5C shows eight threshold voltage distributions corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A–G represent memory cells that are programmed and are therefore also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values ​​for the set of data bits. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage levels depends on the data encoding scheme used for the cells. In one embodiment, data values ​​are assigned to the threshold voltage ranges using a Gray code assignment, so that if the threshold voltage of a memory cell mistakenly shifts into its adjacent physical state, only one bit is affected.Table 2 provides an example of an encoding scheme for embodiments in which each of the three data bits stored in a memory cell is located on different logical sides, referred to as the bottom side (LP), middle side (MP) and top side (UP). Table 2 Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0076] Fig. 5C shows seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sensing operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., A, B, C, D, etc.) of a memory cell.

[0077] Fig. 5C also shows seven verification reference voltages: VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when memory cells are programmed to data state A, the system checks whether these memory cells have a threshold voltage greater than or equal to VvA. When memory cells are programmed to data state B, the system checks whether the memory cells have threshold voltages greater than or equal to VvB. When memory cells are programmed to data state C, the system determines whether the threshold voltage of the memory cells is greater than or equal to VvC. When memory cells are programmed to data state D, the system checks whether the threshold voltage of the memory cells is greater than or equal to VvD. When memory cells are programmed to data state E, the system checks whether the threshold voltage of the memory cells is greater than or equal to VvE.When memory cells are programmed to data state F, the system checks whether the threshold voltage of the memory cells is greater than or equal to VvF. When memory cells are programmed to data state G, the system checks whether the threshold voltage of the memory cells is greater than or equal to VvG. Fig. 5C also displays Vev, a voltage level used to check if a memory cell has been correctly erased.

[0078] In an embodiment that uses full-sequence programming, the memory cells can be directly programmed from the erased data state Er into one of the programmed data states AG, using the process of Fig. 6 (see below). For example, a population of memory cells to be programmed can first be erased so that all memory cells in the population are in the erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and / or G. For example, while some memory cells are programmed from data state ER to data state A, other memory cells are programmed from data state ER to data state B and / or from data state ER to data state C, and so on. The arrows of Fig. 5C represents full sequence programming. In some embodiments, the data states AG can overlap, with the control chip 211 and / or memory controller 120 relying on error correction to identify the correct data to be stored. It should be noted that in some embodiments, the system can also use multipass programming processes known in the prior art instead of full sequence programming.

[0079] In general, during verification and read operations, the selected word line is connected to a voltage (an example of a reference signal), the level of which is determined for each read operation (see, for example, read comparison level VrA, VrB, VrC, VrD, VrE, VrF and VrG). Fig. 5) or verification process (see, for example, verification target level VvA, VvB, VvC, VvD, VvE, VvF and VvG from Fig. 5C) is specified to determine whether a threshold voltage of the relevant memory cell has reached the respective level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell is switched on (conducting current) in response to the voltage applied to the word line. If the conduction current, according to measurements, is greater than a specified value, then it is assumed that the memory cell is switched on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current, according to measurements, is not greater than the specified value, then it is assumed that the memory cell is not switched on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell.During a read or verification process, the unselected memory cells are provided with one or more read pass voltages (also known as bypass voltages) at their control gates, so that these memory cells act as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

[0080] There are many ways to measure the conduction current of a memory cell during a read or verification operation. In one example, the conduction current of a memory cell is measured by the rate at which it discharges or charges a dedicated capacitor in the sensing amplifier. In another example, the conduction current of the selected memory cell in the NAND chain that encloses the memory cell allows (or prevents) it to discharge a corresponding bit line. The voltage on the bit line is measured after a certain time to see if it has discharged or not. It should be noted that the technology described herein can be used with various methods known in the prior art for verification / reading. Other read and verification techniques known in the prior art can also be used.

[0081] Fig. 5D represents the threshold voltage distribution when each memory cell stores four data bits, which is another example of MLC data. Fig. 5D shows that there can be some overlap between the threshold voltage distributions (data states) S0 to S15. This overlap can occur due to factors such as charge loss from memory cells (and therefore a drop in the threshold voltage). A programming error can unintentionally increase the threshold voltage of a memory cell. Similarly, a read error can unintentionally increase the threshold voltage of a memory cell. Over time, the positions of the threshold voltage distributions can change. Such changes can increase the bit error rate, thereby increasing the decoding time or even making decoding impossible. Changing the read reference voltages can help mitigate such effects. Using ECC during the read process can resolve errors and ambiguities.It should be noted that in some embodiments the threshold voltage distributions for a population of memory cells storing four data bits per memory cell do not overlap and are separated from each other; for example, as in . Fig. 5E is shown. The threshold voltage distributions in Fig. 5D includes read reference voltages and verification reference voltages, as described above.

[0082] When using four bits per memory cell, the memory can be programmed using the full-sequence programming described above or using the multipass programming processes known in the prior art. Each threshold voltage distribution (data state) of Fig. 5D corresponds to predetermined values ​​for the set of data bits. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage levels depends on the data encoding scheme used for the cells. Table 3 provides an example of an encoding scheme for embodiments where each of the four data bits stored in a memory cell lies on different logical sides, designated as the bottom side (LP), middle side (MP), top side (UP), and top side (TP).

[0083] Fig. 5F represents the threshold voltage distribution when each memory cell stores five data bits, which is another example of MLC data. In an example implementation, when the memory cells store five data bits, the data is stored in one of thirty-two data states (e.g., S0-S31).

[0084] Fig. Figure 6 is a flowchart describing one embodiment of a process for programming memory cells. For the purposes of this document, the terms program and programming are synonymous with writing and writing. In one exemplary embodiment, the process is described by Fig. 6 for the memory array 202 using one or more control circuits (e.g., system control logic 260, column control switching logic 210, row control switching logic 220) described above. In an exemplary embodiment, the process is carried out by Fig. 6. The integrated memory assembly 207 uses one or more control circuits (e.g., system control logic 260, column control switching logic 210, row control switching logic 220) of the control chip 211 to program memory cells on the memory chip 201. The process includes several loops, each of which includes a programming phase and a verification phase. The process in Fig. Step 6 is performed to implement full sequence programming as well as other programming schemes, including multipass programming. When implementing multipass programming, the process is made from Fig. 6 is used to implement each individual pass of the multipass programming process.

[0085] Typically, the programming voltage applied to the control gates (via a selected data word line) during a programming operation is provided as a series of programming pulses (e.g., voltage pulses). Between programming pulses, a set of verification pulses (e.g., voltage pulses) is used to perform verification. In many implementations, the size of the programming pulses is incremented by a predetermined step size with each successive pulse. In step 602 of Fig. 6. The programming voltage signal (Vpgm) is initialized to the starting value (e.g., ~12-16 V or another suitable level), and a program counter PC controlled by the state machine 262 is initialized to 1. In one embodiment, the group of selected memory cells to be programmed (referred to herein as the selected memory cells) is programmed simultaneously and all are connected to the same word line (the selected word line). There will likely be other memory cells not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line is also connected to memory cells whose programming is actually intended to be inhibited. Furthermore, when memory cells reach their intended target data state, they are inhibited from further programming. In the case of NAND chains (e.g.,In the case of unselected NAND chains that include memory cells connected to the selected word line and whose programming is to be inhibited, their channels are amplified to inhibit programming. If a channel has an amplified voltage, the voltage difference between the channel and the word line is not large enough to cause programming. To assist with the amplified effect, in step 604, the control chip preloads channels of NAND chains that include memory cells connected to the selected word line and whose programming is to be inhibited. In step 606, the NAND chains that include memory cells connected to the selected word line and whose programming is to be inhibited have amplified channels to inhibit programming. Such NAND chains are referred to herein as "unselected NAND chains".In one embodiment, the unselected word lines receive one or more amplified voltages (e.g., ~7-11 volts), also known as forward voltages, to implement the amplification scheme. A program inhibit voltage is applied to the bit lines coupled to the unselected NAND chain.

[0086] In step 608, a programming voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line chosen for programming). If a memory cell in a NAND chain is to be programmed, the corresponding bit line is biased with a programming enable voltage. In step 608, the programming pulse is applied simultaneously to all memory cells connected to the selected word line, so that all memory cells connected to the selected word line are programmed simultaneously (provided their programming is not inhibited). That is, they are programmed at the same time or during overlapping times (both of which are considered simultaneous). In this way, all memory cells connected to the selected word line change their threshold voltage simultaneously, provided their programming is not inhibited.

[0087] In step 610, program verification is performed, and the memory cells that have reached their target state are locked by the control chip to prevent further programming. Step 610 includes performing the verification of the programming by sensing at one or more verification reference levels. In one embodiment, the verification process is performed by checking whether the threshold voltages of the memory cells selected for programming have reached the appropriate verification reference voltage. In step 610, a memory cell can be locked after it has been verified (by testing the threshold voltage) that the memory cell has reached its target state.

[0088] If step 612 determines that all memory cells have reached their target threshold voltages (passed), the programming process is complete and successful, as all selected memory cells have been programmed and their target states verified. Step 614 reports a status of "PASSED". If, however, step 612 determines that not all memory cells have reached their target threshold voltages (failed), the programming process continues with step 616.

[0089] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution is counted. That is, the number of memory cells that have not yet reached their target state is counted. This count can be performed by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count value that represents the total number of currently programmed memory cells that have failed the last verification step. In another embodiment, separate count values ​​are determined for each data state.

[0090] Step 618 determines whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read operation for the page of memory cells. If the number of failed memory cells is less than or equal to the predetermined limit, the programming process can be terminated, and the status "PASSED" is reported in step 614. In this situation, enough memory cells can be correctly programmed that the few remaining memory cells that were not fully programmed can be corrected using ECC during the read operation.In some embodiments, the predetermined limit used in step 618 is smaller than the number of bits that can be corrected by error correction codes (ECC) during a read process to account for future / additional errors. If fewer than all memory cells for a page are programmed, or if a count is compared for only one data state (or fewer than all states), the predetermined limit can be a proportion (pro rata or non-pro rata) of the number of bits that can be corrected by ECC during a read process for that page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program / erase cycles performed, or other criteria.

[0091] If the number of failed memory cells is not less than the predetermined limit, the programming process proceeds to step 620, and the program counter PC is checked against the program limit (PL). Examples of program limits include 6, 12, 16, 19, 20, and 30; however, other values ​​can be used. If the program counter PC is not less than the program limit PL, the program process is considered to have failed, and the status "FAILED" is reported in step 624. If the program counter PC is less than the program limit PL, the process proceeds to step 626. During this time, the program counter PC is incremented by 1, and the programming voltage signal Vpgm is increased to the next value. For example, the next pulse has an amplitude one step size ΔVpgm larger than the previous pulse (e.g., a step size of 0.1–1.0 volts).After step 626, the process returns to step 604 and (from the control chip) another programming pulse is applied to the selected word line, so that another iteration (steps 604 to 626) of the programming process of . Fig. 6 is carried out.

[0092] In one embodiment, the memory cells are erased before programming, and erasure is the process by which the threshold voltage of one or more memory cells is changed from a programmed data state to a erased data state. For example, changing the threshold voltage of one or more memory cells from state P to state E. Fig. 5A, from state A / B / C to state E Fig. 5B, from state AG to state Er Fig. 5C or from state S1-S15 to state S0 of Fig. 5D.

[0093] One technique for erasing memory cells in some storage devices is to bias a p-well substrate (or other types of substrates) to a high voltage to charge a NAND channel. An erase-release voltage (e.g., low voltage) is applied to the control gates of memory cells while the NAND channel is at a high voltage to erase the non-volatile storage elements (memory cells). This is referred to herein as the p-well erase process.

[0094] Another approach to erasing memory cells is to generate gate-induced drain leakage current (GIDL current) to charge the NAND chain channel. An erase-enable voltage is applied to the control gates of the memory cells while the NAND chain channel potential is maintained to erase the memory cells. This is referred to here as the GIDL erase operation. Both the p-well erase operation and the GIDL erase operation can be used to lower the threshold voltage (Vt) of memory cells.

[0095] In one embodiment, the GIDL current is generated by applying a drain-to-gate voltage to a selection transistor (e.g., SGD and / or SGS). A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current can arise when the drain voltage of the selection transistor is significantly higher than the control-gate voltage of the selection transistor. The GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and / or trap-assisted generation. In one embodiment, the GIDL current can cause one type of carrier, e.g., holes, to move predominantly into the NAND channel, thereby raising the channel's potential. The other types of carriers, e.g., electrons, are extracted from the channel toward a bit line or toward a source line by an electric field.During erasure, the holes can tunnel from the channel to a charge storage region of memory cells and recombine with electrons there to lower the threshold voltage of the memory cells.

[0096] The GIDL current can be generated at either end of the NAND chain. A first GIDL voltage can be generated between two terminals of a selector transistor (e.g., a drain-side selector transistor) connected to or near a bit line to generate a first GIDL current. A second GIDL voltage can be generated between two terminals of a selector transistor (e.g., a source-side selector transistor) connected to or near a source line to generate a second GIDL current. Erasing based on the GIDL current at only one end of the NAND chain is called a one-sided GIDL erase operation. Erasing based on the GIDL current at both ends of the NAND chain is called a two-sided GIDL erase operation.

[0097] In some embodiments, the controller, control chip, or memory chip performs the ECC decoding process (see ECC engine). Error correction is used to correct errors that may occur when storing data. During the programming process, the ECC engine encodes the data to add ECC information. The ECC engine is used, for example, to generate codewords. In one embodiment, data is programmed in units of pages. Since errors can occur during programming or reading, and errors can occur when storing data (e.g., due to electron drift, data retention problems, or other phenomena), error correction is used with the programming of one page of data. Many error-correcting coding schemes are well known in the prior art.These conventional error correction codes (ECCs) are especially useful with generously sized memories, including flash memory (and other non-volatile) memory, because of the considerable impact on production yield and device reliability that such coding schemes can provide when they modify devices that have some unprogrammable or defective cells to make them usable. Of course, there is a trade-off between the yield savings and the cost of providing additional memory cells to store the code bits (i.e., the code "rate"). As such, some ECC codes are better suited to flash memory devices than others. In general, ECC codes for flash memory devices tend to have higher code rates (i.e., higher bit rates).to have a lower ratio of code bits to data bits than the codes used in data communication applications (which can have code rates as low as 1 / 2). Examples of well-known ECC codes commonly used in conjunction with flash memory include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Sometimes, the error correction codes used in conjunction with flash memory are "systematic" in that the data portion of the final codeword remains unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete codeword. In other embodiments, the actual data is modified.

[0098] The specific parameters for a given error correction code include the type of code, the size of the block of actual data from which the codeword is derived, and the total length of the codeword after encoding. For example, a common BCH code applied to 512 bytes (4096 bits) of data can correct up to four error bits when at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a common Reed-Solomon code can correct up to four errors in a 512-byte data sector using approximately 72 ECC bits. In the context of flash memory, error correction encoding provides a significant improvement in production yield as well as the reliability of the flash memory over time.

[0099] In some embodiments, the controller receives host data, also called information bits, which are to be stored in a memory structure. The information bits are represented by the matrix i=[1 0] (note that two bits are used only as an example, and many embodiments have codewords longer than two bits). An error-correcting coding process (such as one of the processes mentioned above or below) is implemented, in which parity bits are added to the information bits to provide data represented by the matrix or codeword v=[1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in a more complex way. For example, low-density parity check codes (LDPC), also known as Gallager codes, can be used.More details about LDPC codes can be found in R.G. Galler, “Low-density parity-check codes,” IRE Trans. Inform. Theory, Vol. IT-8, p. 21, January 28, 1962; and D. MacKay, Information Theory, Inference and Learning Algorithms, Cambridge University Press 2003, Chapter 47. In practice, such LDPC codes are usually applied to multiple pages encoded across a number of memory elements, but they need not be applied across multiple pages. The data bits can be mapped to a logical page and stored in memory structure 326 by programming one or more memory cells to one or more programming states corresponding to v.

[0100] One possible implementation uses an iterative probabilistic decoding process that implements error-correcting decoding equivalent to the coding implemented in the Controller 120. Further details regarding iterative probabilistic decoding can be found in the aforementioned text by D. MacKay. Iterative probabilistic decoding attempts to decode a codeword by assigning initial probability metrics to each bit in the codeword. The probability metrics indicate the reliability of each bit, that is, how likely it is that the bit is not faulty. In one approach, the probability metrics are logarithmic probability ratios (LLRs) obtained from LLR tables. LLR values ​​are measures of the reliability with which the values ​​of various binary bits read from the memory elements are known.

[0101] The LLR for one bit is given by: Q=log2P(v=0|Y)P(v=1|Y), where P(v=0|Y) is the probability that a bit is a 0, given that the read state is Y, and P(v=1|Y) is the probability that a bit is a 1, given that the read state is Y. Thus, an LLR>0 indicates that a bit is more likely to be a 0 than a 1, while an LLR<0 indicates that a bit is more likely to be a 1 than a 0 to satisfy one or more parity checks of the error correction code. Furthermore, a larger value indicates a greater probability or reliability. Thus, a bit with an LLR=63 is more likely to be a 0 than a bit with an LLR=5, and a bit with an LLR=-63 is more likely to be a 1 than a bit with an LLR=-5. LLR=0 indicates that the bit is equally likely to be a 0 or a 1.

[0102] An LLR value can be provided for each of the bit positions in a codeword. Furthermore, the LLR tables can accommodate multiple read results, so a larger LLR is used if the bit value is consistent across different codewords.

[0103] The controller receives the codeword Y1 and the LLRs and iterates successively to determine whether the parity checks (equations) of the error encoding process have been satisfied. If all parity checks have been satisfied, the decoding process has converged and the codeword has been error-corrected. If one or more parity checks have not been satisfied, the decoder will adjust the LLRs of one or more of the bits that do not match a parity check and then reapply the parity check, or the next check in the process, to determine whether it has been satisfied. For example, the size and / or polarity of the LLRs can be adjusted. If the parity check in question is still not satisfied, the LLR can be adjusted again in another iteration. Adjusting the LLRs can result in a bit being inverted (e.g., from 0 to 1 or from 1 to 0) in some, but not all, cases.In one embodiment, a further parity check is applied to the codeword, if applicable, as soon as the relevant parity check is satisfied. In others, the process moves on to the next parity check, returning to the failed check at a later time. The process continues in an attempt to satisfy all parity checks. Thus, the decoding process of Y1 is completed to obtain the decoded information, including the parity bits v and the decoded information bits i.

[0104] Fig. Figure 7 illustrates a conventional read flow that includes ECC correction and read error handling. Step 701 is a read of the data stored in the memory cells to determine a "hardbit" (HB), where the hardbit values ​​correspond to a standard read operation in which the values ​​Vri from Fig. 5A-5C can be used to distinguish the different states when they are well-defined, separate distributions such as in Fig. Steps 5A-5C would be used. In step 703, it is determined whether the read data can be corrected using ECC techniques, and if so, the read process is carried out in step 705. If the hard bit data becomes uncorrectable by the ECC in step 703, a read error handling flow can be called in step 707, which may include various read methods to recover the read data.Some examples of read types that can be used to recover the data content, depending on the embodiment, are: “CFh Read” 711, which is a reread of the hard bit but allows a longer settling time for bias stages such as the voltage of the selected word line; a “Soft Bit” Read 713, which provides information about the reliability of the hard bit value; a “BES Read” 715, which attempts to shift the hard bit read stages to extract the data; and “DLA Read” 717, which takes into account the effects of adjacent word lines on the read selected word line. One or more of these can be combined in various sequences or combinations to attempt to extract the data content if the basic ECC process fails.As soon as the read error handling flow 707 is called as step 703, all embodiments experience a significant degradation in performance. Techniques for using soft bit data while simultaneously reducing the impact on memory performance are presented below. Fig. Section 8 examines the use of soft bits in detail.

[0105] Fig. Figure 8 can illustrate the concept of hard bits and soft bits. Fig. Figure 8 illustrates the overlap of the distribution of two adjacent data states and a set of read values ​​that can be used to determine the data state of a cell and the reliability of such a read operation, with the corresponding hard bits and soft bits shown in the table below for a given encoding of values. The read value VH is an initial data state value or hard read value used to determine a hard bit value (HB value) and corresponds to the values ​​Vri from Fig. 5A, Fig. 5B or Fig. 5C, which are used to distinguish the different states when they are well-defined, separate distributions such as in Fig. 5A-5C would be. The additional read levels VS+, slightly above VH, and VS-, slightly below VH, are "soft read" values ​​and can be used to provide "soft bit" (SB) values. The soft bit values ​​provide information about the quality or reliability of the initial data state values ​​or hard bit data, as the soft bit data provides information about the degree of propagation of the distributions. Some implementations of ECC codes, such as low-density parity codes (LDPC), can use both the hard bit and soft bit data to enhance their capability. Although Fig. While Figure 8 only shows the pair of soft bit read values, other embodiments can use additional edge read values ​​to generate more soft bit values ​​for a given hard bit when higher resolution is desired. Generally, the hard bit corresponds to the presumed data value based on the sensing operation, and the soft information, which can be a single binary soft bit, multiple soft bits, or a decimal / fractional value, indicates the reliability or confidence level of the hard bit value. In ECC methods that use soft information, the soft information can be treated as the probability that a corresponding hard bit value is correct.

[0106] If, during a read operation, VH is below the threshold of the memory cell, the memory cell is non-conductive and the read data value (HB) is read as "0". If a memory cell is located in the middle region of one of the two distributions of Fig. If the data is located at stage 8, a read operation at VS+ and VS- will provide the same result; if these values ​​differ, the threshold voltage of the memory cell lies between these values ​​and could originate from the tail region of either the upper or lower distribution, making the HB data unreliable. Reading at both stages and XNORing the results yields an SB value of "1" if the data is considered reliable and an SB value of "0" if it is unreliable.

[0107] For example, if both SB+ and SB- are "0", then: SB=(SB+)XNOR(SB−) ="0" XNOR "0" =1, SB=1 and the HB read value is treated as reliable. With soft bit decoding in ECC, this results in a memory cell in the upper distribution having HB=“0” and SB=“1” indicates a reliable correct bit (RCB), while a memory cell with a threshold voltage between SB+ and SB- results in SB=“0” to indicate that the HB value is unreliable.

[0108] Fig. 9A and Fig. Figure 9B shows the read levels for calculating hard bit and soft bit values ​​for the lower side of the data in an embodiment with three data bits per memory cell using the encoding of Table 2 above, where soft bit values ​​of 1 and 0 respectively indicate that the hard bit value is reliable and unreliable, respectively. Fig. Figure 9A shows the threshold voltage distribution of memory cells in a 3-bit per cell, similar to that in Fig. 5C, however, the distributions are not as well defined and exhibit a degree of overlap. This overlap can have various causes, such as charge leaks or disturbances where operations on a word line or bit line affect the data state stored in adjacent memory cells. Furthermore, during an actual write operation, the distributions are often not as well defined as in 5C. Fig. 5C has shown that writing memory cells with such high accuracy is detrimental to performance, as it requires a larger number of fine-tuning steps and some cells are difficult or too fast to program. For this reason, programming algorithms typically allow a degree of overlap and rely on ECC to accurately extract the contents of the user data.

[0109] The read points used to distinguish a lower-side data value are represented as dashed vertical lines between states Er and A and between states D and E, along with the corresponding hard bit values ​​below. Due to overlapping distributions, a number of memory cells storing Er or E data are incorrectly read as HB=0, and a number of memory cells storing A or D data are incorrectly read as HB=1. The optimal read values ​​can be determined as part of the device characterization and stored, for example, as melt values ​​for the control switching logic. In some embodiments, the control circuitry can shift these values ​​to improve their accuracy as part of a standard read operation or as part of a read error handling flow 707, known as BES read 715.

[0110] To handle higher error rates, a stronger ECC can be used. However, this requires storing more parity bits, which reduces the proportion of memory cells available for user data and effectively decreases the storage capacity. Performance is also impacted because more calculations are required to encode and decode the codewords and to write and read the additional ECC data. Furthermore, more ECC data must be transferred to and from the ECC switching logic over the data bus structures.

[0111] Fig. Figure 9B shows the soft bit values ​​and the read points that can be used to determine the soft bit values ​​corresponding to the hard bit values ​​on the lower side. Fig. 9A. As shown, the soft bit values ​​are determined based on a pair of read values ​​located on either side of the basic hard bit read value. These soft bit read values ​​can be based on offsets to the hard bit read values, either symmetrical or asymmetrical, and stored as melt values ​​in a register, which is determined, for example, as part of the device characterization. In other embodiments, they can be determined or updated dynamically.Although the use of soft bits in step 713 can be very effective in extracting data content that cannot be extracted in step 703, it comes with a performance disadvantage because it must be called in response to an ECC error in step 703, requires two additional reads for each hard bit read, the soft bit data must be output after the additional reads, and additional calculations must be performed.

[0112] To improve this situation, embodiments of an "efficient soft-sensing mode" are presented below. In this sensing mode, the reading of hard bits and soft bits can be combined into a single sequence that uses two sensing stages to reduce the sensing duration. By using efficient soft-sensing reads as the default mode, the additional soft-bit information for ECC correction can be provided, triggering a read error handling flow. Since only two sensing operations are used to generate both the hard-bit and soft-bit data, this technique avoids the tripling of sensing time that occurs with a standard hard-read and soft-read operation. Furthermore, combining hard-bit and soft-bit sensing into a single sequence avoids much of the additional overhead associated with read sequence operations (e.g.,(activation of charge pumps, startup of word lines, etc.). Fig. Figure 10 illustrates the use of the efficient soft-sensing mode.

[0113] Fig. Figure 10 illustrates the mapping of hard bit and soft bit values ​​together with the read levels used in one embodiment for efficient soft sensing. Fig. 10 resembles Fig. Figure 8 shows the Vth distribution of memory cells for two data states that again overlap in the central region. A hard bit read is performed again, but instead of attempting to be placed in or near the center of the overlap region at a point optimized for distinguishing the two states, in this embodiment the hard bit read is shifted to the lower side of Vth, so that any memory cell reading at or below VH is reliably in the lower data state (illustrated here by a "1" as in the example in Figure 8). Fig. 8). Furthermore, it is assigned a soft bit value of “0”, whereas in contrast to the embodiment of Fig. 8. An SB=0 value now indicates a reliable HB value. If the memory cell reads above VH, its hard bit value corresponds to the higher Vth data state with HB=0. Instead of the two soft bit read operations of Fig. 8 is in the embodiment of Fig. 10 Only a single soft bit read operation is performed as an offset of the VS value to the higher Vth side. If the Vth of the memory cell is above VS, it is assigned an HB value of HB=0 and is considered reliable (HS=0). For a memory cell with a Vth that lies between VH and VS, the memory cell is assigned HB=0 but is considered unreliable (SB=1). It should be noted that in the embodiment of Fig. 10 Only one of the two states is checked for soft bit data, so only the state HB=0 can have one of the two SB values, while the memory cell HB=1 always has SB=0. In other words, soft bit data is determined only on one side (here the lower side, for HB=0) of the pair of overlapping distributions, but not on the other side (here the higher side, for HB=1). In this embodiment, the individual VS read is performed to the left (higher Vth) of the VH read, but in other embodiments the arrangement can also be reversed.

[0114] Although the total amount of data in the embodiment of Fig. 10 is generated, which is less than that of Fig. 8, the efficient soft-sensing mode of Fig. 10 are often sufficient to extract the content of the user data without having to resort to further read error handling. Since only two read operations are required against the provisions of Fig. With 10 involved, the sensing times are shorter and can be reduced even further by performing both read operations as a single sensing operation, as described in relation to Fig. 12 described. Furthermore, less data is transferred to the ECC engine(s): in Fig. 8 results in four combinations of (HB, SB) data, while in Fig. There are only three combinations in 10, meaning 25% less data. The increased error tolerance provided by efficient soft sensing can also improve write performance, as the data does not need to be programmed as precisely, allowing for lower programming tolerance.

[0115] Fig. Figure 11 illustrates the application of the efficient soft-sensing mode to bottom-side data in an embodiment with three data bits per memory cell using the encoding of Table 2. Fig. 11 resembles Fig. 9A and Fig. 9B, however, combines the HB and SB values ​​into a single number and uses the single SB read level for a given HB read level of efficient soft sensing, instead of a pair of SB reads for a given HB. For example, when distinguishing between the Er state and the A state, in the left-hand read, the memory cells on the left reliably have a "1" for the lower side value, with (HB, SB) = (1, 0), where, again, in this encoding, SB = 0 indicates a reliable HB value and SB = 1 an unreliable HB value. In the right-hand read for Er, A, a memory cell on the right indicates a memory cell that has a reliable lower side value of "0", or (HB, SB) = (0, 0). Memory cells with a Vth between the left and right read levels are assigned a lower-side hard bit value of 0, but are considered unreliable, so (HB, SB)=(0,1).In order to distinguish between states D and E during the read operations, the memory cells to the left of the left read operation are reliably “0” ((HB, SB)=(0,0)), the memory cells above the right read operation are reliable data of the lower side “1” ((HB, SB)=(1,0)), and the memory cells between the two are assigned an unreliable value of the lower side “1” ((HB, SB)=(1,1)).

[0116] Fig. Figure 12 illustrates an embodiment for the sensing operations for the reading of the lower page data in an efficient soft-sensing read operation, according to the one described in Fig. 11 illustrated reading points. Illustrated above. Fig. 12 a control gate read voltage waveform VCGRV that can be applied to the word line of a selected memory cell as a function of time for efficient soft sensing for lower page data of a 3-bit-per-cell memory cell, wherein the dashed vertical lines correspond to the four read points that are also in Fig. Eleven values ​​are marked by dashed lines (although, as will be explained later, the order of determination differs). Below the waveform, it is shown how these readings correspond to the Vth values ​​of the D and E state distributions in relation to the waveform above.

[0117] To improve reading time, the embodiment uses in Fig. 12. A "reverse order" read mode is provided, although other embodiments may also use the standard order. In a standard read order, the read voltage applied to the selected memory cells starts with the lower values ​​and works its way up. In the reverse order read mode, the control gate read voltage (VCGRV) applied to a selected word line is first ramped up to a high value and then reads from higher Vth states to lower Vth states. In this bottom-page read example, the read to distinguish states D and E is performed before the read to distinguish state A from the erased state Er. Consequently, after the initial ramp-up, the VCGRV voltage falls to the read level for state E (ER) and then to the read level for state A (AR).This sequence can reduce the time required for much of the additional overhead in read sequence operations (e.g., activating charge pumps, starting up word lines, etc.).

[0118] For each read voltage level, two sensing operations are performed to generate the hard bit and the soft value. This allows for a faster sensing time than if separate read voltages were used. Referring to the state distributions D and E below in Fig. Figure 12 shows that both the dashed line for the HB limit and the dashed line for the SB limit are relatively close to the Vth values, with the SB limit being shifted to the right at a higher Vth value. If the read voltage ER is chosen such that both the HB and SB Vth values ​​conduct to some degree, but to different degrees, then in one embodiment, sensing is based on the discharge of a voltage through the selected memory cell. The HB limit corresponds to a lower Vth value because a memory cell at this point is more conductive than one at the SB limit, consequently discharges faster, and can be determined with a shorter sensing interval. The more slowly discharging SB limit is detected with the same control gate voltage but a longer sensing time.

[0119] Fig. Figure 13 illustrates an embodiment of a sensing amplifier circuit that can be used to determine the hard bit and soft bit values ​​of a memory cell. The sensing amplifier circuit of Fig. 13 can be added to the Sensing Amplifier(s) 230 from Fig. 2A or Fig. 2B correspond and fit into the structure of Fig. 3 be included. In the embodiment of Fig. 13. The state of a memory cell is determined by precharging a sensing line or node SEN 1305 to a predetermined level, connecting the sensing node to the bit line of a precharged selected memory cell, and determining the extent to which the node SEN 1305 discharges over a sensing interval. Depending on the embodiment, a number of variations are possible, but the embodiment of Fig. Figure 13 illustrates some common elements. The node SEN 1305 can be preloaded to a VHLB stage via the switch SPC 1323, where the notation for many of the MOSFET switches here uses the same name for the transistor and the corresponding control signal, with the various control signals from processor 330, state machine 262 and / or other control elements of the embodiments of Fig. 2A, Fig. 2B, and Fig. 3. The node SEN 1305 can be connected to a selected memory cell along a bit line BL 1309 via a switch XXL 1319 to a node SCOM 1307 and then, after any intermediate elements, to a bit line selection switch BLS 1327, which corresponds to the decoding and selection circuitry of the storage device. The SEN node 1305 is connected via the switch BLQ 1313 to the local data bus LBUS 1301, which in turn can be connected via the switch DSW 1311 to the data bus DBUS 1303. A switch LPC 1321 can be preloaded up to one level VLPC, the values ​​of VHLB and VLPC depending on the details of the embodiment and the specifics of the implementation.

[0120] In a sensing operation, a selected memory cell is biased by setting its corresponding selected word line to a read voltage level as described above. In a NAND array implementation, the select gates and the unselected word lines of the selected word line's NAND chains are also biased to be turned on. Once the array is biased, the selected memory cell conducts a level based on the ratio of the applied read voltage to the memory cell's threshold voltage. Capacitor 1325 can be used to store charge on the SEN node 1305, whereby during precharging, the CLK stage (and the bottom plate of capacitor 1325) can be set to a low voltage (e.g., ground or VSS) so that the voltage at the SEN node 1305 is referenced to this low voltage.The pre-charged SEN node 1305 of a selected memory is connected via XXL 1319 and BLS 1327 to the corresponding bit line 1309 and the selected bit lines. It is then allowed to discharge for a sensing interval to a level that depends on the threshold voltage of the memory cell relative to the voltage level applied to the control gate of the selected memory cell. At the end of the sensing interval, XXL 1319 can be switched off to trap the accumulated charge in SEN 1305. At this point, the CLK level can be raised slightly, which also raises the voltage at SEN 1305 to account for voltage drops across intermediate elements (such as XXL 1319) in the discharge path. Consequently, the voltage level at SEN 1305, which controls the degree to which transistor 1317 is switched on, reflects the data state of the selected memory cell relative to the applied read voltage.The local data LBUS 1301 is also pre-charged, so that when the strobe transistor STB 1315 is switched on for a strobe interval, the LBUS discharges onto the CLK node, which is determined by the voltage stage at SEN 1305. At the end of the strobe interval, STB 1315 is switched off to set the sensing value on the LBUS, and the result can be latched in one of the latches, as shown in [reference]. Fig. 3 illustrated.

[0121] Now, referring again to Fig. 12. After biasing the selected memory cell to voltage level ER and biasing other arrays (selection gates, unselected word lines, etc.) as needed, the pre-charged SEN node 1305 is discharged for the interval ER between the dashed lines: if the SEN level is high enough to discharge LBUS 1301 when STB 1315 is strobed, the memory cell's Vth is below HB; otherwise, it is above HB. After discharging for the additional interval ER+, STB 1315 is strobed again: if LBUS 1301 now discharges, the memory cell's Vth is between HB and SB; otherwise, it is above SB. The process is then repeated with the VCGRV value at the AR level to determine the HB and SB values ​​for distinguishing between the A and erased states.

[0122] Consequently, in the Fig. In the 12 illustrated embodiment, for each VCGRV stage, the left sensing result is used to generate HB data, and the right sensing result is combined with the left sensing result to generate SB data. To optimize performance for two sensing operations (left / right), the embodiment in Fig. 12 the “sensing time modulation” for Vth separation without a change in the voltage level of the word line.

[0123] Regarding the efficient soft-sensing controls and parameters for the read stage, these can, similar to the usual implementations of read parameters, be determined as part of the device characterization process and stored as register values ​​(e.g., as control data parameters set as melt values ​​in memory 266), determined dynamically, or a combination of these. In one set of embodiments, the hard-bit and soft-bit read stages for efficient soft-sensing can be referenced to the standard hard-bit read values. Even when the efficient soft-sensing read process is used as the standard read operation, a storage device often has a standard read operation (i.e., hard-bit only) as a read mode option, so the standard read values ​​of Fig. 5A-5C are available as a read option. For example, to access Fig. Returning to section 11 and the read levels related to the distinction between the distributions of states D and E, the efficient soft-sensing levels can be referenced relative to the normal HB read trim values, represented by the thicker dashed line at the vertex of the distributions of states D and E. The efficient soft-sensing read levels for left read (the efficient soft-sensing hard bit, minus level) and right read (the efficient soft-sensing soft bit, plus level) can be specified relative to the normal HB read levels. This allows the reuse of fixed feature registers to generate the efficient soft-sensing left / right shifts, and in a set of embodiments, a common setting for all levels with individual settings for each of the states can be used.

[0124] Fig. Figure 14 is a high-level flowchart for an embodiment of an efficient soft-sensing process. The process is described in the context of a storage system as described above with reference to Fig. 1-4G and those relating to Fig. The embodiment described in section 12 is described. The process begins at step 1401 with the execution of a first sensing operation on a plurality of memory cells to determine hard bit values ​​that distinguish between two of the data states of the memory cells. In an efficient soft-sensing implementation, both the hard bit read operations of step 1401 and the soft bit read operations of step 1403 can be performed in response to a single read instruction. Referring again to Fig. 1. The host 102 and / or the non-volatile memory controller 120 can, for example, send an efficient soft-sensing command to one or more of the memory locations 130. The system control logic 260 ( Fig. 2A and Fig. 2B) then performs a sensing operation, such as reading a lower data page in the preceding examples, to determine both a hard bit value and a soft bit value of the memory cells, as in Fig. 11 illustrated.

[0125] To perform the hardbit determination of step 1401, in the embodiments described above, the memory array is biased for the read operation and the sensing node of the corresponding sensing amplifier(s) is preloaded. Specifically, in the embodiments used herein as examples, the control gates of the selected memory cells are biased with a read voltage via their corresponding word lines to distinguish between the data states, and other array elements (e.g., selected gates and unselected word lines of NAND chains) are biased as needed based on the memory architecture. When using a sensing amplifier, such as the one described in Fig. 13, in which the data states are determined when unloading a sensing node SEN 1305, the sensing node SEN 1305 is preloaded and connected to the bit line of a selected memory cell to unload itself for a first sensing interval (the area delimited by ER (HB) in Fig. 12), to determine the hard bit value.

[0126] As with regard to the embodiment of Fig. As illustrated in Figure 11, the hard bit determination is shifted to a lower Vth value, so that memory cells detected below this value are reliably within this value, while memory cells detected above this value include both reliable and unreliable hard bit values. In embodiments using the more traditional sequence sensing, hard bit sensing would be performed first for the hard bit, followed by the soft bit for distinguishing between the Er and A states, and then the hard bit and soft bit for distinguishing between the D and E states, requiring a different bias and preload of the sensing node for each sensing operation. With reference to Fig. The sensing process illustrated in Figure 12 is performed in reverse order. First, the hard bit and soft bit values ​​for D-state and E-state differentiation are determined, followed by the determination of the hard bit and soft bit values ​​for the Er- and A-states. Although the process in Fig. While step 14 represents the hard bit determination (step 1401) before the soft bit determination (step 1403), the order may be reversed in some embodiments. Furthermore, the sequence of Fig. 14 only contains a single hard bit and a single soft bit definition. In many cases (as in Fig. 12) Several hard bit / soft bit pairs are determined.

[0127] In step 1403, a second sensing operation is performed to determine a soft bit. In the efficient soft-sensing process, reliability information is only determined for memory cells that have a first, but no second, of the hard bit values. In the embodiment of Fig. For example, in version 11 the hard bit limit is shifted downwards and the soft bit value only applies to the higher of the hard bit values. In the Fig. In the embodiment described in Section 12, the second sensing process is based on a longer discharge time of the pre-charged sensing node SEN 1305. If it is necessary to distinguish between the states of a pair during reading (as, for example, in an embodiment of a binary memory cell), only that one hard bit / soft bit pair is determined. In multi-level memory cells, additional hard bit / soft bit pairs are determined, as in the preceding examples in Fig. 11 and Fig. Step 12, where a soft-sensing operation for the lower side also determines a hard bit / soft bit pair, similar to steps 1401 and 1403 for Er / A state determination. Once the hard bit and soft bit data values ​​are determined, they can be used in step 1405 to perform an ECC operation. This can be done on the non-volatile memory controller 120 in the ECC engine 158, on the control chip 211, or a combination of both.

[0128] Although the use of efficient soft sensing reduces the amount of detected soft bit data, and consequently the amount of soft bit data to be transferred to an ECC engine, compared to a standard hard bit / soft bit arrangement, it still represents a significant increase in data compared to using hard bit data. To reduce the amount of data that needs to be transferred from a memory chip to the ECC engine, the soft bit data can be compressed in memory before being transferred to the non-volatile memory controller via the bus structure. Techniques for compressing soft bit data are presented below. These techniques can be applied to both efficient and standard soft sensing, although the following discussion primarily uses an efficient soft sensing implementation as an example.

[0129] In particular, the exemplary embodiments presented below are primarily based on the efficient soft-sensing mode as described above in relation to Fig. 10-14. As described above, the efficient soft-sensing mode can reduce the performance degradation when using soft-bit data, making it practical as a standard read mode with one page of hard-bit data output and one page of soft-bit data output in a read sequence. These pages of soft-bit and hard-bit data are then transferred to an error correction engine, which extracts the data content of the user data page. In some embodiments, some or all of the ECC operations can be performed on the control chip 211 of Fig. 2B or the memory chip 200 from Fig. 2A, but typically the ECC operations are performed on an ECC engine 158 on the non-volatile memory controller 120, whereby the read hard bit and soft bit data must be transferred from interface 269 to the controller 120 via the external data bus structure. To give an example of the data volumes, a data page from a single layer in one embodiment of 3D NAND memory can represent 16 KB of user data along with the corresponding parity bits and redundancy data for defective memory locations. Consequently, without compression, in addition to the 16+ kilobytes of hard bit data per layer, 16+ kilobytes of soft bit data per layer would also be transferred.

[0130] To maintain storage performance, the soft bit data can be compressed before transmission to the memory chip 200 or the control chip 211. For example, if a compression factor N is used, the amount of transmitted soft bit data is reduced by 1 / N, so the choice of compression factor is a trade-off between speed and the amount of soft bit data available to the ECC engine. A number of compression techniques with different compression factors can be used. For example, a compression factor of N=4 can be implemented by a logical AND operation on the soft bit data in sets of four soft bits. While this would not indicate the individual reliability of the corresponding hard bit values, it would suggest that at least one of a set of four hard bit values ​​should be treated as unreliable.

[0131] Fig. Figure 15 is a block diagram of an embodiment for some of the control circuit elements of a memory device, which includes a soft-bit compression element. The example shown relates to a four-level memory device, and most of the elements shown can be repeated for each level, but other embodiments may use fewer or more levels. Depending on the embodiment, this control circuitry may be located on a control chip 211, which is connected to one or more memory chips 201, as shown in Figure 15. Fig. 2B shown. In other embodiments, the one or more control circuits can be located on a memory chip 200 containing the memory arrays 202, for example, located at the periphery of the memory chip 200 or formed on the substrate under the 3D NAND memory structure described above.

[0132] In Fig. For the sake of simplicity, only the common blocks of level 3 (1501-3) are labeled in section 15, but it is self-evident that each of the common blocks (level 0, 1501-0; level 1, 1501-1; level 2, 1501-2; and level 3, 1501-3) includes the respective common blocks 1505, 1507, and 1509. These blocks correspond to the elements of the row control logic 220, the column control logic, and the system control logic 260. Fig. 2A and Fig. 2B, but are more representative of how these elements are physically arranged in some embodiments. On either side of each layer are line decoders 1503-L and 1503-R, which can decode connections to the word lines and select lines of the layer's array and to the line decoders 222 and other elements of the line control switching logic 220 of Fig. 2A and Fig. 2B can correspond. A column control circuit 1509 can correspond to the column control switching logic 210 of Fig. 2A and Fig. 2B corresponds. On both sides above and below the column control circuit for columns 1509 are a set of sensing amplifiers 1505, including the internal data latches, and a cache buffer 1507. Referring again to the sensing amplifier switching logic of Fig. Level 3 can correspond to the internal data latches of 1505, ADL, BDL, and CDL, and the cache buffer 1507 can correspond to the transfer data latches XDL. The other levels, while not labeled, contain similar elements. Instead, arrows are included in the other levels to indicate the data flows for data transferred between the level's memory cells and the I / O interface. Similar transfers may also occur in level 3 (1501-3), but these are not shown to allow the block labels to be displayed.

[0133] The in Fig. The control circuit(s) shown in Figure 15 also includes an input / output (IO) circuit, including IO pads 1517 and a data path block 1515, which performs (multibit) serial-to-parallel transformations for incoming write data and parallel-to-(multibit) serial transformations for outgoing read data. The DP block 1515 is connected to the byte-width (in this example) IO pads 1517 to transfer data to and from the non-volatile memory controller 120 via an external data bus. In the block diagram of Fig. The DP block 1515 and the IO pads 1517 are located in level 1 1501-1. However, these elements can be placed on any of the levels or distributed between the levels, with placement on one of the central levels (level 1 1501-1 or level 2 1501-2) reducing routing. A global data bus GDB 1511 within the storage device spans the levels and enables the transfer of data to and from each level and the DP block 1515. The vertical arrows in Fig. Figure 15 illustrates the data flow for transferring data between the upper sensing amplifier blocks 1505 and the I / O pads 1517, excluding those for layer 3 (1501-3) to allow block labeling. During a read operation, data pages from a layer's memory array are captured by the sensing amplifiers 1505 and stored in the corresponding internal data latches. They are then moved to the cache buffer 1507 of the transfer latches and forwarded to the global data bus 1511 via the column control circuitry 1509. From the global data bus 1511, the hard bit data is then converted into (byte-width) serial data via the DP block 1515, which is output via the I / O pads 1517. When writing data, the data flow can be reversed along the path used by the hard bit data.

[0134] With regard to the corresponding soft bit data, the soft bit data is compressed after its intended use (whether for efficient soft sensing or conventional soft sensing) before being output from the storage device to the ECC engine. The embodiments for compressing the soft bit data presented in the following discussion perform the compression within the SA / internal data latches 1505 and the transfer latches of the cache buffer 1507. After compression, the compressed soft bit data can take the same path as the hard bit data from the cache buffer 1507 to the I / O pads 1517. Since the compression process can affect the logical address assignment of the soft bit data, the DP block 1515 can contain assignment logic to ensure that the compressed soft bit data is correctly assigned. Fig. 16, Fig. 17A and Fig. 17B provides further details of embodiments for the data latches that can be used in the softbit data compression process.

[0135] Fig. Figure 16 is a schematic representation of the correspondence between the SA / internal data latches 1505 and the transfer latches of the cache buffer 1507. Fig. 15 and the sentences of data latches 340, 342, 344 and 346 from Fig. 3. The internal data latches connected to the sensing amplifier of SA / internal DLs may, depending on the embodiment, include the ADL, BDL, and CDL latches, as well as the sensing amplifier data latch (SDL) and possibly other data latches. The cache buffer includes the transmit data latches XDL and also additional latches, such as the DTCT latches for temporary data storage and operations like bit scanning. The internal data latches are connected via a local data bus LBUS, with the internal data latches being connected to the transmit data latches via a data bus DBUS. This is shown in Fig. 17A is illustrated in more detail.

[0136] Fig. Figure 17A is a schematic representation of the structure for one embodiment of the data latches. The example in Fig. 17A relates to an embodiment with 3 bits per cell, in which each sensing amplifier (SA) has a set of associated data latches forming a “layer,” including a sensing amplifier data latch (SDL), the data latches for the 3-bit data states (ADL, BDL, CDL), and an auxiliary data latch (TDL), which can be used, for example, for implementing fast-running write operations. Within each of these stacks of data latches, data can be transferred between the sensing amplifier and its associated set of latches via a local bus LBUS. In some embodiments, each of the sensing amplifiers and the corresponding set of internal data latches of a layer, associated with a bit line, can be grouped for a corresponding “column” of bit lines and formed on a memory chip within the spacing of the column of memory cells along the periphery of the memory cell array.The example described herein uses an embodiment in which 16 bit lines form a column, so that a 16-bit word is physically contained within the array. A memory array might, for example, have 1000 such columns, corresponding to 16K bit lines. In the embodiment of... Fig. In the 4B topology, each sensing amplifier and its set of associated data latches of a layer are connected along an internal bus structure of DBUSes, over which data can be transferred between each layer of latches and a corresponding XDL. In the embodiment described below, the XDL transfer latches can transfer data to and from the I / O interface, but the other data latches of the layer (e.g., ADL) are not arranged to transfer data directly to or from the I / O interface, but must take the detour via the transfer data latch XDL.

[0137] Fig. 17B illustrates an embodiment for the group of columns from Fig. 17A. Fig. 17B repeats the structure of Fig. Figure 17A shows 16 times, with only the internal data latches of level 0 of each set being shown. Each DBUS is connected to a set of 16 XDLs. Each of the horizontal rows (as shown in the figures) is connected to one of the XBUS lines, so that the bottom row (or "XDL level") of XDLs is connected to XBUS. <0> is connected to the next line or level of XDLs with XBUS <1> is connected and so on, with the XDLs of XDL level 15 connected to XBUS <15> are connected. Fig. Figure 17B also illustrates an arrangement of the DTCT latches, with one DTCT latch for each sensing amplifier level / DBUS value, which is also connected to one of the XDL levels / XBUS values. In this arrangement, each DTCT latch is connected to DBUS and XBUS connected for an i-value, so that the leftmost DTCT is connected to both DBUS <0> as well as with XBUS <0> is connected, the next DTCT is connected to both DBUS <1> as well as with XBUS <1> is connected and so on, until the rightmost DTCT is connected to both DBUS <15> as well as with XBUS <15> is connected. The compression of softbit data values ​​within the data latch structures, which is described below, is related to the embodiment of Fig. Figure 17B shows a compression technique, although other embodiments can also be used. Furthermore, although these compression techniques are discussed in the context of compressing soft-bit data, and in particular an efficient soft-sensing implementation, they can also be applied to compressing other data stored in the storage device.

[0138] In a vertical compression scheme, the data within a word unit is compressed. The soft bit (or other data) stored in an internal data latch is compressed and then written to the XDL latches or, alternatively, back to the internal data latches. The compressed data is then reordered within the allocation logic of DP block 1515 during streaming to bring the compressed data into the logical order of the user columns. Fig. Figure 18 illustrates the first step of the process for an exemplary embodiment.

[0139] Fig. Figure 18 illustrates the compression of the original softbit data from one set of internal data latches to another set of data latches. In this example, the original softbit data is stored in the ADL latches, compressed with a compression factor of N=4, and stored in the BDL latches, but other embodiments may use different combinations of internal data latches. (See above.) Fig. Figure 18 is a 16x16 table with vertically arranged sensing amplifier (SA) layers and horizontally arranged XDL layers as in Fig. Figure 17B shows the entries corresponding to the soft bit data of an efficient soft-sensing operation, with the squares for the "0" values ​​highlighted by dot stitching. In a vertical compression scheme, the data for each XDL level (i.e., one column in) Fig. 18) In N=4 compression, 16 values ​​are compressed to 4 values, so that the compressed data can be stored in only four sensing amplifier levels of BDL latches, with SA levels 0-3 storing the compressed data and dummy entries (here "1") being entered into the other SA levels for the BDL latches. In particular, in the embodiment of Fig. 18. The soft bit data of each XDL layer are grouped into sets of 4 SA layers and the values ​​are combined according to the AND compression algorithm: where & represents the logical AND of the ADL entries: e.g. &ADL[3:0] = ADL[3] AND ADL[2] AND ADL[1] AND ADL[0].

[0140] The lower part of Fig. Figure 18 shows the entries in the compressed efficient soft-sensing data values ​​in the BDL latches, with the compressed soft-bit data located in the lower four rows of SA levels 0-3, as highlighted by the dotted line, and the other rows being filled with dummy "1" values. For example, with regard to the first column for the XDL level 0 values, the SA level 0 value is "0" to reflect the presence of a "0" in ADL[3:0] at SA level 1, while SA levels 1, 2, and 3 are all "1" because there are no other "0" values ​​in ADL[7:4], ADL[11:8], or ADL[15:12]. In the example of XDL level 15 (rightmost column), the “0” softbit values ​​in SA levels 0 and 13 for ADL are reflected in the compressed values ​​of BDL[3:0]= (0110).It should be noted that in this N=4 compression algorithm, a compressed value of "0" means that at least one of the four soft bit values ​​is "0", so all four corresponding hard bit values ​​are treated as unreliable. Although the compressed soft bit data does not provide as fine a resolution as uncompressed soft bit data, it is usually sufficient to significantly facilitate data decoding. Also note that the example of soft data above is in... Fig. 18 has a relatively high number of "0" values ​​to facilitate discussion.

[0141] Fig. Figure 19 again illustrates an N=4 compression of the original ADL<15:0> data to BDL<3:0>, but in an embodiment using a spatial compression algorithm. The original soft bit is recompressed and stored in SA levels 0-3 of the BDL latches, with dummy "1" values ​​entered in the other SA levels. To illustrate the spatial algorithm, the uncompressed soft bit data in the ADL latches has a "0" along the antidiagonal of the entries where the number of SA levels equals the number of XDL levels. The BDL<3:0> values ​​are then a 4-bit value indicating an SA level with a "0" soft bit value. For example, at XDL level 2, the "0" of SA level 2 corresponds to the 4-bit binary value (0010) = 2. For other cases, such as no "0" soft bit values ​​or more than one "0", one of the values ​​(e.g., (1111)) can also be used for these cases.

[0142] Fig. Figure 20 illustrates the shifting of compressed softbit data from the BDL SA layer<3:0> to another SA layer based on XDL layer information. In this embodiment, the compressed softbit data values ​​of the XDL layers are Fig. 18 are shifted upwards by an amount dependent on the XDL level to the various SA levels, this being done cyclically, and XDL levels 0, 4, 8, and 12 are not shifted; XDL levels 1, 5, 9, and 13 are shifted upwards by 4 SA levels; XDL levels 2, 6, 10, and 14 are shifted upwards by 8 SA levels; and XDL levels 3, 7, 11, and 15 are shifted upwards by 12 SA levels. In some embodiments, the Fig. 18 or Fig. 19 illustrated compression step with the change from Fig. 20 can be combined. Other latches can be used to store the XDL layer information of this shift, with this data being created for either the XBUS side or the DBUS side. In the embodiment of Fig. 20. The XDL layer information is stored in the CDL and TDL latches as 2-bit values, where (00) indicates that the compressed data has not been shifted, (01) indicates that it has been shifted up 4 SA layers, (10) indicates that it has been shifted up 8 SA layers, and (11) indicates that it has been shifted up 12 SA layers. The compressed data is then shifted from the internal data latches to the XDL transfer latches, which can be a standard, direct shift from BDL to XDL, so that the data is again as in Fig. 20 would be arranged, but now in the XDL latches, which is in the upper section of Fig. 21 is shown.

[0143] Fig. Figure 21 illustrates a transfer within the transfer latches for compressing the data. Referring again to Fig. 17B allows XDL-to-XDL transfers to be performed over the XBUS structure using temporary storage in the DTCT latches. As in Fig. As illustrated in Figure 21, the compressed data in each of the XDL levels 1, 2, and 3 can be moved to XDL level 0, the compressed data in each of the XDL levels 4, 5, 6, and 7 can be moved to XDL level 1, and so on for the other XDL levels, which are indicated by the grouping and the arrows in Figure 21. Fig. Figure 21 illustrates this. At the end of the process, the compressed data is consolidated or condensed into XDL levels 0-3, while the previous data can remain in the other levels until it needs to be overwritten later. The purpose of this condensation is to summarize the compressed data in a limited number of XDL levels to reduce the time required for data output (output from 16 levels to output from 4 levels in the example with a compression factor of N=4).

[0144] With renewed reference to Fig. 15. The compressed softbit data can be processed after they have been, as in Fig. Figure 21 illustrates how the data was loaded into the transfer latches of the cache buffer 1507, transferred via the control circuit for columns 1509 to the global data bus 1511, and then to the data path block 1515 for transmission via the I / O pads 1517. The data shown in Fig. However, the data movements illustrated in Figures 18-21 can affect the position of the data in the external data latches relative to their local user address positions. To account for this, the assignment logic in data path block 1515 can be used to rearrange the data bits of the compressed soft bit data so that they are in a sequential logical column order when the data is output.

[0145] Fig. Figure 22 is a schematic representation of the rearrangement of the compressed data bits into a logical sequence. As in Fig. As shown in Figure 21 below, the compressed data in the XDL layers are formed into 16-bit words, which are transferred from the transfer latches of cache buffer 1507 to DP block 1515; due to the in Fig. However, in the manipulations illustrated in 18-21, the data bits can be shuffled during the data output process to bring them into the order of the logical user column addresses. In the exemplary embodiment, where groups of 4 bits of the compressed data are used as in Fig. Figure 21 illustrates that to form the 16-bit words in the XDL layers, these 4-bit units are rearranged using the assignment logic in DP block 1515. Fig. Figure 22 illustrates an embodiment in which the data is received from the global data bus 1511 in a parallel 8 x 16-bit word format, with the word W0 containing bits 0-15, W1 containing bits 16-31, and so on up to W7 containing bits 112-127, as illustrated on the left. These words W0-W7 are partitioned into sets of 4 bits to form the words W0'-W7', with the first 4 bits of W0-W3 each going into W0', the next 4 bits of W0-W1 each going into W2', the third 4 bits of W0-W1 each going into W4', and the last 4 bits of W0-W1 each going into W6'. The words W4-W7 are similarly rearranged into W1', W3', W5', and W7'. These words W0'-W7' can then be output in this newly arranged word order in (byte-width) serial format via the IO pads 1517.

[0146] In relation to Fig. 2A and Fig. 2B, the DP block 1515, including the assignment logic, can be part of the interface 268, which is controlled by the system control logic 260. Depending on the embodiment, additional latches or FIFOs, along with switching logic for multiplexing, can be included in the DP block 1515 to facilitate the reordering of the compressed data into the sequence of the logical user column addresses.

[0147] Fig. Figure 23 is a block diagram of an alternative embodiment for some of the elements of the control circuit of a storage device, which includes a soft-bit compression element. The embodiment of Fig. 23 repeats the elements of Fig. 15, which have a similar number (i.e., cache buffer 1505 is now 2305, global data bus GDB 1511 is now 2311, etc.), now additionally or alternatively includes the assignment logic within the control circuit for column 2309, in addition to or as an alternative to the assignment logic in DP block 1515. Depending on the implementation of the control circuit logic of Fig. 15 or Fig. 23. It may be easier or more efficient to rearrange the compressed data bits, in whole or in part, into the logical order in the column control circuit for columns 2309 than in the DV block 1515 or 2315.

[0148] For example, due to time constraints, the available space for the switching logic, or the switching logic topology, it may be difficult to completely reorder the compressed data bits into the user's logical order using DP block 2315. To completely reorder the compressed data bits, in one embodiment, the compressed data bits are partially reordered in the assignment logic of the control circuit for columns 2309 before being transferred to the global data bus 2311, transferred to DP block 2315, and then further reordered to be completely in the user's logical order in the assignment logic of DP block 2315 before being output from the device via the IO pads 2317. With this arrangement, the Fig. Figures 18-21 illustrate the process of compressing the read soft bits or other data until the compressed data is consolidated or condensed at the end of Fig. 21 be the same. However, instead of transmitting the condensed, compressed data at this point via the global data bus 2311 and only performing the reorganization process as in Fig. As illustrated in DP block 2315, the reorganization can be carried out as in 22. Fig. 24A and Fig. 24B is illustrated.

[0149] Fig. 24A and Fig. Figure 24B is a schematic representation of an alternative embodiment of rearranging the compressed data bits into a logical sequence using the embodiment of Fig. 23. The in Fig. 24A and Fig. The steps illustrated in section 24B can begin with the compressed data bit being compacted in the XDL latches of the cache buffer 2307, as shown below. Fig. 21 illustrated. Fig. Figure 21 illustrates data condensed into three XDL levels, such as W0<3:0> for the word zero, with the other XDL levels remaining open for other condensed words of data. In this N=4 example, three further data condensations can be stored. If, for example, a read page (e.g., word line) corresponds to M such words, then (in the N=4 example) the word line can be divided into four sections of M / 4 words, such that W0 is in the first XDL levels <3:0>, W(M / 4) in the XDL levels <7:4>, W(2M / 4) in the XDL levels <11:8>, and W(3M / 4) in the XDL levels <15:12>, with the next word in each of these sections being grouped with W1, and so on. This is shown above in Fig. Figure 24A illustrates an example of (M / 4)=288. As can be seen in each of the lines, the various bits in a compressed word can therefore include bits from words that, before compression, originated from widely separated logical words, so that, for example, W1 in the XDL latches of cache buffer 2307 can contain compressed data bits from the logical words W1, W289, W577, and W864. To accomplish this, in one embodiment, a first step for reordering can occur when the compressed and compacted data bits are transferred from the XBUSs of cache buffer 2307 to an IOBUS of the control logic for columns 2309, as shown below. Fig. 24A illustrates this.

[0150] In the example of Fig. In 24A, the IO bus within the control logic for columns 2309 has two 16-bit wide buses, IOBUS A and IOBUS B. In this first stage of the reorganization, the compressed and condensed data words are rearranged by the assignment logic of the control logic for columns 2309 so that the addresses of the logical words are grouped for a specific subdivision. One embodiment for the placement of the compressed data for the first 64 logical words for the pair of IO bus values ​​0-8 for IOBUS A and IOBUS B is shown. In this example, the compressed bits for the logical words W0, W16, W32, and W48 are located on IOBUS0A, with the values ​​of the logical words on IOBUS1A being incremented by 1, and so on, with the values ​​on IOBUS B being incremented by 8 logical words.The specific width of the IO bus and the number of buses are implementation-specific and depend on the degree of parallelism used in the different phases of the data transmission process.

[0151] By using multiplexing switching logic within the control switching logic for columns 2309, the compressed data bits can be shifted from the arrangement below into Fig. 24A to the words of the order above in Fig. 24B can be further rearranged. In one embodiment, in the partially rearranged form, the compressed data bits are transferred via the global data bus 2311 to the DP block 2315, where the multiplexing switching logic within the assignment logic can then complete the reordering in the sequence of logical addresses, as shown in the lower part of Fig. Figure 24B illustrates this. Within DP block 2315, the multiplexing switching logic within the assignment logic can complete the restructuring of the compressed data, similar to that in Fig. The process described in section 22, and the restructured compressed data can then be output via the IO pads 2317.

[0152] Fig. Figure 25 is a flowchart for an embodiment of performing data compression within the data latches connected to the sensing amplifiers of a non-volatile storage device. Starting with step 2501, a read operation is performed on multiple memory cells using the sensing amplifier circuits, with the results of the read operation being stored in the internal data latches corresponding to the read amplifiers in step 2503. With reference to Fig. 15. These steps are performed in the SA / internal DLs 1505, with the internal data latches (ADL, BDL, ...) in the Fig. 17A and Fig. The layer structure illustrated in Figure 17B can be arranged. Regarding Fig. 2A and Fig. 2B, the reading process is performed as described above using the control switching logic of the row control switching logic 220, the column control switching logic 210, and the system control logic 260. In the main example here, soft bit data is processed in an efficient soft-sensing operation with reference to Fig. 10-14 can be determined. In general, the compression process can be applied to the usual type of soft bit data, as in Fig. As described in sections 8-9B, or applied to other data. In any case, in the example described above, at the end of step 2503 the soft bit or other read data is stored in the ADL latches.

[0153] The compression process begins in step 2505 with the compression of the data within the sets of internal data latches, as shown in Fig. 18 or Fig. Figure 19 illustrates where the data is compressed in ADL<15:0> and stored in BDL<3:0> for each of the XDL layers. Referring again to Fig. 3. This process and the subsequent data latch manipulations can be controlled by processor 330 and system logic 260. After compression, the data can be rearranged within the internal data latches in step 2507, as shown in Fig. Figure 20 illustrates this, and then in step 2509 the data is copied from the internal data latches to the external data latches XDL of the cache buffer 1507. Depending on the embodiment, a number of variations are possible, such as combining steps 2505 and 2507, using different latches, different compression algorithms, or different rearrangements of the compressed data, wherein Fig. 18-22 are just one example. In any case, the soft bit or other data can be compressed within the internal data latches before the compressed data is transferred to the cache buffer 1507.

[0154] Once the compressed data is stored in the transfer latches of the cache buffer 1507, the compressed data can be consolidated in step 2511, as with the compression in Fig. 21, to be transmitted more efficiently via the global data bus 1511 to the input / output interface elements of the DP block 1515 and the IO pads 1517. The compressed data bits can be rearranged into a user-defined logical sequence in step 2513 and then output via an external data bus in step 2515. As above with respect to Fig. 15 and Fig. As described in section 22, the reordering can be carried out in the assignment logic of DP block 1515; within the assignment logic of the control switching logic of the control circuit for columns 2309; or a combination of these, as described in Fig. 23, Fig. 24A, and Fig. 24B described. In the case of softbit data, this may include transmission to an ECC engine (e.g., 158 from Fig. 1). Fig. Figure 22 illustrates an example of the reordering of the compressed data for the specific reorderings of the preceding steps of the exemplary embodiment, but in other cases the reordering could be different or not take place before transmission, with the reordering being carried out later if necessary.

[0155] According to a first set of considerations, a non-volatile storage device includes a control circuit configured for a plurality of bit lines, each connected to a corresponding plurality of memory cells. The control circuit includes: a plurality of sensing amplifiers, each configured to read data from the memory cells connected to one or more corresponding bit lines; a plurality of sets of internal data latches, each set of internal data latches configured to store data connected to a corresponding set of sensing amplifiers; and an input-output interface configured to provide data to an external data bus.The control circuit is configured to: perform a read operation by each of the sensing amplifiers on a plurality of memory cells; store the results of the read operation by each of the sensing amplifiers in the corresponding set of internal data latches; compress the results of the read operation by each of the sensing amplifiers within the corresponding set of internal data latches; and transfer the compressed results of the read operation to the external data bus via the input-output interface.

[0156] In further terms, a method includes the following: performing a read operation by each of a plurality of sensing amplifiers on a plurality of memory cells; storing the results of the read operation by each of the sensing amplifiers in a corresponding set of internal data latches; performing, within the corresponding set of internal data latches, a data compression operation of the results of the read operations by each of the sensing amplifiers; and transferring the compressed results of the read operations from the sets of internal data latches to an input-output interface.

[0157] Additional features include a non-volatile storage device comprising: a plurality of bit lines, each connected to a corresponding plurality of non-volatile memory cells; a plurality of sensing amplifier circuits, each configured to read data from a memory connected to one or more corresponding bit lines; a plurality of sets of internal data latches, each set of internal data latches configured to store data connected to a corresponding sensing amplifier; a cache buffer comprising a plurality of sets of transfer data latches, each corresponding to one of the sets of internal data latches; and an input / output interface configured to provide data to an external data bus.and one or more control circuits connected to the sensing amplifier circuits, the sets of internal data latches, the cache buffer, and the input / output interface. The one or more control circuits are configured to: perform a read operation by each of the plurality of sensing amplifiers on a plurality of the corresponding memory cells; store the results of the read operation by each of the sensing amplifiers in the corresponding set of internal data latches; compress the results of the read operation by each of the sensing amplifiers within the corresponding set of internal data latches; transfer the compressed results of the read operation from each of the sets of internal data latches to the corresponding set of transfer data latches; and transfer the compressed results of the read operation from the sets of transfer data latches to the input / output interface.

[0158] For the purposes of this document, a reference in the patent specification to “one embodiment”, “some embodiments” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0159] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is described as connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intermediary elements. When an element is described as directly connected to another element, there are no intermediary elements between the element and the other element. Two devices are "in communication" when they are connected to each other, directly or indirectly, such that they can transmit electronic signals to each other.

[0160] For the purposes of this document, the term “based on” can be read as “at least partially based on”.

[0161] For the purposes of this document, without additional context, the use of numerical expressions such as a "first" object, a "second" object, and a "third" object may not imply a sequence of objects, but may instead be used for identification purposes to distinguish between different objects.

[0162] For the purposes of this document, the term “set” of objects can refer to a “set” of one or more of the objects.

[0163] The preceding detailed description has been provided for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the exact form disclosed. Many modifications and variations are possible, taking into account the teaching stated above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, and thus to enable other skilled persons to best utilize it in various embodiments and with various modifications suitable for their respective intended uses. The scope of protection is intended to be defined by the claims included herein.

Claims

[1] Non-volatile storage device comprising: a control circuit configured to connect to a plurality of bit lines, each of which is connected to a corresponding plurality of memory cells, wherein the control circuit comprises the following: a plurality of sensing amplifiers (230), each configured to read data from the memory cells connected by one or more corresponding bit lines; a plurality of sets of internal data latches (340, 342, 344, 346), each set of internal data latches (340, 342, 344, 346) being configured to store data connected to a corresponding sensing amplifier (230); and an input / output interface configured to provide data for an external data bus (334), the control circuit is set up to: to perform a read operation through each of the sensing amplifiers (230) on a plurality of memory cells; to store the results of the reading operation by each of the sensing amplifiers (230) in the corresponding set of internal data latches (340, 342, 344, 346); to compress the results of the reading operation by each of the sensing amplifiers (230) within the corresponding set of internal data latches (340, 342, 344, 346); and to transfer the compressed results of the read operation via the input / output interface to the external data bus (334); and a cache buffer (1507) which has a plurality of sets of transfer data latches, each corresponding to one of the sets of internal data latches (340, 342, 344, 346), wherein, in order to transmit the compressed results of the reading operation via the input-output interface to the external data bus (334), the control circuit is further configured to: to transfer the compressed results of the read operation from each of the sets of internal data latches (340, 342, 344, 346) to a corresponding set of transfer data latches; to compress the results of the read operation from the sets of transfer data latches into a smaller number of sets of transfer latches; and to transfer the compressed results of the read operation to the input-output interface before transferring the compressed results of the read operation to the external data bus (334). [2] Non-volatile storage device according to claim 1, wherein the control circuit is formed on a control chip (211), the non-volatile storage device further comprising: a memory chip that includes the plurality of bit lines and corresponding plurality of non-volatile memory cells, wherein the memory chip is designed separately from and connected to the control chip (211). [3] Non-volatile storage device according to claim 1, wherein the results of the read operation are soft bit data values. [4] Non-volatile storage device according to claim 3, wherein the control circuit is further configured to: to perform a hard bit read operation through each of the sensing amplifiers (230) on the plurality of memory cells in order to determine a hard bit value for each of the plurality of memory cells, indicating whether the memory cell is either reliably in a first data state or unreliably in a second data state, wherein each of the soft bit data values ​​corresponds to one of the hard bit values ​​and indicates the reliability value of memory cells that have been determined to be in the second data state, but not for memory cells that have been determined to be in the first data state. [5] Non-volatile storage device according to claim 1, wherein the control circuit is further configured to: to rearrange the bits of the compressed results of the read operation before the compressed results of the read operation are transferred to the external data bus (334). [6] Non-volatile storage device according to claim 1, wherein the control circuit is further configured to: to receive the compressed results of the read operation at the input-output interface in a parallel format; and to convert the compressed results of the read operation before the compressed results of the read operation are transferred to the external data bus (334). [7] Non-volatile storage device according to claim 1, wherein, for the purpose of compressing the results of the read operation by each of the sensing amplifiers (230) within the corresponding set of internal data latches (340, 342, 344, 346), the control circuit is further configured to: to perform logical combinations of several ones of the results of the reading process by each of the sensing amplifiers (230). [8] Non-volatile storage device according to claim 1, further comprising: an array of non-volatile memory cells that includes the multitude of bit lines, each corresponding to a multitude of memory cells, formed according to a three-dimensional NAND architecture. [9] Methods, exhibiting: Performing a read operation by each of a plurality of sensing amplifiers (230) on a plurality of memory cells; Storing the results of the reading operation by each of the sensing amplifiers (230) in a corresponding set of internal data latches (340, 342, 344, 346); Perform, within the corresponding set of internal data latches (340, 342, 344, 346), a data compression operation of the results of the read operations by each of the sensing amplifiers (230); and Transferring the compressed results of the read operations from the sets of internal data latches to an input-output interface, where transferring the compressed results of the read operation from the sets of internal data latches (340, 342, 344, 346) to the input-output interface includes the following: Transferring the compressed results of the read operation from each of the sets of internal data latches (340, 342, 344, 346) to a corresponding set of transfer data latches; Compressing the compressed results of the read operation from the sets of transfer data latches into a smaller number of sets of transfer latches; and Transferring the condensed, compressed results of the reading process to the input / output interface. [10] Method according to claim 9, further comprising: Rearranging the bits of the compressed results of the read operation in the input / output interface. [11] Method according to claim 10, further comprising: Receiving the compressed results of the read operation at the input / output interface in a parallel format; and Converting the compressed results of the read operation into a serial format before transferring the compressed results of the read operation to the external data bus (334). [12] Method according to claim 9, wherein the results of the reading operation are soft bit data values. [13] Method according to claim 12, further comprising: Performing a hard bit read operation by each of the sensing amplifiers (230) on the plurality of memory cells to determine a hard bit value for each of the plurality of memory cells, indicating whether the memory cell is either reliably in a first data state or unreliably in a second data state, wherein each of the soft bit data values ​​corresponds to one of the hard bit values ​​and indicates a reliability value for memory cells that have been determined to be in the second data state, but not for memory cells that have been determined to be in the first data state. [14] Method according to claim 13, further comprising: Transferring the hard bit values ​​and the corresponding soft bit data values ​​from the input / output interface to an error correction code engine. [15] Non-volatile storage device comprising: a multitude of bit lines, each connected to a corresponding multitude of non-volatile memory cells; a multitude of sensing amplifier circuits, each configured to read data from a memory connected to one or more corresponding bit lines; a plurality of sets of internal data latches (340, 342, 344, 346), each set of internal data latches (340, 342, 344, 346) being configured to store data connected to a corresponding sensing amplifier (230); a cache buffer (1507) which has a plurality of sets of transfer data latches, each corresponding to one of the sets of internal data latches (340, 342, 344, 346); an input / output interface configured to provide data for an external data bus (334); and one or more control circuits connected to the sensing amplifier circuits, the sets of internal data latches (340, 342, 344, 346), the cache buffer (1507) and the input / output interface, wherein the one or more control circuits are configured to: to perform a read operation through each of the plurality of sensing amplifiers (230) at a plurality of the corresponding memory cells; to store the results of the reading operation by each of the sensing amplifiers (230) in the corresponding set of internal data latches (340, 342, 344, 346); to compress the results of the reading process by each of the sensing amplifiers (230) within the corresponding set of internal data latches (334); to transfer the compressed results of the read operation from each of the sets of internal data latches to the corresponding set of transfer data latches; and to transfer the compressed results of the read operation from the sets of the transfer latches data latches to the input-output interface, where one or more control circuits remain set up to: to compress the results of the read operation from the sets of transfer data latches into a smaller number of sets of transfer latches before transferring the results of the read operation from the sets of transfer latches to the input / output interface. [16] Non-volatile storage device according to claim 15, wherein the results of the read operation are soft bit data values. [17] Non-volatile storage device according to claim 15, wherein the non-volatile storage device includes: a control chip (211) on which one or more control circuits are formed; and a memory chip that includes the plurality of bit lines and corresponding plurality of non-volatile memory cells, wherein the memory chip is designed separately from and connected to the control chip (211).

Images