LATERAL BIPOLAR TRANSISTOR

Abstract

Comprehensive structure: an intrinsic basis (30) comprising semiconductor material in a channel region of a semiconductor substrate (12); an extrinsic basis (32) vertically above the intrinsic basis (30); an isolation region (28) in the channel region and below the intrinsic base (30); an elevated collector region (40) on the semiconductor substrate (12) and laterally connected to the intrinsic base (30); and an elevated emitter region (38) on the semiconductor substrate (12) and laterally connected to the intrinsic base (30).

Description

AREA OF INVENTION

[0001] The present disclosure relates to semiconductor structures and in particular a lateral bipolar transistor and manufacturing process. BACKGROUND

[0002] Bipolar transistors can be vertical or lateral. In a vertical bipolar transistor, the carriers flow in a vertical direction. Because the collector region is located deep within the wafer surface, the emitter-collector resistance increases, making the transistor unsuitable for high-speed operation. Additionally, the transistor requires a highly concentrated buried layer, an epitaxial collector layer, and deep trench insulation, among other things. Consequently, the number of processing steps increases, and therefore, so do the costs.

[0003] On the other hand, the lateral bipolar transistor is simpler in construction than the vertical bipolar transistor. Furthermore, in a lateral bipolar transistor, a collector electrode can be brought directly into contact with a collector region, which is advantageous for high-speed operation. However, current integration schemes can result in high Ccb (parasitic capacitance) and high Rb, which is a problem in bipolar technologies because it limits device scaling for improved fT / fMAX. Lateral bipolar transistors, in which the emitter, base, and collector of the transistor are placed directly on an insulating layer of an SOI substrate, are described, for example, in US 2012 / 0 139 009 A1, US 2013 / 0 256 757 A1, and the document by NING, Tak H.; CAI, Jin: On the performance and scaling of symmetric lateral bipolar transistors on SOI. In: IEEE Journal of the Electron Devices Society, Vol. 1, 2013, No. 1, pp. 21-27. - ISSN 2168-6734 known.Furthermore, semiconductor structures are known from US 2015 / 0 102 348 A1 and US 10 037 989 B1 which feature bipolar transistors and field-effect transistors in different areas of a semiconductor substrate. BRIEF SUMMARY

[0004] In one aspect of the disclosure, a structure comprises: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; an isolation region in the channel region and below the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substrate and laterally connected to the intrinsic base.

[0005] In one aspect of the disclosure, a structure comprises a lateral heterojunction bipolar transistor on a substrate material, wherein the lateral heterojunction bipolar transistor comprises: an intrinsic base region in a channel region of the substrate material; an extrinsic base region above the intrinsic base region; an isolation region in the channel region and below the intrinsic base; a raised collector region comprising epitaxial semiconductor material adjacent to the extrinsic base; and a raised emitter region comprising the epitaxial semiconductor material adjacent to the extrinsic base; and a gate structure on the substrate material, wherein the gate structure comprises a gate material and raised source / drain regions comprising the epitaxial semiconductor material; and isolation regions that isolate the gate structure from the lateral heterojunction bipolar transistor.

[0006] In one aspect of the disclosure, a process comprises: forming an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; forming an extrinsic base vertically above the intrinsic base; forming an insulator material in the channel region and below the intrinsic base; forming a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and forming a raised emitter region on the semiconductor substrate and laterally connected to the intrinsic base. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is described in the following detailed description with reference to the aforementioned multitude of drawings, using non-limiting examples of exemplary embodiments of the present disclosure. Fig. Figure 1 shows a substrate and a gate structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 2 shows a liner encapsulating the gate structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 3 shows an opening in a stack of materials formed over a hard mask, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 4 shows an inner spacer material formed within the opening, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 5 shows a smaller opening in the stack of materials, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 6 shows an isolation region formed in the substrate by the smaller opening, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 7 shows the underlying substrate, which is exposed in the smaller opening, along with other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 8 shows an intrinsic base and an extrinsic base formed in the smaller opening, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 9 shows elevated epitaxial regions on sides of the extrinsic base and the gate structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. Figure 10 shows a silicide and contacts to a lateral bipolar transistor and a CMOS transistor, among other features, and respective manufacturing processes according to aspects of the present disclosure. DETAILED DESCRIPTION

[0008] The present disclosure relates to semiconductor structures and, in particular, a lateral bipolar transistor and fabrication method. Specifically, the lateral bipolar transistor is formed by a self-aligned trench on a fully depleted semiconductor-on-insulator (FDSOI) substrate. Advantageously, the lateral bipolar transistor minimizes parasitic capacitance and provides tunability based on a base width, e.g., a base width (Wb) of < 20 nm, which is defined by separate structuring, thus enabling the tunability.

[0009] In embodiments, the lateral bipolar transistor can be a lateral NPN heterojunction transistor comprising an intrinsic SiGe base laterally connected to an emitter and a collector. The intrinsic SiGe base provides an Ft / Fmax improvement due to its smaller SiGe bandgap. The lateral bipolar transistor also includes an extrinsic base vertically above the intrinsic base. Spacers are formed on both sides of the extrinsic base to provide isolation from the emitter and collector regions. A silicide, e.g., NiSi, can also be formed on the extrinsic base for improved base contact. The intrinsic base can be SiGe extending into a recess in a channel of a semiconductor-on-insulator (SOI) substrate, while allowing maximum tuning freedom using an intrinsic base width (< 20 nm) (without degrading the bipolar device).In some embodiments, the base width is much smaller than the CMOS gate length (Lg). The lateral bipolar transistor can be fabricated on the same chip as a planar CMOS device, particularly for RF SOC (> 1 THz) applications.

[0010] The lateral bipolar transistor of this disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools used are those for forming structures with dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to fabricate the lateral bipolar transistor of this disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films that are patterned on the top side of a wafer by photolithographic processes.In particular, the fabrication of the lateral bipolar transistor uses three basic building blocks: (i) deposition of thin material films on a substrate, (ii) application of a structured mask to the top of the films by photolithographic imaging, and (iii) etching the films selectively with respect to the mask.

[0011] Fig. Figure 1 shows a substrate and a gate structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. In particular, the structure 10 comprises a substrate 12 and a gate structure 16 composed of exit work metals, polysilicon material, and a gate dielectric material. In embodiments, a cap layer 16a, e.g., polysilicon material, can be formed on an upper surface of the gate structure 16. The cap layer 16a can, as a non-limiting illustrative example, be composed of an oxide liner and a nitride cap material on the oxide liner. The gate dielectric material can be a high-k gate dielectric material, e.g., HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations comprising multilayers thereof.

[0012] Although not critical for understanding the present disclosure, the gate structure 16 can be fabricated using conventional CMOS processes. For example, the gate structure 16 can be fabricated using standard CMOS or replacement gate processes. In standard CMOS processing, e.g., a gate-first process, the gate materials, e.g., a gate dielectric, exit work metal, polysilicon, and the cap layer 16a, are formed onto the substrate 12, e.g., deposited, followed by a structuring process. The structuring process can be a conventional etching process, such as reactive ion etching (RIE), to form a stack of materials comprising the gate structure 16.

[0013] The substrate 12 is preferably a fully depleted semiconductor-on-insulator (FDSOI) substrate. For example, the substrate 12 comprises a semiconductor handle substrate 12a, an insulator layer 12b, and a semiconductor layer 12c. In embodiments, the semiconductor handle substrate 12a and the semiconductor layer 12c can be composed of any suitable material comprising, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The semiconductor handle substrate 12a can be a p-type substrate. The semiconductor layer 12c can also comprise any suitable crystallographic orientation (e.g., a crystallographic (100), (110), (111), or (001) orientation). Depending on the desired device performance, the semiconductor layer 12c, which is used as a channel region for subsequently formed devices, can be deposited to different thicknesses (Tsi).The insulating layer 12b can comprise a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof, and preferably a buried oxide layer (BOX) supported on the semiconductor handle substrate 12a.

[0014] Referring further to Fig. 1. Flat trench isolation structures 14 are formed in the semiconductor layer 12c, extending to the insulator layer 12b. The flat trench isolation structures 14 can be formed by conventional lithography, etching, and deposition processes known to those skilled in the art. For example, a resist formed above the semiconductor layer 12c is exposed to energy (light) to form a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to transfer the structure from the structured resist layer to the semiconductor layer 12c, forming one or more trenches in the semiconductor layer 12c through the openings of the resist. Following resist removal by a conventional oxygen ashing process or other known stripping agents, the resist can be removed by any conventional deposition process, e.g.,Insulator material (e.g., oxide-based material) can be deposited via chemical vapor deposition (CVD) processes. Any remaining material on the surface of semiconductor layer 12c can be removed by conventional chemical mechanical polishing (CMP) processes.

[0015] In Fig. 2 is a liner 18 formed on the semiconductor layer 12c and over the gate structure 16. In embodiments, the liner 18 encapsulates the gate structure 16. The liner 18 can be an oxide material deposited as a blanket on the semiconductor layer 12c and the gate structure 16. A hard mask 20 can be formed over the liner 18. In embodiments, the hard mask 20 can be deposited as a blanket over the liner 18 by conventional deposition processes, e.g., CVD. The hard mask 20 can, for example, be SiCN.

[0016] As further in Fig. As shown in Figure 3, a stack of materials 22 can be formed over the hard mask 20. The stack of materials 22 can include materials used in lithography and etching processes. For example, the stack of materials 22 can include SOH 22a, SiON 22b, and an antireflective coating 22c (e.g., a bottom anti-reflective coating (BARC)). An opening 24 can be formed in the antireflective coating 22c and material 22b using conventional lithography and etching processes as described herein. In embodiments, the opening 24 has a cross-section “x”. In embodiments, the cross-section “x” can have a minimum critical dimension, e.g., approximately 20 nm to 50 nm in width or diameter. The opening 24 can also extend partially into material 22a.

[0017] In Fig. 4. The antireflective coating 22c can be removed using known stripping agents. An inner spacer material 25 can be formed above the material 22b and within the opening 24. The inner spacer material 25 can, for example, be an oxide material. The inner spacer material 25 can be deposited by a conventional deposition process, such as CVD. As should be clear to those skilled in the art, the inner spacer material 25 effectively reduces the cross-sectional area of ​​the opening to a dimension “y”. In embodiments, the dimension “y” is tunable based on the thickness of the inner spacer material 25. For example, a thicker inner spacer material 25 reduces the dimension “y”; whereas a thinner inner spacer material 25 increases the dimension “y”.

[0018] In Fig. 5. The dimension “y” can be transferred to the material 22a by an etching process that forms an opening 26. In this process, the etching process removes the horizontal surfaces of the inner spacer material 25 inside and outside the opening, extending such an opening 26 into the material 22a. In embodiments, the opening 26 can also extend partially within the hard mask 20. The dimension “y” can be approximately 20 nm or less; although this dimension is tunable to other cross-sectional dimensions, e.g., diameters or widths. In further embodiments, the dimension “y” is less than a gate length (Lg) of the gate structure 16.

[0019] As further in Fig. As shown in Figure 6, the opening 26 (and its dimension “y”) can be extended through the hard mask 20, exposing the liner 18. The material 22b and the inner spacer material 25 can be removed by conventional etching or stripping processes. The underlying semiconductor substrate 12c can be subjected to an ion implantation process, as indicated by the arrows, to form an isolation region 28 within a channel region of the semiconductor substrate 12c. In embodiments, the ion implantation is a lightly doped P+ implant, e.g., BF2, in the underlying semiconductor substrate 12c using conventional ion implantation processes.

[0020] In Fig. 7. The exposed liner 18 within the opening 26 can be removed by a conventional etching process. The isolation region 28 can also be thinned or recessed to match an intrinsic base that is formed over the isolation region 28 in subsequent manufacturing processes.

[0021] As in Fig. As shown in Figure 8, a semiconductor material 30, e.g., an intrinsic base, can be formed within the opening 26, followed by a semiconductor material 32, e.g., an extrinsic base, and a cap material 34 within the opening 26. In embodiments, the opening 26 allows self-alignment of the semiconductor material 30, e.g., the intrinsic base, the semiconductor material 32, e.g., the extrinsic base, and the cap material 34, each of which now has a dimension “y” of the opening 26.

[0022] The semiconductor material 30, e.g., the intrinsic base, can be undoped SiGe material formed within the recessed section of the channel region, i.e., above the isolation region 28, which is aligned with the opening 26. The semiconductor material 32, e.g., the extrinsic base, can be, for example, P+-doped Si material also formed in the opening 26. Furthermore, both the semiconductor material 30, e.g., the intrinsic base, and the semiconductor material 32, e.g., the extrinsic base, can be epitaxially grown semiconductor material, with the P+ doping of the semiconductor material 32 being carried out, for example, in situ. The cap material 34 is preferably the same material as the cap layer 16a of the gate structure 16, e.g., oxide / nitride. A CMP or non-selective etching process can be performed to remove any excess cap material 34 from the hard mask 20.

[0023] As should be clear to those skilled in the art, the semiconductor material 30, e.g., the intrinsic base, and the semiconductor material 32, e.g., the extrinsic base, can both be tuned by adjusting their width and / or thickness. For example, a larger opening 26 would result in a wider base width; whereas a smaller opening would result in a narrower base width. Similarly, the thickness of the isolation region 28 can be tuned to provide more or less semiconductor material 30, e.g., the intrinsic base, and semiconductor material 32, e.g., the extrinsic base. For example, a thinner isolation region 28 in the channel region would result in a thicker intrinsic base, and vice versa.

[0024] As further in Fig. As shown in Figure 9, the hard mask 20 and the liner 18 can be removed, e.g., stripped, using conventional etching or stripping processes. This exposes both the extrinsic base material 32 (with the cap material 34) and the gate structure 16 (with the cap layer 16a). Sidewall spacers 36 are formed on the sidewalls of the extrinsic base material 32 and the gate structure 16. In embodiments, the sidewall spacers 36 can be a low-k spacer material, i.e., an oxide formed by a conventional blanket deposition process followed by an anisotropic etching process. Advantageously, the sidewall spacers 36 can be formed on the sidewalls of the extrinsic base material 32 and the gate structure 16 in the same manufacturing processes.

[0025] On the sides of the sidewall spacer 36 of the extrinsic base, e.g., the semiconductor material 32, a raised emitter region 38 and a raised collector region 40 can be formed to create a lateral bipolar transistor 100. In particular, the raised emitter region 38 and the raised collector region 40 can be N+ doped semiconductor material, thus forming a lateral NPN heterojunction bipolar transistor 100. In embodiments, the intrinsic base 30 can be laterally connected to the raised emitter region 38 and the raised collector region 40.

[0026] Fig. Figure 9 further shows raised source / drain regions 42 formed on the sides of the sidewall spacer 36 of the gate structure 16 to form a planar CMOS transistor 200. In embodiments, the raised emitter region 38, the raised collector region 40, and the raised source / drain regions 42 can be formed by an epitaxial growth process. For example, the raised emitter region 38, the raised collector region 40, and the raised source / drain regions 42 can be formed from Si material, and preferably N+-doped Si material, using the same conventional selective epitaxial growth process.

[0027] In Fig. 10. The cap material 34 and the cap layer 16a can be removed by a stripping process, e.g., a nitride hard mask stripping process, which is known to those skilled in the art. A silicide 44 can be formed on the exposed semiconductor material 32 (e.g., the extrinsic base) and the polysilicon gate material of the gate structure 16, in addition to the raised emitter region 38, the raised collector region 40, and the raised source / drain regions 42. In embodiments, the silicide 44 provides an improved base contact and thus, compared to conventional structures, a lower base resistance.

[0028] As should be clear to those skilled in the art, the silicide process begins with the deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over fully formed and structured semiconductor devices (e.g., semiconductor material 32, polysilicon material, and raised epitaxial regions 38, 40, 42). After deposition of the material, the structure is heated, allowing the transition metal to react with exposed silicon (or another semiconductor material, as described herein) in the active regions of the devices, forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 44 in the active regions of the device.

[0029] Referring further to Fig.10, contacts 48a-48f are formed at the silicide contacts 44. In embodiments, the contacts 48a-48f are formed by conventional lithography-etching and deposition processes within an interlevel dielectric material 46. In embodiments, the interlevel dielectric material 46 can be a stack of materials, e.g., oxide and nitride.

[0030] In a more specific example, the interlevel dielectric material 46 can be deposited by conventional CVD processes, followed by trenching to expose the silicide contacts 44 of the semiconductor material 32 (e.g., the extrinsic base), the emitter region 38, and the collector region 40 of the lateral bipolar transistor 100, alongside the epitaxial source / drain regions 42 and the polysilicon material of the gate structure 16 of the CMOS transistor 200. Within the trenches, a conductive material, e.g., aluminum or Wolf space, can be deposited to form the contacts 48a-48f to the respective regions 38, 32, 40, 42, and 16. Any excess conductive material can be removed from the surface of the interlevel dielectric material 46 by a conventional CMP process.

[0031] The lateral bipolar transistor can be used in system-on-a-chip (SoC) technology. An SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume far less power and occupy much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant technology in mobile computing (such as in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0032] The process(s) described above is / are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic substrate with conductors attached to a motherboard or other higher-level support) or in a multi-chip package (such as a ceramic substrate having one or both surface interconnects or buried interconnects). In each case, the chip is then integrated with other chips, discrete switching elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that feature a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure encompassing: an intrinsic basis (30) comprising semiconductor material in a channel region of a semiconductor substrate (12); an extrinsic basis (32) vertically above the intrinsic basis (30); an isolation region (28) in the channel region and below the intrinsic base (30); an elevated collector region (40) on the semiconductor substrate (12) and laterally connected to the intrinsic base (30); and an elevated emitter region (38) on the semiconductor substrate (12) and laterally connected to the intrinsic base (30). [2] Structure according to claim 1, wherein the intrinsic basis (30) is recessed in the channel region of the semiconductor substrate (12). [3] Structure according to claim 1 or 2, wherein the intrinsic basis (30) comprises SiGe. [4] Structure according to claim 3, wherein the isolation region (28) comprises a P+ isolation region (28), and wherein the semiconductor substrate (12) comprises semiconductor-on-insulator material with the P+ isolation region (28) in the channel region. [5] Structure according to claim 4, wherein the P+ isolation region comprises a recess and the intrinsic base (30) is located in the recess. [6] Structure according to any one of claims 1 to 5, further comprising a gate structure (16) on the semiconductor substrate (12), wherein a width of the intrinsic base (30) is less than a gate length of the gate structure (16). [7] Structure according to claim 6, wherein the width of the intrinsic base (30) is less than 20 nm. [8] Structure according to claim 6 or 7, wherein the gate structure (16) comprises epitaxial raised source / drain regions (42) comprising the same material as the raised collector region (40) and the raised emitter region (38). [9] Structure according to any one of claims 1 to 8, further comprising a sidewall spacer (36) on sidewalls of the extrinsic base (32), wherein the sidewall spacer (36) isolates the extrinsic base (32) from both the raised collector region (40) and the raised emitter region (38). [10] Structure according to any one of claims 1 to 9, wherein the raised collector region (40) and the raised emitter region (38) comprise N+ doped semiconductor material and the extrinsic base (32) comprise a P+ doped semiconductor material, and the N+ doped semiconductor material and the P+ doped semiconductor material comprise a lateral NPN heterojunction transistor. [11] Structure according to any one of claims 1 to 10, further comprising a silicide (44) at the extrinsic base (32). [12] Structure encompassing: a lateral heterojunction bipolar transistor (100) on a substrate material, wherein the lateral heterojunction bipolar transistor (100) comprises: an intrinsic base region (30) in a channel region of the substrate material; an extrinsic base region (32) over the intrinsic base region (30); an isolation region (28) in the channel region and below the intrinsic basal region (30); an elevated collector region (40) comprising epitaxial semiconductor material adjacent to the extrinsic base region (32); and an elevated emitter region (38) comprising the epitaxial semiconductor material adjacent to the extrinsic base region (32); and a gate structure (16) on the substrate material, wherein the gate structure (16) comprises a gate material and raised source / drain regions (42) that encompass the epitaxial semiconductor material; and Isolation regions (14a) which isolate the gate structure (16) from the lateral heterojunction bipolar transistor (100). [13] Structure according to claim 12, wherein the lateral heterojunction bipolar transistor (100) comprises a lateral NPN heterojunction bipolar transistor. [14] Structure according to claim 13, wherein the epitaxial semiconductor material of the raised emitter region (38) and the raised collector region (40) comprises N+ doped semiconductor material and the extrinsic base region (32) comprises a P+ doped semiconductor material. [15] Structure according to claim 14, wherein the raised source / drain regions (42) comprise N+ doped semiconductor material. [16] Structure according to one of claims 12 to 15, wherein the intrinsic base region (30) comprises SiGe material and is laterally connected to the raised collector region (40) and the raised emitter region (38). [17] Structure according to one of claims 12 to 16, wherein the extrinsic base region (32) is isolated from the raised collector region (40) and the raised emitter region (38) by a sidewall spacer material (36) on sidewalls of the extrinsic base region (32). [18] Structure according to one of claims 12 to 17, further comprising a silicide (44) at at least the extrinsic base region (32). [19] Structure according to any one of claims 12 to 18, wherein the width of the intrinsic base region (30) is less than the length of the gate structure (16). [20] Procedure encompassing: Forming an intrinsic basis (30) comprising semiconductor material in a channel region of a semiconductor substrate (12); Forming an extrinsic basis (32) vertically above the intrinsic basis (30); Formation of an insulator material (28) in the channel region and under the intrinsic base (30); Forming an elevated collector region (40) on the semiconductor substrate (12) and laterally connected to the intrinsic base (30); and Forming an elevated emitter region (38) on the semiconductor substrate (12) and laterally connected to the intrinsic base (30).

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