semiconductor device

Abstract

Semiconductor device comprising: - an insulating layer (1) having a first surface and a second surface opposite the first surface; - at least one semiconductor element (2) located on the side of the first surface; - a first metal sintered material (3a) which is in contact with the first surface of the insulating layer (1) and the semiconductor element (2) and connects the insulating layer (1) and the semiconductor element (2); - a second metal sintered material (3b) which is in contact with the second surface of the insulating layer (1); - a housing (5) covering the semiconductor element (2); and - a third metal sintered material (3c) which is in contact with the first surface of the insulating layer (1), wherein an adhesive (6) is provided between the third metal sintered material (3c) and the housing (5).

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to semiconductor devices.Description of the Prior ArtFor example, Japanese Patent Application JP 2021-027 288 A discloses a technology for connecting, using a metal sintered material, semiconductor chips and a wiring layer connected to an insulating plate.However, in a semiconductor device as described above, stress is caused at an interface between the wiring layer and the metal sintered materials and at an interface between the wiring layer and the insulating plate due to heat generated by driving the semiconductor chips. This results in errors at these interfaces, thereby reducing reliability.JP 2015-109 299 A relates to a heat dissipation plate having a metallization layer integrated directly with a base and good adhesion. The heat dissipation plate is composed of a base made of nitride ceramic and a heat dissipation layer containing copper as a main component and a glass component directly applied to at least one surface of the base. The glass component contains 0.5 mol % or more and 5 mol % or less of AgO.JP 2019-125 720 A discloses an electronic device that can supply a high current to a circuit pattern without having to convert it into a thick film structure. The device includes a substrate, a wiring layer formed on the upper surface of the substrate, an electronic component mounted on the upper surface of the wiring layer, and a connection layer disposed between the electronic component and the wiring layer. The wiring layer and the connection layer are porous layers having holes. The connection layer has a higher bulk density than the wiring layer except for the areas immediately below the electronic component.SummaryThe present invention is devised in view of a problem described above, and it is an object of the present invention to provide a technology that enables reliability of a semiconductor device to be increased.The object on which the invention is based is achieved in a semiconductor device according to the invention with the features of claim 1. Advantageous refinements are the subject matter of the respective dependent claims.A semiconductor device according to the present invention includes: an insulating layer having a first surface and a second surface opposite to the first surface; at least one semiconductor element located on a side of the first surface; a first metal sintered material that is in contact with the first surface of the insulating layer and the semiconductor element and that connects the insulating layer and the semiconductor element; a second metal sintered material that is in contact with the second surface of the insulating layer, a case that covers the semiconductor element; and a third metal sintered material that is in contact with the first surface of the insulating layer, wherein an adhesive is provided between the third metal sintered material and the case.Reliability of the semiconductor device can be increased.These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.Brief Description of the FiguresFIG. 1 is a plan view illustrating a configuration of a semiconductor device according to Embodiment 1 for further background of the present invention; FIG. 2 is a cross-sectional view illustrating the configuration of the semiconductor device according to Embodiment 1 for further background of the present invention; FIG. 3 is a cross-sectional view illustrating a configuration of a first connected semiconductor device for further background of the present invention; FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 2 of the present invention; FIG. 5 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 3 of the present invention; FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 4 of the present invention; and FIG. 7 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 5 of the present invention.DESCRIPTION OF EMBODIMENTSHereinafter, embodiments related to the other technical background and the invention itself will be described with reference to the accompanying drawings. Features described in the following embodiments are examples, and not all features are required. In the following description, similar components in the embodiments bear identical or similar reference numerals, and different components will be mainly described. In the following description, specific locations and directions such as "upper", "lower", "left", "right", "front", and "rear" do not necessarily coincide with locations and directions in an actual implementation.<Ausführungsform 1 for Further Technical Background of the Invention>FIG. 1 is a plan view illustrating a configuration of a semiconductor device according to Embodiment 1 for further background of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1.The semiconductor device according to Embodiment 1 for further background of the present invention includes an insulating layer 1, semiconductor elements 2, a first metal sintered material 3 a, a second metal sintered material 3 b, a base plate 4, a case 5, an adhesive 6, a lid 7, gate electrodes 8, an emitter electrode 10, wires 11, and a sealing material 12 illustrated in FIG. 2, and a collector electrode 9 illustrated in FIG. 1.As illustrated in FIG. 2, the insulating layer 1 has an upper surface as a first surface and a lower surface as a second surface that is opposite to the first surface. The insulating layer 1 is an insulating plate formed of, for example, ceramic.The semiconductor elements 2 are located on a side of the upper surface of the insulating layer 1. the semiconductor elements 2 include, for example, semiconductor switching elements such as insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs), or diodes such as pn junction diodes (PND) and Schottky diodes (SBD). A material for the semiconductor elements 2 is silicon (Si) as a typical material in Embodiment 1 for further background of the present invention, but is not limited to silicon as described below. The number of semiconductor elements 2 is two in Embodiment 1 for further background of the present invention, but it is only required to be one or more.The first metal sintered material 3 ais in contact with the upper surface of the insulating layer 1 and the semiconductor elements 2, and connects the insulating layer 1 and the semiconductor element 2. the second metal sintered material 3 bis in contact with the lower surface of the insulating layer 1. metal sintering is a technology for hardening a metal at a temperature below its melting point, that is, baking a metal at a temperature below its melting point. A metal sintered material is formed by applying a paste material obtained by mixing a solution with metal particles such as copper (Cu) and silver (Ag), and hardening the paste material by metal sintering. The first metal sintered material 3 afunctions as a circuit structure in Embodiment 1 for further background of the present invention.The base plate 4 is in contact with the second metal sintered material 3 b, and is connected to the insulating layer 1 through the second metal sintered material 3 b. The case 5 covers outer peripheries (here, sides) of the semiconductor elements 2. the adhesive 6 bonds the case 5 to the base plate 4. in an example illustrated in FIGS. 1 and 2, the case 5 has holes 5 a, and is fixed to the base plate 4 by bolts and the like through the holes 5 a. The lid 7 covers the upper surfaces of the semiconductor elements 2, and the base plate 4, the case 5, and the lid 7 form an inner space which is insulated from an outer space.The gate electrodes 8, the collector electrodes 9, and the emitter electrode 10 are each provided integrally with the case 5, one end and the other end thereof being located in the inner space and the outer space, respectively. The semiconductor elements 2 in the inner space are electrically connected to the ends of the gate electrodes 8 and the emitter electrode 10 by wires 11. The semiconductor elements 2 are also electrically connected to the end in the inner space of the collector electrode 9 by wires 11 and the first metal sintered material 3 aas illustrated in FIG. 1. The sealing material 12 in FIG. 2 is formed of, for example, an insulating material, and fills the internal space in which the semiconductor elements 2 and the wires 11 are present.The semiconductor device as described above is used for an inverter circuit, for example, in which a main current flowing through the collector electrode 9, the wires 11, the first metal sintered material 3 a, the semiconductor elements 2, the wires 11, and the emitter electrode 10 in this order is controllable by a voltage across the gate electrodes 8.Semiconductor devices (hereinafter referred to as a first connected semiconductor device and a second connected semiconductor device) connected to the semiconductor device according to Embodiment 1 for further background of the present invention will be described herein. FIG. 3 is a cross-sectional view illustrating a configuration of the first connected semiconductor device.In the first connected semiconductor device, the insulating layer 1 and a copper pattern 14 awhich is not a metal sintered material are connected by a silver brazing material 13 a, and the insulating layer 1 and a copper pattern 14 bwhich is not a metal sintered material are connected by a silver brazing material 13 b. The copper pattern 14 aand the semiconductor elements 2 are connected by solders 15 a, and the copper pattern 14 band the base plate 4 are connected by a solder 15 b.By the configuration of the semiconductor device connected as described above, stress is repeatedly applied to the solders 15 aand 15 bas the temperature in the first connected semiconductor device increases and decreases due to driving for repeatedly turning on and off the semiconductor elements 2. This results in cracks starting from the solders 15 aand 15 band the like, thereby reducing reliability such as product life. Further, since the silver brazing materials 13 aand 13 b, the main component of which is silver, are used as joining materials between the insulating layer 1 and the copper pattern 14 aand between the insulating layer 1 and the copper pattern 14 b, whiskers (whiskers) are formed, thereby reducing reliability.The second connected semiconductor device, which is not illustrated, will be described next. In the second connected semiconductor device, typical wiring layers are provided between the first metal sintered material 3 aand the insulating layer 1 and between the second metal sintered material 3 band the insulating layer 1 in the configuration of the semiconductor device according to Embodiment 1 for further background of the present invention of FIG. 1. When the above stress acts on the interfaces between the wiring layer and the first metal sintered material 3 aand between the wiring layer and the second metal sintered material 3 band on interfaces between the wiring layers and the insulating layer 1 in the second connected semiconductor device described above, a defect occurs at the interfaces, thereby reducing reliability.On the other hand, in Embodiment 1 for further background of the present invention, the solders 15 aand 15 bof the first connected semiconductor device are not used, so that the product life such as a turn-on cycle and a temperature cycle can be extended to increase reliability. Moreover, the silver brazing materials 13 aand 13 bof the first connected semiconductor device are not used, so that generation of whiskers can be suppressed to increase reliability of the semiconductor device.The second connected semiconductor device has two kinds of interfaces including the interfaces between the wiring layer and the first metal sintered material 3 aand between the wiring layer and the second metal sintered material 3 band the interfaces between the wiring layers and the insulating layer 1. On the other hand, in Embodiment 1 for further background of the present invention, no interfaces exist between the wiring layers and the insulating layer 1, and the interfaces can be reduced to only one type of interfaces including the interfaces between the first metal sintered material 3 aand the insulating layer 1 and between the second metal sintered material 3 band the insulating layer 1.< Embodiment 2>FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 2 of the present invention.The semiconductor device according to Embodiment 2 of the present invention does not include the base plate 4 described in Embodiment 1 for the background art, and the second metal sintered material 3 bon the lower surface of the insulating layer 1 serves as the base plate 4 for heat dissipation. According to such a configuration, the number of elements can be reduced. A reduction in profile (size) of the semiconductor device can also be expected.The semiconductor device according to Embodiment 2 of the present invention further includes a third metal sintered material 3 cthat is in contact with the upper surface of the insulating layer 1, and the adhesive 6 is provided between the third metal sintered material 3 cand the case 5. According to such a configuration, stress acting from the case 5 on the insulating layer 1 can be reduced, so that a crack and the like of the insulating layer 1 can be suppressed to increase reliability of the semiconductor device.< Embodiment 3> According to the InventionFIG. 5 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 3 of the present invention. The semiconductor device according to Embodiment 3 of the present invention includes a metal plate material 17 instead of wires 11 connecting the semiconductor elements 2 in Embodiment 2 of the present invention. The metal plate material 17 is opposite to the insulating layer 1 with respect to the semiconductor elements 2, and is bonded to the semiconductor elements 2. According to the semiconductor device according to Embodiment 3 of the present invention including the metal plate material 17 for wiring, a duty cycle life can be extended or an internal inductance of the semiconductor device can be reduced as compared with a configuration including the wires 11 for wiring.Joining materials for joining the semiconductor elements 2 and the metal plate material 17 may be a solder or the like, but metal sintering materials are used in Embodiment 3 according to the present invention. That is, the semiconductor device according to Embodiment 3 of the present invention further includes fourth metal sintered materials 3 dthat connect the semiconductor elements 2 and the metal plate material 17 and that include the same material as the first metal sintered material 3 aand the second metal sintered material 3 b.If the joining materials for joining the semiconductor elements 2 and the metal plate material 17 have a material different from the first metal sintering material 3 aand the like, these elements deviate in melting point, and thus it is necessary to use an element having a low melting point as one of these elements which are bonded or sintered later in a manufacturing process. In Embodiment 3 of the present invention, on the other hand, these elements have substantially the same melting point and thus can be sintered simultaneously. It is not necessary to use the low melting point element, thereby enabling high temperature operation of the semiconductor elements 2.Although Embodiment 3 of the present invention has been applied to Embodiment 2 in the above description, Embodiment 3 may be applied to Embodiment 1.< Embodiment 4> According to the InventionFIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 4 of the present invention. In Embodiment 4 of the present invention, the first metal sintered material 3 aamong the semiconductor elements 2 has a relatively large thickness of 0.2 mm or more in the configuration in Embodiment 3 of the present invention. According to such a configuration, exothermic heat can be efficiently dissipated from the semiconductor elements 2, and a maximum temperature in the semiconductor device during driving can be reduced, so that, for example, a product life can be extended.The first metal sintered material 3 amay have a thickness larger than that of the second sintered material 3 band may have a thickness larger than any one of the second metal sintered material 3 b, the third metal sintered material 3 c, and the fourth metal sintered material 3 d. According to such a configuration, exothermic heat from the semiconductor elements 2 can horizontally spread between the semiconductor elements 2 and the insulating layer 1, and thus can be efficiently dissipated. As a result, even in a configuration in which a low thermal conductivity member is used for the insulating layer 1, a reduction in heat dissipation can be suppressed to increase reliability. The inner space typically has a relatively large height, so that the size of the semiconductor device can be maintained even when the thickness of the first metal sintered material 3 ais increased.The first metal sintered material 3 aand the second metal sintered material 3 bneed only to have different thicknesses, and two or more of the first metal sintered material 3 a, the second metal sintered material 3 b, the third metal sintered material 3 c, and the fourth metal sintered material 3 dare only required to have different thicknesses. The first metal sintered material 3 ato the fourth metal sintered material 3 dhave stress reduction and heat dissipation improvement effects, and these effects can be optimized by causing the first metal sintered material 3 ato the fourth metal sintered material 3 dto have thicknesses suitable for the effects.Although Embodiment 4 of the present invention has been applied to Embodiment 3 in the description given above, Embodiment 4 can be applied to any of Embodiments 1 and 2.< Embodiment 5> According to the InventionFIG. 7 is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 5 of the present invention. In Embodiment 5 of the present invention, the first metal sintered material 3 aamong the semiconductor elements 2 has a recess 18 along outer peripheries of the semiconductor elements 2 in the configuration in Embodiment 4 of the present invention. An outer periphery of the first metal sintered material 3 aprotrudes upward. According to such a configuration, the recess 18 can suppress the first metal sintered material 3 afrom smoldering the semiconductor elements 2 during sintering, and thus abnormal operation of the semiconductor device can be suppressed.Although in the above description of Embodiment 5 according to the present invention, it is applied to Embodiment 4, Embodiment 5 according to the present invention can be applied to any of Embodiments 2 and 3 according to the present invention.< 1>In Embodiments 2 to 5 according to the present invention, a main component of the first metal sintered material 3 aand / or the second metal sintered material 3 bmay be copper, and a main component of at least one of the first metal sintered material 3 ato the fourth metal sintered material 3 dmay be copper. Copper has a relatively high thermal conductivity and a relatively low electric resistance, so that densification of the semiconductor device can be expected. Due to the suppression of the use of silver, formation of whiskers can be suppressed.< 2>In embodiments 2 to 5 according to the invention, the material of the semiconductor elements 2 can comprise a semiconductor with a wide band gap. The wide band gap semiconductor includes, for example, silicon carbide (SiC), gallium nitride (GaN), and diamond. The above-described improvement in heat dissipation and reduction in inductance are particularly effective in a configuration in which the material for the semiconductor elements 2 includes silicon carbide suitable for high-temperature operation and includes loss reduction during high-frequency use, enabling improvement in quality and improvement in characteristics of the semiconductor device.< 3>In embodiments 2 to 5 according to the invention, the semiconductor elements 2 may include reverse conducting IGBTs (RC-IGBTs). In a configuration in which the semiconductor elements 2 include the RC-IGBTs, exothermic heat from the semiconductor elements 2 increases, but disadvantages of the exothermic heat from the semiconductor elements 2 can be reduced by high heat dissipation and high reliability at a high temperature as described above. By using the RC-IGBTs, on the other hand, advantages can be achieved by a densification of the semiconductor device.

Claims

A semiconductor device comprising: an insulating layer (1) having a first surface and a second surface opposite to the first surface; at least one semiconductor element (2) located on the side of the first surface; a first metal sintered material (3a) in contact with the first surface of the insulating layer (1) and the semiconductor element (2) and connecting the insulating layer (1) and the semiconductor element (2); a second metal sintered material (3b) in contact with the second surface of the insulating layer (1); a case (5) covering the semiconductor element (2); and a third metal sintered material (3c) which is in contact with the first surface of the insulating layer (1), wherein an adhesive (6) is provided between the third metal sintered material (3c) and the case (5).The semiconductor device according to claim 1, further comprising a base plate (4) which is in contact with the second metal sintered material (3b) and which is connected to the insulating layer (1) through the second metal sintered material (3b).The semiconductor device according to any one of the preceding claims, wherein: - the at least one semiconductor element (2) comprises a plurality of semiconductor elements (2), and - the semiconductor device further comprises a metal plate material (17) which is opposite to the insulating layer (1) with respect to the plurality of semiconductor elements (2) and which is connected to the plurality of semiconductor elements (2).The semiconductor device according to claim 3, further comprising a fourth metal sintered material (3d) that connects the plurality of semiconductor elements (2) and the metal plate material (17), and that comprises the same material as the first metal sintered material (3a) and the second metal sintered material (3b).The semiconductor device according to any one of the preceding claims, wherein the first metal sintered material (3a) has a thickness of 0.2 mm or more.The semiconductor device according to any one of the preceding claims, wherein the first metal sintered material (3a) has a thickness larger than that of the second metal sintered material (3b).The semiconductor device according to any one of the preceding claims, wherein the first metal sintered material (3a) and the second metal sintered material (3b) have different thicknesses.The semiconductor device according to any one of the preceding claims, wherein a main component of the first metal sintered material (3a) and / or the second metal sintered material (3b) is copper.A semiconductor device according to any preceding claim, wherein a material for the semiconductor element (2) comprises a wide bandgap semiconductor.The semiconductor device according to any one of the preceding claims, wherein the semiconductor element (2) comprises an RC-IGBT.

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