METHOD FOR MANUFACTURING A SUPERJUNCTION COMPONENT AND SUPERJUNCTION TRANSITOR COMPONENT

Abstract

A process that exhibits: Forming trenches (103) in a first semiconductor layer (110) of a semiconductor body (100) such that mesa regions (111) are formed between the trenches (103), wherein the first semiconductor layer (110) contains a basic doping of dopant atoms of a first doping type and dopant atoms of a second doping type complementary to the first doping type, and wherein the dopant atoms of the second doping type have a diffusion coefficient different from the diffusion coefficient of the dopant atoms of the first doping type; Filling the trenches (103) with a monocrystalline semiconductor material (121); and Performing a first thermal process such that first regions (11) with an effective doping of the first doping type are formed based on the dopant atoms of the first doping type contained in the basic doping, and second regions (12) with an effective doping of the second doping type are formed based on the dopant atoms of the second doping type contained in the basic doping, the procedure further exhibits: Implanting further dopant atoms of the first doping type into the first semiconductor layer (110) to form at least one first implanted region (131); and Activating the implanted additional dopant atoms of the first doping type to form at least one third region (13), wherein at least one first implanted area (131) is formed such that it has an area-specific vertical dopant dose which is between 5% and 40% of a breakdown charge of the semiconductor material of the first semiconductor layer (110).

Description

[0001] This disclosure relates generally to a method for manufacturing a superjunction device, in particular a superjunction transistor device.

[0002] A superjunction device contains a superjunction region with multiple first regions of a first doping type and multiple second regions of a second doping type complementary to the first, with the first and second regions arranged alternately. In some publications, the first regions are referred to as drift regions and the second doping regions as compensation regions.

[0003] US Patent 2017 / 0263720A1 describes a method for fabricating a superjunction transistor device. The fabrication of a drift region with multiple first regions of a first doping type and multiple second regions of a second doping type complementary to the first doping type includes fabricating a semiconductor layer containing dopant atoms of a first doping type and a second doping type complementary to the first doping type, fabricating trenches in the semiconductor layer, filling the trenches with a semiconductor material, and performing a temperature process by which dopant atoms diffuse into the semiconductor material used to fill the trenches. The method also includes fabricating source and body regions in the area of ​​a surface of the semiconductor layer.

[0004] US Patent 2013 / 0026560 A1 describes a superjunction transistor device with a drift region comprising several first regions of a first doping type and several second regions of a second doping type complementary to the first. The transistor device also includes several source regions of the first doping type, each embedded within body regions of the second doping type. The first regions of the drift region exhibit a higher doping concentration in areas adjacent to body regions than in areas spaced away from the body regions, which are of the second doping type.

[0005] US 2001 / 0052601A1 and US 2009 / 0057713A1 each describe a superjunction transistor device with a drift region comprising several first regions of a first doping type and several second regions of a second doping type complementary to the first. The transistor device also includes several source regions of the first doping type, each embedded within body regions of the second doping type. The second regions of the drift region exhibit a higher doping concentration in areas adjacent to body regions than in areas spaced away from the body regions, which are of the second doping type.

[0006] There is a need to manufacture a superjunction component with high avalanche resistance in a cost-effective manner.

[0007] One embodiment of the invention relates to a method according to claim 1. Another embodiment of the invention relates to a superjunction transistor device according to claim 26.

[0008] Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are shown. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. The Fig. Figures 1A-1C show an example of a method for forming a superjunction region, wherein the method involves forming trenches in a first semiconductor layer, implanting dopant atoms, filling the trenches with a monocrystalline semiconductor material, and a temperature process to form first, second, and third doped regions; Fig. Figure 2 shows a top view of the first semiconductor layer after the formation of the trenches; The Fig. Figures 3A - 3B show doping profiles of first-type and second-type dopant atoms in mesa regions of the first semiconductor layer and the monocrystalline semiconductor material filling the trenches, before and after the temperature process; The Fig. Figures 4A - 4B show a top view and a vertical cross-sectional view of third areas according to an example; The Fig. Figures 5A - 5B show a top view and a vertical cross-sectional view of third areas according to another example; The Fig. Figures 6A - 6C show a top view and a vertical cross-sectional view of third areas according to another example; Fig. Figure 7 shows an example of a method for implanting dopant atoms into upper sections of the trenches before filling the trenches; The Fig. Figures 8A-8B show examples of implanted regions containing implanted dopant atoms, and third regions resulting from the implanted regions in the temperature process; The Fig. Figures 9A-9B show an example of a method for creating implanted areas from the one in Fig. 8A type shown; The Fig. Figures 10A-10F show an example of a method for forming a [something] in the Fig. 8A - 8B shown implantation mask; Fig. Figure 11 shows another example of a procedure for forming an implanted area; Fig. Figure 12 shows an example of a superjunction transistor device containing a superjunction region and several transistor cells; Fig. Figure 13 shows a profile of the electric field in a superjunction transistor device from the one in Fig. 12 type shown, when the transistor element is in a blocking state; The Fig. Figures 14A - 14B show the profile of the electric field in a superjunction transistor device with a superjunction region that is perfectly balanced with respect to the amount of dopant atoms of the first type and dopant atoms of the second type; Fig. 15 shows an additional process step in the procedure according to the Fig. 1A - 1C; Fig. Figure 16 shows an example of a superjunction transistor device that is constructed according to the method described in the Fig. 1A - 1C and the additional process step after Fig. 15 formed superjunction areas; Fig. Figure 17 shows a profile of the electric field in a superjunction transistor device from the one in Fig. 11 type shown, when the transistor device is in a blocking state; and Fig. Figure 18 shows another example of a transistor cell.

[0009] The following detailed description refers to the accompanying drawings. The drawings form part of the description and show examples of how the invention can be used and implemented. It is understood that the features of the various embodiments described herein can be combined unless expressly stated otherwise.

[0010] The Fig. Figures 1A-1C show an example of a method for forming a superjunction region of a superjunction device. The superjunction device is, for example, a superjunction transistor. The superjunction region contains several first regions 11 and several second regions 12, wherein the first and second regions 11, 12 are arranged alternately in a first lateral direction x of a semiconductor body 100. The first regions 11 have an effective doping concentration of a first dopant type, and the second regions 12 have an effective doping concentration of a second dopant type complementary to the first dopant type. In the finished superjunction device, the first regions 11 can form drift regions, and the second regions 12 can form compensation regions.

[0011] Referring to Fig. Method 1A involves forming trenches 103 in a first semiconductor layer 110 of the semiconductor body 100, such that mesa regions 111 are formed between the trenches 103. According to an example, the trenches 103 extend from a first surface 101 in a vertical direction z into the first semiconductor layer 110. The “vertical direction” z of the semiconductor body 100 is a direction that is essentially perpendicular to a first surface 101.

[0012] The first semiconductor layer 110 is a co-doped semiconductor layer. That is, the first semiconductor layer 110 contains a base doping consisting of dopant atoms of a first doping type (n or p) and dopant atoms of a second doping type (p or n) complementary to the first doping type. The dopant atoms of the first doping type are hereinafter also referred to as first-type dopants, and the dopant atoms of the second doping type are hereinafter also referred to as second-type dopants. By way of example, the first and second dopant atoms in the first semiconductor layer 110 are essentially homogeneously distributed. A doping concentration of the first-type dopants is hereinafter also referred to as the first doping concentration, and a doping concentration of the second-type dopants is hereinafter also referred to as the second doping concentration.

[0013] The first semiconductor layer 110 is, for example, a monocrystalline silicon layer. According to one example, the first semiconductor layer 110 is an epitaxial layer that is doped in situ with first- and second-type dopants during an epitaxial growth process in which the epitaxial layer is grown.

[0014] According to one example, the first doping concentration is essentially the same as the second doping concentration. According to another example, "essentially the same" means that each of the first and second doping concentrations is less than 5%, less than 1%, less than 10%, respectively. -1 % (1E-1 %) or even less than 10 -2 % (1E-2%) deviates from an average of the first and second doping concentrations. For example, the first and second doping concentrations in the first semiconductor layer 110 each differ between 5E15 cm³. -3 (5·10 15 cm -3 ) and 1E17 cm -3(1·10 17 cm -3 ) selected.

[0015] As in Fig. As shown in Figure 1B, the process further involves filling the trenches 103 with a monocrystalline semiconductor material 121. The semiconductor material 121 filling the trenches 103 is of the same type as the semiconductor material of the first semiconductor layer 110. In one example, both the first semiconductor layer 110 and the semiconductor material 121 filling the trenches 103 contain monocrystalline silicon. The semiconductor material 121 filling the trenches 103 is also referred to as the filler material 121.

[0016] The filling of the trenches 103 can involve an epitaxial growth process in which the filling material 121 is epitaxially grown on the sidewalls 104, 105 and bottoms 106 of the trenches 103 to completely fill the trenches 103 with a monocrystalline semiconductor material. Methods for filling trenches in a semiconductor layer with a monocrystalline semiconductor material are known, so no further explanation is required in this respect.

[0017] According to one example, the monocrystalline filling material 121 formed in the trenches 103 is intrinsic. According to another example, the term "intrinsic" implies that the semiconductor material 121 is not intentionally doped, such that the doping concentration of dopant atoms of either type n or type p in the filling material 121 is less than 1E14 cm⁻¹. -3 (1·10 14 cm -3 ) or even less than 1 x 13 cm -3 (1·10 13 cm -3 ) amounts.

[0018] Referring to Fig. Procedure 1C further includes carrying out a thermal process such that first regions 11 are formed with effective doping of the first doping type based on dopant atoms of the first type, and second regions 12 are formed with effective doping of the second doping type based on dopant atoms of the second type. This thermal process is hereinafter also referred to as the first thermal process. The dopant atoms of the first and second types are selected such that they have different diffusion coefficients, so that during the thermal process one type of dopant atoms diffuses faster than the other type of dopant atoms.According to one example, the dopant atoms of the second type have a higher diffusion coefficient than the dopant atoms of the first type, so that the dopant atoms of the second type diffuse faster than the dopant atoms of the first type. In this example, the first regions 11 are formed mainly in the mesa regions 111 and the second regions 12 are formed mainly in the trench fill material 121.

[0019] According to one example, the first-type dopants are arsenic (As) or antimony (Sb) atoms, and the second-type dopants are boron (B) atoms. Arsenic and antimony (Sb) atoms are type n dopants in silicon, and boron atoms are type p dopants in silicon. Boron atoms diffuse faster than arsenic or antimony atoms, so in this example, the (As-doped) first regions 11 are formed mainly in the mesa regions 111, and the (B-doped) second regions 12 are formed mainly in the trench fill material 121.

[0020] Referring to Fig. As shown in Figure 1C, the process further includes the formation of at least one third region 13 of the first doping type in the first semiconductor layer 110. This at least one third region 13 is formed based on implanted regions 131 containing dopant atoms of the first doping type in addition to the dopant atoms of the first doping type contained in the base doping. The dopant atoms of the first type contained in the implanted regions 131, in addition to the dopant atoms of the first type contained in the base doping, are hereinafter referred to as further dopant atoms of the first type. The implanted regions 131 are formed by implanting the further dopant atoms of the first type into the first semiconductor layer 110.At least one third region 13 is formed based on the implanted regions 131 in a thermal process (healing process), whereby the thermal process activates the implanted further dopant atoms of the first type and these dopant atoms can diffuse.

[0021] The implanted areas 131 can be formed in various ways. Some examples of the formation of the implanted areas 131 are briefly summarized below. (a) According to a Fig. In the example shown in Figure 1B, the implanted regions 131 are formed in the mesa regions 111 after the formation of the trenches 103 and before the filling of the trenches 103. In this example, the formation of the implanted regions 131 involves the implantation of the additional dopant atoms of the first type into the mesa regions 111 via the sidewalls of the trenches 103. (b) According to another example (in the Fig. (1A - 1C not shown) the implanted regions 131 are formed in the first semiconductor layer 110 after the trenches 103 have been filled. In this example, the formation of the implanted regions 131 involves implanting the additional type 1 dopant atoms through the first surface 101 into the first semiconductor layer 110 with the filled trenches 103. The formation of the implanted regions 131 can involve implanting the type 1 dopant atoms using an implantation mask, wherein the implantation mask defines a size and a corresponding position of the implanted regions 131. (c) According to another example (in the Fig. (Figures 1A-1C not shown) the implanted regions 131 are formed in the first semiconductor layer 110 before the trenches 103 are formed. In this example, forming the implanted regions 131 involves implanting the type-one dopant atoms through the first surface 101 into the first semiconductor layer 110. Forming the implanted regions 131 may involve implanting further type-one dopant atoms using an implantation mask, the implantation mask defining a size and corresponding position for the implanted regions 131. Forming the implanted regions 131 may involve forming implanted regions larger than the desired implanted regions 131 and removing portions of these larger implanted regions to form the implanted regions 131 when forming the trenches 103.

[0022] In examples (a) and (c) above, the first thermal process can be used both to diffuse the dopant atoms of the first and second type of base doping and to form the at least one third region 13 based on the implanted regions 131. In example (b), the implanted regions 131 can be formed (i) before the first thermal process or (ii) after the first thermal process. In example (i), the first thermal process can be used to diffuse the dopant atoms of the first and second type of base doping and to form the at least one third region 13 based on the implanted regions 131. In example (ii), a second thermal process can be performed to form the at least one third region 13 based on the implanted regions 131.

[0023] In the Fig. 1B and Fig. In the examples shown in Figure 1C, the implanted regions 131 are formed for illustrative purposes only by implanting further dopant atoms of the first type into sidewalls of the trenches 103, and the at least one third region 13 is formed based on the implanted regions 131 by the same thermal process which diffuses the dopant atoms of the first and second type contained in the basic doping.

[0024] In any case, the at least one third region 13 is a semiconductor region that, after the thermal process, contains type 1 dopants from the implanted regions 131, that is, type 1 dopants that were implanted (before or after filling the trenches 103) into the first semiconductor layer 110 and that are added to the type 1 dopants of the base doping. The at least one third region 13 can have an effective doping concentration of type 1 or an effective doping concentration of type 2. More detailed examples of the at least one third region 13 are explained below.

[0025] As detailed below, the at least one third region 13 influences (more precisely: reduces) the voltage-blocking capability of the finished semiconductor device, which will be explained in detail below. The influence of the at least one third region 131 on the voltage-blocking capability depends, among other things, on the area-specific vertical dose of first-type dopants of the at least one third region 13. Referring to the above, the at least one third region 13 results from the implanted regions 131. The "area-specific vertical dose of first-type dopants" of the at least one third region 13 is given by the total amount of additional first-type dopants in the implanted regions 131 divided by the total area of ​​the mesa regions 111 and the filled trenches 103 in the first surface phase 101.The “total amount of additional dopant atoms of the first type in the implanted regions 131” is equal to the integral of the additional dopant atoms of the first type contained in the implanted regions 131 in the vertical direction.

[0026] According to one example, the implanted regions 131 are designed such that the area-specific vertical dose of first-type dopants is chosen to be between 5% and 40% of the so-called breakdown charge (critical area charge) of the semiconductor material of the semiconductor body. For example, the breakdown charge in silicon is approximately 2E12 dopants per cm². 2 (2E12 cm -2 ).

[0027] In one example, the first semiconductor layer 110 is an epitaxial layer grown onto a second semiconductor layer 140, such as a semiconductor substrate. In another example, the second semiconductor layer 140 and the first semiconductor layer 110 contain the same semiconductor material, such as silicon. The second semiconductor layer 140, for example, has a doping concentration of the first doping type.

[0028] The thickness d110 of the first semiconductor layer 110 depends on the desired voltage blocking capability of the finished superjunction device. For example, the thickness d110, which is a dimension of the first semiconductor layer 110 in a vertical direction z of the semiconductor body 100, is chosen between 10 micrometers (µm) and 150 micrometers, particularly between 30 micrometers and 80 micrometers.

[0029] The formation of the in Fig. The trenches 103 shown in Figure 1A can involve a conventional etching process for forming trenches in a semiconductor layer. Etching the trenches 103 can involve forming an etch mask on the first surface 101 (where the etch mask is in Fig. (1A not shown) and involve etching the trenches to a desired depth. Depending on the etching method, the trenches 103 have either vertical sidewalls 104, 105, which are sidewalls 104, 105 perpendicular to the first surface 101, or tapered sidewalls 104, 105, which are sidewalls inclined relative to a normal of the first surface 101. The aspect ratio of the trenches, which is a ratio between a trench depth d103 and a trench width w103, is greater than 5:1, greater than 8:1, or greater than 12:1. For trenches 103 with tapered side walls, the "trench width w103" refers either to an average trench width or a maximum trench width of the respective trench 103. According to an example, the trenches 103 are designed such that they have a trench width selected between 1 micrometer and 5 micrometers.For example, the width w111 of the mesa areas 111 is equal to the trench width, where the "mesa width" w111 denotes either the average mesa width or the maximum mesa width when the trenches 103 taper. A pitch p is given by the center-to-center distance of two adjacent trenches, the center-to-center distance of two adjacent mesa areas 111, or the trench width w103 plus the mesa width w111, p = w103 + w111. For example, the pitch p is chosen to be between 2 micrometers and 10 micrometers.

[0030] According to a Fig. In the example shown in Figure 1A, the trenches 103 are formed such that they extend through the first semiconductor layer 110 into the second semiconductor layer 140, so that a section of the trenches is located in the second semiconductor layer 140. According to one example, the vertical dimension of the trench section located in the second semiconductor layer 140 is between 1% and 5% of the trench depth d103. For example, in a semiconductor device with a trench depth of 40 micrometers (µm), the vertical dimension of the trench section located in the second semiconductor layer 140 is between 0.4 µm and 2 µm.

[0031] Referring to Fig. In Figure 1A, the trenches 103 and the mesa regions 111 are arranged alternately in a first lateral direction x of the semiconductor body 100. According to an example, the trenches 103 are elongated trenches in a second lateral direction y perpendicular to the first lateral direction x. This is shown in Figure 1A. Fig. Figure 2, which shows a top view of a section of the semiconductor body 100 after the formation of the trenches 103, is shown.

[0032] Referring to the above, the dopants of the first and second types diffuse into the mesa areas 111 and the trench fill material 121 during the thermal process. This will be described below with reference to the Fig. 3A and Fig. 3B explained. It should be noted that the Fig. 3A and Fig. 3B shows the doping situation in areas that are spaced vertically z away from the implanted areas 131 or the third areas 13.

[0033] Fig. Figure 3A schematically shows the doping situation in the mesa areas 111 and the trench fill material 121 before the thermal process. Referring to Fig. 3A are the mesa regions 111 co-doped regions, the dopant atoms of the first type with the first doping concentration N D1and dopant atoms of the second type with the second doping concentration N D2 included. In the Fig. In example 3A, the first doping concentration N is shown. D1 essentially the same as the second doping concentration N D2 According to an example, the trench fill material 121 is an intrinsic material, so that a doping concentration of the trench fill material 121 compared to the first and second doping concentrations N D1 , N D2 negligible.

[0034] Fig. 3B shows the doping concentration N D1 ' of the dopant atoms of the first type and the doping concentration N D2' of the second-type dopant atoms after the thermal process. The temperature and duration of the thermal process are adapted to the diffusion coefficients of the first- and second-type dopant atoms, such that the first regions 11 are formed with an effective doping concentration of the first dopant type and the second regions 12 with an effective doping concentration of the second dopant type. Furthermore, the temperature and duration can be chosen depending on the type of atmosphere in which the thermal process takes place. For example, the atmosphere is a moist oxidizing atmosphere, the duration of the thermal process is several hours, such as between 2 and 10 hours, and the temperature is higher than 900 °C, such as between 900 °C and 1150 °C.

[0035] At the in Fig. In the example shown in Figure 3B, the dopants of the second type are chosen to diffuse faster than the dopants of the first type. In this example, the temperature and duration of the thermal process are chosen such that the dopant atoms of the first type remain mainly in the mesa regions 111, so that the maximum of the doping concentration N D1 'The number of dopant atoms of the first type after the diffusion process is essentially equal to the doping concentration N' D1 of the first type or slightly lower than the doping concentration N D1 of the first type, such as between 90% and 99% of the doping concentration of the first type. However, the dopant of the second type diffuses considerably during the thermal process, resulting in a doping concentration N D2 'The number of dopant atoms of the second type in mesa region 111 becomes considerably lower than the doping concentration N D1' of the dopant atoms of the first type. In the trench fill material 121, the doping concentration N D2 'The concentration of dopant atoms of the second type is significantly higher than the doping concentration N' D1 ' of the dopant atoms of the first type. After the diffusion process, the first regions 11 are regions where the dopant atoms of the first type predominate, resulting in an effective doping concentration of the first doping type. The second regions 12 are regions where the dopant atoms of the second type predominate, resulting in an effective doping concentration of the second doping type.

[0036] Referring to Fig. 3B can determine the doping concentration N D2 ' of the dopant atoms of the second type may be variable, so that maxima of the doping concentration N D2 ' are located in the mesa area 111 and minima of the doping concentration N are present D2' are located in the trench fill material 121. In principle, the longer the thermal process lasts at a given temperature, the smaller the difference between the maxima and minima. Conversely, the longer the duration of the thermal process, the greater the diffusion of the dopants of the first type and the lower the maxima of the doping concentration N. D1 ' of the first type of dopants after the diffusion process. Taking these effects into account, the duration of the thermal process at a given temperature can be appropriately selected to achieve a desired doping profile.

[0037] Referring to the above, the implanted areas 131 can be formed in various ways. According to a Fig. In the example shown in Figure 4, the formation of the implanted regions 131 involves the implantation of dopant atoms into sidewalls 104, 105 of the trenches 103 before filling the trenches 103 with the trench filler material 121. The formation of the implanted regions 131 can include the formation of an implantation mask 200 on the mesa regions 111, wherein the implantation mask 200 prevents dopant atoms from being implanted into the mesa regions 111 via the first surface 101.

[0038] Referring to the above, the at least one third area 13 can be implemented in various ways. Several examples of the at least one third area 13 are explained below.

[0039] The Fig. 4A and Fig. Figure 4B shows a possible implementation of a third area 13, where Fig. Figure 4A shows a top view of a section of the semiconductor body 100 and Fig. Figure 4B shows a vertical cross-sectional view of the semiconductor body 100 after forming the third region 13.

[0040] In the Fig. 4A and Fig. In the example shown in Figure 4B, the semiconductor body 100 contains a third region 13 formed in the mesa regions 111 and the trench fill material 121. The third region 13 borders the first and second regions 11, 12 and is located in the vertical direction z between the first surface 101 and the first and second regions 11, 12. Fig. 4A, the first and second areas 11, 12 are located outside the field of view. However, the position of these areas 11, 12 below the third area 13 is indicated by dashed lines.

[0041] The Fig. 5A and Fig. Figure 5B shows an example in which several third regions 13 were formed in the semiconductor body 100. In this example, the third regions 13 are spaced apart from each other in the first lateral direction x. In the second lateral direction y, the third regions 13 are elongated regions and extend along the trench fill material 121 and the mesa regions 111.

[0042] The Fig. Figures 6A-6C show another example where several third regions 13 have been formed in the semiconductor body 100. In this example, the third regions 13 are spaced apart in the second lateral direction y. According to one example (as shown), the third regions 13 are contiguous regions in the first lateral direction x. According to another example (not shown), the semiconductor body 100 contains several third regions 13 that are spaced apart in the first lateral direction x.

[0043] In each case, with reference to the Fig. In the examples 4A-4B, 5A-5B, and 6A-6C, the at least one third region contains 13 additional dopants of the first type, which have been implanted into the first semiconductor layer 110. In addition to these implanted additional dopants of the first type, the at least one third region can contain 13 dopants of the first type and dopants of the second type resulting from the initial doping of the first semiconductor layer 110.

[0044] Each of the ones referring to the Fig. The third regions 13 described in sections 4A-4B, 5A-5B, and 6A-6C can contain a first section 131 and a second section 132. The first section 131 is a section in which the dopant atoms of the first and second types of the base doping predominate. The second section 132 is a section in which the dopant atoms of the second type predominate. The first section 131 of the third regions 13 therefore overlaps the first regions 11 of the superjunction region, and the second sections 132 of the third regions 13 overlap the second regions 12 of the superjunction region. The first section 131 is located mainly in a respective mesa area 111 and the second section 132 is located mainly in a respective trench fill material 121. The first section 131 has an effective doping concentration of the first doping type.The second section 132 has either an effective doping concentration of the first doping type or an effective doping concentration of the second doping type. Whether the effective doping concentration of the second section 132 is of the first or second doping type depends on the amount of dopant atoms of the first and second type contained in the base doping and the amount of additional dopant atoms of the first type implanted in the first semiconductor layer 110.

[0045] In the example according to the Fig. In 4A - 4B, the third region 13 is formed such that the effective doping concentration of the respective second sections 132 is of the second doping type. In the examples according to the Fig. 5A - 5B and 6A - 6B the third regions 13 can be formed such that the effective doping concentration of the respective second sections 132 is either of the first doping type or of the second doping type.

[0046] Referring to the above, at least one third region contains 13 additional dopant atoms of the first type. These dopant atoms of the first type are implanted into the semiconductor body 100 to form implanted regions 131 and diffuse and are activated during the thermal process.

[0047] According to one example, the implantation of the first-type dopant atoms involves implanting the first-type dopant atoms into sidewalls of the mesa areas 111 prior to filling the trenches with the trench fill material 121. Fig. Figure 7 shows a vertical cross-sectional view of the semiconductor body 100 after this type of implantation process. Fig. The seven arrows shown indicate directions (implantation angles) in which the additional dopant atoms of the first doping type are implanted into the trench sidewalls 104, 105 to form the implanted regions 131. For example, the implanted regions 131 are formed in the upper sections of the sidewalls 104, 105, which are sections adjacent to the first surface 101. A vertical dimension (depth) d131 of the implanted regions 131 is set by appropriately selecting the implantation angles depending on the trench width w103 and the thickness (vertical dimension) of the implantation mask 200. For example, the implanted regions 131 are formed such that their respective vertical dimension is less than 50%, less than 20%, or less than 10% of the thickness d110 of the first semiconductor layer 110. For example, the depth d131 lies between 1.5 and 2.5 micrometers (µm).

[0048] For example, the implantation angle is greater than 15°, 20° or even 25°.

[0049] Each of the in the Fig. The third areas 13 shown in 4A - 4B, 5A - 5B, 6A - 6C can be based on the one in Fig. The process described in section 7 is formed. That is, each of these third areas 13 can be formed by forming implanted areas 131 according to the procedure described in section 7. Fig. 7 and carrying out a thermal process.

[0050] Based on the in Fig. The process depicted in section 7 can be a coherent third area 13 of the one in the Fig. The type shown in Figures 4A-4B is formed, for example, by implanting type 1 dopants, which diffuse faster in the thermal process than the type 1 dopants of the base doping, into the side walls 104, 105 of the trenches 103 such that a continuous third region 13 is formed based on several implanted regions 131 created in the implantation process. According to one example, the faster-diffused type 1 dopants are phosphorus (P) atoms. Phosphorus atoms are type n dopants in silicon. According to another example, if the type 1 dopants are antimony (Sb) atoms, the other type 1 dopants are arsenic (As) atoms, which diffuse faster than Sb atoms.

[0051] Based on the in Fig. The process depicted in 7 can be further divided into third areas 13 of the one in the Fig. The type shown in 5A - 5B is obtained by implanting dopant atoms of the first type, which diffuse more slowly than dopant atoms of the first type, to form a third region 13 of the one shown in the Fig. The type shown in 4A - 4B is used to form third regions. According to an example for forming third regions 13 of the one in the Fig. The types shown in Figures 5A-5B are the type first dopants implanted into the sidewalls of the mesa regions 111. These dopants are of the same element as the type first dopants contained in the base doping of the first semiconductor layer 110. For example, the type first dopants implanted into the semiconductor body 100 during the implantation process are arsenic (As) atoms.

[0052] The Fig. Figures 8A-8B show an example of a procedure for forming third regions 13 of the one described in the Fig. 6A - 6C of the type shown. Fig. Figure 8A is a top view of the semiconductor body 100 after the formation of several implanted areas 131. Fig. Figure 8B is a top view of the semiconductor body 100 after the thermal process, wherein the thermal process forms the first and second regions 11, 12 based on the basic doping of the first semiconductor layer 110 and the third regions 13 based on the first-type dopant atoms contained in the implanted regions 131.

[0053] Referring to Fig. 8A involves forming the implanted regions 131, specifically the formation of multiple implanted regions 131 in each side wall of each mesa region 111 such that the implanted regions 131 are spaced apart from one another in the second lateral direction y. A distance d131 between adjacent implanted regions 131 is adapted to the diffusion coefficient of the dopant atoms of the first type and the parameters of the thermal process, such as temperature and duration of the thermal process, such that after the thermal process, the third regions 13 resulting from the implanted regions 131 are spaced apart from one another in the second lateral direction y. In the first lateral direction x, adjacent third regions 13 can be adjacent to one another, so that a continuous third region 13 extending laterally in the first lateral direction x is formed.

[0054] For example, the distance d131 between adjacent implanted areas 131 is between 0.2 and 2 times the pitch p (0.2p < d131 < 2p) or between 0.4 and 1.0 times the pitch p (0.4p < d131 < p). The width w131 of the implanted areas 131 is selected between 0.2 and 0.8 times the pitch p (0.2p < w131 < 0.8p).

[0055] In Fig. Figure 8B shows the position of the implanted areas 131 before the thermal process, indicated by dashed lines. The position of the first and second areas 11, 12 below the third area 13 is also shown. Fig. 8B is also shown using dashed lines.

[0056] The in Fig. The implanted regions 131 shown in Figure 8A can be formed by implanting type 1 dopant atoms into the sidewalls of the mesa regions 111. Fig. Figures 9A-9B show an example of a procedure for forming implanted areas 131 of the in Fig. 8A of the type shown.

[0057] Each of the Fig. Figures 9A-9B show a vertical cross-section of a section of the semiconductor body 100 during the implantation process, in which the implanted areas 131 are arranged according to Fig. 8A will be formed. Fig. Figure 9A shows a vertical cross-sectional view in a first section plane EE, and Fig. Figure 9B shows a vertical cross-sectional view in a second section plane FF. The first section EE intersects an area in which first implanted areas 131 are formed, and the second section plane FF intersects an area that is free of implanted areas 131.

[0058] Referring to Fig. 9A includes the formation of the implanted regions 131 and the implantation of type-one dopants into the sidewalls 104, 105 of the mesa regions 111. To prevent type-one dopants from being implanted into certain regions of the semiconductor body 100, the implantation mask 200 covers those sections of the trenches 103 and the adjacent sections of the mesa regions 111 that are to be protected from the implantation of type-one dopants (see Fig. 9B). Everything relating to the in Fig. The implantation process described in section 7 applies to the procedure described in the Fig. The implantation process shown in 9A - 9B corresponds to this.

[0059] According to one example, forming third areas involves 13 of those in the Fig. Figures 8A-8B depict the type of dopant atoms implanted, which diffuse faster in the thermal process than the type 1 dopant atoms of the base dopant. For example, the type 1 dopant atoms are phosphorus (P) atoms. Phosphorus atoms are type n dopant atoms in silicon.

[0060] The Fig. Figures 10A-10F show an example of a method for forming an implantation mask 200 of the in the Fig. 9A - 9B of the type shown. The Fig. 10A, Fig. 10B, Fig. 10E and Fig. Figure 10F shows vertical cross-sectional views and the Fig. 10C and Fig. Figure 10D shows top views of a section of the semiconductor body 100 in the various stages of the manufacturing process of the implantation mask 200.

[0061] Referring to Fig. Procedure 10A includes filling the trenches 103 with a sacrificial material 201. Filling the trenches 103 with the sacrificial material 201 may involve (a) depositing the sacrificial material such that the sacrificial material fills the trenches 103 and covers the first surface 101 on the mesa regions 111, and (b) performing a planarization process in which the sacrificial material is removed from the first surface 101. The planarization process may involve any type of polishing or etching process, or a combination thereof. The sacrificial material 201 is a material that can be selectively removed relative to the semiconductor material of the semiconductor body 100 and the material of the etch mask 200. By way of example, the sacrificial material 201 is carbon.

[0062] Referring to Fig. Procedure 10B further includes the formation of an etch mask layer 202 that completely covers the mesa areas 111 and the sacrificial material 201 in the trenches 103. The formation of the etch mask layer 202 may involve the deposition of the etch mask layer 202. According to one example, the etch mask layer 202 contains an oxide, a nitride, or combinations thereof.

[0063] Fig. Figure 10C shows a top view of the etching mask layer 202. The dashed lines in Fig. Figure 10C illustrates the position of the trenches filled with sacrificial material 201 and the mesa areas 111 below the etching mask layer 202.

[0064] Referring to Fig. In 10D, the process further includes structuring the etch mask layer 202 to form the etch mask 200. Structuring the etch mask layer 202 involves creating openings 203 in the etch mask layer 202 over sections of the sacrificial material 201 that fills the trenches 103. The positions of these openings 203 and their dimension in the second lateral direction y define the positions of the implanted areas 131 and their dimension in the second lateral direction y, respectively. Creating the openings 203 can involve forming a mask in a lithographic process and etching those sections of the etch mask layer 202 that are not covered by the mask.

[0065] Fig. Figure 10E shows a vertical cross-sectional view of the semiconductor body 100 and the etch mask 200 in a first section plane GG, in which the etch mask 200 covers the sacrificial material 201. Fig. Figure 10F shows a vertical cross-sectional view of the semiconductor body 100 and the etch mask 200 in a second section plane HH, in which the etch mask 200 does not cover the sacrificial material 201.

[0066] The process of forming the etching mask 200 further involves removing the sacrificial material 201 from the trenches 103 to create an arrangement as in the Fig. Figures 9A-9B illustrate how to achieve this. Removing the sacrificial material 201 from the trenches 103 can involve an etching process that selectively etches the sacrificial material 201 relative to the semiconductor body material 100 and relative to the etch mask material 200. According to another example, the sacrificial material 201 contains carbon, and removing the sacrificial material 201 involves ashing the sacrificial material 201 in a high-temperature process.

[0067] Referring to the above, the formation of implanted areas 131 according to the Fig. 4A - 4B, 5A - 5B, or 6A - 6C involve the implantation of further dopant atoms of the first type into the trench sidewalls 104, 105, that is, the sidewalls of the mesa regions 111. However, this is only one example. In addition to, or alternatively, the implantation of further dopant atoms of the first type into the sidewalls of the mesa regions 111, the formation of the implanted regions 131 can involve the implantation of further dopant atoms of the first type into the semiconductor body 100 via the first surface 101. An example of a method for implanting further dopant atoms of the first type into the semiconductor body 100 via the first surface 101 is shown in Fig. 11 shown.

[0068] Fig. Figure 11 shows a vertical cross-sectional view of the semiconductor body 100 after the implantation of further type 1 dopant atoms via the first surface 101 into the semiconductor body 100 to form the implanted regions 131. The implantation of the type 1 dopant atoms can involve forming an implantation mask 210 on the first surface 101 and implanting the type 1 dopant atoms into those surface regions not covered by the implantation mask 210.

[0069] As in Fig. As shown in Figure 11, the implantation of the first-type dopant atoms can involve implanting the first-type dopant atoms after filling the trenches with the trench fill material 121. However, this is only one example. It is equally possible to implant the first-type dopant atoms into the mesa areas 111 via the first surface 101 before filling the trenches.

[0070] Based on the in Fig. The procedures described in the 11 images can be used to implant 111 areas 131 of the mesa region in the Fig. 7 and Fig. 8A are formed. That is, instead of implanting the further dopant atoms of the first type into the trench sidewalls 104, 105, the further dopant atoms of the first type can be implanted via the first surface 101 into the mesa regions 111. Everything else relating to the formation of the in the Fig. 7 and Fig. The implanted areas 131 shown in Figure 8A, such as the type of dopant atoms, also apply to the procedure in which the implanted areas 131 are formed by implanting the further dopant atoms of the first type via the first surface 101.

[0071] The formation of the third areas 13, as in the Fig. 4A-4B, 5A-5B, or 6A-6C, but is not limited to forming implanted areas 131 only in the mesa areas 111. It is also possible to form the implanted areas 131 by implanting type 1 dopant atoms via the first surface 101 such that they are located only in the filler material 121, or such that they are located in both the mesa areas and the filler material. The size and position of the implanted areas 131 formed by implanting type 1 dopant atoms via the first surface 101 can be controlled by an implantation mask 210 of the one shown in Fig. The type of implanted regions 131 shown in Figure 11 is defined. The size and position of the implanted regions 131 required to form a specific type of third region 13 depend, among other things, on the diffusion coefficient of the implanted additional dopants of the first type, as well as on the temperature and duration of the thermal process used to activate the implanted dopants of the first type (and to form at least one third region 13 based on the implanted regions 131). For example, if the implanted regions 131 are formed after the first thermal process, which diffuses the dopants of the first and second types of the base doping, then rapidly diffusing dopants of the first type, such as phosphorus (P) atoms, can be used to generate the implanted regions 131.In this example, the third regions 13 are formed based on the implanted regions 131 in a second thermal process. In this case, the second thermal process can be a special process for activating the implanted dopants of the first type and can be short enough to avoid significant diffusion of the implanted dopants of the first type.

[0072] According to another example, forming a third area involves 13 of the area in the Fig. 4A - 4B of the type shown, the formation of an implanted area 131 by a blanket implantation process, that is, an implantation process in which the further dopant atoms of the first type are implanted into the entire surface area containing the mesa areas 111 and the trenches filled by the filler material 121.

[0073] Fig. Figure 12 shows a vertical cross-sectional view of a section of a superjunction transistor device formed from the semiconductor body 100 according to one of the examples previously described herein. The first, second, and third regions 11, 12, 13 are the superjunction regions of the superjunction device. In addition to the superjunction region, the transistor device contains several transistor cells 2. Each of these transistor cells 2 contains a body region 21 of the second doping type, a source region 22 of the first doping type, and a gate electrode 23. The gate electrode 23 is located adjacent to the body region 21 and is dielectrically isolated from the body region 21 by a gate dielectric 24.

[0074] Referring to Fig. In Figure 12, the gate electrodes 23 of the individual transistor cells are connected to a common gate node G. Furthermore, the source and body regions 22, 21 of the individual transistor cells are connected to a common source node S of the transistor device. Connections between the gate electrodes 23 and the gate node G, and connections between the source and body regions 22, 21 and the common source node S, are shown in Figure 12. Fig. Figure 12 is shown only schematically. These connections can be implemented in a conventional manner.

[0075] In the transistor component according to Fig. The first 12 regions of the first doping type are drift regions, and the second 12 regions of the second doping type are compensation regions. For example, the compensation regions 12 are coupled to the source node S. The compensation regions 12 can be adjacent to the body regions 21 of the transistor cells 2, which, as explained above, are connected to the source node S.

[0076] At least one third area 13 is in Fig. 12 is shown only schematically. At least one third area 13 can be implemented according to one of the examples explained above. Referring to the Fig. In examples 5A-5B, 6A-6C, and 8A-8B, the semiconductor body 100 can contain several third regions 13 spaced apart from one another. In these examples, sections of the compensation regions 12 adjacent to the third regions 13 extend towards the first surface 101 and border the body regions 21, thus connecting to the body regions 21 and, via the body regions 21, to the source node S. Referring to the above, in the example according to the Fig. 4A - 4B, the second sections 132 of the third region 13 are formed such that they are of the second doping type, so that the compensation regions 12 are connected to the body regions 21 via these second sections 132. The gate electrodes 23 serve in a conventional manner to control conducting channels in the body regions 24 along the gate dielectrics 24 between the source regions 22 and the drift regions 11. The transistor device is in an on-state (conducting state) when conducting channels exist in the body regions 21 along the gate dielectrics 24.

[0077] Sections of the body regions 21 adjacent to the gate dielectrics 24 are hereinafter referred to as channel regions. The transistor device is implemented such that the drift regions 11 and / or the first sections 131 of the third regions 13 are adjacent to the channel regions, allowing current to flow between the source and drift regions 22, 11 of the transistor device in the on-state.

[0078] The body regions 21 can be formed by implanting dopant atoms of the second doping type into the semiconductor body 100 via the first surface 101 and by activating the implanted dopant atoms. The source regions 22 can be formed by implanting dopant atoms of the first doping type into the semiconductor body 100 via the first surface 101 and by activating the implanted dopant atoms. The activation of the implanted dopant atoms involves a thermal process.

[0079] In one example, the dopant atoms for forming the body and source regions 21, 22 are implanted into the semiconductor body 100 after the thermal process that forms the first and second regions 11, 12 based on the initial doping and that forms the third region 13 based on the implanted regions 131. In another example, the dopant atoms for forming the body and source regions 21, 22 are implanted before the thermal process that forms the first, second, and third regions 11, 12, 13. In this example, the same thermal process is used to form the first, second, and third regions 11, 12, 13 and to form the body and source regions 21, 22.

[0080] According to one example, the body regions 21 are formed such that they have a doping concentration between 1E16 cm -3 and 1E18 cm -3is, exhibit, and the source areas 22 are formed such that they have a doping concentration between 1E18 cm -3 and 1E21 cm -3 is, exhibit.

[0081] Referring to Fig. In the transistor device 12, a drain region 14 is connected to a drain node D. According to one example, the drain region 14 is formed by the second semiconductor layer 140. Referring to the above, the second semiconductor layer 140 can contain a semiconductor substrate 141. According to another example, the drain region 14 is formed by the semiconductor substrate. The first semiconductor layer 110 can be grown onto the substrate. In this example, the drift and compensation regions 11, 12 border the drain region 14. According to another example, which is described in Fig. As shown in Figure 12 by means of dashed lines, a buffer layer 142 is epitaxially grown onto the substrate 141. In this example, the buffer layer 142 forms a buffer region 15 of the transistor device, and the drift and compensation regions 11, 12 border the buffer region 15.

[0082] For example, buffer zone 15 is of the first doping type and has a lower doping concentration than drain zone 14. For example, the doping concentration of drain zone 14 is between 1E18 cm -3 and 1E21 cm -3 selected and the doping concentration of buffer area 15 is between 5E14 cm -3 and 1E17 cm -3 chosen.

[0083] The transistor device can be implemented as a type n or a type p transistor device. In a type n device, the doped regions of the first doping type are n-doped regions, and the doped regions of the second doping type are p-doped regions. In a type p device, the doped regions of the first doping type are p-doped regions, and the doped regions of the second doping type are n-doped regions. Furthermore, the transistor device can be implemented as an enhancement device or a depletion device.

[0084] The transistor device switches on or off depending on a drive voltage received between the gate node G and the source node S. The transistor device is always in the on state when the drive voltage is higher than a threshold voltage of the device, such that a conductive channel exists in the body regions 21 along the gate dielectric 24. For example, in an enhancement device of type n, the threshold voltage is a positive voltage in the range of several volts.

[0085] The device is always in the off state when the conductive channels along the gate dielectrics 24 are interrupted and a voltage is applied between the drain node D and the source node S such that p / n junctions between the drift regions 11 and the body regions 21 and / or p / n junctions between the first sections 131 of the third regions 13 and the body regions 21 are reverse biased. In this operating mode, space charge regions (depletion regions) are formed in the drift and compensation regions 11, 12 and the at least one third region 13. Generally, the higher the voltage applied between the drain node D and the source node S, the more the depletion regions expand in the drift and compensation regions 11, 12 and the third region 13. The extent of impoverished areas is associated with an electric field.An avalanche breakdown occurs when the strength of the electric field at any point in the semiconductor body 100 reaches a critical value Ecrit. This critical value Ecrit depends mainly on the type of semiconductor material of the semiconductor body 100 and is also dependent on the doping concentration in the regions where the depletion region extends.

[0086] Fig. 13 is a signal diagram that is generated in a semiconductor device by the one in Fig. 12 types shown, the amount |E vert | the vertical component of the electric field at different vertical positions of the semiconductor body 100 when the transistor device is in the off state, illustrated. Fig. Figure 13 shows the electric field along a curve extending in the vertical direction z from the first surface 101 through the first semiconductor layer 110 to the second semiconductor layer 140. In the off state, the electric field is essentially the same at every position along a vertical section plane. Therefore, it represents Fig. 13 the electric field in the vertical direction z at each horizontal position of the transistor element. That is, Fig. 13 represents the electric field along a curve that extends either through one of the drift regions 11 or through one of the compensation regions 12.

[0087] Referring to Fig. 13 A maximum Emax of the electric field occurs at a vertical position that, in the vertical direction z, as seen from the first surface 101, lies below the body regions 21 and above the vertical position z2 of a lower end of the at least one third region 13. The “lower end” of the at least one third region 13 is the end of the at least one third region 13 that faces the drain region 14. In the Fig. 13 denotes z1 the vertical position of an upper end of the at least one third region 13. The "upper end" of the at least one third region 13 faces the first surface 101. Furthermore, z0 denotes the vertical position of the first surface 101.

[0088] Referring to Fig. 13 The electric field in the off-state is essentially equal at every vertical position between position z2 of the lower end of the at least one third region 13 and position z3 of a lower end of the superjunction region. That is, the curve representing the electric field is essentially horizontal between the lower end of the at least one third region 13 and the lower end of the superjunction region, which contains the drift and compensation regions 11, 12. This is the case because at every vertical position between the lower end of the at least one third region 13 and the lower end of the superjunction region, the quantity of first-type dopant atoms and the quantity of second-type dopant atoms are essentially balanced. In this region of the semiconductor body 100, the first-type and second-type dopant atoms result essentially from the base doping.Referring to the above, the basic doping essentially contains the same concentration of dopant atoms of the first type and dopant atoms of the second type.

[0089] The increase of the electric field towards the first surface 101, such that the maximum (the peak) of the electric field occurs in the region of the at least one third region 13, results from an imbalance between the quantity of dopant atoms of the first type and the quantity of dopant atoms of the second type. This imbalance is caused by the presence of the at least one third region 13.

[0090] The transistor device possesses a voltage-blocking capability, which is the maximum drain-source voltage between the drain node D and the source node S that the transistor device can withstand. An avalanche breakdown occurs when the drain-source voltage exceeds the voltage-blocking capability. At the onset of an avalanche breakdown, the maximum Emax of the electric field essentially corresponds to the critical value Ecrit.

[0091] The voltage-blocking capability of the transistor device is essentially given by the integral of the magnitude |Evert| of the electric field along the vertical direction z. That is, the voltage-blocking capability is essentially proportional to the area under the curve representing the Fig. The magnitude of the electric field is represented by the area shown in Figure 13. The presence of at least one third region 13 reduces the voltage-blocking capability compared to a transistor device where at least one third region 13 is omitted. However, at least one third region 13 increases the robustness of the transistor device with respect to the so-called Egawa effect. This will be discussed below with reference to the Fig. 14A and Fig. 14B explained.

[0092] Fig. Figure 14A shows the magnitude of the electric field in a superjunction region where dopant atoms of the first type and dopant atoms of the second type are perfectly balanced. Fig. 14 represents z10 the vertical position of the interface between the body area and the superjunction area, and z30 represents the vertical position of the interface between the superjunction area and the drain area. Fig. Figure 14A shows the magnitude of the electric field in a static state of the transistor device at the onset of avalanche breakdown. The static state implies that no avalanche current flows through the transistor device. The drain-source voltage at which avalanche breakdown occurs is proportional to the area under curve 301, which represents the magnitude of the electric field. Fig. 14A represents.

[0093] In Fig. Figure 14B shows curve 302, which depicts the magnitude of the electric field in an avalanche state where an avalanche current flows through the superjunction region. This avalanche current can cause a local increase in charge carriers in a region near the drain region of the transistor device (i.e., near the vertical position z30). This local increase in charge carriers can have the effect of pinning the magnitude of the electric field at the position containing the local maximum of charge carriers to the critical value Ecrit and causing the magnitude of the electric field within the superjunction region to decrease. The area under curve 302 is smaller than the area under curve 301, so the maximum drain-source voltage decreases when the avalanche current begins. This is known as the Egawa effect. This effect can lead to current filamenting and can damage the device.

[0094] In the transistor component according to Fig. 12. A local increase in charge carriers in the superjunction region due to an avalanche current can lead to an increase in the magnitude of the electric field towards the drain region 14. This is in Fig. 13 is represented by dashed lines. Since the maximum of the electric field still occurs in the region of the third region 13, the increase of the electric field towards the drain region 14 leads to an increase in the drain-source voltage (that is, there is an increase in the area under the curve), which counteracts the danger of current filamentation.

[0095] Referring to the above, at least one third region 13 locally increases the doping concentration of the dopant atoms of the first type in the superjunction region in a section near the body regions 21, so that the maximum of the electric field occurs in this region and so that a “safety margin” exists for a local increase of the electric field in the direction of the drain region 14 after the onset of an avalanche current.

[0096] The avalanche current contains charge carriers of a first type (such as electrons), which flow in the drift regions 11 to the drain region 14, and charge carriers of a second type (such as holes), which flow in the compensation region 12 to the body regions 21. Third regions 13 according to the in the Fig. In examples 5A-5B and 6A-6C, the cross-sectional area of ​​the compensation regions 12 narrows towards the body regions 21, thus causing filamentation of the current of the second type of charge carriers in the compensation regions 12. Such current filamentation causes a local increase in the current density of the second type of charge carriers, and this local increase in the current density of the second type of charge carriers promotes an avalanche breakdown in the compensation regions 12. More precisely, an avalanche breakdown occurs when a high electric field is present and when charge carriers are available that cause impact ionization. A local increase in the charge carrier density promotes such impact ionization and thus an avalanche breakdown. An avalanche breakdown occurring in the compensation region 12 contributes to further increasing the robustness of the transistor device.

[0097] According to a Fig. In the example shown in Figure 15, the procedure for forming the superjunction region further includes the implantation of dopant atoms of the second doping type via floors 106 of the trenches 103 into the second semiconductor layer 140 to form second implanted regions 161.

[0098] Referring to Fig. Figure 16, which shows a vertical cross-sectional view of the finished transistor device, shows that in the temperature process, 140 doped regions 16 containing dopant atoms of the second doping type are formed in the second semiconductor layer. According to one example, these doped regions 16 are mainly formed in or near the buffer region 15.

[0099] Referring to Fig. 17, which determines the magnitude |E| of the electric field in the blocking state of a transistor device from that in Fig. As shown in Figure 16, the doped regions 16 of the second doping type cause a second peak in the electric field in the buffer region 15. According to an example, the implantation doses for forming the first implanted regions 131 and the second implanted regions 161 are matched such that the first peak, caused by the third regions 13, is higher than the second peak, caused by the second regions 16. The presence of the second regions 16 leads to an increase in the voltage blocking capability.

[0100] At the in Fig. In the example shown in Figure 12, the gate electrodes 23 are trench electrodes, which are electrodes located in gate trenches. The gate trenches extend from the first surface 101 into the semiconductor body 100. However, implementing the transistor cells 2 with trench gate electrodes is only one example. It is also possible to implement the transistor cells 2 with planar gate electrodes, which are gate electrodes located above the first surface 101 of the semiconductor body 100.

[0101] An example of transistor cells 2 implemented with planar gate electrodes 23 is shown in Fig. 18 schematically represented. It should be noted that Fig. Figure 18 shows only an upper section of the first semiconductor layer 110, in which the transistor cells 2 are implemented. The drain region 14 and the optional buffer region 15 are shown in Fig. 18 not shown.

[0102] According to the transistor components Fig. 12 and Fig. In 18, each of the first and second regions 11, 12 of the superjunction region is an elongated region, and each of the body and source regions 21, 22 of the transistor cells 2 is an elongated region. In the examples according to the Fig. 12 and Fig. 18 the elongated first and second regions 11, 12 and the elongated body and source regions 21, 22 extend laterally in the same direction as approximately the second lateral direction y.

[0103] Some of the aspects discussed above are summarized below with reference to numbered examples.

[0104] Example 1. A method comprising: forming trenches in a first semiconductor layer of a semiconductor body such that mesa regions are formed between the trenches, wherein the first semiconductor layer contains a base doping of dopant atoms of a first doping type and dopant atoms of a second doping type complementary to the first doping type, and wherein the dopant atoms of the second doping type have a diffusion coefficient different from that of the dopant atoms of the first doping type; filling the trenches with a monocrystalline semiconductor material;and performing a first thermal process such that first regions with effective doping of the first doping type are formed based on the dopant atoms of the first doping type contained in the base doping, and second regions with effective doping of the second doping type are formed based on the dopant atoms of the second doping type contained in the base doping, the process further comprising: implanting additional dopant atoms of the first doping type into the first semiconductor layer to form at least one first implanted region; and activating the implanted additional dopant atoms of the first doping type to form at least one third region.

[0105] Example 2. Method according to Example 1, wherein the implantation of the further dopant atoms of the first doping type includes the implantation of the further dopant atoms of the first doping type into sidewalls of the trenches before filling the trenches.

[0106] Example 3. Method according to Example 1, wherein the implantation of the further dopant atoms of the first doping type involves implanting the further dopant atoms of the first doping type into the first semiconductor layer via a first surface of the first semiconductor layer.

[0107] Example 4. Method according to Example 3, wherein the implantation of the further dopant atoms of the first doping type includes the implantation of the further dopant atoms of the first doping type after filling the trenches.

[0108] Example 5. Method according to Example 4, wherein the implanted regions are formed prior to the first thermal process, and wherein the first thermal process activates the implanted further dopant atoms of the first doping type to form the at least one third region.

[0109] Example 6. Method according to Example 4, wherein the implanted regions are formed after the first thermal process, and wherein the activation of the implanted further dopant atoms of the first doping type to form the at least one third region involves a second thermal process.

[0110] Example 7. Method according to one of the preceding examples, wherein the at least one first implanted region contains several first implanted regions spaced apart from each other in a lateral direction of the first semiconductor layer, such that the third regions are spaced apart from each other in the lateral direction after the temperature process.

[0111] Example 8. Method according to any of the preceding examples, wherein the first semiconductor layer has a thickness in a vertical direction, and wherein the first implanted regions are formed such that a dimension of the first implanted regions in the vertical direction is less than 25% of the thickness of the first semiconductor layer.

[0112] Example 9. Method according to any of the preceding claims, wherein the at least one first implanted area is formed such that it has an area-specific vertical dopant dose which is between 5% and 40% of a breakdown charge of the semiconductor material of the first semiconductor layer.

[0113] Example 10. Method according to any of Examples 1 to 9, wherein the dopant atoms of the first doping type contain atoms of a first element, wherein the dopant atoms of the second doping type contain atoms of a second element, and wherein the further dopant atoms of the first doping type contain atoms of a third element different from the first element.

[0114] Example 11. Method according to Example 10, wherein the first element is arsenic, the second element is boron, and the third element is phosphorus.

[0115] Example 12. Method according to Example 10, wherein the first element is antimony, the second element is boron, and the third element is phosphorus or arsenic.

[0116] Example 13. Method according to any one of Examples 1 to 9, wherein the dopant atoms of the first doping type have atoms of a first element, wherein the dopant atoms of the second doping type contain atoms of a second element, and wherein the further dopant atoms of the first doping type contain atoms of the first element.

[0117] Example 14. Method according to Example 13, where the first element is arsenic and the second element is boron.

[0118] Example 15. Method according to one of the preceding claims, further comprising: forming several transistor cells, each comprising a body region of the second doping type, a source region of the first doping type and a gate electrode arranged adjacent to the body region and dielectrically isolated from the body region by a gate dielectric.

[0119] Example 16. Method according to Example 15, wherein the transistor cells are formed such that each body region borders at least a second region and at least a third region.

[0120] Example 17. Procedure according to one of the preceding examples, wherein the trenches are formed such that they have an aspect ratio of more than 5:1, more than 7:1 or more than 12:1.

[0121] Example 18. Method according to any of the preceding examples, wherein each of a first doping concentration of the dopant atoms of the first doping type and a second doping concentration of the dopant atoms of the second doping type contained in the base doping deviates by less than 1% from an average of the first and second doping concentrations.

[0122] Example 19. Method according to one of the preceding examples, wherein the semiconductor body further contains a second semiconductor layer of the first doping type, wherein the first semiconductor layer is formed on the second semiconductor layer.

[0123] Example 20. Method according to Example 19, wherein the trenches are formed such that they extend from a first surface of the first semiconductor layer through the first semiconductor layer into the second semiconductor layer.

[0124] Example 21. Method according to Example 19 or 20, wherein the second semiconductor layer includes a first sublayer and a second sublayer arranged between the first sublayer and the first semiconductor layer, wherein the first sublayer has a higher doping concentration than the second sublayer.

[0125] Example 22. Method according to Example 21, wherein the trenches are formed in such a way that they extend into the second sub-layer and are spaced apart from the first sub-layer.

[0126] Example 23. Method according to Example 21, wherein the trenches are formed in such a way that they extend through the second sub-layer into the first sub-layer.

[0127] Example 24. Method according to any of the preceding claims, further comprising: implanting further second dopant atoms of the second doping type into the bottoms of the trenches before filling the trenches with the monocrystalline semiconductor material.

[0128] Example 25. Method according to Example 24, wherein the further dopant atoms of the second doping type contain atoms of the same element as the dopant atoms of the second doping type contained in the basic doping.

[0129] Example 26. Method according to one of the preceding claims, wherein the first semiconductor layer contains monocrystalline silicon.

[0130] Example 27. Superjunction transistor device containing: several transistor cells, each containing a body region, a source region and a gate electrode, which is dielectrically isolated from the body region by a gate dielectric;a superjunction region adjacent to the body regions of the transistor cells, wherein the superjunction region contains several first regions of a first doping type and several second regions of a second doping type arranged alternately in a lateral direction of a first semiconductor layer, wherein the first regions and the second regions contain dopant atoms resulting from an epitaxial growth process of the first semiconductor layer, wherein the superjunction region further contains at least one third region overlapping the first and second regions in sections adjacent to the body regions, wherein the third regions contain further dopant atoms of the first type resulting from an implantation process.

[0131] Example 28. Superjunction transistor device according to Example 27, wherein the at least one third region contains several third regions spaced apart from each other.

Claims

[1] Method which features: Forming trenches (103) in a first semiconductor layer (110) of a semiconductor body (100) such that mesa regions (111) are formed between the trenches (103), wherein the first semiconductor layer (110) contains a basic doping of dopant atoms of a first doping type and dopant atoms of a second doping type complementary to the first doping type, and wherein the dopant atoms of the second doping type have a diffusion coefficient different from the diffusion coefficient of the dopant atoms of the first doping type; Filling the trenches (103) with a monocrystalline semiconductor material (121); and Performing a first thermal process such that first regions (11) with an effective doping of the first doping type are formed based on the dopant atoms of the first doping type contained in the basic doping, and second regions (12) with an effective doping of the second doping type are formed based on the dopant atoms of the second doping type contained in the basic doping, the procedure further exhibits: Implanting further dopant atoms of the first doping type into the first semiconductor layer (110) to form at least one first implanted region (131); and Activating the implanted additional dopant atoms of the first doping type to form at least one third region (13), wherein at least one first implanted area (131) is formed such that it has an area-specific vertical dopant dose which is between 5% and 40% of a breakdown charge of the semiconductor material of the first semiconductor layer (110). [2] Method according to claim 1, wherein the implantation of the further dopant atoms of the first doping type comprises the implantation of the further dopant atoms of the first doping type into side walls (104, 105) of the trenches (103) prior to filling the trenches (103). [3] Method according to claim 1, wherein the implantation of the further dopant atoms of the first doping type comprises the implantation of the further dopant atoms of the first doping type into the first semiconductor layer (110) via a first surface (101) of the first semiconductor layer (110). [4] Method according to claim 3, wherein the implantation of the further dopant atoms of the first doping type comprises the implantation of the further dopant atoms of the first doping type after filling the trenches (103). [5] Method according to claim 4, wherein the implanted areas (131) are formed prior to the first thermal process, and wherein the first thermal process activates the implanted further dopant atoms of the first doping type to form at least a third region (13). [6] Method according to claim 4, wherein the implanted areas (131) are formed after the first thermal process, and wherein the activation of the implanted further dopant atoms of the first doping type to form at least a third region (13) involves a second thermal process. [7] Method according to any one of the preceding claims, wherein at least one first implanted region (131) has several first implanted regions (131) that are spaced apart from each other in a lateral direction (y) of the first semiconductor layer (110), such that the third regions (13) are spaced apart from each other in the lateral direction (y) after the temperature process. [8] Method according to any one of the preceding claims, wherein the first semiconductor layer (110) has a thickness (d110) in a vertical direction (z), and wherein the first implanted regions (131) are formed such that a dimension (d131) of the first implanted regions (131) in the vertical direction (z) is less than 25% of the thickness of the first semiconductor layer (110). [9] Method according to any one of claims 1 to 8, wherein the dopant atoms of the first doping type have atoms of a first element, wherein the dopant atoms of the second doping type have atoms of a second element, and wherein the further dopant atoms of the first doping type contain atoms of a third element different from the first element. [10] Method according to claim 9, wherein the first element arsenic is, the second element is boron, and The third element is phosphorus. [11] Method according to claim 9, wherein the first element is antimony the second element is boron, and the third element is phosphorus or arsenic. [12] Method according to any one of claims 1 to 8, wherein the dopant atoms of the first doping type have atoms of a first element, wherein the dopant atoms of the second doping type have atoms of a second element, and wherein the other dopant atoms of the first doping type contain atoms of the first element. [13] Method according to claim 12, wherein the first element is arsenic, and the second element is boron. [14] A method according to any of the preceding claims, further comprising: forming several transistor cells, each comprising a body region (21) of the second doping type, a source region (22) of the first doping type and a gate electrode (23) which is arranged adjacent to the body region (21) and is dielectrically isolated from the body region (21) by a gate dielectric (24). [15] Method according to claim 14, wherein the transistor cells are formed such that each body region (21) is adjacent to at least a second region (12) and to at least a third region (13). [16] Method according to any of the preceding claims, wherein the trenches (103) are formed such that they have an aspect ratio of more than 5:1, more than 7:1 or more than 12:

1. [17] Method according to any of the preceding claims, wherein each of a first doping concentration of dopant atoms of the first doping type and a second doping concentration of dopant atoms of the second doping type contained in the base doping deviates by less than 1% from an average of the first and second doping concentrations. [18] Method according to any one of the preceding claims, wherein the semiconductor body (100) further comprises a second semiconductor layer (140) of the first doping type, wherein the first semiconductor layer (110) is formed on the second semiconductor layer (140). [19] Method according to claim 18, wherein the trenches (103) are formed such that they extend from a first surface (101) of the first semiconductor layer (110) through the first semiconductor layer (110) into the second semiconductor layer (140). [20] Method according to claim 18 or 19, wherein the second semiconductor layer (140) comprises a first sublayer (141) and a second sublayer (142) which is arranged between the first sublayer (141) and the first semiconductor layer (110), wherein the first sublayer (141) has a higher doping concentration than the second sublayer (142). [21] Method according to claim 20, wherein the trenches (103) are formed such that they extend into the second sublayer (142) and are spaced apart from the first sublayer (141). [22] Method according to claim 20, wherein the trenches (103) are formed such that they extend through the second sublayer (142) into the first sublayer (141). [23] A method according to any of the preceding claims, further comprising: Implanting further second dopant atoms of the second doping type into bottoms (106) of the trenches (103) before filling the trenches (103) with the monocrystalline semiconductor material. [24] Method according to claim 23, wherein the further dopant atoms of the second doping type comprise atoms of the same element as the dopant atoms of the second doping type contained in the basic doping. [25] Method according to any of the preceding claims, wherein the first semiconductor layer (110) comprises monocrystalline silicon. [26] Superjunction transistor device which features: several transistor cells (2), each comprising a body region (21), a source region (22) and a gate electrode (23) which is dielectrically insulated from the body region (21) by a gate dielectric (24); a superjunction region adjacent to the body regions (21) of the transistor cells (21), wherein the superjunction region contains several first regions (11) of a first doping type and several second regions (12) of a second doping type arranged alternately in a lateral direction of a first semiconductor layer (110), wherein the first regions (11) and the second regions (12) contain dopant atoms resulting from an epitaxial growth process of the first semiconductor layer (110), wherein the superjunction area continues to contain at least a third area (13) that overlaps the first and second areas (11, 12) in sections adjacent to the body regions (21), wherein at least a third region (13) contains further dopant atoms of the first type resulting from an implantation process in which the further dopant atoms are implanted such that at least a first implanted region is created with an area-specific vertical dopant dose which is between 5% and 40% of a breakdown charge of the semiconductor material of the first semiconductor layer (110). [27] Superjunction transistor device according to claim 26, wherein the at least one third region contains several third regions (13) that are spaced apart from each other.

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