Semiconductor device and method for manufacturing a semiconductor device

Abstract

Semiconductor device (10, 10b), comprising: a semiconductor base body (100) having a first main surface (100a) and a second main surface (100b); a first electrode (4); and a second electrode (5), wherein the semiconductor base body (100) comprises: a first semiconductor layer (2) of a first conductivity type, which is arranged on the side of the second main surface (100b) of the semiconductor base body (100); a second semiconductor layer (1) of the first conductivity type, which has a concentration of impurities of the first conductivity type that is lower than that of the first semiconductor layer (2) and is located closer to the first main surface (100a) than the first semiconductor layer (2); and a third semiconductor layer (3) of a second conductivity type, which is located closer to the first main surface (100a) than the second semiconductor layer (1), wherein the first semiconductor layer (2) is electrically connected to the second electrode (5) in the second main surface (100b), wherein the third semiconductor layer (3) is electrically connected to the first electrode (4) in the first main surface (100a), wherein a defect concentration distribution of the third semiconductor layer (3) with respect to a thickness direction of the semiconductor base body (100) exhibits a plurality of peak values, wherein a thickness W of the third semiconductor layer (3), a thickness W N- the second semiconductor layer (1), the elementary charge q, a relative permittivity ε s of the semiconductor material of the semiconductor base body (100), the vacuum permittivity ε0, a nominal voltage V r , a nominal current density J r , a charge carrier lifetime τ of a charge carrier of the second conductivity type in the second semiconductor layer (1), a dosage amount D A the third semiconductor layer (3), a mean charge carrier concentration n Avg , an electric charge density N' D , and α(τ), which is given below as Formula 2 and which represents a ratio between an average charge carrier concentration of the second semiconductor layer (1) in a one-state of the semiconductor device (10, 10b) and an electrical charge concentration in a depletion layer around a boundary of the second semiconductor layer (1) and the third semiconductor layer (3) in the middle of the second semiconductor layer (1) during a recovery process of the semiconductor device (10, 10b), where α(τ) is a factor of proportionality and is represented by the following Formula 1, N ' D = α ( τ ) n A vg fulfill the following formula 3: α ( τ ) = 4.15 ( I n ( 2.58 τ + 1 ) ) 4.77 + 225 W > 1.6 ε s ε 0 V rq DA − 2 q WN − DA 2.5 α ( τ ) J r τ

Description

Background of the invention; Field of the invention

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Description of the background of the state of the art

[0002] Publication JP 2013 - 21 142 A discloses a semiconductor device which has a configuration for reducing switching losses.

[0003] DE 10 2017 121 878 A1 describes a power diode comprising a semiconductor body coupled to an anode metallization and a cathode metallization of the power diode. The semiconductor body has a drift region of a first conductivity type and an anode region of a second conductivity type. The anode region comprises a contact zone arranged in contact with the anode metallization; a field-stop zone arranged below the contact zone; and a body zone arranged below the field-stop zone and above the drift region. An electrically activated dopant concentration of the anode region exhibits a profile along a vertical direction, according to which a first maximum is present in the contact zone; a second maximum is present in the field-stop zone; and the dopant concentration decreases steadily from the first maximum to a local minimum and increases steadily from the local minimum to the second maximum (32).

[0004] DE 11 2017 000 689 T5 describes a semiconductor device with a contact trench. The semiconductor device comprises a semiconductor substrate; a first-type conductivity drift region provided on a top side of the semiconductor substrate; a second-type conductivity base region provided above the drift region; a first-type conductivity source region provided above the base region; two or more trench sections extending through the source region and the base region from an upper end face of the source region; a contact trench provided in direct contact with the source region between adjacent trench sections; and a second-type conductivity contact layer provided below the contact trench. A peak of doping concentration in the contact layer is positioned shallower than a position at the lower end of the source region.

[0005] In semiconductor devices, a problem exists where a semiconductor layer becomes completely depleted, and the semiconductor device fails during recovery operations with high current and high voltage. Summary

[0006] The present disclosure has an objective of providing a semiconductor device that is suitable for preventing complete depletion of a semiconductor layer during recovery operation with a high current and a high voltage, and is suitable for preventing failure of the semiconductor device due to complete depletion of the semiconductor layer.

[0007] The semiconductor device of the present disclosure comprises: a semiconductor base body having a first principal surface and a second principal surface; a first electrode; and a second electrode. The semiconductor base body comprises: a first semiconductor layer of a first conductivity type, provided on the side of the second principal surface of the semiconductor base body; a second semiconductor layer of the first conductivity type, having a lower impurity concentration of the first conductivity type than that of the first semiconductor layer and being located closer to the first principal surface than the first semiconductor layer; and a third semiconductor layer of a second conductivity type, being located closer to the first principal surface than the second semiconductor layer. The first semiconductor layer is electrically connected to the second electrode on the second principal surface.The third semiconductor layer is electrically connected to the first electrode in the first main surface. The impurity concentration distribution of the third semiconductor layer with respect to a thickness direction of the semiconductor substrate exhibits a plurality of peak values. The thickness W of the third semiconductor layer is defined as a specific thickness W. N- the second semiconductor layer, the elementary charge q, a relative permittivity ε s of the semiconductor material, the vacuum permittivity ε0, a nominal voltage V r , a nominal current density J r , a charge carrier lifetime τ of a charge carrier of the second conductivity type in the second semiconductor layer, a dosage quantity D A the third semiconductor layer and α(τ) = 4.15 / (ln(2.58τ + 1)) 4.77+ 225), which represents a ratio between an average charge carrier concentration of the second semiconductor layer in an on-state of the semiconductor device and an electrical charge concentration in a depletion layer around a boundary of the second semiconductor layer and the third semiconductor layer in the middle of the second semiconductor layer during a recovery process of the semiconductor device, satisfies W > (1.6ε s ε0V r ) / qD A - (2qW N- D A ) / (2.5α(τ)J r τ).

[0008] According to the present invention, a semiconductor device is created which is suitable to prevent complete depletion of a semiconductor layer during recovery operation with a high current and a high voltage and failure of the semiconductor device due to complete depletion of the semiconductor layer.

[0009] These and other tasks, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when viewed in conjunction with the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a diagram showing a semiconductor device according to embodiment 1. Fig. Figure 2 is a diagram showing a semiconductor device according to embodiment 2. Fig. Figure 3 is a diagram showing the impurity concentration distribution according to embodiment 1 and a comparative example. Fig. Figure 4 is a diagram showing the relationship between the maximum value of the impurity concentration and the maximum recovery blocking power in the semiconductor devices according to embodiment 1 and according to the comparative example. Fig. Figure 5 is a diagram showing the relationship between the forward voltage drop and the recovery loss of the semiconductor devices according to embodiment 1 and the comparative examples. Fig. Figure 6 is a diagram showing a leakage current of the semiconductor devices of the comparison examples and embodiment 1. Fig. 7, Fig. 8 to Fig. Figure 9 shows a state of the semiconductor device during manufacturing in the manufacturing process according to embodiment 1. Fig. 10, Fig. 11 to Fig. Figure 12 shows the time dependence of a current and a voltage during a recovery operation of the semiconductor device according to embodiment 1. Fig. Figure 13 is a diagram showing the electric field distribution around the PN junction 6, which forms the boundary between the N --Type substrate 1 and the P-type diffusion layer 3 is shown in the semiconductor device according to embodiment 1. Fig. 14, Fig. 15 to Fig. Figure 16 shows diagrams illustrating charge carrier concentrations in an on-state and recovery states in the semiconductor device according to embodiment 1. Fig. Figure 17 is a diagram showing the factor of a proportionality α(τ) which is obtained empirically. Fig. Figure 18 is a diagram showing a representative value of the power supply voltage for each of the nominal voltages in the semiconductor device according to embodiment 1. Fig. Figure 19 is a diagram showing a representative value of a nominal current density and a representative value of a high current density in an on-state just before switching for each of the nominal voltages in the semiconductor device according to embodiment 1. Fig. 20 is a diagram showing a representative value of the thickness of N - -Type substrate 1 for each of the nominal voltages in the semiconductor devices according to embodiment 1 is shown. Fig. 21 and Fig. Figure 22 are diagrams showing the semiconductor devices according to comparative examples. Fig. Figure 23 is a flowchart showing a manufacturing process for a semiconductor device according to embodiment 1. Description of preferred embodiments

[0010] In the following description, an N-type and a P-type, which are the conductivity types of the semiconductor, are interchangeable. <vergleichsbeispiel>

[0011] Fig. Figure 21 shows a semiconductor device 10z1 according to a comparative example. Fig. Figure 22 shows a semiconductor device 10z2 according to a comparative example.

[0012] The semiconductor device 10z1 comprises a semiconductor base body 100, an anode electrode 4 and a cathode electrode 5.

[0013] The semiconductor base body 100 has a first main surface 100a and a second main surface 100b. The semiconductor base body 100 has an N - -Type substrate 1, an N-type diffusion layer 2 and a P-type diffusion layer 3z1.

[0014] The N-type diffusion layer 2 is located on the side of the second main surface 100b of the semiconductor base body 100. The N - -Type substrate 1 is closer to the first main surface 100a than the N-type diffusion layer 2. The P-type diffusion layer 3 is closer to the first main surface 100a than the N - -Type substrate 1. An N-type defect concentration of N - -Type substrate 1 is lower than an N-type defect concentration of the N-type diffusion layer 2.

[0015] Compared to semiconductor device 10z1, semiconductor device 10z2 has a P-type diffusion layer 3z2 instead of the P-type diffusion layer 3z1. Additionally, lifetime limiters 7 are incorporated into the N - -Type substrate 1 is provided in the semiconductor device 10z2.

[0016] Semiconductor device 10z1 and semiconductor device 10z2 are each diodes. In the following description, semiconductor device 10z1 can be referred to as comparative example 1 and semiconductor device 10z2 can be referred to as comparative example 2.

[0017] Fig. Figure 3 shows the defect concentration of the P-type diffusion layer 3z1 and the N - -Type substrate 1 along the in Fig. BB line shown in 21 (comparative example 1 in Fig. 3).

[0018] Fig. Figure 3 shows the defect concentration of the P-type diffusion layer 3z2 and the N - -Type substrate 1 along the in Fig. CC line shown in Figure 22 (comparative example 2 in Fig. 3).

[0019] In Fig. 3 represents the horizontal axis positions with respect to a thickness direction. Fig. 3 corresponds to the position with a depth of 0 µm to the first main surface 100a.

[0020] In semiconductor device 10z1, to reduce switching losses, the dosage amount to the P-type diffusion layer 3z1 is reduced, and the impurity concentration of the P-type diffusion layer 3z1 is decreased. Nevertheless, in a case where the impurity concentration of the P-type diffusion layer 3z1 is less than or equal to 2.5 x 16 cm⁻¹, -3 During recovery operation after switching from an on-state in which a high voltage is applied and a high current flows in a forward direction, a depletion layer forms around the boundary of the P-type diffusion layer 3z1 and the N - -Type substrate 1 the anode electrode 4, and the device fails due to the recovery current in the P-type diffusion layer 3z1. Thus, there is a limit to reducing switching losses by decreasing the impurity concentration of the P-type diffusion layer 3z1.

[0021] In the semiconductor device 10z2, lifetime limiters 7 are located in the N - An N-type substrate 1 is provided to reduce switching losses. The lifetime limiters 7 are formed by electron beam irradiation from the side of the second main surface 100b. Since the electron beam passes through the N-type diffusion layer 2, which is a surface layer of the semiconductor base body 100 on the side of the second main surface 100b, the electron beam irradiation increases the non-uniformity of properties among the semiconductor devices 10z2.

[0022] To reduce switching losses, configurations are used in which the impurity concentration of the P-type diffusion layer 3z1 or the P-type diffusion layer 3z2 is varied depending on its position in a plane, and P+ regions with a relatively high impurity concentration and P regions with a relatively low impurity concentration are arranged alternately in one of the directions in the plane. In this case, when the reverse high voltage is applied during recovery operation after switching from an on-state with the high let-through current, an avalanche current is generated by the concentration of the electric field at the interface between the P+ regions and the P regions, and the interface between the P+ regions and the P regions fails due to heat. <A. Ausführungsform 1><A-1. Konfiguration und Betrieb>

[0023] Fig. Figure 1 shows a semiconductor device 10 according to embodiment 1.

[0024] The semiconductor device 10 comprises a semiconductor base body 100, an anode electrode 4 and a cathode electrode 5.

[0025] The semiconductor base body 100 has a first main surface 100a and a second main surface 100b. The semiconductor base body 100 has an N - The semiconductor base body 100 comprises an N-type substrate 1 (an example of a second semiconductor layer), an N-type diffusion layer 2 (an example of a first semiconductor layer), and a P-type diffusion layer 3 (an example of a third semiconductor layer). The P-type diffusion layer 3, which is composed of a semiconductor layer of a conductivity type, is located in the surface layer on the first main surface 100a.

[0026] The transition part between the N - The -type substrate 1 and the P-type diffusion layer 3 is referred to as the PN transition part 6.

[0027] The P-type diffusion layer 3 is electrically connected to the anode electrode 4 in the first main surface 100a. The N-type diffusion layer 2 is electrically connected to the cathode electrode 5 in the second main surface 100b.

[0028] The P-type diffusion layer 3 has a P-type diffusion layer 3a, a P-type diffusion layer 3b and a P-type diffusion layer 3c.

[0029] The N-type diffusion layer 2 is located in the surface layer on the side of the second main surface 100b of the semiconductor base body 100.

[0030] The N - -Type substrate 1 is closer to the first main surface 100a than the N-type diffusion layer 2. The P-type diffusion layer 3 is closer to the first main surface 100a than the N - -Type substrate 1. The N-type defect concentration of N - The concentration of N-type impurities in substrate 1 is lower than the concentration of N-type impurities in the N-type diffusion layer 2.

[0031] The N - -Type substrate 1 is a semiconductor layer that contains, for example, arsenic or phosphorus as N-type defects.

[0032] A diode structure is formed by the N-type diffusion layer 2, the P-type diffusion layer 3 and the N - -Type substrate 1 formed.

[0033] The semiconductor device 10 is a diode. The semiconductor device 10 can be a power semiconductor device which includes a diode as part of it, such as an inverting insulated-gate bipolar transistor (RC-IGBT).

[0034] The N-type defect concentration of N - -Type substrate 1 is 1.0E12 cm -3 up to 1.0E14 cm -3 .

[0035] The N-type diffusion layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as N-type defects. The N-type defect concentration of the N-type diffusion layer 2 is 1.0 x 10⁻⁴ cm⁻¹. -3 up to 1.0E21 cm -3 .

[0036] The P-type diffusion layer 3 is a semiconductor layer containing, for example, boron or aluminum as P-type defects. The P-type defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction exhibits multiple peak values. The following describes a case in which the P-type defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction has, as an example, two peak values. However, the P-type defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction can exhibit more than two peak values.

[0037] P-type diffusion layer 3a and P-type diffusion layer 3c are each the region around each of the two peak values ​​of the P-type defect concentration distribution of P-type diffusion layer 3 with respect to the thickness direction. P-type diffusion layer 3b is a region between the two peak values, that is, a region between P-type diffusion layer 3a and P-type diffusion layer 3c.

[0038] Fig. Figure 3 shows an example of the defect concentration distribution along the AA line in Fig. 1 (shown as embodiment 1 in Fig. 3). In Fig. 3 corresponds to the position with a depth of 0 µm to the first main surface 100a. In Fig. Figure 3 shows the difference between the N-type and P-type defect concentrations. In the P-type diffusion layer 3b, the defect concentration of P-type defects is higher than the defect concentration of N-type defects. In the N - In type 1 substrate, the concentration of N-type defects is higher than the concentration of P-type defects.

[0039] The maximum value of the defect concentration distribution of the P-type diffusion layer 3 is less than or equal to 1.0E17 cm. -3 .

[0040] The P-type defect concentration of the P-type diffusion layer 3b is higher than the N-type defect concentration N D of the N - -Type substrate 1. As a consequence, latch-up is prevented. The same applies if the P-type defect concentration distribution of the P-type diffusion layer 3 has more than two peak values ​​with respect to the thickness direction. That is, in a region of the P-type diffusion layer 3 that lies between the peak value closest to the first main surface 100a and the peak value closest to the second main surface 100b, and is among the peak values ​​of the defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction, the minimum value of the P-type concentration is higher than the N-type concentration of the N - -Type substrate 1.

[0041] The P-type defect concentration of the P-type diffusion layer 3b is higher than 1.0 × 10¹³ cm⁻¹. -3 .

[0042] Of the two peak values ​​of the P-type defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction, the defect concentrations are highest at the peak value closer to the first main surface 100a. In the case where the P-type defect concentration distribution of the P-type diffusion layer 3 has more than two peak values ​​with respect to the thickness direction, the defect concentrations are, for example, highest at the peak value closest to the main surface 100a among the more than two peak values.

[0043] The P-type defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction can exhibit two peak values, with the defect concentration being highest at the peak value closest to the second main surface 100b of the two peak values. Similarly, if the P-type defect concentration distribution of the P-type diffusion layer 3 has more than two peak values ​​with respect to the thickness direction, the defect concentration can be highest, for example, at the peak value closest to the second main surface 100b among the more than two peak values. <A-2. Vergleich mit dem Vergleichsbeispiel>

[0044] Fig. 4, Fig. 5 to Fig. Figure 6 shows the result of a comparison between the semiconductor devices according to the present embodiment and the semiconductor devices according to the comparison example.

[0045] Fig. Figure 4 shows the relationship between the maximum value of the impurity concentration of the P-type diffusion layer 3 and the maximum recovery blocking power Prr in the semiconductor devices 10z1 of the comparison example and in the semiconductor devices 10 of embodiment 1. Fig. Figure 4 shows the data at 150°C. The maximum recovery blocking power is the maximum value of the electrical power of the reverse current allowed for semiconductor devices 10z1 or semiconductor devices 10. As shown in Fig. As shown in Figure 4, in the configuration of comparison example 1 Prr, it essentially decreases in the case where the maximum value of the impurity concentration of the P-type diffusion layer 3z1 is less than or equal to 2.5E16 cm -3 On the other hand, in the configuration of the current embodiment, Prr shows no significant decrease even in the case where the maximum value of the defect concentration of the P-type diffusion layer 3 is less than or equal to 2.5 x 16 cm³. -3 As described above, the configuration in which the P-type defect concentration distribution of the P-type diffusion layer 3 has two peaks with respect to the thickness direction can reduce the amount of defect implanted into the P-type diffusion layer 3, thereby preventing a reduction in the maximum recovery blocking power Prr. By reducing the amount of defect implanted into the P-type diffusion layer 3, a flux of holes from the P-type diffusion layer 3 into the N - -Type substrate 1 is prevented, and switching loss is prevented.

[0046] Fig. Figure 5 shows the trade-off relationship between a forward voltage drop Vf and the recovery loss Erec of the semiconductor devices of embodiment 1, comparative example 1, comparative example 2, and comparative example 3. Fig. Figure 5 represents Comparison Example 3, the configuration in which a modification is made to increase the P-type defect concentration of the P-type diffusion layer 3z1 compared to Comparison Example 1. In the semiconductor device 10z1 of Comparison Example 1, suppressing the reduction of the maximum recovery blocking power Prr is incompatible with the configuration with the low Erec. In the semiconductor device of Comparison Example 3, the forward voltage drop Vf is lower and the recovery power Erec is higher compared to those of Comparison Example 2. In the semiconductor device 10 of the current embodiment and the semiconductor device 10z2 of Comparison Example 2, a reduction of the maximum recovery blocking power Prr is suppressed and Erec is low.In the semiconductor device 10 of the current embodiment, Erec is almost comparable to Erec of the semiconductor device 10z2 of comparison example 2, without having to realize the formation of lifetime limiters by electron beam irradiation.

[0047] Fig. Figure 6 shows the leakage current Irrm of the semiconductor devices of the comparative examples and of the semiconductor device 10 of embodiment 1. Fig. Figure 6 shows the variation of the error between the products with error bars. In the semiconductor devices 10z2, in which the lifetime limiters 7 are formed by electron beam irradiation, the variation of the leakage current among the products is increased because the electron beam passes through the N-type diffusion layer 2 during electron beam irradiation. As a consequence, the variation of the reverse recovery safe operating area (RRSOA) among the products increases in the semiconductor devices 10z2. In the semiconductor devices 10 of the current embodiment, the variation of the leakage current is suppressed compared to that of the semiconductor devices 10z2. As a consequence, the variation of the RRSOA among the products is suppressed in the semiconductor devices 10 of the current embodiment. <A-3. Dicke W der P-Typ-Diffusionsschicht 3>

[0048] The thickness W of the P-type diffusion layer 3 is preferably less than or equal to 20 µm due to the restriction by high-energy (i.e., MeV-class) ion implantation devices and the restriction by time and temperature in thermal diffusion.

[0049] A lower limit of the thickness W of the P-type diffusion layer 3 depends on the use of the semiconductor device 10 and a charge carrier lifetime of the N. - -Type substrate 1, of a thickness W N- of the N - -Type substrate 1 and dosage amount D A the P-type diffusion layer 3. The use of the semiconductor device 10 means, for example, how the current density J and a power supply voltage V cc in the on-state. The following describes the lower limit of the thickness W of the P-type diffusion layer 3, which is desirable to avoid damage to the semiconductor device 10. <A-3-1. Gründe eines Ausfalls der Halbleitervorrichtungen 10>

[0050] Reasons for failure of semiconductor device 10 during recovery operations include power outages and voltage failures. There are three types of voltage failure: complete depletion of the P-type diffusion layer 3, a dynamic avalanche, and an overvoltage.

[0051] Complete depletion of the P-type diffusion layer 3 occurs while the voltage V ka , which is the voltage between the anode electrode 4 and the cathode electrode 5, in the direction of the power supply voltage V cc increases after the voltage V ka from a forward voltage to a reverse voltage. The voltage V ka is defined as being positive when a reverse voltage is applied. A low impurity concentration in the P-type diffusion layer 3, a high current density in a one-state, and a long charge carrier lifetime in the N - -Type substrate 1 and the like make the complete depletion of the P-type diffusion layer 3 more likely. The mechanism of failure of the semiconductor device 10 due to the complete depletion of the P-type diffusion layer 3 is as follows. Since the charge carrier concentration in the N - If the -type substrate 1 is high, the depletion layer extends from the boundary between the N - -type substrate 1 and the P-type diffusion layer 3 extend towards the P-type diffusion layer 3, to the anode layer 4. The anode layer is completely depleted, without the electric field in the PN junction 6, which forms the boundary between the N - The critical electric field is exceeded between the -type substrate 1 and the P-type diffusion layer 3. As a consequence, a recovery current in the depletion layer increases drastically, and then the semiconductor device 10 fails.

[0052] The dynamic avalanche occurs while V ka in the direction of the power supply voltage V cc increases after the voltage V ka from a forward voltage to a reverse voltage. A high impurity concentration in the P-type diffusion layer 3, a high current density in a one-state, a long charge carrier lifetime in the N - -Type substrate 1 and the like make the dynamic avalanche more likely to occur. The mechanism of failure of the semiconductor device 10 by the dynamic avalanche is as follows. Since the charge carrier concentration in the P-type diffusion layer 3 and the N - -Type substrate 1 is high, the electric field in the PN junction 6, which forms the boundary between the N - -Type substrate 1 and the P-type diffusion layer 3, the critical electric field, although V ka an avalanche failure occurs if the static breakdown voltage is less than or equal to the static breakdown voltage.

[0053] The overvoltage (also called snap-off) occurs while the voltage V ka via the power supply voltage V cc increases after the voltage V ka from a forward voltage to a reverse voltage. A low current density in an on-state, a short charge carrier lifetime in the N - -Type substrate 1 and the like make an overvoltage more likely. The mechanism of failure of the semiconductor device 10 due to the overvoltage is as follows. The charge carrier concentration in the N - -Type substrate 1 decreases drastically; a voltage higher than the static breakdown voltage is instantly applied between the anode electrode 4 and the cathode electrode 5; the electric field in the PN junction 6, which forms the boundary between the N - -Type substrate 1 and the P-type diffusion layer 3, exceeds the critical electric field, and then an avalanche failure occurs.

[0054] In the following, the lower limit of the thickness W of the P-type diffusion layer 3 is derived as a condition to prevent the complete depletion of the P-type diffusion layer 3 during the voltage failure. <A-3-2. Verarmung der P-Typ-Diffusionsschicht 3 in einem Erholungsbetrieb>

[0055] The impurity concentration of the P-type diffusion layer 3 is higher than the impurity concentration of the N - -Type substrate 1, and the first one is, for example, 10 4 up to 10 7 times as high as the last one. As a consequence, when the blocking voltage is statically applied to the semiconductor device 10, the depletion layer extends around the boundary of the N - -Type substrate 1 and the P-type diffusion layer 3 mainly in the direction of N - -Type substrate 1, and the extent of the depletion layer in the P-type diffusion layer 3 is negligible.

[0056] On the other hand, the way the impoverishment layer is distributed around the boundary of N differs. - -Type substrate 1 and the P-type diffusion layer 3 during recovery operation, from the case in which the blocking voltage is statically applied to the semiconductor device 10.

[0057] In the on-state of the semiconductor device 10, charge carriers flow from the P-type diffusion layer 3 and the N-type diffusion layer 2 into the N - -Type substrate 1, and a conductivity modulation occurs. In the on-state of the semiconductor device 10, a charge carrier concentration of N - -Type substrate 1 higher than the impurity concentration of N - -Type substrate 1 and the first one is 10 2 up to 10 5 times as high as the last one. Immediately after switching the semiconductor device 10, that is, immediately after the voltage applied to the semiconductor device 10 is changed from a forward direction to a reverse direction, the charge carrier concentration of N remains - -Type substrate 1 high, and the charge carrier concentration of N - The charge carrier concentration of the N-type substrate 1 and the charge carrier concentration of the P-type diffusion layer 3 are relatively close together. As a consequence, during recovery operation after switching on the semiconductor device 10, the depletion layer extends around the boundary between the N-type substrate 1 and the P-type diffusion layer 3. - -Type substrate 1 and the P-type diffusion layer 3 both in the direction of the N - -Type substrate 1 as well as in the direction of the P-type diffusion layer 3.

[0058] When the current is high in the on state, because the charge carrier concentration of the N - When the impurity concentration of the N-type substrate 1 is high during recovery operation, the extent of the depletion layer in the P-type diffusion layer 3 is large. When the impurity concentration of the P-type diffusion layer 3 is low, the extent of the depletion layer in the P-type diffusion layer 3 is large. For the purpose of increasing the switching speed of the semiconductor device 10, there are cases in which the impurity concentration of the P-type diffusion layer 3 is set as low as, for example, the charge carrier concentration of the N-type substrate 1. - -Type substrate 1 in the one state. In such cases, the depletion layer spreads easily into the P-type diffusion layer 3. <A-3-3. Zeit zu der die Verarmungsschicht in der P-Typ-Diffusionsschicht 3 in einem Erholungsbetrieb am größten ist>

[0059] In a recreational facility, if the voltage V ka The depletion layer is large when the current between anode electrode 4 and cathode electrode 5 is high. If the reverse current is high during recovery operation, the electric charge density in the N - -Type substrate 1 is high, therefore the depletion layer in the P-type diffusion layer 3 is large.

[0060] Therefore, if the voltage V ka and the reverse current is almost at its highest during recovery operation, the depletion layer in the P-type diffusion layer 3 is at its largest, and the semiconductor device 10 is more likely to fail due to the depletion of the P-type diffusion layer 3.

[0061] Fig. 10, Fig. 11 to Fig. Figure 12 shows the time dependence of the voltage V ka and the current I during the recovery operation of the semiconductor devices 10 with different configurations in the in<A. Ausführungsform 1 > described scope. In Fig. 10, Fig. 11 to Fig. 12. The current I is defined such that it is positive if the current is a forward current.

[0062] As in Fig. 10, Fig. 11 to Fig. As shown in Figure 12, after switching for a time t = 1 µs, the absolute value of the current I assumes an almost maximum value around the time t1, at which V ka equal to the power supply voltage V cc This is approximately assumed to mean that the depletion layer in the anode layer is largest when V ka equal to the power supply voltage V cc is. <A-3-4. Analyse des strukturellen Faktors der Verarmung der P-Typ-Diffusionsschicht 3>

[0063] Based on the preceding analysis, the following analysis examines how the depletion layer in the P-type diffusion layer 3 depends on the configuration of the semiconductor device 10. Based on the analysis in <A-3-3. Zeit zu der die Verarmungsschicht in der P-Typ-Diffusionsschicht 3 in einem Erholungsbetrieb am größten ist> A width W will be A the depletion layer in the P-type diffusion layer 3 in a state (hereinafter referred to as state S) in which the blocking voltage, which is equal to V cc is considered during a recreational operation at the PN transition section 6.

[0064] Fig. Figure 13 shows the electric field distribution around the PN junction 6, which forms the boundary between the N - The -type substrate 1 and the P-type diffusion layer 3 are in state S. For analysis, the PN junction 6 is modeled as an abrupt PN junction, that is, as a stepwise electric field strength distribution around the PN junction 6. Based on the Poisson equation, the voltage V applied to the PN junction 6 satisfies cc in state S, the mean impurity concentration N A in the P-type diffusion layer 3, the width W A the depletion layer in the P-type diffusion layer 3 in state S, the electric charge density N' D in the impoverishment layer in the N - -Type substrate 1 in state S and width W DD the impoverishment layer in the N - -Type substrate 1 in state S the ratios shown in Formula 1 and Formula 2. Vcc=12qNAεsε0WA2+12qN'Dεsε0WDD2 qNAεsε0WA=qN'Dεsε0WDD

[0065] Here, q is the elementary charge, ε s is the relative permittivity of the semiconductor material of the P-type diffusion layer 3 and the N - -Type substrate 1, and ε0 is the vacuum permittivity. N A is the mean defect concentration of the P-type diffusion layer 3. For the purpose of approximate modeling, an unevenness of the P-type defect concentration of the P-type diffusion layer 3 with respect to its position in the thickness direction is neglected, and the mean defect concentration N is defined. A we used.

[0066] Formula 2 leads to Formula 1, and then to Formula 3. Vcc=12qNAεsε0WA2+12qN'Dεsε0(NAWAN'D)2

[0067] Formula 3 determines the width W A the depletion layer in the P-type diffusion layer 3 in state S as formula 6 obtained by formula 4 and formula 5. Vcc=12qNAεsε0WA2+12qNA2εsε0N'DWA2 2εsε0VccqNA=WA2+NAN'DWA2 WA=2εsε0VccqNA(1+NAN'D)

[0068] To prevent complete depletion of the P-type diffusion layer 3, it is necessary that the thickness W of the P-type diffusion layer 3 is greater than the width W. A of the depletion layer in the P-type diffusion layer 3. Thus, the thickness W of the P-type diffusion layer 3 preferably satisfies the condition of formula 7. W>WA=2εsε0VccqNA(1+NAN'D)

[0069] In the following, the condition of formula 7 is transformed into a form that does not include the electric charge density N'. D in the impoverishment layer in the N - -Type substrate 1 in state S.

[0070] For this purpose, the ratio between an average charge carrier concentration n is first determined. Avg in the N - -Type substrate 1 in on-states before switching, a current density J in on-states before switching and a lifetime τ of the charge carrier whose conductivity type is the same as the P-type diffusion layer 3 (namely the P-type charge carrier) in which N - -Type substrate 1, and the thickness W N- of the N - -Type substrate 1 considered.

[0071] Fig. 14, Fig. 15 to Fig. 16 represent charge carrier concentrations in the N - -Type substrate 1 in on-states and recovery states of the semiconductor device 10. In the on-states, since the electron concentration and hole concentration are almost equal, both the electron concentration and the hole concentration are shown as charge carrier concentrations by the same line in the figures.

[0072] Fig. Figure 14 shows data in the case where the current density is low in the on-state (lines 14a, 14b and 14c in Figure 14). Fig. 14), and in the case where the current density in the on-state is high (lines 14d, 14e and 14f in Fig. 14).

[0073] Fig. Figure 15 shows data in the case where the charge carrier lifetime of the P-type charge carriers in the N - -Type substrate 1 is short (lines 15a, 15b and 15c in Fig. 15), and in the case where the charge carrier lifetime of the P-type charge carriers in the N - -Type substrate 1 is long (lines 15d, 15e and 15f in Fig. 15).

[0074] Fig. 16 shows data in the case where N - -Type substrate 1 is thick (lines 16a, 16b and 16c in Fig. 16), and in the case where the N - -Type substrate 1 is thin (lines 16d, 16e and 16f in Fig. 16).

[0075] In Fig. 14, Fig. 15 to Fig. Lines 14a, 15a, 16a, 14d, 15d and 16d represent the charge carrier concentrations in the on states.

[0076] In Fig. 14, Fig. 15 to Fig. 16 represent lines 14b, 15b, 16b, 14e, 15e and 16e hole concentrations during recovery states.

[0077] In Fig. 14, Fig. 15 to Fig. Lines 14c, 15c, 16c, 14f, 15f and 16f represent the hole concentrations during the recovery states.

[0078] In Fig. 14, Fig. 15 to Fig. 16 represents the horizontal axis X positions in the thickness direction of the N - -Type substrate 1. In Fig. 14 and Fig. 15 represents X = X0 the boundary between N - -type substrate 1 and the P-type diffusion layer 3, and X = X1 represents the boundary between the N - -Type substrate 1 and the N-type diffusion layer 2. In Fig. 16 represents X = X0 the boundary between N - -type substrate 1 and the P-type diffusion layer 3, and X = X1 represents the boundary between the N - -Type substrate 1 and the N-type diffusion layer 2 in the case where the N - -Type substrate 1 is thick.

[0079] In Fig. 14, Fig. 15 to Fig. 16 are all data of the recovery states data at the moment when the voltage V ka between the anode electrode 4 and the cathode electrode 5 assume the same specific value in the recovery state.

[0080] From Fig. 14, Fig. 15 to Fig. 16 The following relationships (a), (b) and (c) are derived. (a) The higher the current density J in the on state, the higher the charge carrier concentration in the N - -Type substrate 1 in the one state. (b) The longer the charge carrier lifetime τ of the P-type charge carrier in the N - The more type 1 substrate it is, the higher the charge carrier concentration in the N - -Type substrate 1 in the one state. (c) The thinner the thickness W N- of the N - The larger the substrate type (type 1), the higher the charge carrier concentration in the N - -Type substrate 1 in the one state.

[0081] Therefore, the average charge carrier concentration n Avg in the N - -Type substrate 1 in the on-state approximately by using the current density J in the on-state, the charge carrier lifetime τ of the P-type charge carrier in the N - -Type substrate 1 and thickness W N- of the N - -Type substrate 1 is represented. The following ratio in formula 8 is known (see e.g. Baliga, B. Jayant, “Fundamentals of Power Semiconductor Devices”, p. 212, Springer, 2008). nAvg=Jτ2qWN−

[0082] Next, we derive the relationship between the electric charge density N' D in the impoverishment layer of N - -Type substrate 1 in state S and the mean landing carrier concentration n Avg in the N - -Type substrate 1 in the on state. The electric charge density N' D in the impoverishment layer in the N - -Type substrate 1 in state S can be represented as a sum of four elements, as shown in formula 9. N'D=p−n+ND−R

[0083] Here, p is the hole concentration in the N - -Type substrate 1 in state S, n is the electron concentration in the N - -Type substrate 1 in state S and N D is the concentration of N at the faults - -Type substrate 1. R represents a contribution of electrons and holes to the electric charge density, which is found in low levels in the N - -Type substrate 1 is trapped in state S. R is obtained by subtracting the concentration of holes trapped in the low levels from the concentration of electrons trapped in the low levels. Upon reunification in the low levels, an electron and a hole combine. However, during the reunification process, the number of electrons and holes trapped in the low levels is different; thus, the electrons and holes trapped in the low levels contribute to an overall electric charge.

[0084] From Fig. 14, Fig. 15 to Fig. 16. It can be seen that p >> N D and p > n. Thus, formula 9 leads to formula 10. N'D≈p−n−R

[0085] From Fig. 14, Fig. 15 to Fig. 16. It can be seen that, the higher the mean charge carrier concentration n Avg in the N - The more type 1 substrate it is, the higher the charge carrier concentration in the depletion layer of the N - -Type substrate 1 is in state S. From Fig. 14, Fig. 15 to Fig. 16. It can also be seen that the charge carrier concentration in the depletion layer of N - -Type substrate 1 in state S of the mean charge carrier concentration n Avg in the N - -Type substrate 1 in the one state depends.

[0086] The contribution R of electrons and holes, which are in low levels in the N - -Type substrate 1, the electrical charge density depends on the charge carrier lifetime τ of the hole in the N - -Type substrate 1. Thus, the ratio between N' D and n Avg approximately represented as Formula 11. N'D=α(τ)nAvg

[0087] Here, α(τ) is a factor in a proportionality that is empirically obtained. From fitting it to simulation results, we obtain formula 12. α(τ)=4.15(In(2.58τ+1))4.77+225

[0088] On the right side of formula 12, τ represents the value when τ is represented in the unit of µs. Fig. Figure 17 shows α(τ) obtained through the simulations and formula 12 obtained by fitting. Fig. Figure 17 shows the α(τ) obtained from the simulations, represented by open triangles, and formula 12 is shown by a solid line. Differences between formula 12 and the α(τ) obtained from the simulations are within 5%. Fig. 17 also shows N' D and n Avg , which are obtained through simulations.

[0089] By using formula 8 and formula 12, formula 7 leads to formulas 13 to 15. W>2εsε0VccqNA(1+NAα(τ)nAvg) W>2εsε0VccqNA(1+NAα(τ)Jτ2qWN−) W>2εsε0VccqNA(1+2qWN−NAα(τ)nAvg)

[0090] The average concentration of defects N A in the P-type diffusion layer 3, the dosage amount D A and the thickness W of the P-type diffusion layer 3 fulfills the ratio of formula 16. NA=DAWD

[0091] Therefore, Formula 15 is rewritten as Formulas 17 to 20 using Formula 16. W>2εsε0VccqDAW(1+2qWN−DAα(τ)JτW) W2>2εsε0VccqDAW(1+2qWN−DAα(τ)JτW) W21W(1+2qWN−DAα(τ)JτW)>2εsε0VccqDA W+2qWN−DAα(τ)Jτ>2εsε0VccqDA

[0092] Based on the foregoing argument, it is desirable that the thickness W of the P-type diffusion layer 3 fulfills the ratio of formula 20 in order to prevent the complete depletion of the P-type diffusion layer 3 during recovery operation.

[0093] After switching, V ka temporarily higher than the power supply voltage V cc , such as in Fig. 10, Fig. 11 to Fig. 12 shown. Thus V ka If a nominal voltage is not exceeded, the power supply voltage V cc , when the semiconductor device 10 is used, is set so that it is lower than the nominal voltage V r . Fig. Figure 18 shows a representative value of the power supply voltage V cc , which is for each of the nominal voltages V r the semiconductor device 10 is assumed. For example, in the case where the thickness W of the P-type diffusion layer 3 satisfies the condition that is obtained by substituting 0.8 times the nominal voltage V r for the power supply voltage V cc as obtained in formula 20, the complete depletion of the P-type diffusion layer 3 during the recovery operation of the semiconductor device 10 is prevented when the in Fig. 18 shown power supply voltage V cc is used. In the case where the thickness W of the P-type diffusion layer 3 fulfills the condition determined by substituting 0.9 times the nominal voltage V r for the power supply voltage V cc as obtained in formula 20, the complete depletion of the P-type diffusion layer 3 during the recovery operation of the semiconductor device 10 is further prevented.

[0094] A nominal current density J r can be used as the current density J in the on-state. Since complete depletion of the P-type diffusion layer 3 occurs when the current in the on-state is high just before switching, a case can be considered in which the current density J in the on-state just before switching is higher than the nominal current density Jr to ensure design flexibility. A representative value of the current density J, which is assumed to be a high current density in the on-state just before switching, is, for example, 2.5 times the nominal current density J. r .

[0095] Fig. Figure 19 shows the nominal current density J r , which is an assumed representative value, and 2.5 times the nominal current density J r , which is the representative value of the current density, which is assumed to be a high current density in the on-state just before switching, for each of the nominal voltages V r of the semiconductor devices 10.

[0096] By assuming 2.5 times the nominal current density J r Assuming a current density J in the on-state immediately before switching, the complete depletion of the P-type diffusion layer 3 is suppressed in the case where a large current flows in the on-state immediately before switching. By assuming 3 times the nominal current density J r As the current density J in the on-state just before switching decreases, the complete depletion of the P-type diffusion layer 3 is further suppressed.

[0097] In the case where the power supply voltage V cc as 0.8 times the nominal voltage V r It is assumed that the current density J in the on-state immediately before switching is 2.5 times the nominal current density J. r Assuming the thickness W of the P-type diffusion layer fulfills 3 W>1.6εsε0VrqDA−2qWN−DA2.5α(τ)Jrτ

[0098] This prevents the complete depletion of the P-type diffusion layer 3 during the recovery operation of a high current and high voltage in the semiconductor device 10.

[0099] In the case where the power supply voltage V cc as 0.9 times the nominal voltage V r It is assumed that the current density J in the on-state immediately before switching is 2.5 times the nominal current density J. r Assuming the thickness W of the P-type diffusion layer fulfills 3 W>1.8εsε0VrqDA−2qWN−DA2.5α(τ)Jrτ

[0100] In the case where the power supply voltage V cc as 0.8 times the nominal voltage V r It is assumed that the current density J in the on-state immediately before switching is 3 times the nominal current density J. r Assuming the thickness W of the P-type diffusion layer fulfills 3 W>1.6εsε0VrqDA−2qWN−DA3α(τ)Jrτ

[0101] In the case where the power supply voltage V cc as 0.9 times the nominal voltage V r It is assumed that the current density J in the on-state immediately before switching is 3 times the nominal current density J. r Assuming the thickness W of the P-type diffusion layer fulfills 3 W>1.8εsε0VrqDA−2qWN−DA3α(τ)Jrτ

[0102] The problem of complete depletion of the P-type diffusion layer 3 during the recovery operation of a high current and high voltage is more likely to occur in semiconductor devices for a high-speed application (e.g., for electric trains) than in semiconductor devices for a low-speed application (e.g., for an electrical power system). In the semiconductor device 10, which has the configuration described in the current embodiment, even if it is for a high-speed application, the complete depletion of the P-type diffusion layer 3 during the recovery operation of a high current and high voltage can be prevented, and failure of the semiconductor device 10 due to complete depletion of the P-type diffusion layer 3 is prevented.

[0103] The nominal current density J r The nominal current density J is obtained by dividing the nominal current of the semiconductor device 10 by the area of ​​the active region, that is, the region where the current flows in a top view. In the case where the semiconductor device 10 is combined with a transistor, as in the case of an RC-IGBT, the nominal current density J r by dividing the rated forward current of the diode by the area of ​​the active region of the diode, which represents the N - -Type substrate 1, comprising the N-type diffusion layer 2 and the P-type diffusion layer 3, are obtained.

[0104] Fig. 20 shows a representative value of the thickness W N- of the N - -Type substrate 1 for each of the nominal voltages of the semiconductor devices 10.

[0105] For the purpose of reducing the switching loss of the semiconductor device 10, it is desirable that the maximum value of the impurity concentration of the P-type diffusion layer 3 be less than or equal to 1.0E17 cm -3 is. Accordingly, it is desirable that the dosage amount D A the P-type diffusion layer 3 is determined such that the maximum value of the impurity concentration of the P-type diffusion layer 3 is less than or equal to 1.0E17 cm -3 is.

[0106] In the derivations of formulas 21 to 24, it is assumed that the P-type defect concentration in the P-type diffusion layer 3 is constant with respect to the thickness direction. Accordingly, it is desirable that the defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction does not deviate too much from this assumption. That is, it is desirable that the minimum value of the P-type defect concentration in the P-type diffusion layer 3b is greater than or equal to 1 / 10 times the maximum value of the defect concentration in the P-type diffusion layer 3a and is greater than or equal to 1 / 10 times the maximum value of the defect concentration in the P-type diffusion layer 3c. The same applies if the defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction has more than two maximum values.That is, in the region of the P-type diffusion layer 3, which lies between the maximum value closest to the first main surface 100a and the maximum value closest to the second main surface 100b among the maximum values ​​of the impurity concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction, it is desirable that the minimum value of the impurity concentration of the region is greater than 1 / 10 times the maximum value of the impurity concentration distribution in the P-type diffusion layer 3 with respect to the thickness direction. <A-4. Fertigungsverfahren>

[0107] Fig. Figure 23 is a flowchart showing a manufacturing process for the semiconductor device 10.

[0108] Fig. 7 and Fig. Figure 8 shows a state in a process of manufacturing the semiconductor device 10.

[0109] First, in step S1, the N - -Type substrate 1 prepared.

[0110] Next, in step S2, a first ion implantation will be performed into the surface layer of the side of the first main surface 100a of the N. - -Type substrate 1 executed (see Fig. 7) As a result, a faulty area 30 is found in the N - -Type substrate 1 is formed. The ions that enter the N in step S2 - Examples of substrates that can be implanted using type 1 include boron.

[0111] Next, in step S3, a second ion implantation is performed into the surface layer of the side of the first main surface 100a of the N. - -Type substrate 1 executed (see Fig. 8) As a result, a faulty area 31 is found in the N - -Type substrate 1 is formed. In step S3, ions are implanted into the area, which is shallower than the area where the ions are implanted in step S2. The ions that are implanted into the N in step S3 - Examples of substrates that can be implanted using type 1 include boron.

[0112] Next, in step S4, the disruption sites implanted in steps S2 and S3 are activated. As a result, the P-type diffusion layer 3 is formed (see Fig. 1).

[0113] Next, in step S5, an anode electrode 4 is formed.

[0114] Next, in step S6, an N-type diffusion layer 2 is formed by ion implantation and heat treatment.

[0115] Next, in step S7, a cathode electrode 5 is formed.

[0116] The processes described above will result in the Fig. 1 Semiconductor device 10 shown.

[0117] In the manufacturing process of the semiconductor device of the present embodiment, it is decided that the thickness W of the P-type diffusion layer 3 satisfies formula 21. In step S2 and step S3, for example, the depth of ion implantation can be adjusted by setting the energy of the ion beam, and the thickness W of the P-type diffusion layer 3 can be adjusted.

[0118] By adjusting the amount of ions implanted in step S2 and step S3, the defect concentration can be adjusted to the maximum value of the defect concentration distribution of the P-type diffusion layer 3.

[0119] As described above, in the manufacturing process of the semiconductor device of the present embodiment, the ratio between the average charge carrier concentration n Avg in the N - -Type substrate 1 in the on-state and electrical charge concentration in the depletion layer around the boundary of the N - -Type substrate 1 and the P-type diffusion layer 3 in the middle of the N - -Type substrate 1 is obtained in the recovery process, and then the thickness of the P-type diffusion layer 3 is determined based on the ratio. <B. Zweite Ausführungsform>

[0120] Fig. Figure 2 shows a semiconductor device 10b of the second embodiment.

[0121] In semiconductor device 10b, the impurity concentration of the P-type diffusion layer 3 varies depending on its position in a plane. With respect to other aspects, semiconductor device 10b is identical to semiconductor device 10 of embodiment 1.

[0122] In semiconductor device 10b, the P-type diffusion layer 3a comprises P-type diffusion layers 3a1 and P-type diffusion layers 3a2. The P-type defect concentration of P-type diffusion layers 3a1 is higher than the P-type defect concentration of P-type diffusion layers 3a2. The P-type defect concentration of P-type diffusion layers 3a2 is higher than the P-type defect concentration of P-type diffusion layer 3b. The maximum value of the defect concentration of P-type diffusion layers 3a2 is less than or equal to 1.0 × 10¹⁷ cm⁻¹. -3 .

[0123] The P-type diffusion layers 3a1 and the P-type diffusion layers 3a2, for example, are arranged alternately in one of the directions in a plane, as shown in Fig. Figure 2 shows that the P-type diffusion layers 3a1 and the P-type diffusion layers 3a2 are arranged, for example, alternately in one of the directions in the plane with a constant cycle. The P-type diffusion layers 3a1 and the P-type diffusion layers 3a2 can extend in a direction that intersects one of the directions in the plane. The P-type diffusion layers 3a1 and the P-type diffusion layers 3a2 can also be arranged alternately in the direction that intersects one of the directions in the plane.

[0124] The same applies if the defect concentration distribution of the P-type diffusion layer 3 has more than two peak values ​​with respect to the thickness direction. The defect concentration at the peak value closest to the first main surface 100a, the highest value among the peak values ​​of the defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction, varies depending on its position in the plane. For example, the P-type defect concentrations at the peak value closest to the first main surface 100a, the highest value among the peak values ​​of the defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction, are arranged alternately in one of the directions in the plane.The P-type defect concentration at the highest value closest to the first main surface 100a, the highest value among the highest values ​​of the defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction, are arranged, for example, alternating in one of the directions in the plane with a constant cycle.

[0125] The impurity concentration of the P-type diffusion layer 3a varies depending on its position in the plane; thus, the resistance of the P-type diffusion layer 3a and the anode electrode 4 is suppressed, and a flow of holes from the P-type diffusion layer 3 into the N - -Type substrate 1 is suppressed. The switching loss can be reduced by suppressing the flow of holes into the N - -Type substrate 1 will be reduced.

[0126] As above in <vergleichsbeispiel>It is explained that if the impurity concentration of the P-type diffusion layer 3z1 of the semiconductor device 10z1 or the impurity concentration of the P-type diffusion layer 3z2 of the semiconductor device 10z2 varies depending on the position in the plane, a complete depletion of the P-type diffusion layer 3z1 or the P-type diffusion layer 3z2 can occur at the position where the impurity concentration is low, and the semiconductor devices can fail.In the present embodiment, the complete depletion of the P-type diffusion layer 3 during the recovery operation of a high current and a high voltage is prevented, and the failure of the semiconductor device due to complete depletion is prevented because the P-type defect concentration of the P-type diffusion layer 3 has a plurality of peak values ​​with respect to the thickness direction, and the defect concentration at the peak value closest to the main surface 100a varies depending on the direction in the plane.

[0127] The P-type defect concentration distribution of the P-type diffusion layer 3 with respect to the thickness direction exhibits a plurality of peak values; thus, the gradient of the defect concentration in the P-type diffusion layer 3 in the plane in the part of the P-type diffusion layer 3a on the side of the N - -Type substrate 1 is attenuated, and the failure of the semiconductor device 10b by the dynamic avalanche is prevented.

[0128] Although the revelation has been shown and described in detail, the foregoing description is descriptive in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be devised.< / vergleichsbeispiel> < / vergleichsbeispiel>

Claims

[1] Semiconductor device (10, 10b), comprising: a semiconductor base body (100) having a first main surface (100a) and a second main surface (100b); a first electrode (4); and a second electrode (5), wherein the semiconductor base body (100) comprises: a first semiconductor layer (2) of a first conductivity type, which is arranged on the side of the second main surface (100b) of the semiconductor base body (100); a second semiconductor layer (1) of the first conductivity type, which has a concentration of impurities of the first conductivity type that is lower than that of the first semiconductor layer (2) and is located closer to the first main surface (100a) than the first semiconductor layer (2); and a third semiconductor layer (3) of a second conductivity type, which is located closer to the first main surface (100a) than the second semiconductor layer (1), wherein the first semiconductor layer (2) is electrically connected to the second electrode (5) in the second main surface (100b), wherein the third semiconductor layer (3) is electrically connected to the first electrode (4) in the first main surface (100a), wherein a defect concentration distribution of the third semiconductor layer (3) with respect to a thickness direction of the semiconductor base body (100) exhibits a plurality of peak values, wherein a thickness W of the third semiconductor layer (3), a thickness W N- the second semiconductor layer (1), the elementary charge q, a relative permittivity ε s of the semiconductor material of the semiconductor base body (100), the vacuum permittivity ε0, a nominal voltage V r , a nominal current density J r , a charge carrier lifetime τ of a charge carrier of the second conductivity type in the second semiconductor layer (1), a dosage amount D A the third semiconductor layer (3), a mean charge carrier concentration n Avg , an electric charge density N' D , and α(τ), which is given below as Formula 2 and which represents a ratio between an average charge carrier concentration of the second semiconductor layer (1) in a one-state of the semiconductor device (10, 10b) and an electrical charge concentration in a depletion layer around a boundary of the second semiconductor layer (1) and the third semiconductor layer (3) in the middle of the second semiconductor layer (1) during a recovery process of the semiconductor device (10, 10b), where α(τ) is a factor of proportionality and is represented by the following Formula 1, N'D=α(τ)nAvg fulfill the following formula 3: α(τ)=4.15(In(2.58τ+1))4.77+225 W>1.6εsε0VrqDA−2qWN−DA2.5α(τ)Jrτ [2] Semiconductor device (10, 10b) according to claim 1, wherein the thickness W of the third semiconductor layer (3), the thickness W N- the second semiconductor layer (1), the elementary charge q, the relative permittivity ε s of the semiconductor material, the vacuum permittivity ε0, the nominal voltages V r , the nominal current density J r , the charge carrier lifetime τ of the charge carrier of the second conductivity type in the second semiconductor layer (1), the dosage amount D A the third semiconductor layer (3), and the α(τ) The following formula 4 must be fulfilled. W>1.8εsε0VrqDA−2qWN−DA2.5α(τ)Jrτ [3] Semiconductor device (10, 10b) according to claim 1, wherein the thickness W of the third semiconductor layer (3), the thickness W N- the second semiconductor layer (1), the elementary charge q, the relative permittivity ε s of the semiconductor material, the vacuum permittivity ε0, the nominal voltages V r , the nominal current density J r , the charge carrier lifetime τ of the charge carrier of the second conductivity type in the second semiconductor layer (1), the dosage amount D A the third semiconductor layer (3), and the α(τ) The following formula 5 must be fulfilled. W>1.6εsε0VrqDA−2qWN−DA3α(τ)Jrτ [4] Semiconductor device (10, 10b) according to any one of claims 1 to 3, wherein the thickness W of the third semiconductor layer (3), the thickness W N- the second semiconductor layer (1), the elementary charge q, the relative permittivity ε s of the semiconductor material, the vacuum permittivity ε0, the nominal voltages V r , the nominal current density J r , the charge carrier lifetime τ of the charge carrier of the second conductivity type in the second semiconductor layer (1), the dosage amount D A the third semiconductor layer (3), and the α(τ) The following formula 6 must be fulfilled. W>1.8εsε0VrqDA−2qWN−DA3α(τ)Jrτ [5] Semiconductor device (10, 10b) according to any one of claims 1 to 4, wherein a minimum value of a concentration of defects of the second conductivity type in a region of the third semiconductor layer (3) between a maximum value nearest to the first main surface (100a) of the plurality of maximum values ​​of the defect concentration distribution and a maximum value nearest to the second main surface (100b) of the plurality of maximum values ​​of the defect concentration distribution is higher than a concentration of defects of the first conductivity type of the second semiconductor layer (1). [6] Semiconductor device (10, 10b) according to any one of claims 1 to 5, wherein a maximum value of the defect concentration distribution of the third semiconductor layer (3) is less than or equal to 1.0E17 cm -3 is. [7] Semiconductor device (10, 10b) according to any one of claims 1 to 6, wherein a maximum value of the defect concentration distribution of the third semiconductor layer (3) is less than or equal to 2.5E16 cm -3 is. [8] Semiconductor device (10, 10b) according to any one of claims 1 to 7, wherein a minimum value of a concentration of impurities of the second conductivity type in a region of the third semiconductor layer (3) between a maximum value closest to the first main surface (100a) of the plurality of maximum values ​​of the impurity concentration distribution and a maximum value closest to the second main surface (100b) of the plurality of maximum values ​​of the impurity concentration distribution is greater than or equal to 1 / 10 times a maximum value of the impurity concentration distribution of the third semiconductor layer (3). [9] Semiconductor device (10, 10b) according to any one of claims 1 to 8, wherein the impurity concentration in the third semiconductor layer (3) is highest at a maximum value closest to the second main surface (100b) of the plurality of maximum values ​​of the impurity concentration distribution of the third semiconductor layer (3). [10] Semiconductor device (10b) according to any one of claims 1 to 9, wherein in the third semiconductor layer (3) an impurity concentration varies in a maximum value at the nearest to the first main surface (100a) of the plurality of maximum values ​​of the impurity concentration distribution depending on a position in a plane. [11] Semiconductor device (10b) according to claim 10, wherein in the third semiconductor layer (3) in the maximum value closest to the first main surface (100a) the plurality of maximum values ​​of the defect concentration distribution areas with relatively high defect concentration and areas with relatively low defect concentration are arranged alternately in one of directions in a plane. [12] Method of manufacturing a semiconductor device comprising: Providing a semiconductor base body (100) having a first principal surface (100a) and a second principal surface (100b); Arranging a first electrode (4); and Arranging a second electrode (5), wherein the semiconductor base body (100) comprises: a first semiconductor layer (2) of a first conductivity type, which is arranged on the side of the second main surface (100b) of the semiconductor base body (100); a second semiconductor layer (1) of the first conductivity type, which has a first conductivity type impurity concentration that is lower than that of the first semiconductor layer (2) and is located closer to the first main surface (100a) than the first semiconductor layer (2); and a third semiconductor layer (3) of a second conductivity type, which is located closer to the first main surface (100a) than the second semiconductor layer (1), wherein the first semiconductor layer (2) is electrically connected to the second electrode (5) in the second main surface (100b), wherein the third semiconductor layer (3) is electrically connected to the first electrode (4) in the first main surface (100a), wherein a defect concentration distribution of the third semiconductor layer (3) with respect to a thickness direction of the semiconductor base body (100) exhibits a plurality of peak values, wherein a thickness W of the third semiconductor layer (3), a thickness W N- the second semiconductor layer (1), the elementary charge q, a relative permittivity ε s of the semiconductor material of the semiconductor base body (100), the vacuum permittivity ε0, a nominal voltage V r , a nominal current density J r , a charge carrier lifetime τ of a charge carrier of the second conductivity type in the second semiconductor layer (1), a dosage amount D A the third semiconductor layer (3), a mean charge carrier concentration n Avg , an electric charge density N' D , and α(τ), which is given below as Formula 2 and which represents a ratio between an average charge carrier concentration of the second semiconductor layer (1) in a one-state of the semiconductor device (10, 10b) and an electrical charge concentration in a depletion layer around a boundary of the second semiconductor layer (1) and the third semiconductor layer (3) in the middle of the second semiconductor layer (1) during a recovery process of the semiconductor device (10, 10b), where α(τ) is a factor of proportionality and is represented by the following Formula 1, N'D=α(τ)nAvg fulfill the following formula 3: α(τ)=4.15(In(2.58τ+1))4.77+225 W>1.6εsε0VrqDA−2qWN−DA2.5α(τ)Jrτ

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