Isolated temperature sensor package with embedded spacer in dielectric opening, method and system

Abstract

Electronic device (100) comprising the following: a substrate (101) with a dielectric layer (106), a die pad (107), a first lead (109), a second lead (110), a conductive via (112) and a conductor track (114), wherein the dielectric layer (106) has a side (118) and an opening (108) extending into the side, the die pad (107) is coupled to the first lead (109), the second lead (110) is coupled to the conductive via (112), the conductor track (114) is coupled to the conductive via (112) and the conductor track (114) extends on the side (118) of the dielectric layer (106); a dielectric spacer (104) above the die pad (107) in the opening (108); a semiconductor die (102) above the dielectric spacer (104), wherein the semiconductor die (102) includes a temperature sensor; an electrical connection (116) that couples the semiconductor die (102) to the conductor track (114); and a package structure (120) extending on one side of the dielectric layer (106), on the semiconductor die (102) and on the conductor track (114), wherein the package structure (120) extends around the dielectric spacer (104) and to the die pad (107) in the opening (108).

Description

BACKGROUND

[0001] Electronic temperature sensors can be used in high-voltage systems where the temperature to be measured is located in or near a high-voltage circuit. Excessive electric fields can damage a semiconductor-based electronic temperature sensor or contribute to its loss of quality. US Patent 2011 / 140211 A1 discloses several flow sensor structures, wherein at least one flow sensor structure is designed to seal the surface of an electrical control circuit and a portion of a semiconductor device using a manufacturing process that can prevent the formation of burrs or chip cracks when clamping the semiconductor device using a mold. SUMMARY

[0002] The invention relates to an electronic device, a method, and a system. In one aspect, the electronic device comprises a substrate, a dielectric spacer, a semiconductor die, and a package structure. The substrate has a dielectric layer, a die pad, first and second leads, a conductive via, and a conductor track. The dielectric layer has an opening extending into one side. The die pad is coupled to the first lead, the second lead is coupled to the conductive via, and the conductor track is coupled to the via. The dielectric spacer is mounted above the die pad in the opening, and the semiconductor die is mounted above the dielectric spacer. The semiconductor die includes a temperature sensor, and an electrical connection couples the semiconductor die to the conductor track.The package structure extends on one side of the dielectric layer, on the semiconductor die and on the conductor track, with the package structure extending around the dielectric spacer and to the die pad in the opening.

[0003] In another aspect, the process involves mounting a dielectric spacer over a die pad in an opening in a dielectric layer of a substrate, mounting a semiconductor die over the dielectric spacer, forming an electrical connection that couples the semiconductor die to a conductor track on one side of the dielectric layer of the substrate, and performing a forming process to create a package structure that extends on the side of the dielectric layer, on the semiconductor die, and on the conductor track, with the package structure extending around the dielectric spacer and to the die pad in the opening.

[0004] In another aspect, the system comprises a printed circuit board (PCB) and an electronic device. The PCB has a PCB trace. The electronic device is mounted on the PCB and comprises a substrate, a dielectric spacer, a semiconductor die, and a package structure. The substrate has a dielectric layer, a die pad, first and second leads, a conductive via, and a conductor. The dielectric layer has an opening extending to one side. The die pad is thermally coupled to the PCB trace and to the first lead. The second lead is coupled to the conductive via, and the conductor is coupled to the via.The dielectric spacer is mounted above the die pad in the aperture, and the semiconductor die is mounted above the dielectric spacer. The semiconductor die includes a temperature sensor, and an electrical connection couples the semiconductor die to the conductor track. The package structure extends on one side of the dielectric layer, onto the semiconductor die, and onto the conductor track, with the package structure extending around the dielectric spacer and to the die pad in the aperture. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a perspective view of an encapsulated electronic device with a temperature sensor die mounted on a spacer in an opening of a laminate package substrate from above. Fig. 1A is a side section elevation of the encapsulated electronic device along line 1A-1A of Fig. 1. Fig. 1B is a top view of the encapsulated electronic device of Fig. 1 from the top. Fig. Figure 2 is a flowchart of a process for manufacturing an electronic device. Fig. Figures 3-10 are side-section elevations of the encapsulated electronic device undergoing manufacturing processing according to the method of Fig. 2 is subjected to. Fig. 11, Fig. 12 and Fig. Figure 13 shows simulated load-volume-performance graphs. Fig. Figure 14 is a perspective partial view of the encapsulated electronic device of Fig. 1 on a printed circuit board for measuring the busbar conductor temperature from above. DETAILED DESCRIPTION

[0005] In all drawings, the same reference numerals refer to the same elements, and the various features are not necessarily drawn to scale. Furthermore, the term "couple" or "couples" encompasses an indirect or direct electrical or mechanical connection, or combinations thereof. For example, if a first device couples to or is coupled with a second device, this connection may be by a direct electrical connection or by an indirect electrical connection via one or more intervening devices and connections. One or more operating characteristics of various circuits, systems, and / or components are described below in the context of functions that, in some cases, result from a configuration and / or connection of various structures when a circuit arrangement is powered and operating.

[0006] With initial reference to Fig. 1-1B shows Fig. 1 an encapsulated electronic device 100 with a package substrate 101 and a temperature sensor in a semiconductor die 102, which is mounted using a first die mounting film 103 which causes the semiconductor die 102 to adhere to a dielectric spacer 104 in order to mount the semiconductor die 102 over the dielectric spacer 104. Fig. Figure 1A shows a side section view of the encapsulated electronic device 100 along line 1A-1A of Fig. 1 and Fig. Figure 1B shows a top view of the encapsulated electronic device 100. In one example, the substrate 101 is a conductor frame. In another example, the substrate 101 is a partially etched conductor frame. In another example, the substrate 101 is a pre-molded conductor frame. In yet another example, the substrate 101 is a Molded Interconnect Substrate (MIS). Fig. In 1-1B, substrate 101 is a rectangular structure with lateral ends spaced apart along a first direction (labeled “X” in the illustrated orientation), lateral sides spaced apart along an orthogonal second direction (labeled “Y”), and a top and bottom side spaced apart along a third direction (labeled “Z”) that is orthogonal to the first and second directions.

[0007] The semiconductor die 102 includes a temperature sensor. The semiconductor die 102 can be, in various implementations, a discrete semiconductor device such as a bipolar transistor, several discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or an integrated circuit with multiple semiconductor devices or electronic components. The semiconductor die 102 can include passive devices such as resistors, inductors, and filters, and / or it can include active devices such as transistors. In the illustrated example, the semiconductor die 102 includes a temperature sensor comprising one or more electronic components. The temperature sensor component or circuit is designed to detect the temperature of the die pad 107 by thermally coupling the underside of the semiconductor die 102 via the dielectric spacer 104.

[0008] In one example, the dielectric spacer 104 is aluminum oxide (e.g., Al₂O₃), aluminum nitride (AlN), or aluminum oxynitride, or comprises these materials. In other implementations, the dielectric spacer 104 is titanium oxide (TiO₂) and / or hafnium oxide (HfO₂) and / or barium titanium dioxide (BTO) and / or molybdenum disulfide (MoS₂) and / or silicon carbide (SiC), composites of these materials and glass, or comprises these materials. In one example, the dielectric spacer 104 is a good thermal conductor with a thermal conductivity greater than 10 W / mK to facilitate heat transfer from the die pad 107 to the semiconductor die 102 for temperature sensing. Furthermore, the dielectric spacer 104 is an electrical insulator to electrically isolate a low-voltage temperature sensing circuit arrangement of the semiconductor die 102 from potentially high voltages on the die pad 107 during the operation of the electronic device 100.In certain examples, the dielectric spacer 104 has a thickness along the Z-direction of 50 to 500 µm, for example 125 to 250 µm.

[0009] A second die-attachment film 105 causes the dielectric spacer 104 to adhere to a die pad 107 of the substrate 101. The dielectric spacer 104 is mounted above the die pad 100 in an opening 108 of a dielectric layer 106. Fig. In 1-1B, the opening 108 is rectangular. In other examples, the opening may have a different shape. In one example, the dielectric layer 106 is a laminate layer of the substrate 101. In another example, the dielectric layer 106 is a shaped layer of the substrate 101.

[0010] The substrate 101 has first leads 109 at one end and second leads 110 at the opposite end to allow, for example, soldering to a host circuit board (e.g. Fig. 14 below). In the example of Fig. In Figure 1-1B, substrate 101 has a solder mask 111 on its underside between leads 109 and 110 and the die pad 107. Substrate 101 also has conductive vias 112 and conductor tracks 114. The second leads 110 are coupled to the respective conductive vias 112, and the conductor tracks 114 are coupled to the respective conductive vias 112. Bond wires 116 form electrical connections between individual conductor tracks 114 and respective conductive pads of the semiconductor die 102. Another bond wire 116 is coupled between another conductive pad of the semiconductor die 102 and one of the first leads 109, as shown in Figure 1-1B. Fig. 1 and Fig. 1B shown.

[0011] The dielectric layer 106 has a top surface 118, and the opening 108 extends downward into the side 118 to the die pad 107. The die pad 107 is coupled to the first leads 109. The conductor tracks 114 extend inward on the side 118 of the dielectric layer 106 from the respective vias 112 (e.g., along the negative X direction in the illustrated orientation of the electronic device 100). In the illustrated example, the top surface of the first die mounting film 103 and the bottom surface of the semiconductor die 102 are approximately coplanar with the top surface 118 of the dielectric layer 106. In other implementations, the bottom surface of the semiconductor die 102 may be located above or below the plane of the top surface 118 of the dielectric layer 106 along the Z direction in the illustrated orientation.During operation, when energized, the temperature sensor of the semiconductor die 102 detects the temperature of the die pad 107 through thermal coupling via the dielectric spacer 104. The dielectric spacer 104 provides high-voltage isolation of the semiconductor die 102 from potentially high voltage levels of the die pad 107. One or more output signals from the semiconductor die 102 are supplied via respective bond wires 116 to the conductor track or tracks 114 on the top surface 118 of the dielectric layer 106, for example, in an isolated low-voltage circuit of a host printed circuit board (not shown), which is coupled to the second supply line or lines 110.

[0012] The electronic device 100 comprises a package structure 120, such as a molding compound material, which extends on side 118 of the dielectric layer 106, on the semiconductor die 102, and on the conductor track 114. The package structure 120 extends around the dielectric spacer 104 and to the die pad 107 in the opening 108, as shown in Fig. Figure 1A shows this arrangement. In this configuration, the dielectric spacer 104 has sufficient thickness to couple the temperature sensor of the semiconductor die 102 to a signal or surface for sensing the temperature, such as a structure soldered to the underside of the die pad 107 and / or to one or more of the first leads 109, while the semiconductor die 102 is electrically isolated from the surface or signal to be sensed. Where the sensed surface has a high voltage relative to the temperature sensor of the semiconductor die 102, the semiconductor die 102 is isolated from the electric field that may arise due to the high voltage. Input and / or output signals of the conductor tracks 114 and the associated bond wires 116 are also electrically isolated from the die pad 107 and can be used to provide control and data signals for the temperature sensor of the semiconductor die 102. Fig. Figure 14 below illustrates an example of the encapsulated electronic device 100, installed in a system for measuring the temperature of a high-voltage conductor track of a host printed circuit board.

[0013] With reference to the following Fig. 2-10 shows Fig. 2 a method 200 for manufacturing an electronic device, and Fig. Figures 3-10 show side views of the encapsulated electronic device 100, which undergoes manufacturing processing according to method 200. A package substrate is fabricated at 201 with an opening in a dielectric layer. Fig. Figure 3 shows an example in which a process 300 is carried out, which provides the substrate 101 with the opening 108 in the dielectric layer 106, the conductive die pad 107, and the leads 109 and 110 and the conductive traces 114 on the top surface 118 of the dielectric layer 106, as described above. In one example, a laminate substrate manufacturing process is used with a dielectric laminate layer 106 having the opening 108 that exposes all or part of the top surface of the die pad 107. In another example, a compression molding process is used, for example, with a molded dielectric layer 106 having the opening 108.

[0014] At 202 in Fig. 2. A thermally conductive dielectric spacer is mounted over the die pad. Fig. 4 and Fig. Figure 5 shows an example in which the thermally conductive dielectric spacer 104 is mounted over the die pad using the die-attachment film 105. A process 400 is performed to deposit or otherwise form the die-attachment film 105 on all or part of the top surface of the die pad 107 exposed in the opening 108 of the dielectric layer 106. The process 400 proceeds in Fig. 5 continued, wherein the dielectric spacer 104 is positioned or otherwise mounted on the die mounting film 105 above the die pad 107.

[0015] Procedure 200 passes through 203. Fig. 2 continues with the mounting of a semiconductor die over the dielectric spacer. Fig. 6 and Fig. Figure 7 shows an example in which a die mounting process 600 is carried out, in which the semiconductor die 102 is mounted over the dielectric spacer 104 using the die mounting film 103. Fig. Process 600 comprises forming the die attachment film 103 on the dielectric spacer 104. The die attachment process 600 proceeds as described in Fig. Figure 7 shows the semiconductor die 102 being mounted on the die mounting film 103 over the dielectric spacer 104 using an automatic placement device (not shown).

[0016] At 204 in Fig. 2 includes the process 200 forming an electrical connection that couples the semiconductor die to a conductor track on one side of the dielectric layer of the substrate 101.

[0017] Fig. Figure 8 shows an example in which a wire bonding process 800 is carried out, in which bond wires 116 are formed between the semiconductor die 102 and the conductor track 114 on the top surface 118 of the dielectric layer 106. In other implementations, a different electrical connection process is used, in which one or more electrical connections are formed that couple the semiconductor die 102 to the conductor track 114.

[0018] Method 200 also includes package forms in 205. Fig. Figure 9 shows an example in which a forming process 900 is carried out, in which the package structure 120, extending on the top surface 118 of the dielectric layer 106, on the semiconductor die 102, and on the conductor track 114, is formed. The package structure 120 extends around the dielectric spacer 104 and to the die pad 107 to fill the opening 108 by means of the forming process 900.

[0019] In one example, a solder mask is added at 206 to select sections of the underside of substrate 101. Fig. Figure 10 shows an example in which a process 1000 is performed, in which the solder mask 111 is formed on selected sections of the underside of the substrate 101 between the leads 109 and 110 and the die pad 107. In another implementation, the solder mask processing at 206 is omitted.

[0020] Method 200 also includes package separation in 208. In one example, in 208, individual encapsulated electronic devices 100 are separated from a panel array structure, for example by sawing or laser cutting along the X and Y directions, in order to achieve the above in Fig. 1-1B encapsulated electronic device 1000 to yield.

[0021] Fig. 11, Fig. 12 and Fig. Figure 13 shows load-volume-performance graphs. Fig. Figure 11 shows a graph 1100 with curves 1101 and 1102, which represent a load volume in cubic meters (m³). 3) as a function of an applied electric field E (v / µm). Curves 1101 correspond to examples of the electronic device 100 in a system where the first leads 109 are coupled to a high-voltage node and the second leads 110 are coupled to a low-voltage circuit arrangement. Curves 1102 show the load volume for, for example, electronic land-grid array (LGA) and small-outline integrated circuit (SOIC) temperature sensor devices. For comparison, the illustrated curves show a load volume power in the device structure for 2 v / µm using a potential difference between the high- and low-voltage nodes of 4 kVrms. In this example, the packages exhibit some electric field leakage at 4 kvrms, and the lateral conductor finger-to-high-side pad distance Δx can be seen increasing along arrow 1103.The electronic device 100 exhibits a lower generation of stress volume with increasing distance Δx between conductor finger (e.g., conductor tracks 114) and pad (e.g., die pad 107), as shown by curves 1101. The proposed design generates less electrical current than existing devices below 3 V / µm. The proposed design can be improved with a multilayer substrate approach by implementing shielding layers.

[0022] A graph 1200 in Fig. Figure 12 shows a load volume rate (e.g., dsv / dE) with electric field spectrum including curves 1201 and 1202, which represent a load volume rate in m 4 / v as a function of an applied electric field E (v / µm). Curves 1201 correspond to examples of the electronic device 100 in a system where the first leads 109 are coupled to a high-voltage node and the second leads 110 are coupled to a low-voltage circuit arrangement. Curves 1202 show the load volume for, for example, LGA and SOIC devices. In this example, peak load volume rates occur at low load values, and it can be seen that the lateral conductor finger-to-high-side pad distance Δx increases along arrow 1203.

[0023] Fig. Figure 13 shows a graph 1300 of the load volume as a function of the lateral conductor finger-to-high-side-pad distance Δx in mm for the encapsulated electronic device 100 including a curve 1301 showing the load volume at an electric field strength of 2 v / µm, a curve 1302 showing the load volume at an electric field strength of 3 v / µm, a curve 1303 showing the load volume at an electric field strength of 4 v / µm, a curve 1304 showing the load volume at an electric field strength of 5 v / µm and a line 1305 showing the load volume of an LGA device.

[0024] Fig.Figure 14 shows a partial top view of a high-voltage system 1400 with the encapsulated electronic device 100 mounted on a printed circuit board 1402. In this example, the die pad 107 is thermally coupled to the printed circuit board trace 1404, for example, by direct contact or soldering. The temperature sensor of the semiconductor die 102 detects the temperature of the high-voltage busbar printed circuit board trace 1404. In this example, each of the second supply lines 110 is connected to a low-voltage circuit arrangement via printed circuit board traces 1405, 1406, and 1407. The dielectric spacer 104 thermally couples the semiconductor die 102 to the printed circuit board trace 1404 and provides electrical isolation between the high voltages of the printed circuit board trace 1404 and the low voltage circuit arrangement of the semiconductor die 102 and the circuits coupled to the printed circuit board traces 1405, 1406 and 1407.

[0025] The described examples provide solutions for high-voltage temperature sensing systems and devices, mitigating electric field stray outside the package by utilizing a variety of different package dielectric types, such as laminated or molded dielectric layers for isolated temperature sensors, with a dielectric spacer embedded in the substrate within an opening of the dielectric layer. The dielectric spacer exhibits high thermal conductivity to allow heat transfer to the semiconductor die, and the described arrangements can be implemented in molded or laminate-based substrates, thin-profile package substrates, and other types and shapes of package substrates with a dielectric spacer embedded in the laminate substrate within an opening of a dielectric layer.The arrangements of the described examples allow the locations of the low-voltage conductor tracks (e.g., finger 114) to have low electric fields outside the package, and the described examples exhibit levels of external electric fields that are as good as or better than existing simple insulation devices.

Claims

[1] Electronic device (100) comprising: a substrate (101) having a dielectric layer (106), a die pad (107), a first lead (109), a second lead (110), a conductive via (112), and a conductive trace (114), wherein the dielectric layer (106) has a side (118) and an opening (108) extending into the side, the die pad (107) is coupled to the first lead (109), the second lead (110) is coupled to the conductive via (112), the conductive trace (114) is coupled to the conductive via (112), and the conductive trace (114) extends on the side (118) of the dielectric layer (106); a dielectric spacer (104) over the die pad (107) in the opening (108); a semiconductor die (102) over the dielectric spacer (104), the semiconductor die (102) comprising a temperature sensor; an electrical connection (116) coupling the semiconductor die (102) to the conductive trace (114); and a package structure (120) extending on one side of the dielectric layer (106), on the semiconductor die (102) and on the conductive trace (114), the package structure (120) extending around the dielectric spacer (104) and to the die pad (107) in the opening (108). [2] The electronic device of claim 1, wherein the dielectric layer (106) is a laminate layer. [3] The electronic device of claim 1, wherein the dielectric layer (106) is a molded layer. [4] The electronic device of claim 1, wherein the dielectric spacer (104) has a thermal conductivity of more than 10 W / mK. [5] The electronic device of claim 1, wherein the dielectric spacer (104) comprises aluminum oxide, aluminum nitride, or aluminum oxynitride. [6] The electronic device of claim 1, further comprising: a first die attach film (103) that causes the semiconductor die (102) to adhere to the dielectric spacer (104); and a second die attach film (105) that causes the dielectric spacer (104) to adhere to the die pad. [7] The electronic device according to claim 1, wherein the dielectric spacer (104) has a thickness of 50 to 500 µm. [8] The electronic device of claim 1, wherein the electrical connection (116) is a bond wire. [9] The electronic device of claim 1, wherein the substrate (101) is a lead frame, a partially etched lead frame, a pre-formed lead frame, or a molded interconnect substrate. [10] Procedure (200), which includes: Mounting (201) a dielectric spacer (104) over a die pad (107) in an opening (108) in a dielectric layer (106) of a substrate (101); Mounting (202) a semiconductor die (102) over the dielectric spacer (104); Forming (204) an electrical connection (116) coupling the semiconductor die (102) to a conductive trace (114) on one side of the dielectric layer (106) of the substrate (101); and Performing (205) a molding process to form a package structure (120) extending on the side of the dielectric layer (106), on the semiconductor die (102) and on the conductive line (114), wherein the package structure (120) extends around the dielectric spacer (104) and to the die pad (107) in the opening (108). [11] The method of claim 10, wherein mounting (202) the semiconductor die (102) over the dielectric spacer (104) comprises: forming a die attach film (103) on the dielectric spacer (104); and mounting the semiconductor die (102) on the die attach film (103) over the dielectric spacer (104). [12] The method of claim 11, wherein mounting (202) the dielectric spacer (104) over the die pad (107) comprises: forming a second die attach film (105) on the die pad (107) in the opening (108); and mounting the dielectric spacer (104) to the second die attach film (105) over the die pad (107). [13] The method of claim 10, wherein mounting (202) the dielectric spacer (104) over the die pad (107) comprises: forming a die attach film (103) on the die pad (107) in the opening (108); and mounting the dielectric spacer (104) to the die attach film (103) over the die pad (107). [14] The method of claim 10, wherein forming (204) the electrical connection (116) coupling the semiconductor die (102) to the conductive trace (114) comprises connecting a bond wire between the semiconductor die (102) and the conductive trace (114). [15] System (1400), which includes: a printed circuit board, PCB, (1402) with a PCB conductor track (1404); and an electronic device (100) mounted on the PCB (1402), the electronic device (100) comprising: a substrate (101) having a dielectric layer (106), a die pad (107), a first lead (109), a second lead (110), a conductive via (112), and a conductive trace (114), wherein the die pad (107) is thermally coupled to the PCB conductive trace (1404), the dielectric layer (106) has a side (118) and an opening (108) extending into the side, the die pad (107) is coupled to the first lead (109), the second lead (110) is coupled to the conductive via (112), the conductive trace (114) is coupled to the conductive via (112), and the conductive trace (114) extends on the side of the dielectric layer (106); a dielectric spacer (104) over the die pad (107) in the opening (108); a semiconductor die (102) over the dielectric spacer (104), the semiconductor die (102) comprising a temperature sensor; an electrical connection (116) coupling the semiconductor die (102) to the conductive trace (114); and a package structure (120) extending on one side of the dielectric layer (106), on the semiconductor die (102) and on the conductive trace (114), the package structure (120) extending around the dielectric spacer (104) and to the die pad (107) in the opening (108). [16] The system of claim 15, wherein the dielectric spacer (104) has a thermal conductivity of more than 10 W / mK. [17] The system of claim 15, wherein the dielectric spacer (104) comprises aluminum oxide, aluminum nitride, or aluminum oxynitride. [18] The system of claim 15, further comprising: a first die attach film (103) that causes the semiconductor die (102) to adhere to the dielectric spacer (104); and a second die attach film (105) that causes the dielectric spacer (104) to adhere to the die pad (107). [19] The system of claim 15, wherein the electrical connection (116) is a bond wire. [20] The system of claim 15, wherein the substrate (101) is a lead frame, a partially etched lead frame, a pre-formed lead frame, or a molded interconnect substrate.

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