Grooved bond pad in a wafer stack structure and manufacturing process

Abstract

Integrated chip structure (100) with: one or more interconnects (106) arranged in a dielectric structure (104) over a substrate (102); and a bond pad (112) having a top surface disposed along a top surface of the dielectric structure (104), the top surface of the bond pad (112) comprising a plurality of discrete top surface segments (112u) that, when viewed in a sectional view, are laterally separated from one another by one or more non-zero distances extending between inner sidewalls (112s) of the bond pad (112), wherein the dielectric structure (104) is arranged directly between the inner side walls (112s) of the bond pad (112), wherein the bond pad (112) comprises: a lower segment (114) extending laterally between opposing sidewalls connected to a bottom surface of the bond pad (112); and an upper segment (116) having a bottom surface disposed on a top surface of the lower segment (114), the upper segment (116) extending laterally between opposite outermost side walls of the bond pad (112), wherein the inner side walls (112s) of the bond pad (112) are arranged in the upper segment (116) and are connected to horizontally extending surfaces of the bond pad (112) which are located directly above the underside of the upper segment (116).

Description

background

[0001] A multidimensional integrated chip is an integrated circuit comprising multiple substrates and / or dies that are vertically stacked and electrically connected to each other. Because the stacked substrates and / or dies are electrically connected to each other, the multidimensional integrated chip functions as a single device, enabling improved performance, lower power consumption, and a smaller footprint than conventional integrated chips. Therefore, multidimensional integrated chips provide a path to further meeting the performance and cost requirements of next-generation integrated circuits.

[0002] US 2021 / 0 335 737 A1 discloses a metallic bond pad with a grid structure arranged in a dielectric substrate. US 2010 / 0 096 760 A1 describes a structured bond pad with a plurality of electrically interconnected sections and at least one opening filled with a dielectric material.

[0003] Bond pads are also known from DE 10 2017 127 227 A1. Short description of the drawings

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1A and Fig. 1B illustrate some embodiments of an integrated chip structure having a bond pad with one or more recesses configured to reduce dishing of the bond pad. Fig. 2 shows a sectional view of some embodiments of a multidimensional integrated chip structure with bond pads each having one or more recesses. The Fig. 3A and Fig. 3B show some further embodiments of an integrated chip structure with a bond pad having one or more recesses. The Fig. 4A and Fig. 4B show some further embodiments of an integrated chip structure with a bond pad having one or more recesses. Fig. 5 shows a cross-sectional view of some embodiments of a multidimensional integrated chip structure with bond pads each having one or more recesses. The Fig. 6A and Fig. 6B show some further embodiments of an integrated chip structure with a bond pad having one or more recesses. The Fig. 7A to 7C show top views of some further embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses having different shapes and / or spatial configurations. The Fig. 8A to 8C show some further embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses. The Fig. 9A to 9C show top views of some further embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses having different shapes and / or spatial configurations. The Fig. 10A to 10C show some further embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses. The Fig. 11 to 18 illustrate some embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. The Fig. 19 to 28 show some further embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. The Fig. 29 to 35 show some further embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. Fig. 36 shows a flow diagram of some embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. Detailed description

[0005] The invention provides integrated chip structures having the features of claim 1 and 8, respectively, and a method for producing an integrated chip structure having the features of claim 16. Exemplary embodiments are specified in the dependent claims.

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the fabrication of a first element over or on top of a second element may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] Multidimensional integrated chip structures [e.g., chip-on-wafer (CoW) structures, wafer-on-wafer (WoW) structures, three-dimensional integrated chip (3DIC) structures, or the like] are fabricated by stacking a plurality of integrated chip dies. The plurality of integrated chip dies are individually fabricated by forming interconnects in interlayer dielectric (ILD) layers disposed over one or more semiconductor substrates. Then, one or more bond pads are formed over a top surface of the interconnects. The one or more bond pads may be formed by depositing a conductive material (e.g., a metal such as copper) in a bond pad opening extending through a dielectric material over the ILD layers, followed by a planarization process (e.g., a chemical mechanical planarization; CMP) process.The bond pads of the integrated chip dies are then combined to electrically connect the integrated chip dies.

[0009] When the planarization process is performed on the conductive material (e.g., copper) of the one or more bond pads, a polishing pad is brought into contact with the conductive material and the surrounding dielectric material. Because the conductive material is softer than the surrounding dielectric material, the polishing pad removes the conductive material faster than the surrounding dielectric material, thus dishing out the conductive material (dishing). This dishing results in the one or more bond pads having a concave top surface that lies beneath a top surface of the surrounding dielectric material. When the bond pads of the two integrated chip dies are later joined, a void (e.g., a gap) may form between the concave top surfaces of the bond pads.The cavity can lead to poor electrical connection between the integrated chip dies, which can degrade the performance of a multi-dimensional integrated chip structure and / or ultimately lead to failure of that chip structure.

[0010] The present disclosure relates to an integrated chip structure having a bond pad configured to mitigate dishing along a top surface of the bond pad. The disclosed integrated chip structure includes a bond pad disposed in a dielectric structure over a substrate. The bond pad has inner sidewalls defining one or more recesses enclosed by the bond pad. The one or more recesses are filled with a dielectric material of the dielectric structure such that, when viewed in a cross-sectional view, a top surface of the bond pad includes a plurality of discrete top surface segments laterally separated from each other by the dielectric structure.Because the dielectric material is disposed directly between the plurality of discrete top-side segments, a polishing pad used to fabricate the bond pad has a relatively small overlap with individual top-side segments. This relatively small overlap reduces dishing of the individual top-side segments. Reduced dishing reduces the formation of voids when bond pads of a single integrated chip die are joined, thereby improving electrical performance and / or reliability of a multidimensional integrated chip structure.

[0011] Fig. 1A shows a cross-sectional view of some embodiments of an integrated chip structure 100 having a bond pad with one or more recesses configured to reduce dishing of the bond pad.

[0012] The integrated chip structure 100 includes one or more interconnects 106 disposed in a dielectric structure 104 over a substrate 102. A bond pad 112 is disposed in the dielectric structure 104 over the one or more interconnects 106. The bond pad 112 has a top surface disposed along a top surface of the dielectric structure 104. In some embodiments, the top surface of the bond pad 112 is substantially coplanar with the top surface of the dielectric structure 104. The plurality of interconnects 106 includes a topmost interconnect 108 disposed in the dielectric structure 104. The topmost interconnect 108 has a top surface 108u that directly contacts a bottom surface of the bond pad 112. In some embodiments, the top surface 108u may extend continuously beyond outermost sidewalls of the bottom surface of the bond pad 112.

[0013] In some embodiments, the bond pad 112 includes a lower segment 114 and an upper segment 116 above the lower segment 114. The lower segment 114 extends laterally between opposite outermost edges of lower sidewalls of the bond pad 112. The lower sidewalls are disposed along a bottom surface of the bond pad 112. The upper segment 116 extends laterally between opposite outermost edges of upper sidewalls of the bond pad 112. The upper sidewalls are disposed along a top surface of the bond pad 112. In some embodiments, the upper segment 116 has a bottom surface that extends laterally from a region directly above the lower segment 114 to laterally beyond one or more of the lower sidewalls.

[0014] The bond pad 112 further includes one or more inner side walls 112s defining one or more recesses 113 (e.g., one or more grooves) in the top surface of the bond pad 112. When viewed in the sectional view of Fig. 1A, the one or more recesses 113 separate the top surface of the bond pad 112 into a plurality of discrete top-surface segments 112u. The dielectric structure 104 is disposed within the one or more recesses 113 and directly between the plurality of discrete top-surface segments 112u. In some embodiments, the bottom surface of the bond pad 112 extends laterally and continuously beyond one or more of the inner sidewalls 112s defining the one or more recesses 113.

[0015] Because the dielectric structure 104 is disposed directly between the plurality of discrete top-side segments 112u, an overlap between individual ones of the plurality of discrete top-side segments 112u and a CMP pad used to form the bond pad 112 is smaller than that for a bond pad that does not have recesses. The smaller overlap reduces dishing of the individual ones of the plurality of discrete top-side segments 112u. The reduced dishing mitigates the formation of voids when contacting the bond pad 112 with another bond pad, thereby improving electrical performance and / or reliability of a multidimensional integrated chip structure.

[0016] Fig. 1B shows a top view 118 of some embodiments of the integrated chip structure 100 of Fig. 1A along a section line A - A'. In some embodiments, the sectional view of Fig. 1A can also be created along a section line B - B' of the top view 118.

[0017] As shown in top view 118, the bond pad 112 is enclosed by the dielectric structure 104. The upper segment 116 of the bond pad 112 extends around the one or more recesses 113 (e.g., one or more grooves) filled with the dielectric structure 104. In some embodiments, the upper segment 116 extends continuously between outermost sidewalls of the bond pad 112 along a first direction 120 and / or along a second direction 122 perpendicular to the first direction 120. In some embodiments, the upper segment 116 continuously encloses the one or more recesses 113 in a closed and uninterrupted loop. The upper segment 116 is located directly above a portion of the lower segment 114. In some embodiments, the one or more recesses 113 may also be located directly above a portion of the lower segment 114.

[0018] Fig. 2 shows a cross-sectional view of some embodiments of a multi-dimensional integrated chip structure 200 having bond pads with one or more recesses.

[0019] The multi-dimensional integrated chip structure 200 includes a first integrated circuit (IC) die 202 having a plurality of interconnects 106 disposed in a dielectric structure 104 over a substrate 102. In some embodiments, the plurality of interconnects 106 includes a top interconnect 108 contacting a bond pad 112 disposed in the dielectric structure 104. In some embodiments, the plurality of interconnects 106 may electrically connect a bond pad 112 to one or more semiconductor devices 204 on and / or in the substrate 102. In various embodiments, the one or more semiconductor devices 204 may comprise a transistor device [e.g., a transistor]. The sensor device may be a device (e.g., a planar FET, a FinFET, a gate-all-around (GAA) device, etc.), an image sensor device (e.g., a photodiode), a MEMS device (MEMS: microelectromechanical system), and / or the like.The bond pad 112 has a top surface facing away from the substrate 102. The top surface of the bond pad 112 is arranged along a top surface of the dielectric structure 104 facing away from the substrate 102. The top surface includes a plurality of discrete top surface segments that, when viewed in cross-sectional view, are separated by one or more recesses 113 filled with the dielectric structure 104.

[0020] The multi-dimensional integrated chip structure 200 further comprises a second IC die 208 having a plurality of further interconnects 214 arranged in a further dielectric structure 210 on a further substrate 212. In some embodiments, the one or more further interconnects 214 comprise a further top interconnect 216 contacting a further bond pad 218 arranged in the further dielectric structure 210. In some embodiments, the plurality of further interconnects 214 may electrically connect a further bond pad 218 to one or more further semiconductor devices 222 (e.g., a transistor device, an image sensor device, a MEMS device, and / or the like) on and / or in the further substrate 212. The further bond pad 218 has a top surface facing away from the further substrate 212.The top side of the further bond pad 218 is arranged along a top side of the further dielectric structure 210, which faces away from the further substrate 212. The top side of the further bond pad 218 has a plurality of discrete top side segments, which, when viewed in cross-sectional view, are separated by one or more further recesses 220 filled with the further dielectric structure 210.

[0021] In some embodiments, one or more dummy bond pads 206 may be disposed along the top surface of the dielectric structure 104 facing away from the substrate 102. The one or more dummy bond pads 206 may have the same layout as the bond pad 112. For example, when viewed in cross-sectional view, the one or more dummy bond pads 206 may have a top surface facing away from the substrate 102 and include a plurality of discrete top surface segments separated by one or more recesses filled with the dielectric structure 104. In some embodiments, one or more further dummy bond pads 224 may be disposed along the top surface of the further dielectric structure 210 facing away from the further substrate 212. The one or more further dummy bond pads 224 may have the same layout as the further bond pad 218.

[0022] The first IC die 202 is bonded to the second IC die 208 along a hybrid bond interface, with the bond pad 112 contacting the further bond pad 218 along a conductive interface and the dielectric structure 104 contacting the further dielectric structure 210 along a dielectric interface. In some embodiments, the dielectric structure 104 in the one or more recesses 113 contacts the further dielectric structure 210 in the one or more further recesses 220 along the dielectric interface. In some embodiments, the plurality of discrete top-side segments of the bond pad 112 may laterally overlap the plurality of discrete top-side segments of the top side of the further bond pad 218. In some embodiments, at least one sidewall of the further bond pad 218 may be located directly above the top side of the bond pad 112.

[0023] Because the dielectric structure 104 is disposed directly between the plurality of discrete top surface segments of the bond pad 112, the top surface of the bond pad 112 is substantially planar. Similarly, the top surface of the further bond pad 218 is substantially planar because the further dielectric structure 210 is disposed directly between the plurality of discrete top surface segments of the further bond pad 218. The substantially planar top surface of the bond pad 112 and the substantially planar top surface of the further bond pad 218 mitigate the formation of voids along an interface between the bond pad 112 and the further bond pad 218, thereby improving electrical performance and / or reliability of the multidimensional integrated chip structure 200.

[0024] Fig. 3A shows a cross-sectional view of some further embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses.

[0025] An integrated chip structure 300 includes a dielectric structure 104 over a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of interlevel dielectric (ILD) layers 104a-104d stacked on top of one another. The plurality of ILD layers 104a-104d may be vertically separated from each other by a plurality of etch stop layers 105a-105c. A top dielectric layer 105t is disposed along a top surface of the dielectric structure 104. In some embodiments, the plurality of ILD layers 104a to 104d may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), and / or a porous dielectric material, or the like.In some embodiments, the plurality of etch stop layers 105a to 105c and / or the upper dielectric layer 105t may include a nitride (e.g., silicon nitride, silicon oxide nitride, etc.), a carbide (e.g., silicon carbide, silicon oxide carbide, etc.), or the like.

[0026] A plurality of interconnects 106 are arranged in a lower dielectric structure 104L of the dielectric structure 104. In some embodiments, the plurality of interconnects 106 include conductive contacts, interconnect lines, interconnect vias, and / or the like. The plurality of interconnects 106 includes a top interconnect 108. In some embodiments, the top interconnect 108 may include a conductive core 108c surrounded by a barrier layer 108b. In some embodiments, the conductive core 108c may include copper, aluminum, or the like. In some embodiments, the barrier layer 108b may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0027] A bond pad 112 is disposed within the dielectric structure 104 and contacts the top interconnect 108. The bond pad 112 has a top surface disposed along a top surface of the dielectric structure 104. In some embodiments, the bond pad 112 includes a bottom segment 114 and an upper segment 116 above the bottom segment 114. The bottom segment 114 extends laterally between opposite outermost edges of lower sidewalls that are connected to one or more bottom surfaces of the bond pad 112. In some embodiments, the bottom segment 114 may have a first width 302 that is about 0.2 µm to about 3 µm, or about 0.4 µm to about 2 µm, or other similar values. The upper segment 116 extends laterally between opposite outermost edges of upper outermost sidewalls of the bond pad 112.In some embodiments, the upper segment 116 may have a second width 304 that is greater than about 1.5 µm or about 2 µm, or other similar values. Typically, a bond pad with a top surface that has a relatively large size (e.g., greater than about 1.5 µm) experiences significant dishing, which may lead to the formation of voids. However, by providing one or more recesses 113 in the upper segment 116 of the bond pad 112 filled with the dielectric structure 104, the bond pad 112 may have a relatively large size (e.g., greater than about 1.5 µm), allowing electrical connection to another IC while avoiding significant dishing.

[0028] A bottom surface of the upper segment 116 contacts a top surface of the lower segment 114. In some embodiments, the lower segment 114 may include a first barrier layer 114b surrounding a first conductive core 114c. In some embodiments, the upper segment 116 may include a second barrier layer 116b surrounding a second conductive core 116c. In some embodiments, the second barrier layer 116b may be disposed directly between the second conductive core 116c and the first conductive core 114c. In some embodiments, the first conductive core 114c and the second conductive core 116c may include copper, aluminum, tungsten, or the like. In some embodiments, the first barrier layer 114b and the second barrier layer 116b may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0029] In some embodiments, the second barrier layer 116b of the upper segment 116 may extend at a non-zero distance below an upper end of the first barrier layer 114b and / or the first conductive core 114c. In some embodiments, the first conductive core 114c may extend along sidewalls of the second barrier layer 116b. In these embodiments, the uppermost sidewalls of the bond pad 112 may extend vertically below an upper end of the lower sidewalls of the bond pad 112.

[0030] The top surface of the bond pad 112 includes a plurality of discrete top surface segments 112u laterally separated by one or more recesses 113 defined by inner sidewalls 112s of the bond pad 112. In some embodiments, the top segment 116 also includes discrete bottom surfaces separated by the one or more recesses 113, as viewed in cross-sectional view. In some embodiments, the bottom surfaces may each have a third width 306 that is about 0.2 µm to about 3 µm, or about 0.4 µm to about 2 µm, or other similar values. The dielectric structure 104 is disposed directly between the inner sidewalls 112s of the bond pad 112.

[0031] Fig. 3B shows a top view 308 of some embodiments of the integrated chip structure 300 of Fig. 3A along the section line A - A'. In some embodiments, the sectional view of Fig. 3A can also be created along a section line B - B' of the plan view 308.

[0032] As shown in top view 308, the bond pad 112 is enclosed by the dielectric structure 104. The upper segment 116 of the bond pad 112 extends around a perimeter of the lower segment 114. In some embodiments, the one or more recesses 113 extend through the upper segment 116 and are disposed directly above a portion of the lower segment 114. In some embodiments, the one or more recesses 113 may be rectangular-shaped recesses enclosed by a continuous ring of the upper segment 116. In some embodiments, the continuous ring of the upper segment 116 extends along an outer perimeter of the upper segment 116.

[0033] Fig. 4 shows a cross-sectional view of some further embodiments of an integrated chip structure 400 having a disclosed bond pad with one or more recesses.

[0034] The integrated chip structure 400 includes a bond pad 112 disposed in a dielectric structure 104 over a substrate 102. The bond pad 112 includes a lower segment 114 and an upper segment 116 over the lower segment 114. The lower segment 114 extends laterally between opposite outermost sidewalls connected to a bottom surface of the bond pad 112. The upper segment 116 extends laterally between opposite outermost sidewalls connected to a top surface of the bond pad 112. In some embodiments, the upper segment 116 includes inner sidewalls 112s connected to horizontally extending surfaces 112h facing away from the substrate 102 to form one or more recesses 113 in a top surface of the bond pad 112. The horizontally extending surfaces 112h are located directly above a bottom surface 117 of the upper segment 116.

[0035] In some embodiments, the one or more recesses 113 have a depth that is less than a height of the upper segment 116, such that the upper segment 116 extends along a bottom surface of the one or more recesses 113. In some embodiments, the bottom surface 117 of the upper segment 116 extends laterally and continuously beyond opposite outermost sidewalls of the lower segment 114 and the one or more recesses 113. In some embodiments, the bottom surface 117 completely covers a top surface of the lower segment 114.

[0036] Fig. 4B shows a top view 402 of some embodiments of the integrated chip structure 400 of Fig. 4A along the section line A - A'. In some embodiments, the sectional view of Fig. 4A can also be created along a section line B - B' of the plan view 402.

[0037] As shown in top view 402, the bond pad 112 is enclosed by the dielectric structure 104. The upper segment 116 of the bond pad 112 extends around a boundary of the lower segment 114. In some embodiments, the one or more recesses 113 extend through the upper segment 116 and are disposed directly above the lower segment 114.

[0038] Fig. 5 shows a cross-sectional view of some further embodiments of a multi-dimensional integrated chip structure 500 having disclosed bond pads each having one or more recesses.

[0039] The multidimensional integrated chip structure 500 includes a first IC die 202 with a bond pad 112 disposed in a dielectric structure 104 over a substrate 102. The bond pad 112 has a top surface facing away from the substrate 102. The top surface includes a plurality of discrete top surface segments separated by one or more recesses 113 defined by sidewalls and a horizontally extending top surface of the bond pad 112. The one or more recesses 113 are filled with the dielectric structure 104.

[0040] The multidimensional integrated chip structure 500 further comprises a second IC die 208 with a further bond pad 218 arranged in a further dielectric structure 210 on a further substrate 212. The further bond pad 218 has a top surface facing away from the further substrate 212. The top surface comprises a plurality of discrete segments separated by one or more further recesses 220 defined by sidewalls and a horizontally extending top surface of the further bond pad 218. The one or more further recesses 220 are filled with the further dielectric structure 210.

[0041] In some embodiments, one or more dummy bond pads 206 may be arranged along a top surface of the dielectric structure 104 facing away from the substrate 102. The one or more dummy bond pads 206 may have the same layout as the bond pad 112. In some embodiments, one or more further dummy bond pads 224 may be arranged along a top surface of the further dielectric structure 210 facing away from the further substrate 212. The one or more further dummy bond pads 224 may have the same layout as the further bond pad 218.

[0042] The first IC die 202 is bonded to the second IC die 208 along a hybrid bond interface, with the bond pad 112 contacting the further bond pad 218 along a conductive interface and the dielectric structure 104 contacting the further dielectric structure 210 along a dielectric interface (e.g., the dielectric structure 104 in the one or more recesses 113 contacts the further dielectric structure 210 in the one or more further recesses 220 along the dielectric interface). In some embodiments, the plurality of discrete top-side segments of the bond pad 112 and / or the plurality of discrete top-side segments of the further bond pad 218 may have slight dishing, resulting in small voids 502 forming along the conductive interface.However, because the one or more recesses mitigate CMP dishing, the small cavities 502 have only a minimal impact on performance of the multi-dimensional integrated chip structure 500. In some embodiments, the small cavities 502 may extend laterally along part, but not all, of the interface (e.g., the small cavities 502 may be located some distance, at non-zero distances, from opposite sides of the plurality of discrete top-side segments of the bond pad 112).

[0043] While the disclosed multidimensional integrated chip structures (e.g., multidimensional integrated chip structure 200 and / or 500) are illustrated as three-dimensional integrated chip (3DIC) structures, it should be understood that the disclosed bond pad is not limited to these structures, but rather may be integrated into various multidimensional integrated chip architectures. For example, in alternative embodiments, the disclosed bond pad may be integrated into chip-on-wafer (CoW) structures, wafer-on-wafer (WoW) structures, or the like.

[0044] Fig. 6A shows a cross-sectional view of some further embodiments of an integrated chip structure 600 with a disclosed bond pad having one or more recesses.

[0045] The integrated chip structure 600 includes one or more interconnects 106 disposed in a dielectric structure 104 over a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of ILD layers 104a-104e stacked on top of one another. The plurality of ILD layers 104a-104e may be vertically separated from each other by a plurality of etch stop layers 105a-105d. A top dielectric layer 105t is disposed along a top surface of the dielectric structure 104.

[0046] A bond pad 112 is disposed in the dielectric structure 104. The bond pad 112 contacts a topmost interconnect 108 of the plurality of interconnects 106. The bond pad 112 includes a bottom segment 114 and an upper segment 116 above the bottom segment 114. The bottom segment 114 extends laterally between opposite outermost sidewalls that are connected to a bottom surface of the bond pad 112. The upper segment 116 extends laterally between opposite outermost sidewalls of the bond pad 112. In some embodiments, the bottom segment 114 may include a first barrier layer 114b enclosing a first conductive core 114c. In some embodiments, the upper segment 116 may include a portion of the first barrier layer 114b enclosing a portion of the first conductive core 114c and a second barrier layer 116b enclosing a second conductive core 116c.In some embodiments, the second barrier layer 116b may be disposed directly between the second conductive core 116c and the first conductive core 114c. In some embodiments, the second barrier layer 116b may contact the first conductive core 114c at a position located above a bottom surface of the upper segment 116 (e.g., at a position located above a lower portion of the opposite outermost sidewalls of the bond pad 112). In some embodiments, the second barrier layer 116b may extend a non-zero distance below a top end of the first barrier layer 114b and / or the first conductive core 114c.

[0047] In some embodiments, one or more recesses 113 extend into the upper segment 116 of the bond pad 112. The one or more recesses 113 may be defined by sidewalls of the second barrier layer 116b and by a top surface of the first conductive core 114c. The one or more recesses 113 have a height that is less than a height of the upper segment 116 (e.g., less than heights of the opposite outermost sidewalls of the bond pad 112).

[0048] Fig. 6B shows a top view 602 of some embodiments of the integrated chip structure 600 of Fig. 6A along a section line A - A'. In some embodiments, the sectional view of Fig. 6A can also be created along a section line B - B' of the plan view 602.

[0049] As shown in top view 602, the upper segment 116 of the bond pad 112 is enclosed by the dielectric structure 104 and extends around a boundary of the lower segment 114. In some embodiments, the one or more recesses 113 extend through the upper segment 116 and are located directly above a portion of the lower segment 114. In some embodiments, the one or more recesses 113 may have rectangular regions enclosed by a contiguous ring of the upper segment 116. In some embodiments, the one or more recesses 113 may be located directly above a portion of the lower segment 114.

[0050] It will be appreciated that in various embodiments, an upper segment of the disclosed bond pad may have inner sidewalls defining one or more recesses having different shapes and / or spatial configurations. Fig. 7A to 7C show top views of various embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses having different shapes and / or spatial configurations.

[0051] Fig. 7A shows a top view 700 of some embodiments of an integrated chip structure comprising a bond pad 112 with one or more recesses 113, each having a square shape. The square recesses 113 extend at a first distance 702 along a first direction 120 and at a second distance 704 along a second direction 122 perpendicular to the first direction 120. The first distance 702 is approximately equal to the second distance 704. The square recesses 113 are enclosed by a continuous outer ring of an uppermost segment 116 of the bond pad 112, which encloses the square recesses 113. In some embodiments, the upper segment 116 of the bond pad 112 has a cross-shaped region connected to the outer ring of the upper segment 116.The cross-shaped region separates the one or more recesses 113 from each other along the first direction 120 and the second direction 122. The square recesses 113 and the cross-shaped region are located directly above a lower segment 114 of the bond pad 112. The outer ring of the upper segment 116 is located laterally outside the lower segment 114 of the bond pad 112.

[0052] Fig. 7B shows a top view 706 of some embodiments of an integrated chip structure comprising a bond pad 112 with one or more recesses 113, each having a cross shape. The cross-shaped recess 113 is enclosed by discrete parts of an upper segment 116 of the bond pad 112. The discrete parts of the upper segment 116 of the bond pad 112 are arranged directly above a lower segment 114 of the bond pad 112. The cross-shaped recess 113 has portions that completely separate the discrete parts of the upper segment 116 from each other along a first direction 120 and a second direction 122 perpendicular to the first direction 120.

[0053] Fig. 7C shows a top view 708 of some embodiments of an integrated chip structure including a bond pad 112 with one or more recesses 113, each having a square shape. The square recesses 113 are enclosed by a continuous outer ring of an upper segment 116 of the bond pad 112, which encloses the square recesses 113. The square recesses 113 are located directly above square recesses 113 that extend through a lower segment 114 of the bond pad 112. In some embodiments, the lower segment 114 of the bond pad 112 has the same structure as the upper segment 116 of the bond pad 112.

[0054] Fig. 8A shows a top view of some further embodiments of an integrated chip structure 800 having a disclosed bond pad with one or more recesses.

[0055] The integrated chip structure 800 includes a bond pad 112 disposed within a dielectric structure 104. The bond pad 112 includes a lower segment 114 and an upper segment 116 above the lower segment 114. The upper segment 116 has inner sidewalls defining one or more recesses 113 enclosed by a continuous ring of the bond pad 112. The one or more recesses 113 are filled with the dielectric structure 104.

[0056] The lower segment 114 may include a plurality of discrete lower segments 114d arranged in a matrix. The plurality of discrete lower segments 114d may be spaced a first distance 802 along a first direction 120 and a second distance 804 along a second direction 122 that is perpendicular to the first direction 120. In some embodiments, the plurality of discrete lower segments 114d may include square segments. In other embodiments (not shown), the plurality of discrete lower segments 114d may include segments with other shapes (e.g., circular, octagonal, polygonal segments, or the like). In some embodiments, the plurality of discrete lower segments 114d are completely covered by the upper segment 116.

[0057] Fig. 8B shows a sectional view 806 of some further embodiments of the integrated chip structure of Fig. 8A along a line A - A'.

[0058] As shown in cross-sectional view 806, the one or more recesses 113 extend completely through the bond pad 112, such that a portion of the dielectric structure 104 located between sidewalls of the bond pad 112 extends continuously from a top surface of the bond pad 112 to its bottom surface. In some embodiments, the portion of the dielectric structure 104 located between sidewalls of the bond pad 112 extends continuously from the top surface of the bond pad 112 to a top interconnect 108 in the dielectric structure 104.

[0059] The lower segment 114 of the bond pad 112 extends laterally in the first direction 120 between opposing outer edges of lower sidewalls of the bond pad 112. The lower sidewalls are disposed along a bottom surface of the bond pad 112. In some embodiments, the plurality of discrete lower segments 114d have a plurality of discrete bottom surfaces contacting the topmost interconnect 108 and a plurality of discrete top surfaces contacting the top segment 116. The plurality of discrete bottom surfaces and the plurality of discrete top surfaces of the plurality of discrete lower segments 114d are laterally spaced apart from each other in the first direction 120 by the dielectric structure 104.

[0060] The upper segment 116 of the bond pad 112 extends laterally between outermost sidewalls of the bond pad 112. The outermost sidewalls are disposed along a top surface of the bond pad 112. In some embodiments, the upper segment 116 may have a plurality of discrete bottom surfaces laterally spaced from each other by the dielectric structure 104. In some embodiments, the plurality of discrete bottom surfaces of the upper segment 116 may each have a greater width than respective ones of the plurality of discrete top surfaces of the plurality of discrete lower segments 114d. In some embodiments, the plurality of discrete bottom surfaces of the upper segment 116 may each extend beyond one or more outer edges of the plurality of discrete top surfaces of the plurality of discrete lower segments 114d.

[0061] Fig. 8C shows a sectional view 808 of some further embodiments of the integrated chip structure of Fig. 8A along a line B - B'.

[0062] As shown in cross-sectional view 808, the plurality of discrete lower segments 114d in the lower segment 114 are spaced apart from one another along the second direction 122. The upper segment 116 has a bottom surface that extends continuously in the second direction 122 above the plurality of discrete lower segments 114d.

[0063] It is understood that in various embodiments, a lower segment of the disclosed bond pad may have a plurality of discrete lower segments having different shapes and / or spatial configurations. Fig. 9A to 9C show top views of some further embodiments of an integrated chip structure having a disclosed bond pad with one or more recesses.

[0064] Fig. 9A shows a top view 900 of an integrated chip structure having a bond pad 112 with a bottom segment 114 and a top segment 116. The bottom segment 114 has a plurality of discrete bottom segments 114d arranged in a matrix extending in a first direction 120 and a second direction 122. The top segment 116 is arranged directly above the plurality of discrete bottom segments 114d in the matrix. The top segment 116 has sidewalls defining one or more recesses 113 with rectangular shapes. The rectangular recesses 113 extend a first distance 902 along a first direction 120 and a second distance 904 along a second direction 122. The first distance 902 is smaller than the second distance 904. The rectangular recesses 113 are enclosed by a continuous outer ring of the top segment 116.A cross member extends between portions of the continuous outer ring of the upper segment 116 to separate the rectangular recesses 113.

[0065] Fig. 9B shows a top view 906 of an integrated chip structure including a bond pad 112 with a bottom segment 114 and a top segment 116. The bottom segment 114 includes a plurality of discrete bottom segments 114d arranged in a matrix extending along a first direction 120 and a second direction 122. The top segment 116 is disposed directly above the plurality of discrete bottom segments 114d in the matrix. The top segment 116 has sidewalls defining one or more recesses 113, each having a square shape. The square recesses 113 are enclosed by a continuous outer ring of the top segment 116. A cross-shaped region of the top segment 116 is enclosed by the continuous outer ring and separates the square recesses 113 along a first direction 120 and a second direction 122.The cross-shaped region includes a first cross member extending in the first direction 120 and a second cross member extending in the second direction 122.

[0066] Fig. 9C shows a top view 908 of an integrated chip structure including a bond pad 112 with a bottom segment 114 and a top segment 116. The bottom segment 114 includes a plurality of discrete bottom segments 114d arranged in a matrix extending in a first direction 120 and a second direction 122. The top segment 116 includes a plurality of discrete top segments 116d arranged in a matrix extending in the first direction 120 and the second direction 122. In some embodiments, the plurality of discrete bottom segments 114d may be smaller in size than the plurality of discrete top segments 116d. In some embodiments, the plurality of discrete top segments 116d may completely cover the plurality of discrete bottom segments 114d.

[0067] Fig. 10A shows a top view of some further embodiments of an integrated chip structure 1000 having a disclosed bond pad with one or more recesses.

[0068] The integrated chip structure 1000 includes a bond pad 112 disposed within a dielectric structure 104. The bond pad 112 includes a lower segment 114 and an upper segment 116 above the lower segment 114. The lower segment 114 and the upper segment 116 each have inner sidewalls defining one or more recesses 113 filled with the dielectric structure 104. In some embodiments, the one or more recesses 113 each have a rectangular shape. The lower segment 114 and the upper segment 116 extend contiguously in a closed loop around the one or more recesses 113. In some embodiments, the lower segment 114 is completely covered by the upper segment 116.In these embodiments, the inner sidewalls of the lower segment 114 are spaced a greater distance along the first direction and the second direction than the inner sidewalls of the upper segment 116.

[0069] In some embodiments, the upper segment 116 includes an upper outer ring segment enclosing the one or more recesses 113 and an upper cross member extending between portions of the upper outer ring segment. The lower segment 114 extends continuously in a closed loop around the one or more recesses 113. In some embodiments, the lower segment 114 includes a lower outer ring segment enclosing the one or more recesses 113 and a lower cross member extending between portions of the lower outer ring segment. The upper outer ring segment is disposed directly above the lower outer ring segment, and the upper cross member is disposed directly above the lower cross member. The one or more recesses 113 are filled with the dielectric structure 104.

[0070] Fig. 10B shows a sectional view 1002 of some further embodiments of the integrated chip structure 1000 of Fig. 10A along a line A - A'.

[0071] As shown in cross-sectional view 1002, the bond pad 112 includes a lower segment 114 with discrete top surfaces and an upper segment 116 with discrete bottom surfaces. The plurality of discrete top surfaces and the plurality of discrete bottom surfaces are separated from each other by the dielectric structure 104 along the first direction 120.

[0072] Fig. 10C shows a sectional view 1004 of some further embodiments of the integrated chip structure 1000 of Fig. 10A along a line B - B'.

[0073] As shown in cross-sectional view 1004, the bond pad 112 includes a lower segment 114 having a bottom surface and a top surface, each extending between outer edges of lower sidewalls connected to the bottom surface. The bond pad 112 further includes an upper segment 116 having a bottom surface and a top surface, each extending between outer edges of upper sidewalls connected to the top surface. In some embodiments, the bottom surface of the upper segment 116 extends contiguously beyond opposite sides of the top surface of the lower segment 114.

[0074] The Fig. 11 to 18 show some embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. Fig. Although Figures 11 to 18 are described for a method, it should be understood that the structures disclosed in these figures are not limited to the method, but can be used as structures in their own right and independently of the method.

[0075] As shown in a sectional view 1100 of Fig. 11, a substrate 102 is provided. In various embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layer associated therewith. In various embodiments (not shown), one or more semiconductor devices are fabricated on and / or in the substrate 102. In various embodiments, the one or more semiconductor devices may be a transistor device, an image sensor device, a MEMS device, and / or the like.

[0076] One or more interconnects 106 are formed in a bottom dielectric structure 104L formed over the substrate 102. The bottom dielectric structure 104L may include one or more ILD layers 104a and 104b separated by one or more etch stop layers 105a. In some embodiments, the one or more interconnects 106 may include a top interconnect 108 having a barrier layer 108b and a conductive core 108c. In some embodiments, the top interconnect 108 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process).The damascene process is performed as follows: forming an ILD layer on the substrate 102; etching the ILD layer to create a via opening and / or a trench; filling the via opening and / or the trench with a barrier layer and a conductive material; and performing a planarization process (e.g., a CMP process). In some embodiments, the bottom dielectric structure 104L may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, a porous dielectric material, or the like. In some embodiments, the bottom dielectric structure 104L may be formed using one or more deposition processes [e.g., E.g. a PVD process (PVD: physical vapor deposition), a CVD process (CVD: chemical vapor deposition), a PECVD process (PECVD: plasma-enhanced CVD), an ALD process (ALD: atomic layer deposition), etc.], and the conductive material (e.g., tungsten, copper, aluminum, or the like) can be deposited using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.).

[0077] As shown in a sectional view 1200 of Fig. 12, a first upper dielectric structure 1201 is formed over the lower dielectric structure 104L. In some embodiments, the first upper dielectric structure 1201 includes a first bond pad etch stop layer 105b formed over the lower dielectric structure 104L and a first bond pad ILD layer 104c formed on the first bond pad etch stop layer 105b. In some embodiments, the first bond pad etch stop layer 105b may include a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide, silicon oxide carbide, etc.), or the like. In some embodiments, the first bond pad ILD layer 104c may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, a porous dielectric material, or the like.In some embodiments, the first bond pad etch stop layer 105b and the first bond pad ILD layer 104c may be formed using deposition processes (e.g., a PVD process, a CVD process, a PECVD process, an ALD process, etc.).

[0078] A first bond pad opening 1202 is created in the first upper dielectric structure 1201. In some embodiments, the first bond pad opening 1202 may be created using a first patterning process. In some embodiments, the first patterning process may be performed by selectively treating the first upper dielectric structure 1201 with a first etchant 1204 according to a first mask 1206. The first patterning process forms sidewalls of the first upper dielectric structure 1201 that define the first bond pad opening 1202. In some embodiments, the first etchant 1204 may be a plasma etchant with a fluorine-based etching chemical (e.g., an SF6 plasma or the like). In some embodiments, the first mask 1206 may be a photosensitive material (e.g., a photoresist), a hard mask, or the like.

[0079] As shown in a sectional view 1300 of Fig. 13, a first barrier layer 114b and a first conductive core 114c are formed in the first bond pad opening 1202. In these embodiments, the first barrier layer 114b may be formed along inner surfaces of the first upper dielectric structure 1201 that define the first bond pad opening 1202. The first conductive core 114c may then be formed over the first barrier layer 114b and in the first bond pad opening 1202. In some embodiments, the first barrier layer 114b may be formed using deposition processes (e.g., a PVD process, a CVD process, a PECVD process, an ALD process, etc.). In some embodiments, the first conductive core 114c may be formed by depositing a first conductive material using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.).In various embodiments, the first barrier layer 114b may include titanium, tantalum, titanium nitride, tantalum nitride, or the like. In various embodiments, the first conductive material may include copper, aluminum, tungsten, or the like. After depositing the first conductive material in the first bond pad opening 1202, a planarization process may be performed to remove excess first conductive material over the first dielectric structure 1201 and to define a bottom segment 114 of a bond pad. In some embodiments, the planarization process may be a CMP process. In other embodiments, the planarization process may include, for example, an etching process and / or a grinding process.

[0080] As shown in a sectional view 1400 of Fig. 14, a second upper dielectric structure 1401 is formed over the first upper dielectric structure 1201. In some embodiments, the second upper dielectric structure 1401 includes: a second bond pad etch stop layer 105c formed over the first bond pad ILD layer 104c; a second bond pad ILD layer 104d formed on the second bond pad etch stop layer 105c; and a top dielectric layer 105t formed on the second bond pad ILD layer 104d. In some embodiments, the second bond pad etch stop layer 105c and / or the top dielectric layer 105t may include a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide, silicon oxycarbide, etc.), or the like.In some embodiments, the second bond pad ILD layer 104d may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, a porous dielectric material, or the like. In some embodiments, the second bond pad etch stop layer 105c, the second bond pad ILD layer 104d, and the top dielectric layer 105t may be formed using deposition processes (e.g., a PVD process, a CVD process, a PECVD process, an ALD process, etc.).

[0081] As shown in a sectional view 1500 of Fig. 15, a second bond pad opening 1502 is created in the second upper dielectric structure 1401. In some embodiments, the second bond pad opening 1502 may be created with a second patterning process. In some embodiments, the second patterning process may be performed by selectively treating the second upper dielectric structure 1401 with a second etchant 1504 according to a second mask 1506. With the second patterning process, sidewalls of the second upper dielectric structure 1401 may be formed, which define the second bond pad opening 1502. In some embodiments, the second etchant 1504 may be a plasma etchant having a fluorine-based etching chemistry (e.g., an SF6 plasma or the like). In some embodiments, the second mask 1506 may be a photosensitive material (e.g., a photoresist), a hard mask, or the like.

[0082] As shown in a sectional view 1600 of Fig. 16, a barrier material 1602 and a second conductive material 1604 are deposited in the second bond pad opening 1502 and over the upper dielectric layer 105t. The barrier material 1602 may be deposited along inner surfaces defining the second bond pad opening 1502. Subsequently, the second conductive material 1604 may be deposited over the barrier material 1602 and in the second bond pad opening 1502. In some embodiments, the barrier material 1602 may be deposited using a deposition process (e.g., a PVD process, a CVD process, a PECVD process, an ALD process, etc.). In some embodiments, the second conductive material 1604 may be deposited using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the barrier material 1602 may include titanium, tantalum, titanium nitride, tantalum nitride, or the like.In various embodiments, the second conductive material may include copper, aluminum, tungsten, or the like.

[0083] As shown in a sectional view from 1700 by Fig. 17A and in a plan view 1706 of Fig. 17B, after deposition of the second conductive material (e.g., 1604 of Fig. 16) in the second bond pad opening (e.g. 1502 of Fig. 16) a planarization process (along a line 1702) may be performed. The planarization process removes excess second conductive material over the top dielectric layer 105t to define a top segment 116 of a bond pad 112 on a first IC die 202. The top segment 116 of the bond pad 112 includes a second barrier layer 116b and a second conductive core 116c over the second barrier layer 116b. The top segment 116 of the bond pad 112 has a top surface with a plurality of discrete top segments 112u that, when viewed in cross-sectional view 1700, are laterally separated by one or more recesses 113 defined by inner sidewalls of the bond pad 112. The one or more recesses 113 are filled with the second upper dielectric structure (e.g., the upper dielectric layer 105t, the second bond pad ILD layer 104d, and the second bond pad etch stop layer 105c).

[0084] In some embodiments, the planarization process may be a CMP process. During the CMP process, a top surface of the first IC die 202 is brought into contact with a polishing pad 1704 such that the top dielectric layer 105t and the top segment 116 of the bond pad 112 come into contact with the polishing pad 1704. Because the top dielectric layer 105t is disposed directly between inner sidewalls of the top segment 116 of the bond pad 112, an overlap between the polishing pad 1704 and individual ones of the plurality of discrete top segments 112u is reduced. By reducing the overlap between the polishing pad 1704 and individual ones of the plurality of discrete top segments 112u, dishing of individual ones of the plurality of discrete top segments 112u is reduced.

[0085] As shown in a sectional view 1800 by Fig. As shown in Figure 18, the bond pad 112 of the first IC die 202 is bonded to the further bond pad 218 of a second IC die 208 to create a multidimensional integrated chip structure. During bonding, the plurality of discrete top surface segments of the bond pad 112 are brought into contact with a plurality of discrete segments of the further bond pad 218. Furthermore, top surfaces of the dielectric structure 104 are brought into contact with top surfaces of a further dielectric structure 210 of the second IC die 208 to create a hybrid bond interface between the first IC die 202 and the second IC die 208. By reducing the dishing of the plurality of discrete top side segments of the bond pad 112, the formation of voids between the bond pad 112 and the further bond pad 218 is reduced, thereby improving electrical performance and / or reliability of the multidimensional integrated chip structure.

[0086] The Fig. 19 to 28 show some further embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. Fig. Although Figures 19 to 28 are described for a method, it should be understood that the structures disclosed in these figures are not limited to the method, but can be used as structures in their own right and independently of the method.

[0087] As shown in a sectional view from 1900 by Fig. 19, a substrate 102 is provided. One or more interconnects 106 are formed in a bottom dielectric structure 104L formed over the substrate 102. In some embodiments, the one or more interconnects 106 may include a top interconnect 108 having a barrier layer 108b and a conductive core 108c.

[0088] As shown in a sectional view 2000 of Fig. 20, a first upper dielectric structure 2001 is formed over the lower dielectric structure 104L. In some embodiments, the first upper dielectric structure 2001 includes: a first bond pad etch stop layer 105b formed over the lower dielectric structure 104L; a first bond pad ILD layer 104c formed on the first bond pad etch stop layer 105b; a second bond pad etch stop layer 105c formed on the first bond pad ILD layer 104c; and a second bond pad ILD layer 104d formed on the second bond pad etch stop layer 105c.

[0089] An intermediate bond pad opening 2002 is created in the first upper dielectric structure 2001. In some embodiments, the intermediate bond pad opening 2002 may be created with a first patterning process. In some embodiments, the first patterning process may be performed by selectively treating the first upper dielectric structure 2001 with a first etchant 2004 according to a first mask 2006.

[0090] As shown in a sectional view 2100 of Fig. 21, a sacrificial mask 2102 is formed in the intermediate bond pad opening 2002. The sacrificial mask 2102 may comprise a dielectric material, a photoresist material, or the like.

[0091] As shown in a sectional view 2200 of Fig. As shown in Figure 22, a first bond pad opening 2202 is created in the first upper dielectric structure 2001. In some embodiments, the first bond pad opening 2202 may be created with a second patterning process. In some embodiments, the second patterning process may be performed by selectively treating the first upper dielectric structure 2001 with a second etchant 2204 according to a second mask 2206.

[0092] As shown in a sectional view 2300 of Fig. 23, the sacrificial mask (e.g. 2102 of Fig. 22) is removed from the first bond pad opening 2202. In various embodiments, the sacrificial mask 2102 may be removed using a chemical developer, an etching process, or the like.

[0093] As shown in a sectional view 2400 of Fig. 24, a first barrier layer 114b is formed in the first bond pad opening 2202, and a first conductive core 114c is formed on the first barrier layer 114b and in the first bond pad opening 2202. In these embodiments, the first barrier layer 114b may be deposited along inner surfaces defining the first bond pad opening 2202. Subsequently, the first conductive core 114c may be formed over the first barrier layer 114b and in the first bond pad opening 2202.

[0094] As shown in a sectional view 2500 of Fig. 25, a second upper dielectric structure 2501 is formed over the first upper dielectric structure 2001. In some embodiments, the second upper dielectric structure 2501 includes: a third bond pad etch stop layer 105d formed over the second bond pad ILD layer 104d; a third bond pad ILD layer 104e formed on the third bond pad etch stop layer 105d; and a top dielectric layer 105t formed over the third bond pad ILD layer 104e.

[0095] A second bond pad opening 2502 is created in the second upper dielectric structure 2501. In some embodiments, the second bond pad opening 2502 may be created using a third patterning process. In some embodiments, the third patterning process may be performed by selectively treating the second upper dielectric structure 2501 with a third etchant 2504 according to a third mask 2506. The third patterning process forms sidewalls of the second upper dielectric structure 2501 that define the second bond pad opening 2502.

[0096] As shown in a sectional view 2600 of Fig. 26, a barrier material 2602 and a conductive material 2604 are deposited in the second bond pad opening 2502 and over the upper dielectric layer 105t. In these embodiments, the barrier material 2602 may be deposited along inner surfaces defining the second bond pad opening 2502. Subsequently, the conductive material 2604 may be deposited over the barrier material 2602 and in the second bond pad opening 2502.

[0097] As shown in a sectional view 2700 of Fig. 27A and in a plan view 2706 of Fig. 27B, after deposition of the conductive material (e.g. 2604 of Fig. 26) a planarization process (along a line 2702) may be performed in the second bond pad opening 2502. The planarization process removes excess conductive material over the second top dielectric structure to define a top segment 116 of a bond pad 112 on a first IC die 202. The top segment 116 of the bond pad 112 includes: a portion of the first barrier layer 114b; a portion of the first conductive core 114c; a second barrier layer 116b; and a second conductive core 116c over the second barrier layer 116b. The top segment 116 of the bond pad 112 has a top surface including a plurality of discrete top segments 112u laterally separated by one or more recesses 113 defined by inner sidewalls of the bond pad 112. The one or more recesses 113 are filled with the second upper dielectric structure.

[0098] In some embodiments, the planarization process may be a CMP process. During the CMP process, a top surface of the first IC die 202 is brought into contact with a polishing pad 2704 such that the top dielectric layer 105t and the top segment 116 of the bond pad 112 come into contact with the polishing pad 2704. Because the top dielectric layer 105t is disposed directly between inner sidewalls of the top segment 116 of the bond pad 112, an overlap between the polishing pad 2704 and individual ones of the plurality of discrete top segments 112u is reduced. By reducing the overlap between the polishing pad 2704 and individual ones of the plurality of discrete top segments 112u, dishing of individual ones of the plurality of discrete top segments 112u is reduced.

[0099] As shown in a sectional view 2800 of Fig. 28, the bond pad 112 of the first IC die 202 is bonded to the further bond pad 218 of a second IC die 208. During bonding, the plurality of discrete top surface segments of the bond pad 112 are brought into contact with a plurality of further discrete segments of the further bond pad 218. In addition, top surfaces of the dielectric structure 104 are brought into contact with top surfaces of a further dielectric structure 210 of the second IC die 208 to create a hybrid bond interface between the first IC die 202 and the second IC die 208.

[0100] In some alternative embodiments, the steps of Fig. 25 to 27B are omitted, and a first die containing a bond pad with the structure of Fig. 24, may be bonded along a hybrid bond interface (extending, for example, along top surfaces of the first barrier layer 114b and the first conductive core 114c) to another die having a bond pad with the structure of Fig. 24.

[0101] The Fig. 29 to 35 show some further embodiments of a method for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad. Fig. Although Figures 29 to 35 are described for a method, it should be understood that the structures disclosed in these figures are not limited to the method, but can be used as structures in their own right and independently of the method.

[0102] As shown in a sectional view 2900 of Fig. 29, a substrate 102 is provided. One or more interconnects 106 are formed in a bottom dielectric structure 104L formed over the substrate 102. In some embodiments, the one or more interconnects 106 may include a top interconnect 108 having a barrier layer 108b and a conductive core 108c.

[0103] As shown in a sectional view 3000 of Fig. 30, a first upper dielectric structure 3001 is formed over the lower dielectric structure 104L. In some embodiments, the first upper dielectric structure 3001 comprises: a first bond pad etch stop layer 105b formed over the lower dielectric structure 104L; and a first bond pad ILD layer 104c formed on the first bond pad etch stop layer 105b. One or more first bond pad openings 3002 are formed in the first upper dielectric structure 3001. In some embodiments, the one or more first bond pad openings 3002 may be formed with a first patterning process. In some embodiments, the first patterning process may be performed by selectively treating the first upper dielectric structure 3001 with a first etchant 3004 according to a first mask 3006.

[0104] As shown in a sectional view 3100 of Fig. 31A, a first barrier layer 114b and a first conductive core 114c are formed in the one or more first bond pad openings 3002. In some embodiments, the first barrier layer 114b may be formed along inner surfaces of the first upper dielectric structure 3001 that define the one or more first bond pad openings 3002. Subsequently, the first conductive core 114c may be formed over the first barrier layer 114b and in the one or more first bond pad openings 3002. After depositing the first conductive material in the one or more first bond pad openings 3002, a planarization process may be performed to remove excess first conductive material over the first upper dielectric structure 3001 and to define a bottom segment 114 of a bond pad 112.

[0105] As shown in a top view 3102 of Fig. 31B, in some embodiments, the lower segment 114 of the bond pad 112 may include a plurality of discrete lower segments 114d. The plurality of discrete lower segments 114d may be fabricated in a matrix. The plurality of discrete lower segments 114d may be spaced along a first direction 120 and a second direction 122 perpendicular to the first direction 120. In some embodiments, the cross-sectional view 3100 of Fig. 31A along a section line A - A' of Fig. 31B created.

[0106] As shown in a top view 3104 of Fig. 31C, in some alternative embodiments, the lower segment 114 of the bond pad 112 may be a single, continuous segment that extends continuously in a closed loop around one or more recesses 113. In some embodiments, the one or more recesses 113 each have a rectangular shape. In some embodiments, the sectional view 3100 of Fig. 31A along a section line A - A' of Fig. 31C created.

[0107] As shown in a sectional view 3200 of Fig. 32, a second upper dielectric structure 3201 is formed over the first upper dielectric structure 3001. In some embodiments, the second upper dielectric structure 3201 includes: a second bond pad etch stop layer 105c formed over the first bond pad ILD layer 104c; a second bond pad ILD layer 104d formed on the second bond pad etch stop layer 105c; and a top dielectric layer 105t formed over the second bond pad ILD layer 104d.

[0108] As shown in a sectional view 3300 of Fig. 33, one or more second bond pad openings 3302 are created in the second upper dielectric structure 3201. In some embodiments, the one or more second bond pad openings 3302 may be created using a third patterning process. In some embodiments, the third patterning process may be performed by selectively treating the second upper dielectric structure 3201 with a third etchant 3304 according to a third mask 3306. The third patterning process may form sidewalls of the second upper dielectric structure 3201 that define the one or more second bond pad openings 3302.

[0109] As shown in a sectional view 3400 of Fig. 34A, a second barrier layer 116b and a second conductive core 116c are formed in the one or more second bond pad openings 3302. In these embodiments, the second barrier layer 116b may be formed along interior surfaces defining the one or more second bond pad openings 3302. Subsequently, the second conductive core 116c may be formed over the second barrier layer 116b and in the one or more second bond pad openings 3302. A planarization process may be performed to remove excess portions of the second barrier layer 116b and the second conductive core 116c to form a top segment 116 of a bond pad.

[0110] As shown in a top view 3402 of Fig. 34B, in some embodiments, the upper segment 116 of the bond pad may include a plurality of discrete upper segments 116d. The plurality of discrete upper segments 116d may be arranged in a matrix. The plurality of discrete upper segments 116d may be spaced along a first direction 120 and a second direction 122. In some embodiments, the cross-sectional view 3400 of Fig. 34A along a section line A - A' of Fig. 34B created.

[0111] In some alternative embodiments, shown in a top view 3404 of Fig. 34C and in a plan view 3406 of Fig. 34D, the upper segment 116 of the bond pad may comprise a single contiguous segment that extends contiguously in a closed loop around one or more recesses 113. In some embodiments, the single contiguous segment may be located directly above a plurality of discrete lower segments 114d (such as in Fig. 31B), while in other embodiments the single contiguous segment may be located directly above a single contiguous lower segment (such as in Fig. 31C). In some embodiments, the sectional view 3400 of Fig. 34A along a section line A - A' of Fig. 34C or along a section line A - A' of Fig. 34D created.

[0112] As shown in a sectional view 3500 of Fig. 35, the bond pad 112 of the first IC die 202 is bonded to the further bond pad 218 of a second IC die 208. During bonding, the plurality of discrete top surface segments of the bond pad 112 are brought into contact with a plurality of further discrete segments of the further bond pad 218. In addition, top surfaces of the dielectric structure 104 are brought into contact with top surfaces of a further dielectric structure 210 of the second IC die 208 to create a hybrid bond interface between the first IC die 202 and the second IC die 208.

[0113] Fig. 36 shows a flow diagram of some embodiments of a method 3600 for manufacturing an integrated chip structure having a disclosed bond pad with one or more recesses configured to reduce dishing of the bond pad.

[0114] While method 3600 is illustrated and described herein as a series of steps or events, it should be understood that the illustrated order of these steps or events should not be construed in a limiting sense. For example, some steps may be performed in different orders than illustrated, and / or they may occur concurrently with steps or events other than those illustrated and / or described herein. Moreover, not all of the steps illustrated herein need implement one or more aspects or embodiments of the description, and one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0115] In a step 3602, one or more interconnects are formed in a lower dielectric structure over a substrate. Fig. 11 shows a sectional view 1100 of some embodiments corresponding to step 3602. Fig. 19 shows a sectional view 1900 of some further embodiments corresponding to step 3602. Fig. 29 shows a sectional view 2900 of some further embodiments corresponding to step 3602.

[0116] In a step 3604, a first upper dielectric structure is formed over the lower dielectric structure. Fig. 12 shows a sectional view 1200 of some embodiments corresponding to step 3604. Fig. 20 shows a sectional view 2000 of some further embodiments corresponding to step 3604. Fig. 30 shows a sectional view 3000 of some further embodiments corresponding to step 3604.

[0117] In a step 3606, a first bond pad opening is created in the first upper dielectric structure. Fig. 12 shows a sectional view 1200 of some embodiments corresponding to step 3606. The Fig. 20 to 23 show sectional views 2000 to 2300 of some further embodiments corresponding to step 3606. Fig. 30 shows a sectional view 3000 of some further embodiments corresponding to step 3606.

[0118] In a step 3608, a first barrier layer and a first conductive core are formed in the first bond pad opening. Fig. 13 shows a sectional view 1300 of some embodiments corresponding to step 3608. Fig. 24 shows a sectional view 2400 of some further embodiments corresponding to step 3608. Fig. 31A shows a sectional view 3100 of some further embodiments corresponding to step 3608.

[0119] In a step 3610, a second upper dielectric structure is formed over the first upper dielectric structure. Fig. 14 shows a sectional view 1400 of some embodiments corresponding to step 3610. Fig. 25 shows a sectional view 2500 of some further embodiments corresponding to step 3610. Fig. 32 shows a sectional view 3200 of some further embodiments corresponding to step 3610.

[0120] In a step 3612, a second bond pad opening is created in the second upper dielectric structure to expose the first conductive core and to enclose one or more inner sidewalls of the second upper dielectric structure. Fig. 15 shows a sectional view 1500 of some embodiments corresponding to step 3612. Fig. 25 shows a sectional view 2500 of some further embodiments corresponding to step 3612. Fig. 33 shows a sectional view 3300 of some further embodiments corresponding to step 3612.

[0121] In a step 3614, a barrier material and a conductive material are deposited in the second bond pad opening. Fig. 16 shows a sectional view 1600 of some embodiments corresponding to step 3614. Fig. 26 shows a sectional view 2600 of some further embodiments corresponding to step 3614. Fig. 34A shows a sectional view 3400 of some further embodiments corresponding to step 3614.

[0122] In a step 3616, a CMP process is performed to remove portions of the barrier material and the conductive material to define a bond pad with inner sidewalls forming one or more recesses extending into the bond pad. The inner sidewalls are connected to a top surface of the bond pad. The Fig. 17A and Fig. 17B show some embodiments corresponding to step 3616. The Fig. 27A and Fig. 27B show some further embodiments corresponding to step 3616. Fig. 34 shows a sectional view 3400 of some further embodiments corresponding to step 3616.

[0123] In a step 3618, an integrated chip die having a bond pad is brought into contact with another integrated chip die having another bond pad along a hybrid bond interface. Fig. 18 shows a sectional view 1800 of some embodiments corresponding to step 3618. Fig. 28 shows a sectional view 2800 of some further embodiments corresponding to step 3618. Fig. 35 shows a sectional view 3500 of some further embodiments corresponding to step 3618.

[0124] Thus, the present disclosure relates to an integrated chip structure comprising a bond pad with one or more recesses enclosed by the bond pad and filled with a dielectric material configured to mitigate dishing along a top surface of the bond pad.

Claims

[1] Integrated chip structure (100) with: one or more interconnects (106) arranged in a dielectric structure (104) over a substrate (102); and a bond pad (112) having a top surface disposed along a top surface of the dielectric structure (104), the top surface of the bond pad (112) comprising a plurality of discrete top surface segments (112u) that, when viewed in a sectional view, are laterally separated from one another by one or more non-zero distances extending between inner sidewalls (112s) of the bond pad (112), wherein the dielectric structure (104) is arranged directly between the inner side walls (112s) of the bond pad (112), wherein the bond pad (112) comprises: a lower segment (114) extending laterally between opposing sidewalls connected to a bottom surface of the bond pad (112); and an upper segment (116) having a bottom surface disposed on a top surface of the lower segment (114), the upper segment (116) extending laterally between opposite outermost side walls of the bond pad (112), wherein the inner side walls (112s) of the bond pad (112) are arranged in the upper segment (116) and are connected to horizontally extending surfaces of the bond pad (112) which are located directly above the underside of the upper segment (116). [2] The integrated chip structure (100) of claim 1, wherein a bottom surface of the bond pad (112) extends laterally and continuously beyond one or more of the inner sidewalls (112s) of the bond pad (112). [3] The integrated chip structure (100) of claim 1 or 2, wherein the top surface of the bond pad (112) is substantially coplanar with the top surface of the dielectric structure (104). [4] The integrated chip structure (100) of any preceding claim, wherein the one or more interconnects (106) comprise a top interconnect (108) disposed in the dielectric structure (104), the top interconnect (108) having a top surface directly contacting a bottom surface of the bond pad (112) and extending contiguously beyond outermost sidewalls of the bottom surface of the bond pad (112). [5] The integrated chip structure (100) of any preceding claim, wherein the one or more interconnects (106) comprise a top interconnect (108) disposed in the dielectric structure (104), the dielectric structure (104) extending contiguously from the top of the dielectric structure (104) to the top interconnect (108) between the inner sidewalls (112s) of the bond pad (112). [6] The integrated chip structure (100) of any preceding claim, wherein the bottom surface of the upper segment (116) physically contacts the top surface of the lower segment (114). [7] The integrated chip structure (100) of any preceding claim, wherein the bond pad (112) extends continuously in a non-interrupted loop when viewed in a plan view of the bond pad (112). [8] Integrated chip structure (100) with: one or more interconnects (106) enclosed by a dielectric structure (104) disposed on a substrate (102); and a bond pad (112) enclosed by the dielectric structure (104) and having a lower segment (114) extending between outer edges of lower sidewalls arranged along a bottom side of the bond pad (112) and an upper segment (116) extending between outer edges of upper sidewalls arranged along a top side of the bond pad (112), wherein the upper segment (116) of the bond pad (112) has one or more inner sidewalls (112s) separated by non-zero distances between edges of a top surface of the bond pad (112), wherein the dielectric structure (104) is located between the edges of the top surface of the bond pad (112), wherein the upper side walls extend vertically below an upper end of the lower side walls and / or the upper segment (116) of the bond pad (112) extends a non-zero distance below an upper end of the lower segment (114) of the bond pad (112). [9] The integrated chip structure (200) of claim 8, wherein the upper segment (116) has a bottom surface that extends continuously beyond opposite edges of the lower segment (114). [10] Integrated chip structure (200) according to claim 8 or 9, further comprising: one or more further interconnects (214) enclosed by a further dielectric structure (210) arranged on a second substrate (212); and a further bond pad (218) enclosed by the further dielectric structure (212) and having one or more further inner sidewalls separated by the further dielectric structure (210), wherein the bond pad (112) contacts the further bond pad (218) along a conductive interface and the dielectric structure (104) between edges of the upper side of the bond pad (112) contacts the further dielectric structure (210) separating the one or more further inner sidewalls along a dielectric interface. [11] The integrated chip structure (100) of any one of claims 8 to 10, wherein the upper segment (116) comprises a barrier layer (116b) and a conductive core (116c), the dielectric structure (104) contacting sidewalls of the barrier layer (116b). [12] The integrated chip structure (100) of any one of claims 8 to 11, wherein, when viewed in a cross-sectional view of the bond pad (112), the top surface of the bond pad (112) comprises a plurality of discrete top surface segments (112u), the plurality of discrete top surface segments (112u) being separated from one another by non-zero distances. [13] The integrated chip structure (100) of any one of claims 8 to 12, wherein the inner sidewalls (112s) of the bond pad (112) are further connected to a horizontally extending surface of the bond pad (112) facing away from the substrate (102). [14] The integrated chip structure (100) of any one of claims 8 to 13, wherein the bond pad (112) comprises an outer ring segment extending continuously in a non-interrupted loop. [15] A method (3600) for manufacturing an integrated chip structure (100), comprising: Creating a first bond pad opening (1202) in a first upper dielectric structure (1201) fabricated over a lower dielectric structure (104L) enclosing one or more interconnects (106, 108) over a substrate (102); Forming a first barrier layer (114b) and a first conductive core (114c) in the first bond pad opening (1202); forming a second upper dielectric structure (104) over the first upper dielectric structure (1201); Creating a second bond pad opening (1502) in the second upper dielectric structure (1401) to expose the first conductive core (114c) and to enclose one or more inner sidewalls (112s) of the second upper dielectric structure (1401); Depositing a barrier material (1602) and a conductive material (1604) in the second bond pad opening (1502); and Removing portions of the barrier material (1602) and the conductive material (1604), thereby forming a bond pad (112) having inner sidewalls (112s) forming one or more recesses (113) extending into the bond pad (112). [16] The method (3600) of claim 15, wherein the one or more recesses (113) are filled with the second upper dielectric structure (104). [17] The method (3600) of claim 15 or 16, wherein, when viewed in a sectional view, the bond pad (112) has a plurality of discrete top surfaces (112u) separated from each other by the second top dielectric structure (1401).

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