Method for operating an inverter, inverter and frequency converter

Abstract

Method for operating an inverter (10) comprising the step: - Generation of output voltages (UA, UB, UC) with adjustable frequency (f) and adjustable amplitude (A) from an intermediate circuit voltage (UZK) by means of pulse width modulation, whereby for the pulse width modulation within a respective modulation period (MP) of the pulse width modulation, associated modulation pulses (MPA, MPB, MPC) with adjustable duration are generated for each output voltage (UA, UB, UC), - wherein in a first operating mode (BA1) within a respective modulation period (MP) of the pulse width modulation, the rising edges or the falling edges of at least two modulation pulses (MPA, MPB, MPC) are generated simultaneously, characterized in that - in a second operating mode (BA2), all modulation pulses (MPA, MPB, MPC) are generated centrally symmetrically with respect to the modulation period (MP) within a respective modulation period (MP) of the pulse width modulation, and - the first operating mode (BA1) is only set, - if the amplitudes of the output voltages (UA, UB, UC) fall below a first threshold and / or exceed a second threshold, and / or - in time domains around a zero crossing of the output voltages (UA, UB, UC).

Description

The publication Bharatiraja, C., et al., "Comparative realization of different SVPWM schemes in linear modulation using FPGA". 2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, 2008, pp. 164-68. IEEE Xplore, https: / / doi.org / 10.1109 / SIBIRCON.2008.4602575 discloses various PWM switching patterns, wherein in a so-called first switching pattern all lower or upper switching means are simultaneously switched on at the beginning of a switching cycle and subsequently are sequentially switched off.DE 10 2017 212 568 A1 discloses an electric machine having a plurality of part machines, wherein PWM signals for the part machines are generated in such a way that the PWM pulses for a part machine each start at a starting time of a PWM period.WO 2003 / 105 329 A1 discloses a motor controller with a single current sensor using space vector modulation.The invention is based on the object of providing a method for operating an inverter, an inverter and a frequency converter, which ensure operation that is as reliable as possible.The method serves for operating an inverter, in particular a conventional inverter having, for example, three inverter bridge branches.Conventionally, output voltages with an adjustable frequency and adjustable amplitude are generated by means of the inverter from an intermediate circuit (DC) voltage by means of pulse width modulation. For pulse width modulation, within a respective modulation period of the pulse width modulation, associated modulation pulses with an adjustable duration are generated for each output voltage or each output voltage phase. The modulation pulses typically control the switching state of semiconductor switching means of an associated inverter bridge branch of the inverter. A modulation pulse has the effect, for example, that the upper semiconductor switching means of the bridge branch is / is switched on and the lower semiconductor switching means of the bridge branch is / is switched off, i.e. a positive intermediate circuit potential is output at the associated output of the bridge branch. In the absence of a modulation pulse, the upper semiconductor switching means of the bridge branch is / is switched off and the lower semiconductor switching means of the bridge branch is switched on, i.e. a negative intermediate circuit potential is output at the associated output of the bridge branch. In this respect, reference is also made to the relevant technical literature relating to inverters and their mode of operation. The output voltages can serve for controlling an electric motor, for example for controlling a three-phase motor.According to the invention, in a first operating mode, within a respective modulation period of the pulse width modulation, the rising edges or the falling edges of at least two modulation pulses are generated simultaneously.In one embodiment, in the first operating mode, the rising edges or the falling edges of all modulation pulses are generated simultaneously within a respective modulation period of the pulse width modulation.In one embodiment, exactly three output voltages are generated.In one embodiment, the output voltages are sinusoidally generated.In a second operating mode, within a respective modulation period of the pulse width modulation, all modulation pulses are generated in a center-symmetrical manner with respect to the modulation period.The first operating mode is set only if the amplitudes of the output voltages fall below a first threshold value and / or exceed a second threshold value, and / or in time ranges around a zero crossing of the output voltages.The inverter according to the invention has a control device, for example in the form of a microprocessor, for controlling the operation of the inverter, which control device is designed to control the inverter in such a way that a method according to the invention is carried out.The frequency converter according to the invention has an intermediate circuit connection for connecting the frequency converter to a DC voltage intermediate circuit which conducts an intermediate circuit voltage, and / or a rectifier which serves for generating the intermediate circuit voltage from a mains AC voltage. The frequency converter further comprises an inverter according to the invention, which is fed from the intermediate circuit voltage.An inverter generates one or more frequency- and amplitude-variable output voltages by pulse-width-modulating a DC link voltage, i.e. switching it on and off block by block. As a rule, the length of the blocks or output voltage pulses for pulse width modulation is calculated as a function of an amplitude to be set.The inverter is typically connected to terminals of an electric motor via a cable. If the length of the cable exceeds a critical length, the output voltage pulses generated by the inverter are reflected at the end of the cable according to traveling wave theory. Typically, a damped oscillation is produced which is superimposed on the output voltage pulses of the inverter. A resulting amplitude of the resulting voltage can thereby become twice as large as the amplitude of the output voltage pulses generated by means of the inverter. Motor isolation must be designed for these high reflection-based voltages, otherwise damage to the isolation and ultimately failure of the electric motor occurs.If the output voltage pulses become very short, the oscillation has not yet decayed when a subsequent output voltage pulse is generated. This is the case in particular in the case of pulse width modulation with low instantaneous values or amplitudes of the output voltage.During the switching-off, a damped oscillation occurs as during the switching-on. If it is switched off at an unfavorable point in time, the switch-on oscillation is superimposed with the switch-off oscillation and a voltage edge having a height of 4 times the intermediate circuit voltage is produced. This edge can damage the motor insulation even if it has already been designed for twice the intermediate circuit voltage.When the electric motors are operated with block commutation, for example in BLDC motors, the above-mentioned problem does not occur at low output voltages but at very high speeds. Conversely, the phenomenon also occurs when very high output voltages are set and the pause is very short.For each motor phase, an on and off time of a modulation pulse within the modulation period or the PWM interval is calculated. Conventionally, the modulation pulses are generated centered with respect to the modulation period. This can result in very short output voltage pulses. This is avoided if, according to the invention, the switch-on times or switch-off times of the modulation pulses are synchronized, that is to say the rising edges or the falling edges of the modulation pulses are generated simultaneously within a respective modulation period of the pulse width modulation. In the case of the nonsynchronized edge, differences can of course still result on the basis of the desired motor voltage. However, the time duration of the resulting output voltage pulses doubles with respect to a center-centered drive scheme. In principle, this asymmetrical pulse width modulation can be applied over the entire modulation range. Alternatively, the asymmetric pulse width modulation can also be limited to times or duty cycles in which short pulses would increasingly occur between phase and phase. These are, for example, small duty cycles, all zero crossings and all ranges of maximum amplitude of the converter output voltages.The invention will be described in detail below with reference to the drawings. The following shows: FIG. 1 is a highly schematic view of a frequency converter designed to carry out the method according to the invention, FIG. 2 shows, by way of example, an output voltage generated by means of the frequency converter of FIG. 1, FIG. 3 shows pulse patterns of modulation pulses for driving an inverter of the frequency converter shown in FIG. 1 and resulting output voltage pulses for motor phases of a three-phase motor in a first operating mode, and FIG. 4 shows pulse patterns of modulation pulses for driving an inverter of the frequency converter shown in FIG. 1 and resulting output voltage pulses for motor phases of a three-phase motor in a second operating mode.FIG. 1 shows a highly schematic view of a frequency converter 100 which is designed to carry out the method according to the invention.The frequency converter 100 can have an intermediate circuit connection 15 for connecting the frequency converter 100 to a DC voltage intermediate circuit which conducts an intermediate circuit voltage UZK. Alternatively or additionally, the frequency converter 100 can have a rectifier 1 for independently generating the intermediate circuit voltage UZKfrom a mains AC voltage UN.The frequency converter further comprises an inverter 10 which is fed from the intermediate circuit voltage UZK.The inverter 10 includes a controller 11 for controlling the operation of the inverter 10. The inverter 10 conventionally has three inverter bridge branches with semiconductor switching means 14. In this respect, reference is also made to the relevant technical literature.The inverter 10 may further comprise a register 12 by means of which an amplitude resolution ΔA (see FIG. 2 ) is adjustable by writing a respective amplitude resolution value into the register 12. The amplitude resolution ΔA may be reduced, for example, by masking a number of bits of the amplitude resolution value.A slope ΔU / Δt of output voltage pulses APA, APB, APC, see FIG. 4, can be designed to be adjustable by means of suitable hardware measures.The inverter 10 is conventionally designed to generate three sinusoidal output voltages or phase voltages UA, UB, UC with adjustable frequency f and adjustable amplitude A from the intermediate circuit voltage UZK by means of pulse width modulation at an output terminal 13 having, for example, three poles, see in this regard the output voltage UA illustrated by way of example in FIG. 2. The output voltages or phase voltages UA, UB, UC are conventionally used for driving a three-phase electric motor 20 via an electrical line 30 and preferably have an identical frequency f and an identical amplitude A on average over time.FIG. 3 shows pulse patterns of modulation pulses MPA, MPB, and MPC for driving the inverter 10 and resultant output voltage pulses APA, APB, and APC for motor phases of the three-phase motor 20 in a first operating mode BA 1. A pulse MPA, MPB and MPC of the pulse pattern causes the upper semiconductor switching means 14 of the associated bridge branch to be switched on and the lower semiconductor switching means 14 of the associated bridge branch to be switched off. Without an active pulse MPA, MPB and MPC, respectively, the upper semiconductor switching means 14 of the bridge branch is switched off and the lower semiconductor switching means 14 of the bridge branch is switched on. In this respect, reference is made to the relevant technical literature.As can be seen from FIG. 3, in the first operating mode BA 1, within a respective modulation period MP of the pulse width modulation, the rising edges of all modulation pulses MPA, MPB, MPC are generated simultaneously.For the sake of illustration, FIG. 3 shows only a single modulation period MP of the pulse width modulation. It is understood that the illustrated modulation period MP is periodically followed by further modulation periods MP, optionally with a changed profile of the pulse patterns or output voltage pulses.FIG. 4 shows pulse patterns of the modulation pulses MPA, MPB, and MPC for driving the inverter 10 and resultant output voltage pulses APA, APB, and APC for the motor phases of the three-phase motor 20 in a second mode BA 2.As can be seen from FIG. 4, in the second operating mode BA 2, within a respective modulation period MP of the pulse width modulation, all modulation pulses MPA, MPB, MPC are generated symmetrically in the center with respect to the modulation period (MP).The first operating mode BA 1 is only set when the amplitudes of the output voltages UA, UB, UC fall below a first threshold value, for example fall below 50 V, and / or exceed a second threshold value, for example exceed 200 V; and / or in time ranges around a zero crossing of the output voltages UA, UB, UC.

Claims

Method for operating an inverter (10), having the step: - generating output voltages (UA, UB, UC) with adjustable frequency (f) and adjustable amplitude (A) from an intermediate circuit voltage (UZK) by means of pulse width modulation, wherein, for pulse width modulation within a respective modulation period (MP) of the pulse width modulation, modulation pulses (MPA, MPB, MPC) of adjustable duration associated with each output voltage (UA, UB, UC) are generated, - wherein, in a first operating mode (BA1), within a respective modulation period (MP) of the pulse width modulation, the rising edges or the falling edges of at least two modulation pulses (MPA, MPB, MPC) are generated simultaneously, characterized in that, in a second operating mode (BA2), within a respective modulation period (MP) of the pulse width modulation, all modulation pulses (MPA, MPB, MPC) are generated symmetrically in the center with respect to the modulation period (MP), and the first operating mode (BA1) is only set if the amplitudes of the output voltages (UA, UB, UC) fall below a first threshold value and / or exceed a second threshold value, and / or in time ranges around a zero crossing of the output voltages (UA, UB, UC).Method according to Claim 1, characterized in that - in the first operating mode (BA1), within a respective modulation period (MP) of the pulse width modulation, the rising edges or the falling edges of all modulation pulses (MPA, MPB, MPC) are generated simultaneously.Method according to one of the preceding claims, characterized in that - three output voltages (UA, UB, UC) are generated.Method according to one of the preceding claims, characterized in that - the output voltages (UA, UB, UC) are generated sinusoidally.Inverter (10), comprising: - a control device (11) for controlling the operation of the inverter (10), characterized in that - the control device (11) is configured to control the inverter (10) in such a way that it carries out a method according to one of the preceding claims.Frequency converter (100), comprising: - an intermediate circuit connection for connecting the frequency converter (100) to a DC voltage intermediate circuit which conducts an intermediate circuit voltage (UZK), and / or a rectifier (1) for generating an intermediate circuit voltage (UZK) from a mains AC voltage (UN), and - an inverter (10) according to claim 5, which is fed from the intermediate circuit voltage (UZK).

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