Semiconductor structure and method for its manufacture

Abstract

Semiconductor structure with: an insulating layer (204); a first FET device (FET: field-effect transistor), a second FET device and an isolation FET device between the first and the second FET device, which are fabricated on the insulating layer (204), wherein the first and the second FET device and the isolation FET device each have the following: a fin structure (220) produced on the insulating layer (204), wherein the fin structure has channel layers and a gate structure (250) enclosing the channel layers (212), and a first and a second epitaxial source / drain structure (240-2S1, 240-2S2, 240-1S1, 240-1S2) connected to opposite sides of the channel layers (212), with the isolation FET device being held in an off state; a front-side gate contact (254G) that is made on the first FET device opposite the insulating layer (204), wherein the front-side gate contact (254G) is electrically connected to the gate structure (250) of the first FET device; and a rear gate contact (272G3) which is made through the insulating layer (204) and is electrically connected to the gate structure (250) of the insulating FET device; wherein the semiconductor structure is a standard cell structure, and The isolation FET device is held in an off state to serve as an electrical isolation element between the first and second FET devices.

Description

Background of the invention; Field of the invention

[0001] The present invention relates to a semiconductor structure and a method for manufacturing it, and it relates in particular to a fin field-effect transistor with reduced substrate leakage loss and improved device density and a method for manufacturing it.

[0002] US 2021 / 0242322A1 discloses a semiconductor device with a back-side gate contact. The semiconductor device comprises a transistor mounted on a substrate, which includes a gate region, a channel region, a source region, and a drain region, with the gate region located adjacent to the channel region. The semiconductor device further comprises a back-side gate contact that is electrically connected to a bottom surface of the gate region and extends to the underside of the substrate.

[0003] EP 4 202 991 A1 discloses integrated circuit structures with rear-side power supply. In one example, an integrated circuit structure comprises a component layer within a cell boundary, wherein the component layer has a front and a back side and contains a source and a drain structure. On the front side of the component layer is a source and a drain trench contact structure. The source and drain trench contact structure is coupled to the source and drain structure. On the back side of the component layer is a metal layer. A via structure connects the metal layer to the source and drain trench contact structure. The via structure overlaps and runs parallel to a cell row boundary of the cell boundary.

[0004] US 2021 / 0343639A1 discloses an integrated circuit (IC) comprising a gate structure, a source epitaxy structure, a drain epitaxy structure, a front interconnect structure, a back dielectric layer, an epitaxial regeneration layer, and a back via. The source epitaxy structure and the drain epitaxy structure are located on opposite sides of the gate structure. The front interconnect structure is located over a front face of the source epitaxy structure and a front face of the drain epitaxy structure. The back dielectric layer is located over a back face of the source epitaxy structure and a back face of the drain epitaxy structure. The epitaxial regeneration layer is located on the back face of the first of the source epitaxy structures and the first of the drain epitaxy structures.The backside via extends through the backside dielectric layer and overlaps the epitaxial regeneration layer.

[0005] The invention is defined in the claims. Description of the state of the art

[0006] In recent years, modern integrated circuit (IC) devices have become increasingly multifunctional, and their size has decreased. While the miniaturization process generally increases production efficiency and reduces associated costs, it has also increased the complexity of IC processing and manufacturing. For example, fin field-effect transistors (FinFETs) have been introduced to replace planar transistors. Gate-all-around (GAA) structures, such as nanolayer metal-oxide-semiconductor field-effect transistors (nanolayer MOSFETs), have been developed for these FinFETs, exhibiting very good electrical properties. These properties include improved energy performance and better area scaling than is possible with current FinFET technologies.

[0007] While existing semiconductor structures with nanolayer transistors and existing fabrication methods are suitable for their intended purposes, they are not yet satisfactory in every respect. For example, additional implantation processes are required to implant desired dopants into a bottom surface of a gate structure of a GAA structure mounted on a substrate, in order to reduce substrate leakage. Furthermore, additional area is needed for an insulating element positioned between nanolayer transistors, and functional circuit routing can lead to low device density.

[0008] A novel semiconductor device is desirable to mitigate the problem of substrate leakage and increase device density. Brief description of the invention

[0009] In one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure comprises: an insulating layer; a first FET device (FET: field-effect transistor); a second FET device and an isolation FET device between the first and second FET devices, which are fabricated on the insulating layer; a front-side gate contact and a rear-side gate contact. The first FET device, the second FET device, and the isolation FET device each have a fin structure, a first epitaxial source / drain structure, and a second epitaxial source / drain structure. The fin structure has channel layers and a gate structure that surrounds the channel layers. The first and second epitaxial source / drain structures are connected to opposite sides of the channel layers, with the isolation FET device being held in an off state.The front gate contact is located on the first FET device opposite the insulating layer, and is electrically connected to the gate structure of the first FET device. The rear gate contact is located through the insulating layer and is electrically connected to the gate structure of the insulating FET device.

[0010] Furthermore, in one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure comprises: a first FET device and a second FET device arranged side by side; an isolation FET device; an insulating layer; an interlayer dielectric (ILD) layer; a rear-side gate contact; and a front-side source / drain contact. The first FET device, the second FET device, and the isolation FET device each have a fin structure, a first epitaxial source / drain structure, and a second epitaxial source / drain structure. The fin structure has channel layers and a gate structure that surrounds the channel layers. The first and second epitaxial source / drain structures are connected to opposite sides of the channel layers.The insulating layer has a top surface that is in contact with a lower portion of the gate structure of the first and second FET devices. The ILD layer is positioned on the upper portion of the gate structure of each of the first and second FET devices. The rear gate contact extends through the insulating layer and is electrically connected to the lower portion of the gate structure of the isolation FET device. The front source / drain contact extends through the ILD layer and is electrically connected to either the first or the second epitaxial source / drain structure of the isolation FET device.

[0011] Furthermore, in one embodiment of the present invention, a method for fabricating a semiconductor structure is provided. The method comprises providing a substrate having a substrate layer and an insulating layer on the substrate layer. The method further comprises fabricating a first FET device, a second FET device, and an isolating FET device between the first and second FET devices and directly on the insulating layer. The first FET device, the second FET device, and the isolating FET device each have a fin structure, a first epitaxial source / drain structure, and a second epitaxial source / drain structure. The fin structure has channel layers and a gate structure that surrounds the channel layers.The first and second epitaxial source / drain structures are connected to opposite sides of the channel layers, with the isolation FET device held in an off state. The method further comprises creating a front-side gate contact on the first FET device opposite the isolation layer, the front-side gate contact being electrically connected to the gate structure of the first FET device. The method further comprises removing the substrate layer from the isolation layer. The method further comprises creating a back-side gate contact that extends through the isolation layer and is electrically connected to the gate structure of the isolation FET device. Brief description of the drawings

[0012] The present invention can be better understood by reading the detailed description and examples below with reference to the accompanying drawings. Fig. Figure 1 shows a perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the disclosure. Fig. 1A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line A - A' of Fig. 1 according to some embodiments. Fig. Figure 2 shows a perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the disclosure. Fig. 2A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line A - A' of Fig. 2 according to some embodiments. Fig. Figure 3 shows a perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the disclosure. Fig. 3A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line A - A' of Fig. 3 according to some embodiments. Fig. Figure 4 shows a perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the disclosure. Fig. 4A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line A - A' of Fig. 4 according to some embodiments. Fig. Figure 5 shows a perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the disclosure. Fig. 5A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line A - A' of Fig. 5 according to some embodiments. Fig. 5B shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line B - B' of Fig. 5 according to some embodiments. Fig. 5C shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along a line C - C' of Fig. 5 according to some embodiments. Fig. 6A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along line A - A' of Fig. 5 according to some embodiments. Fig. 6B shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along line B - B' of Fig. 5 according to some embodiments. Fig. 6C shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along the line C - C' of Fig. 5 according to some embodiments. Fig. 7A shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along line A - A' of Fig. 5 according to some embodiments. Fig. 7B shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along line B - B' of Fig. 5 according to some embodiments. Fig. 7C shows a sectional view of an intermediate stage in the fabrication of the semiconductor structure along the line C - C' of Fig. 5 according to some embodiments. The Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. Figure 12 shows sectional views of intermediate stages in the fabrication of the semiconductor structure along the line C - C' of Fig. 5 according to some embodiments. Detailed description of the invention

[0013] The following description serves to explain the general principles of the disclosure with reference to some embodiments. The invention is defined in the claims.

[0014] The inventive concept is described in full below with reference to the accompanying drawings, which show exemplary embodiments of the inventive concept. The advantages and features of the inventive concept and the methods for achieving them should become apparent from the exemplary embodiments described in more detail below with reference to the accompanying drawings. Therefore, the exemplary embodiments serve only to illustrate the inventive concept and to inform those skilled in the art about the category of the inventive concept. Furthermore, the drawings are schematic only. In the drawings, some elements may be enlarged for illustrative purposes and may not be drawn to scale. The dimensions and relative dimensions do not correspond to the actual dimensions when using some embodiments of the disclosure.

[0015] In some embodiments, a semiconductor structure is provided with FET devices, e.g., fin field-effect transistors (FinFETs), such as a gate-all-around transistor (GAA) device. Each FET device has a fin structure fabricated on a semiconductor-on-insulator (SOI) substrate, which includes an upper semiconductor layer containing first semiconductor atoms, e.g., silicon (Si), a middle insulating layer, and a lower substrate layer. Before a stack of alternating channel and sacrificial layers of the fin structure is fabricated, an epitaxial growth process of a semiconductor capping layer is performed, which contains the first semiconductor atoms and second semiconductor atoms, e.g., silicon (Si).Germanium (Ge) is contained in the semiconductor capping layer, and a subsequent thermal process is carried out to drive the second semiconductor atoms of the capping layer into the upper semiconductor layer. This allows the capping layer and the upper semiconductor layer to jointly form another sacrificial layer with a composition (e.g., a Ge concentration in atomic percent) that is similar to or identical to the composition of the sacrificial layers in the stack of alternating channel and sacrificial layers of the fin structure. The sacrificial layers formed by the upper semiconductor layer and the stack of alternating channel and sacrificial layers are then replaced by a gate structure that encloses the channel layers.The gate structure and the epitaxial source / drain structures of the FET device can be fabricated directly on the middle insulating layer of the SOI substrate, without being in contact with any semiconductor layer other than the channel layers of the fin structure. Therefore, the problem of substrate leakage loss can be mitigated without implanting additional dopants into the undersides of the gate structure and the epitaxial source / drain structures.

[0016] Furthermore, the semiconductor structure features an isolation FET device positioned between the other FET devices. The isolation FET device is held in an off state to act as an electrical isolation element between the FET devices. The isolation FET device has a smaller area than conventional STI (shallow trench insulation) elements. Additionally, the semiconductor structure incorporates a backside interconnect structure fabricated directly on the insulating layer opposite a frontside interconnect structure. The backside interconnect structure provides additional area for traces for the isolation FET device and for circuitry for other FET devices located within it. Therefore, the area of ​​the resulting semiconductor structure can be further reduced.

[0017] The Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. Figure 5 shows perspective views of intermediate stages in the fabrication of a semiconductor structure 550 according to some embodiments of the disclosure. Fig. 1A, Fig. 2A, Fig. 5A, Fig. 4A and Fig. Figure 5A shows sectional views of intermediate stages in the fabrication of the semiconductor structure 550 along a line A - A' in the Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5 according to some embodiments. The Fig. 6A and Fig. Figure 7A shows sectional views of later intermediate stages in the fabrication of the semiconductor structure 550 in a channel region along line A - A' of Fig. 5 according to some embodiments. The Fig. 6B and Fig. Figure 7B shows sectional views of later intermediate stages in the fabrication of the semiconductor structure 550 in a source / drain region along a line B - B' of Fig. 5 according to some embodiments. The Fig. 6C and Fig. Figure 7C shows sectional views of later intermediate stages in the fabrication of the semiconductor structure 550 along a fin structure 220-1 along the line C - C' of Fig. 5 according to some embodiments. The Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. Figure 12 shows sectional views of later intermediate stages in the fabrication of the semiconductor structure 550 along the line C - C' of Fig. 5 according to some embodiments. In the present disclosure, reference numerals and / or reference symbols may be repeated in the various examples.

[0018] As in the Fig. 1 and Fig. As shown in Figure 1A, an SOI substrate 200 is provided. The SOI substrate 200 has a lower substrate layer 202, a middle insulating layer 204, and an upper semiconductor layer 206. The middle insulating layer 204, which is fabricated to completely cover a top surface 202T of the lower substrate layer 202, can be a buried oxide layer (BOX layer) or a silicon oxide layer. The upper semiconductor layer 206, which is fabricated to completely cover a top surface 204T of the middle insulating layer 204, can contain initial semiconductor atoms. For example, the upper semiconductor layer 206 has silicon (Si) or silicon germanium (SiGe), and the initial semiconductor atoms are silicon (Si). Alternatively, the upper semiconductor layer 206 may contain only the initial semiconductor atoms (e.g., Si). In some embodiments, the upper semiconductor layer 206 is thinner than the lower substrate layer 202 and the middle insulating layer 204.The thickness of the upper semiconductor layer 206 can be, for example, approximately 8 nm to approximately 12 nm. In some embodiments, the lower substrate layer 202 and the upper semiconductor layer 206 have the same composition.

[0019] As in the Fig. 2 and Fig. As shown in Figure 2A, a semiconductor capping layer 208 is grown epitaxially on the upper semiconductor layer 206. In some embodiments, the semiconductor capping layer 208 contains the first semiconductor atoms and second semiconductor atoms that are different from the first semiconductor atoms. For example, the semiconductor capping layer 208 is a silicon-germanium layer (SiGe layer), the first semiconductor atoms are silicon (Si), and the second semiconductor atoms are germanium (Ge). In some embodiments, the composition of the semiconductor capping layer 208 is the same as that of subsequently fabricated second sacrificial layers 214.In some embodiments, the concentration (in atomic percent) of the second semiconductor atoms in the semiconductor capping layer 208 is higher than that of the subsequently produced second sacrificial layers 214. For example, if the semiconductor capping layer 208 is a silicon germanium layer (SiGe layer), the Ge concentration of the semiconductor capping layer 208 can be approximately 25 atomic percent to approximately 55 atomic percent, e.g., 50 atomic percent. In some embodiments, the thickness of the semiconductor capping layer 208 is equal to or greater than that of the upper semiconductor layer 206. For example, the thickness of the semiconductor capping layer 208 is approximately 8 nm to approximately 20 nm. In some embodiments, the germanium-containing layer 208 is epitaxially grown using an MBE process (molecular beam epitaxy), a MOCVD process (metal-organic chemical vapor deposition), and / or other suitable epitaxial growth processes.

[0020] As in the Fig. 3 and Fig. As shown in 3A, a thermal process is then carried out to decapitate the second semiconductor atoms (e.g. Ge atoms) of the semiconductor capping layer 208 ( Fig. 2 and Fig. 2A) into the upper semiconductor layer 206 ( Fig. 2 and Fig. 2A). Furthermore, the semiconductor capping layer 208 and the upper semiconductor layer 206 can have a uniform concentration of second semiconductor atoms (e.g., Ge atoms). After carrying out the thermal process, the semiconductor capping layer 208 and the upper semiconductor layer 206 collectively form a first sacrificial layer 210. The first sacrificial layer 210 contains the first semiconductor atoms and second semiconductor atoms that are different from the first semiconductor atoms. For example, the first sacrificial layer 210 is a SiGe layer, the first semiconductor atoms are silicon (Si), and the second semiconductor atoms are germanium (Ge). In some embodiments, a concentration (e.g., a Ge concentration) of the second semiconductor atoms of the semiconductor capping layer 208 ( Fig. 2 and Fig. 2A) higher than that of the first sacrificial layer 210. If the first sacrificial layer 210 is, for example, a silicon germanium layer (SiGe layer), the Ge concentration of the first sacrificial layer 210 is approximately 20 atomic% to approximately 30 atomic%, e.g., 25 atomic%.

[0021] In some further embodiments, the upper semiconductor layer 206 of the SOI substrate 200 and the subsequently produced second sacrificial layers 214 both contain the first and second semiconductor atoms, such as a SiGe layer. The upper semiconductor layer 206 can serve as the first sacrificial layer, and the processes for producing the sacrificial layer 210 can be omitted.

[0022] As in the Fig. 4 and Fig. As shown in Figure 4A, a stack 216 of alternating channel layers 212 and second sacrificial layers 214 is grown epitaxially on the first sacrificial layer 210. The first sacrificial layer 210 and the second sacrificial layers 214 are positioned between the channel layers 212. The first sacrificial layer 210 and the second sacrificial layers 214 define a distance between adjacent channel layers 212 and are subsequently removed. In some embodiments, the first sacrificial layer 210 and the second sacrificial layers 214 can be made from the same semiconductor materials and can have the same thickness. The first sacrificial layer 210 and the second sacrificial layers 214 can both contain the first and second semiconductor atoms. The first sacrificial layer 210 can have a first composition, and the second sacrificial layers 214 can have a second composition. The second composition is the same as the first composition.For example, the first sacrificial layer 210 and the second sacrificial layers 214 can be SiGe layers with the same Ge concentration. In some embodiments, the first sacrificial layer 210 has a first thickness T1, and the second sacrificial layers 214 have a second thickness T2 that is equal to the first thickness T1. For example, the first thickness T1 and the second thickness T2 are each approximately 16 nm to approximately 32 nm. The first thickness T1 and the second thickness T2 can have desired ranges according to the device performance.

[0023] As in the Fig. 4 and Fig. As shown in Figure 4A, after the epitaxial growth of the stack 216 of alternating channel layers 212 and second sacrificial layers 214, a bottom layer of the channel layer 212 is in contact with the first sacrificial layer 210. In some embodiments, the channel layers 212 can contain the first semiconductor atoms (e.g., Si) but not the second semiconductor atoms (e.g., Ge). The channel layers 212 have a third composition. This third composition differs from the first composition of the first sacrificial layer 210 and the second composition of the second sacrificial layers 214. For example, if the first sacrificial layer 210 and the second sacrificial layers 214 are SiGe layers, the channel layers 212 are silicon layers (Si layers). Furthermore, the first and third compositions (or the second and third compositions) can have different oxidation rates and / or etch selectivities.In some embodiments, the stack 216 of alternating channel layers 212 and second sacrificial layers 214 contains a first number of channel layers 212 and a second number of second sacrificial layers 214, the first number being different from the second number. For example, the first number is greater than the second number. A difference between the first and second numbers is, for example, 1. In some embodiments, the total number of first sacrificial layers 210 and second sacrificial layers 214 is equal to the number of channel layers 212. It should be noted that although three channel layers 212 and two second sacrificial layers 214 are produced in the figures, the stack 216 of alternating channel layers 212 and second sacrificial layers 214 may contain more or fewer channel layers 212 and second sacrificial layers 214.For example, depending on the desired number of channel layers for fabricating transistors, the stack 216 of alternating channel layers 212 and second sacrificial layers 214 can individually contain 2 to 10 channel layers 212 and 1 to 9 second sacrificial layers 214. In some embodiments, the channel layers 212 have a uniform thickness. Furthermore, the thickness of the channel layers 212 can have a desired range according to the device performance. For example, the thickness of the channel layers 212 can be similar to the first thickness T1 of the first sacrificial layer 210 and the second thickness T2 of the second sacrificial layers 214. In some embodiments, the channel layers 212 and the second sacrificial layers 214 are epitaxially grown using an MBE process, a MOCVD process, or another suitable epitaxial growth process.

[0024] As in the Fig. As shown in Figures 5 and 5A to 5C, the middle insulating layer 204, the first sacrificial layer 210, and the stack 216 of alternating channel layers 212 and second sacrificial layers 214 are structured to create fin structures 220-1 and 220-2 projecting from the SOI substrate 200 and a trench 224 between the fin structures 220-1 and 220-2. The fin structures 220-1 and 220-2 can be used to fabricate GAA devices with different or the same conductivity types. Each of the fin structures 220-1 and 220-2 has a top part 220A and a base part 220B. The upper part 220A is produced by structuring the first sacrificial layer 210 and the stack 216 of alternating channel layers 212 and second sacrificial layers 214. The base part 220B is produced by structuring the middle insulating layer 204 (e.g., of an upper part) of the SOI substrate 200.This means that the base part 220B is made from the middle insulating layer 204.

[0025] As in the Fig. 5A and Fig. As shown in Figure 5B, the trench 224 is formed through the entire stack 216 of alternating channel layers 212 and second sacrificial layers 214, the entire first sacrificial layer 210, and part of the middle insulating layer 204. Therefore, the middle insulating layer 204 is exposed at one bottom of the trench 224. In some embodiments, the fin structures 220-1 and 220-2 are fabricated by double or multiple structuring processes with several cycles of photolithography and etching. The etching process can be dry etching (e.g., reactive ion etching), wet etching, and / or another suitable process.

[0026] As in the Fig. As shown in Figures 6A to 6C, after the fin structures 220-1 and 220-2 have been fabricated, insulating elements 228 are fabricated on the side walls of the base part 220B of each of the fin structures 220-1 and 220-2. The insulating elements 228 are fabricated around the base part 220B of each of the fin structures 220-1 and 220-2. Furthermore, the top surfaces 228T of the insulating elements 228 are lower than the upper surface of the base part 220B in the channel area of ​​each of the fin structures 220-1 and 220-2. In some embodiments, the insulating element 228 contains silicon oxide, silicon nitride, silicon oxide nitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, the insulating element 228 is fabricated by performing a deposition of an insulating material (not shown), a planarization process, and a recessing process.The deposition process can be performed to deposit the insulating material (not shown) that fills the trench 224. The deposition process can include thermal growth, spin coating, chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. A planarization process can be performed so that a top surface of the insulating material (not shown) is at the same level as a top surface of each of the fin structures 220-1 and 220-2. The planarization process can include chemical-mechanical polishing (CMP) or other suitable planarization processes. The recession process can be performed to recess the insulating material to produce the insulating elements 228.The recession process can include reactive ion etching (RIE), dry etching, wet etching, or other suitable etching processes.

[0027] As in the Fig. As shown in Figures 6A to 6C, dummy gate structures 230 are fabricated on the channel regions of the fin structures 220-1 and 220-2 such that they extend over the insulating elements 228. The dummy gate structures 230 can be used to define source / drain regions and channel regions of resulting FET devices (e.g., FET devices 500-1 and 500-2 and an insulating FET device 500-3) of the semiconductor structure 550. In some embodiments, each of the dummy gate structures 230 has a dielectric dummy gate layer (not shown) and a dummy gate electrode layer (not shown) arranged above the dielectric dummy gate layer.In some embodiments, the dielectric dummy gate layer can comprise silicon oxide, silicon nitride, silicon oxide nitride (SiON), or other suitable dielectric materials, and the dummy gate electrode layer can comprise polycrystalline silicon (Poly-Si), polycrystalline silicon germanium (Poly-SiGe), or other suitable conductive materials. In some embodiments, each of the dummy gate structures 230 is fabricated by a deposition process and a subsequent structuring process. The structuring process is performed using hard mask structures 232 fabricated on the dummy gate structures 230 as masks covering the channel regions of the fin structures 220-1 and 220-2. In some embodiments, each of the hard mask structures 232 has multiple layers comprising a silicon nitride layer and a silicon oxide layer on top of the silicon nitride layer.

[0028] As in the Fig. As shown in Figures 6A to 6C, gate spacers 234 are then fabricated on the sidewalls of each of the dummy gate structures 230. In some embodiments, the gate spacers 234 contain a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or other suitable dielectric materials. In some embodiments, the gate spacers 234 are fabricated by a deposition process followed by a etching process. The deposition process can be performed to deposit the dielectric material over the top and sidewalls of each of the dummy gate structures 230. The deposition process can include CVD, flowable CVD, subatmospheric pressure CVD (SACVD), PVD, ALD, or other suitable deposition processes.The etch-back process can be performed to remove a portion of the dielectric material above the top surface of each of the dummy gate structures 230, thereby exposing the hard mask structures 232 and creating the gate spacers 234. The etch-back process can involve wet etching, dry etching, or a combination thereof.

[0029] As in the Fig. 6B and Fig. As shown in Figure 6C, portions of the fin structures 220-1 and 220-2 are removed until the middle insulating layer 204 is exposed to create source / drain recesses 236 in the source / drain regions of each of the fin structures 220-1 and 220-2. The upper part 220A and an upper region of the base part 220B in the source / drain regions of each of the fin structures 220-1 and 220-2 are anisotropically etched using an anisotropic etching process with the dummy gate structures 230 and the gate spacers 234 as etch masks. The source / drain recesses 236 can be created to extend into the base part 220B beneath the top surface 228T of the insulating element 228. In some further embodiments, only the upper part 220A is removed by the anisotropic etching process, and the etching process ends at the base part 220B in the source / drain regions of each of the fin structures 220-1 and 220-2.Therefore, the source / drain recesses 236 cannot be created in such a way that they extend beneath the top surface 228T of the insulating element 228. The middle insulating layer 204 in the source / drain regions is exposed by the source / drain recesses 236. In some embodiments, the anisotropic etching process is a dry etching.

[0030] As in Fig. As shown in Figure 6C, the first sacrificial layer 210 and the second sacrificial layers 214, which have been exposed by the source / drain recesses 236, are then laterally and partially removed by an etching process to create recesses (not shown). During the etching process, the first sacrificial layer 210 and the second sacrificial layers 214 can have a higher etch rate than the channel layers 212. In some embodiments, the etching process can be a wet etching process, a dry etching process, or a combination thereof.

[0031] As in Fig. As shown in Figure 6C, after the source / drain recesses 236 and the recesses (not shown) have been created, internal spacers 238 are produced at the lateral ends of the first sacrificial layer 210 and the second sacrificial layers 214. The internal spacers 238 produced at the lateral ends of the first sacrificial layer 210 are in contact with the middle insulating layer 204. The internal spacers 238 are produced vertically adjacent to each other between and in contact with the channel layers 212. Furthermore, the internal spacers 238 that are in contact with the middle insulating layer 204 of the SOI substrate 200 are also in contact with the bottommost layer of the channel layers 212.In some embodiments, the internal spacers 238 comprise dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. In some embodiments, the internal spacers 238 are produced by depositing a dielectric material (not shown) and a subsequent etching process. The deposition process can be performed to fill the recesses with the dielectric material. In some embodiments, the deposition process includes an ALD or another suitable deposition process. The etching process can be performed to partially remove the insulating layer outside the recesses, thus forming the internal spacers 238.

[0032] As in the Fig. 6B and Fig. As shown in Figure 6C, epitaxial source / drain structures 240 are then produced in the source / drain recesses 236, comprising epitaxial source / drain structures 240-1S1, 240-1S2, 240-2S1, and 240-2S2. The epitaxial source / drain structures 240 are connected to the channel layers 212. Lower parts 240B of the epitaxial source / drain structures 240 are in contact with the middle insulating layer 204 of the SOI substrate 200. Furthermore, the epitaxial source / drain structures 240 are insulated from the bottom substrate layer 202 of the SOI substrate 200 by the middle insulating layer 204. The uppermost layer of the channel layers 212 and the top surface 228T of the insulating elements 228 are located vertically between an upper part 240T and the lower part 240B of the corresponding epitaxial source / drain structure 240. Since the upper semiconductor layer 206 ( Fig. 1 and Fig. 1A) the SOI substrate 200 is converted into the first sacrificial layer 210 and in the source / drain regions each of the fin structures 220-1 and 220-2 is removed in the processes described above, and the lateral ends of the first sacrificial layers 210 in the channel region are covered by the internal spacers 238, then, apart from the corresponding channel layers 212, no subsequently produced epitaxial source / drain structures 240 are in contact with a semiconductor layer above the middle insulating layer 204 of the SOI substrate 200. The substrate leakage loss of the resulting semiconductor structure 550 can be remedied.

[0033] In some embodiments, the epitaxial source / drain structures 240 comprise epitaxial semiconductor materials that are doped in situ or ex situ with an n- or p-type dopant. For example, the epitaxial source / drain structures 240 can comprise phosphorus-doped silicon (Si) for fabricating epitaxial source / drain structures for an n-type semiconductor device (e.g., an n-GAA transistor). The epitaxial source / drain structures 240 can also comprise boron-doped silicon germanium (SiGe) for fabricating epitaxial source / drain structures for a p-type semiconductor device (e.g., a p-GAA transistor). In some embodiments, the epitaxial source / drain structures 240 are epitaxially grown only from the channel layers 212 by MBE, MOCVD, vapor phase epitaxy (VPE) or other suitable epitaxial growth processes.

[0034] As in the Fig. As shown in 7A to 7C, a contact etch stop layer (CESL; not shown) and an ILD layer 242 of a front-side interconnect structure 260 (which is shown in Fig. (as shown in Figure 8) is produced on the epitaxial source / drain structures 240 and the insulating elements 228. In some embodiments, the CESL comprises silicon nitride, silicon oxide nitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the CESL is produced by CVD, PVD, ALD, or other suitable deposition processes. In some embodiments, the ILD layer 242 comprises borophosphosilicate glass (BPSG), silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), TEOS oxide (TEOS: tetraethyl orthosilicate), and / or other suitable dielectric materials. In some embodiments, the ILD layer 242 is produced by CVD, PVD, ALD, or other suitable deposition processes. After the CESL and the ILD layer 242 have been produced, a planarization process can be carried out until the top surfaces of the dummy gate structures 230 are exposed.The planarization process can be a CMP, a re-etching, or a combination of both.

[0035] As in the Fig. As shown in Figures 7A to 7C, after the formation of the epitaxial source / drain structures 240, the dummy gate structures 230, the first sacrificial layer 210, and the second sacrificial layers 214 are selectively removed to expose the channel layers 212 in the channel regions. Additionally, trenches (not shown) are created between the gate spacers 234. In some embodiments, during the selective removal of the first sacrificial layer 210 and the second sacrificial layers 214, a first etch selectivity between the first sacrificial layer 210 and the channel layers 212 is equal to a second etch selectivity between the second sacrificial layers 214 and the channel layers 212. Therefore, the first sacrificial layer 210 and the second sacrificial layers 214 can be removed from the channel layers 212 simultaneously.Furthermore, the dummy gate structures 230, the first sacrificial layer 210, and the second sacrificial layers 214 are selectively removed without damaging the channel layers 212 and the gate spacers 234. After the removal of the first sacrificial layer 210, the top surface 204T of the middle insulating layer 204, separated from the lower substrate layer 202, can serve as the top surface of a resulting substrate 200R. In some embodiments, the dummy gate structures 230, the first sacrificial layer 210, and the second sacrificial layers 214 are selectively removed by a selective etching process, which may be a selective wet etching process, a selective dry etching process, or a combination thereof.

[0036] As in the Fig. As shown in Figures 7A to 7C, gate structures 250 are then fabricated to enclose the channel layers 212, resulting in fin structures 220-1R and 220-2R. Fin structure 220-1R comprises fin structures 220-1R1, 220-1R2, and 220-1R3. The gate structure 250 is also fabricated to fill the gap (not shown) between the gate spacers 234. In some embodiments, each of the fin structures 220-1R1, 220-1R2, and 220-1R3 includes the channel layers 212 and the gate structure 250 enclosing the channel layers 212. Since the first sacrificial layer 210 and the second sacrificial layers 214 have the same thickness (the first thickness T1 of the first sacrificial layer 210 and the second thickness T2 of the second sacrificial layers 214, which in Fig. (as shown in Figure 4A), a first distance D1 between the bottom layer of the channel layers 212 and the top 204T of the middle insulating layer 204 can be equal to a second distance D2 between the bottom layer of the channel layers 212 and the adjacent channel layer 212 opposite the middle insulating layer 204. In other words, a first part (e.g., a bottom part 250B) of the gate structure 250 between the bottom layer of the channel layers 212 and the top 204T of the middle insulating layer 204 has a first thickness (equal to the first distance D1), and a second part 250S of the gate structure 250 between the bottom layer of the channel layers 212 and the adjacent channel layer 212 opposite the middle insulating layer 204 has a second thickness (equal to the second distance D2). The second thickness is equal to the first thickness. Furthermore, the internal spacers 238 are arranged at the lateral ends of the gate structure 250.The internal spacers 238 on the lower part 250B of the gate structure 250 are in contact with the middle insulating layer 204 of the substrate 200R. In some embodiments, each of the fin structures 220-1R1, 220-1R2, and 220-1R3 has the base part 220B beneath the gate structure 250 and the channel layers 212. The base part 220B is also connected to the gate structure 250. In some embodiments, the gate structure 250 can be insulated from the lower substrate layer 202 by the middle insulating layer 204. This eliminates the substrate leakage loss of the resulting semiconductor structure 200.

[0037] In some embodiments, the gate structure 250 comprises a dielectric gate layer (not shown) enclosing the channel layers 212 and a gate electrode layer (not shown) produced on the dielectric gate layer in the channel region. In some embodiments, the dielectric gate layer comprises silicon oxide, silicon nitride, a high-k dielectric material, or another suitable dielectric material, or combinations thereof. In some embodiments, the dielectric gate layer is produced by CVD, PVD, ALD, or other suitable deposition processes. In some embodiments, the gate electrode layer comprises conductive materials. In some embodiments, the gate electrode layer is produced by CVD, PVD, ALD, or other suitable deposition processes.After carrying out the aforementioned processes, the resulting semiconductor structure 550 is completely manufactured, comprising FET devices 500, FET devices 500-1 and 500-2 and an isolation FET device 500-3.

[0038] In some embodiments, the FET devices 500-1 and 500-2 and the isolation FET device 500-3 are arranged side by side. The isolation FET device 500-3 is positioned between the FET device 500-1 and the FET device 500-2. The epitaxial source / drain structure 240-2S2 of the isolation FET device 500-3 is also used as the epitaxial source / drain structure 240-2S2 of the adjacent FET device 500-2. The epitaxial source / drain structure 240-1S1 of the isolation FET device 500-3 is also used as the epitaxial source / drain structure 240-1S1 of the adjacent FET device 500-1. In some embodiments, the isolation FET device 500-3 is held in an off state to be used as an electrical and physical isolation element between the FET devices 500-1 and 500-2.Compared to conventional semiconductor structures embedded in a substrate, such as STI elements, the area of ​​the insulating element of the resulting semiconductor structure can be further reduced 550.

[0039] In some embodiments, the FET devices 500-1 and 500-2 and the isolation FET device 500-3 each comprise the substrate 200R, the fin structure 220-1R (comprising fin structures 220-1R1, 220-1R2, and 220-1R3), the fin structure 220-2R, and the epitaxial source / drain structures 240. The substrate 200R, which is formed from the SOI substrate 200, has the lower substrate layer 202 and the middle insulating layer 204 on the lower substrate layer 202. The fin structures 220-1R1, 220-1R2, and 220-1R3 (or the fin structure 220-2R) are formed on top of the substrate 200R. Each of the fin structures 220-1R1, 220-1R2 and 220-1R3 (or the fin structure 220-2R) has the channel layers 212 and the gate structure 250, which surrounds the channel layers 212. The epitaxial source / drain structures 240 are connected to the channel layers 212.A lower part 240B of each of the epitaxial source / drain structures 240 is in contact with the middle insulating layer 204 of the substrate 200R. The upper semiconductor layer 206 ( Fig. 1 and Fig. 1A) The SOI substrate 200 is converted into the first sacrificial layer 210, which is made from the first semiconductor atoms (e.g., Si), by driving in second semiconductor atoms (e.g., Ge) from the semiconductor capping layer produced on it. The first sacrificial layer 210 and the second sacrificial layers 214, which are made from the first semiconductor atoms (e.g., Si) and the second semiconductor atoms (e.g., Ge), are then removed before the gate structure 250 is fabricated. The epitaxial source / drain structures 240 are in contact with no semiconductor layer above the middle insulating layer 204 of the substrate 200R except for the channel layers 212. Furthermore, the gate structure 250 can be insulated from the lower substrate layer 202 of the substrate 200R by the middle insulating layer 204.This allows the substrate leakage loss of the resulting semiconductor structure 550 to be eliminated without implanting additional dopants into the undersides of the gate structure and the epitaxial source / drain structures.

[0040] As in Fig. As shown in Figure 8, the ILD layer 242 is structured to create openings (not shown) to expose the epitaxial source / drain structure 240-1S1 and the gate structure 250 of the FET device 500-1, and the epitaxial source / drain structures 240-2S1 and 240-2S2 of the FET device 500-2. A deposition process and a subsequent planarization process are then performed to fabricate a front-facing gate contact 254G1 and front-facing source / drain contacts 254S1, 254S2, and 254S3 of the front-facing interconnect structure 260. The front gate contact 254G1 and the front source / drain contacts 254S1, 254S2 and 254S3 of the front interconnect structure 260 are manufactured above the top surface 204T of the insulating layer 204 such that they pass through the ILD layer 242.Furthermore, the front-side gate contact 254G1 and the front-side source / drain contacts 254S1, 254S2, and 254S3 are made on the FET devices 500-1 and 500-2 and the isolation FET device 500-3 relative to the insulating layer 204. In some embodiments, the front-side gate contact 254G1 is electrically connected to the gate structure 250 of the FET device 500-1. The front-side source / drain contacts 254S1 and 254S3 of the front-side interconnect structure 260 are electrically connected to the epitaxial source / drain structures 240-1S1 and 240-2S2 of the isolation FET device 500-3. Furthermore, the front source / drain contact 254S2 is electrically connected to the epitaxial source / drain structure 240-2S1 of the FET device 500-2.In some embodiments, the front-side gate contact 254G1 and the front-side source / drain contacts 254S1, 254S2, and 254S3 contain copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), cobalt (Co), and / or silicide. In some embodiments, the deposition process includes CVD, plasma-enhanced CVD (PECVD), PVD, ALD, or other suitable deposition processes. In some embodiments, the planarization process is CMP, back-etching, or a combination thereof.

[0041] Interconnect elements 264S1, 264S2, 264S3, and 264G1 and an intermetal dielectric layer (IMD layer) 262 of the front-side interconnect structure 260 are fabricated on the ILD layer 242. The interconnect elements 264S1, 264S2, 264S3, and 264G1 are fabricated in the IMD layer 262. The interconnect element 264S1 is electrically connected to the front-side source / drain contact 254S1. The interconnect element 264S2 is electrically connected to the front-side source / drain contact 254S2. The interconnect element 264S3 is electrically connected to the front-side source / drain contact 254S3. The interconnect element 264G1 is electrically connected to the front-side source / drain contact 254G1. In some embodiments, the IMD layer 262 has a composite layer made of dielectric materials.In some embodiments, the processes and materials for fabricating the IMD layer 262 may be similar to or identical with those for fabricating the ILD layer 242. In some embodiments, the interconnect elements 264S1, 264S2, 264S3, and 264G1 comprise: vertical interconnect parts (perpendicular to the top surface 204T of the middle insulating layer 204), such as conductive vias; and horizontal interconnect parts (parallel to the top surface 204T of the middle insulating layer 204), such as conductive traces. In some embodiments, the processes and materials for manufacturing the front source / drain contacts 254S1, 254S2 and 254S3 and the front gate contact 254G1 may be similar to or the same as those for manufacturing the interconnect elements 264S1, 264S2, 264S3 and 264G1.After performing the aforementioned processes, the front-side interconnect structure 260, comprising the ILD layer 242, the front-side gate contact 254G1, the front-side source / drain contacts 254S1, 254S2 and 254S3, the IMD layer 262 and the interconnect elements 264S1, 264S2, 264S3 and 264G1, is completely manufactured. The number of IMD layers 262, the number of front-side gate contacts 254G1, the number of front-side source / drain contacts 254S1, 254S2 and 254S3 and the number of interconnect elements 264S1, 264S2, 264S3 and 264G1, which are in . Fig. The figures shown in point 8 are only examples.

[0042] A front-side passivation layer 270 is then produced on the front-side interconnect structure 260. The front-side passivation layer 270 is produced to protect the underlying front-side interconnect structure 260, the FET devices 500-1 and 500-2, and the isolation FET device 500-3. In some embodiments, the front-side passivation layer 270 comprises silicon oxide, undoped silicate glass (USG), or other suitable dielectric materials. In some embodiments, the passivation layer 270 is produced by a deposition process that includes CVD, PVD, or other suitable deposition processes.

[0043] Then, pads 272 and 274 are produced by the first passivation layer 270 and are electrically connected to the front-side interconnect structure 260. For example, pad 272 is electrically connected to the interconnect element 264S2, and pad 274 is electrically connected to the interconnect element 264G1 of the front-side interconnect structure 260. In some embodiments, pads 272 and 274 provide electrical connections between the resulting semiconductor structure 550 and external circuits (not shown). In some embodiments, pads 272 and 274 comprise copper (Cu), aluminum (Al), or other suitable conductive materials. Furthermore, the number of pads 272 and 274 in Fig. The figures shown in 8 are for illustrative purposes only.

[0044] As in Fig. As shown in Figure 9, a surface 271 of the front-side passivation layer 270 is then mounted to a support 100 opposite the front-side interconnect structure 260. Subsequently, the Fig. The structure shown in Figure 8 can be used for reverse processes, which are located in the Fig. 10, Fig. 11 to Fig. 12 are shown.

[0045] As in Fig. As shown in 10, the lower substrate layer 202 (see Fig. 9) of the substrate 200R is removed from the insulating layer 204 until the underside 204B of the insulating layer 204 is exposed. In some embodiments, the lower substrate layer 202 is removed using CMP or other suitable removal processes.

[0046] As in Fig. As shown in Figure 11, a rear gate contact 272G3 and a rear source / drain contact 272S1 of a rear interconnect structure 280 (which is shown in Figure 11) are then connected. Fig. (as shown in Figure 12) is made through the insulating layer 204. The rear gate contact 272G3 is electrically connected to the lower part 250B of the gate structure 250 of the isolation FET device 500-3. Furthermore, the rear source / drain contact 272S1 is electrically connected to the lower part 240B of the epitaxial source / drain structure 240-1S2 of the FET device 500-1. The rear source / drain contact 272S1 can be connected to a Fig. The circuit 282 shown in Figure 12 (which has power lines Vdd and Vss) can be electrically connected. Therefore, the rear source / drain contact 272S1 can serve as a Vdd / Vss contact. In some embodiments, the processes and materials for manufacturing the rear gate contact 272G3 and the rear source / drain contact 272S1 may be similar to or the same as those for manufacturing the front gate contact 254G1 and the front source / drain contacts 254S1, 254S2, and 254S3.

[0047] As in Fig. As shown in Figure 12, a circuit 284P, interconnect elements 284TG and 284, and an IMD layer 282 of the rear interconnect structure 280 are fabricated directly on the underside 204B of the insulating layer 204. The circuit 284P and the interconnect elements 284TG and 284 are fabricated in the IMD layer 282. The circuit 284P with power lines Vdd and Vss (not shown) is located on the back side 204B of the insulating layer 204 and is electrically connected to the lower part 240B of the epitaxial source / drain structure 240-1S2 of the FET device 500-1 via the rear source / drain contact 272S1, which extends through the insulating layer 204. Therefore, the 284P circuit can serve as a rear-side current loop for the 550 semiconductor structure.The interconnect element 284TG is electrically connected to the lower part 250B of the gate structure 250 of the isolation FET device 500-3 via the rear gate contact 272G3, which extends through the insulating layer 204. Therefore, the isolation FET device 500-3 can be switched off by applying suitable voltages to the interconnect elements 264S1 and 264S3 of the front interconnect structure 260 and the interconnect element 284TG of the rear interconnect structure 280. Furthermore, the interconnect element 284 can be used as a rear termination for one of the FET devices 500-1 and 500-2 and the isolation FET device 500-3.In some embodiments, the interconnect element 284 can be electrically connected to the front source / drain contacts 254S1 and 254S3 of the front interconnect structure 260, so that the gate structure 250 and the epitaxial source / drain structures 240-1S1 and 240-2S2 of the isolation FET device 500-3 can be electrically connected to the rear interconnect structure 280. In some embodiments, the processes and materials for fabricating the IMD layer 282 and the rear source / drain contact 272S1 can be similar to or identical with those for fabricating the IMD layer 262. In some embodiments, the processes and materials for manufacturing the circuit 284P and the interconnect elements 284TG and 284 may be similar to or the same as those for manufacturing the interconnect elements 264S1, 264S2 and 264G1.After performing the aforementioned processes, the rear interconnect structure 280 is completely fabricated, comprising the rear gate contact 272G3, the rear source / drain contact 272S1, the IMD layer 282, the circuit 284P, and the interconnect elements 284TG and 284. In some embodiments, the rear interconnect structure 280 provides an additional trace area for the circuit 284P, which is electrically connected to the epitaxial source / drain structure 240-1S2 of the FET device 500-1, and the interconnect element 284TG, which is electrically connected to the gate structure 250 of the isolation FET device 500-3 located therein. Therefore, the area of ​​the resulting semiconductor structure 550 can be further reduced.Furthermore, the number of IMD layers is 282, the number of rear gate contacts is 272G3, the number of rear source / drain contacts is 272S1, the number of circuits is 284P, and the number of interconnect elements is 284TG and 284, which are in . Fig. 12 are shown.

[0048] Then, a backside passivation layer 290 is fabricated on the backside interconnect structure 280. The backside passivation layer 290 is fabricated to protect the underlying backside interconnect structure 280, the FET devices 500-1 and 500-2, and the isolation FET device 500-3. In some embodiments, the processes and materials for fabricating the backside passivation layer 290 may be similar to or identical with those used for fabricating the frontside passivation layer 270.

[0049] Then, a pad 292 is produced by the rear-side passivation layer 290, which is electrically connected to the rear-side interconnect structure 280. For example, the pad 292 is electrically connected to the circuit 284P. The pad 292 provides an electrical connection between the resulting semiconductor structure 550 and external circuits (not shown). In some embodiments, the materials used to produce the pad 292 may be similar to or identical with those used to produce pads 272 and 274. Furthermore, the number of pads 292 is Fig. 12 is only an example. Then the support 100 can be removed to produce the semiconductor structure 550.

[0050] In some embodiments, the semiconductor structure 550 comprises the FET devices 500-1 and 500-2 and the isolation FET device 500-3, which are fabricated on the middle insulating layer 204, which is made from the SOI substrate 200. The FET devices 500-1 and 500-2 and the isolation FET device 500-3 each have the fin structure 220-1R (with fin structures 220-1R1, 220-1R2, and 220-1R3) which is fabricated on the insulating layer 204. The fin structures 220-1R1, 220-1R2, and 220-1R3 each have the channel layers 212 and the gate structure 250, which surrounds the channel layers 212. Furthermore, the fin structures 220-1R1, 220-1R2, and 220-1R3 each feature epitaxial source / drain structures 240, which are connected to the channel layers 212. The isolation FET device 500-3, which is arranged between the FET devices 500-1 and 500-2, is held in the off state.The semiconductor structure 550 further features the front-side gate contact 254G1, which is formed on the FET device 500-1 opposite the insulating layer 204. The front-side gate contact 254G1 is electrically connected to the gate structure 250 of the first FET device 500-1. The semiconductor structure 550 further features the rear-side gate contact 272G3, which is formed through the insulating layer 204 and is electrically connected to the gate structure 250 of the isolation FET device 500-3. The lower portions 240B of the epitaxial source / drain structures 240 and the lower portions 250B of the gate structures 250 of the FET devices 500-1 and 500-2 are in contact with the middle insulating layer 204 of the substrate 200R. Therefore, the substrate leakage loss of the resulting semiconductor structure 550 can be eliminated without implanting additional dopants into the undersides of the gate structure and the epitaxial source / drain structures.Furthermore, the isolation FET device 500-3, which is held in the off state, can serve as an electrical isolation element between the FET devices 500-1 and 500-2, and it can have a smaller area than conventional STI elements. In addition, the rear interconnect structure 280, which has the rear gate contact 272G3, provides an additional trace area for traces (e.g., the interconnect element 284TG) for the isolation FET device 500-3 and the circuit 284P for the FET device 500-1 located therein. Therefore, the area of ​​the resulting semiconductor structure 550 can be further reduced.

[0051] In the architecture of the GAA standard cell structure (e.g. the semiconductor structure 550), which is manufactured on a contiguous active area, the isolation FET device 500-3 is designed to be positioned between the FET devices 500-1 and 500-2 and is controlled in the off state by means of the rear gate contact 272G3, which is electrically connected to the gate structure 250 of the isolation FET device 500-3. Since the GAA standard cell structure (e.g. the semiconductor structure 550) is designed to have the rear current mesh (e.g. the circuit 284P of the rear interconnect structure 280), the gate structure 250 and the epitaxial source / drain structures 240-1S1 and 240-2S2 of the isolation FET device 500-3 can be electrically connected to the rear gate contact 272G3 and the interconnect element 284 manufactured in the rear interconnect structure 280.Therefore, the electrical connections (which include the front gate contact 254G1 and the front source / drain contact 254S2) of the front interconnect structure 260 can only be designed for the FET devices 500-1 and 500-2 (for signal transmission).

Claims

[1] Semiconductor structure with: an insulating layer (204); a first FET device (FET: field-effect transistor), a second FET device and an isolation FET device between the first and the second FET device, which are fabricated on the insulating layer (204), wherein the first and the second FET device and the isolation FET device each have the following: a fin structure (220) produced on the insulating layer (204), wherein the fin structure has channel layers and a gate structure (250) enclosing the channel layers (212), and a first and a second epitaxial source / drain structure (240-2S1, 240-2S2, 240-1S1, 240-1S2) connected to opposite sides of the channel layers (212), with the isolation FET device being held in an off state; a front-side gate contact (254G) that is made on the first FET device opposite the insulating layer (204), wherein the front-side gate contact (254G) is electrically connected to the gate structure (250) of the first FET device; and a rear gate contact (272G3) which is made through the insulating layer (204) and is electrically connected to the gate structure (250) of the insulating FET device; wherein the semiconductor structure is a standard cell structure, and The isolation FET device is held in an off state to serve as an electrical isolation element between the first and second FET devices. [2] Semiconductor structure according to claim 1, wherein the first epitaxial source / drain structure (240-1S1) of the isolation FET device is the second epitaxial source / drain structure of the second FET device, and the second epitaxial source / drain structure (240-2S2) of the isolation FET device is the first epitaxial source / drain structure of the first FET device. [3] Semiconductor structure according to claim 1 or 2, further comprising: a front interconnect structure (260) manufactured over a top surface (204T) of the insulating layer (204), wherein the front interconnect structure (260) comprises the front gate contact (254G); and a rear interconnect structure (280) which is manufactured directly on a bottom side of the insulating layer (204), wherein the rear interconnect structure (280) has the rear gate contact (272G3). [4] Semiconductor structure according to claim 3, further comprising: a rear source / drain contact (272S) of the rear interconnect structure (280) which is made through the insulating layer (204) and is electrically connected to the second source / drain structure of the first FET device. [5] Semiconductor structure according to claim 4, wherein the rear source / drain contact (272S) is electrically connected to a circuit (282, 284P) of the rear interconnect structure (280). [6] Semiconductor structure according to one of claims 3 to 5, wherein the first epitaxial source / drain structure (240-1S1) and the second epitaxial source / drain structure (240-2S2) of the isolation FET device are electrically connected to the front interconnect structure (260). [7] Semiconductor structure according to any one of claims 3 to 6, further comprising: a front-side passivation layer (270) that is produced on the front-side interconnect structure (260); a rear passivation layer (290) that is produced on the rear interconnect structure (280); a first pad that is manufactured through the front-side passivation layer (270) and is electrically connected to the front-side interconnect structure (260); and a second pad that is manufactured through the rear passivation layer (290) and is electrically connected to the rear interconnect structure (280). [8] Semiconductor structure according to any one of claims 3 to 7, wherein a lower part (240B) of each of the first and second epitaxial source / drain structure is in contact with the insulating layer (204). [9] Semiconductor structure according to one of the preceding claims, wherein a lower part (250B) of the gate structure (250) of each of the first and second FET device is in contact with the insulating layer (204). [10] Semiconductor structure according to one of the preceding claims, wherein a first distance between a bottom layer of the channel layers (212) and the top (204T) of the insulating layer (204) is equal to a second distance between the bottom layer of the channel layers (212) and the adjacent channel layer (212) relative to the insulating layer (204). [11] Semiconductor structure according to any of the preceding claims, further comprising: Internal spacers (238) arranged at lateral ends of the gate structure (250), wherein the internal spacer (238) in contact with the lower part of the gate structure (250) is in contact with the insulating layer (204). [12] Semiconductor structure according to claim 11, wherein the internal spacers (238) which are in contact with the insulating layer (204) are in contact with the lowest layer of the channel layers (212). [13] Semiconductor structure according to one of the preceding claims, wherein the fin structure (220) further comprises a base part (220B) below the gate structure (250) and the channel layers (212), wherein the base part (220B) is made of the insulating layer (204). [14] Semiconductor structure with: a first FET device (FET: field-effect transistor) and a second FET device arranged side by side; an isolation FET device arranged between the first and second FET devices, wherein the first and second FET devices and the isolation FET device each have the following: a fin structure (220) comprising channel layers (212) and a gate structure (250) enclosing the channel layers (212), and a first epitaxial source / drain structure (240-1S2, 240-1S1, 240-2S2) and a second epitaxial source / drain structure (240-1S1, 240-2S2, 240-2S1) connected to opposite sides of the canal layers (212); an insulating layer (204) with a top surface (204T) which is in contact with a lower part of the gate structure (250) of each of the first and second FET devices; an interlayer dielectric layer, ILD layer, which is arranged on and between the gate structures (250) of the first, second and isolation FET device; a rear gate contact (272G3) which is made through the insulating layer (204) and is electrically connected to the lower part of the gate structure (250) of the isolation FET device; and a front-side source / drain contact (254S) that is made through the ILD layer (242) and is electrically connected to the first or the second epitaxial source / drain structure (240-2S2) of the isolation FET device; wherein the semiconductor structure is a standard cell structure, and The isolation FET device is held in an off state to serve as an electrical isolation element between the first and second FET devices. [15] Semiconductor structure according to claim 14, wherein the first epitaxial source / drain structure (240-1S1) of the isolation FET device is the second epitaxial source / drain structure of the second FET device, and the second epitaxial source / drain structure (240-2S2) of the isolation FET device is the first epitaxial source / drain structure of the first FET device. [16] Semiconductor structure according to claim 14 or 15, further comprising: a circuit (282, 284P) which is arranged on a bottom side of the insulating layer (204) and is electrically connected to a lower part of the second source / drain structure of the first FET device by means of a rear source / drain contact (272S) which passes through the insulating layer (204). [17] Semiconductor structure according to claim 16, further comprising: a front interconnect structure (260) manufactured over a top surface (204T) of the insulating layer (204), wherein the front interconnect structure (260) comprises the ILD layer (242) and the front source / drain contact (254S); and a rear interconnect structure (280) which is manufactured directly on the underside of the insulating layer (204), wherein the rear interconnect structure (280) includes the circuit (282, 284P) and the rear gate contact (272G3). [18] Semiconductor structure according to claim 17, further comprising: a front gate contact (254G) of the front interconnect structure (260) which is made through the ILD layer (242), wherein the front gate contact (254G) is electrically connected to the gate structure (250) of the first FET device. [19] Semiconductor structure according to one of claims 17 to 18, further comprising: a front-side passivation layer (270) that is produced on the front-side interconnect structure (260); a rear passivation layer (290) that is produced on the rear interconnect structure (280); a first pad that is manufactured through the front-side passivation layer (270) and is electrically connected to the front-side interconnect structure (260); and a second pad that is manufactured through the rear passivation layer (290) and is electrically connected to the rear interconnect structure (280). [20] Semiconductor structure according to one of claims 14 to 19, wherein a lower part (240B) of each of the first and the second epitaxial source / drain structure is in contact with the insulating layer (204). [21] Semiconductor structure according to one of claims 14 to 20, wherein a lower part (250B) of the gate structure (250) of each of the first and second FET device is in contact with the insulating layer (204). [22] Semiconductor structure according to any one of claims 14 to 21, wherein a first part of the gate structure (250) between a bottom layer of the channel layers (212) and a front side of the insulating layer (204) has a first thickness, and a second part of the gate structure (250) between the lowest layer of the channel layers (212) and the adjacent channel layer (212) opposite the insulating layer (204) has a second thickness, the second thickness being equal to the first thickness. [23] Semiconductor structure according to any one of claims 14 to 22, further comprising: Internal spacers (238) are arranged at lateral ends of the gate structure (250), wherein the internal spacers (238) are in contact with the insulating layer (204) at a lower part of the gate structure (250). [24] Semiconductor structure according to one of claims 14 to 23, wherein the fin structure (220) has a base part (220B) in contact with a lower part of the gate structure (250), wherein the base part (220B) is made of the insulating layer (204). [25] Method for producing a semiconductor structure, comprising: Providing a substrate (200, 200R) comprising a substrate layer (202) and an insulating layer (204) on the substrate layer (202); Fabricating a first FET device (FET: field-effect transistor), a second FET device and an isolation FET device between the first and second FET devices and directly on the insulating layer (204), wherein the first FET device, the second FET device and the isolation FET device each have the following: a fin structure (220) produced on the insulating layer (204), wherein the fin structure has channel layers and a gate structure (250) enclosing the channel layers (212), and a first and a second epitaxial source / drain structure (240-2S2) connected to opposite sides of the channel layers (212), with the isolation FET device being held in an off state; Establishing a front-side gate contact (254G) on the first FET device opposite the insulating layer (204), wherein the front-side gate contact (254G) is electrically connected to the gate structure (250) of the first FET device; Removal of the substrate layer (202) from the insulating layer (204); and Establishing a rear-side gate contact (272G3) that passes through the insulating layer (204) and is electrically connected to the gate structure (250) of the isolation FET device; wherein the semiconductor structure is a standard cell structure, and The isolation FET device is held in an off state to serve as an electrical isolation element between the first and second FET devices. [26] A method for producing a semiconductor structure according to claim 25, further comprising: Prior to removing the substrate layer (202) from the insulating layer (204), a front insulating structure is formed over a top surface (204T) of the insulating layer (204), wherein the front interconnect structure (260) comprises the front gate contact (254G); and Creating a front-side passivation layer (270) on the front-side interconnect structure (260). [27] A method for producing a semiconductor structure according to claim 26, further comprising: Before removing the substrate layer (202) from the insulating layer (204), a surface of the front passivation layer (270) is mounted opposite the front interconnect structure (260) to a support (100); After removing the substrate layer (202) from the insulating layer (204), a rear interconnect structure (280) is fabricated directly on a bottom side of the insulating layer (204), wherein the rear interconnect structure (280) has the rear gate contact (272G3); and Creating a backside passivation layer (290) on the backside interconnect structure (280). [28] Method for producing a semiconductor structure according to claim 27, further comprising: Establishing a first pad through the front-side passivation layer (270) and in electrical connection with the front-side interconnect structure (260); and Producing a second pad through the rear passivation layer (290) and in electrical connection with the rear interconnect structure (280). [29] Method for producing a semiconductor structure according to any one of claims 25 to 28, further comprising: Establishing front-side source / drain contacts (254S) of the front-side interconnect structure (260) through an interlayer dielectric layer, ILD layer (242), and in electrical connection with the first and second epitaxial source / drain structures (240-2S2) of the isolation FET device. [30] Method for producing a semiconductor structure according to any one of claims 25 to 29, wherein the first epitaxial source / drain structure (240-1S2) of the isolation FET device, the second epitaxial source / drain structure (240-2S2) of the second FET device, and the second epitaxial source / drain structure (240-2S2) of the isolation FET device is the first epitaxial source / drain structure (240-1S2) of the first FET device. [31] Method for producing a semiconductor structure according to any one of claims 25 to 30, wherein the substrate (200, 200R) further comprises an upper semiconductor layer (206) containing first semiconductor atoms, on the insulating layer (204), and The fabrication of the first FET device, the second FET device, and the isolation FET device includes the following: epitaxial growth of a semiconductor capping layer (208) on the upper semiconductor layer (206), wherein the semiconductor capping layer (208) contains the first semiconductor atoms and second semiconductor atoms that are different from the first semiconductor atoms; Performing a thermal process to drive the second semiconductor atoms of the semiconductor capping layer (208) into the upper semiconductor layer (206) so that the semiconductor capping layer (208) and the upper semiconductor layer (206) collectively form a first sacrificial layer (210); epitaxial growth of a stack (216) of alternating channel layers (212) of the first FET device, the second FET device and the isolation FET device and of second sacrificial layers (214) on the first sacrificial layer (210); Structuring the insulating layer, which is a middle insulating layer (204), the upper semiconductor layer (206), the first sacrificial layer (210) and the stack (216) of alternating channel layers (212) and second sacrificial layers (214) to produce an intermediate fin structure; Removing parts of the intermediate fin structure until the middle insulating layer (204) is exposed to create source / drain recesses (236); Fabrication of the first epitaxial source / drain structures (240-1S2) and the second epitaxial source / drain structures (240-2S2) of the first FET device, the second FET device and the isolation FET device in the source / drain recesses (236); selective removal of the first sacrificial layer (210) and the second sacrificial layers (214) after the fabrication of the first and second epitaxial source / drain structures (240-2S2); and Fabricating the gate structures (250) of the first FET device, the second FET device and the isolation FET device such that they enclose the channel layers (212). [32] Method for producing a semiconductor structure according to claim 31, wherein a first concentration of second semiconductor atoms in the semiconductor capping layer (208) is higher than a second concentration of second semiconductor atoms in the first sacrificial layer (210). [33] Method for producing a semiconductor structure according to claim 31 or 32, wherein the channel layers (212) contain the first semiconductor atoms but not the second semiconductor atoms. [34] Method for producing a semiconductor structure according to one of claims 31 to 33, wherein the second sacrificial layers (214) contain the first semiconductor atoms and the second semiconductor atoms. [35] Method for producing a semiconductor structure according to any one of claims 31 to 34, wherein the first sacrificial layer (210) has a first composition and the second sacrificial layers (214) have a second composition which is the same as the first composition. [36] Method for producing a semiconductor structure according to claim 31, wherein the first sacrificial layer (210) has a first thickness and the second sacrificial layers (214) have a second thickness, wherein the second thickness is equal to the first thickness. [37] Method for producing a semiconductor structure according to claim 35, wherein the channel layers (212) have a third composition, the third composition being different from the first and the second composition. [38] Method for producing a semiconductor structure according to any one of claims 31 to 37, wherein after the epitaxial growth of the stack (216) of alternating channel layers (212) and second sacrificial layers (214) a bottom layer of the channel layers (212) is in contact with the first sacrificial layer (210). [39] Method for producing a semiconductor structure according to any one of claims 31 to 38, wherein the stack (216) of alternating channel layers (212) and second sacrificial layers (214) comprises a first number of channel layers (212) and a second number of second sacrificial layers (214), wherein the first number is greater than the second number. [40] Method for producing a semiconductor structure according to any one of claims 31 to 39, further comprising: After creating the source / drain recesses, internal spacers (238) are made at the lateral ends of the first sacrificial layer (210) and the second sacrificial layers (214). [41] Method for producing a semiconductor structure according to any one of claims 31 to 40, wherein during the selective removal of the first sacrificial layer (210) and the second sacrificial layers (214) a first etch selectivity between the first sacrificial layer (210) and the channel layers (212) is equal to a second etch selectivity between the second sacrificial layers (214) and the channel layers (212).

Images