INTEGRATED CIRCUIT PACKAGE AND METHOD

Abstract

Device package (300, 550), comprising: an interposer (200), comprising: a semiconductor substrate (202); first vias (201) extending through the semiconductor substrate (202), the vias (201) protruding from a front side of the semiconductor substrate (202); an interconnect structure (206) over the front side of the semiconductor substrate (202), the interconnect structure (206) comprising: a first metallization structure (206A) in an inorganic insulating material (206B); and a passivation film (210, 212) over the first metallization structure (206A); and a first redistribution structure (240) over the passivation film (210, 212), the first redistribution structure (240) comprising a second metallization structure (218, 222, 226, 230, 234) in an organic insulating material (216, 220, 224, 228, 232, 236), the first redistribution structure (240) being flush with the interconnect structure (206) and the semiconductor substrate (202); an integrated circuit die (100A) over and attached to the interposer (200); and a first encapsulation material (304) around the integrated circuit die (100A).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has largely stemmed from repeated reductions in the minimum feature size, allowing more components to be integrated into a given area. With the growing demand for ever-smaller electronic devices, a need has arisen for smaller and more creative packaging techniques for semiconductor dies. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package, providing a high level of integration and component density.PoP technology generally enables the production of semiconductor devices with improved functionality and a small footprint on a printed circuit board (PCB).

[0002] US 2019 / 0 237 430 A1 discloses a 3D IC package comprising a bottom die having a rear connection side opposite a front device side, the rear connection side having a plurality of bottom die connections extending thereto. An upper die has a front device side opposite a rear side, the front device side having a plurality of top die connections. An interposer comprises a redistribution layer (RDL) between the bottom die and the top die, the RDL comprising a plurality of wiring layers extending from its rear RDL connections to its front RDL connections. An under-bump metallization (UBM) couples the rear RDL connections to the plurality of top die connections at a first location, and the front RDL connections are coupled to the plurality of bottom die connections at a second location.The first and second digits must not overlap.

[0003] US 2021 / 0 193 637 A1 discloses a method comprising connecting a first package component and a second package component to an interposer. The first package component comprises a core device chip, and the second package component comprises a memory chip. An IPD (Independent Passive Device) chip is directly connected to the interposer. The IPD chip is electrically connected to the first package component via a first conductive path in the interposer. A package substrate is connected to the interposer chip. The package substrate is located on an opposite side of the interposer from the first package component and the second package component.

[0004] US 2021 / 0 375 768 A1 discloses an array of through-silicon via (TSV) structures through a silicon substrate and package-side metal pads on the backsides of the array of TSV structures. The silicon substrate is arranged over a carrier substrate, and an encapsulation interposer, such as an epoxy molding compound (EMC) interposer, is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer, and at least one semiconductor chip is attached to the die-side redistribution structure. The carrier substrate is removed from under the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer.The interference tolerance between the chassis-side redistribution wiring connections and the chassis-side metal pads increases due to the increased areas of the chassis-side metal pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. The Fig. 1 to 6 show cross-sectional views of the fabrication of an interposer according to some embodiments. The Fig. 7 to 11 show cross-sectional views of the fabrication of an interposer according to some embodiments. Fig. 12 shows a cross-sectional view of an interposer according to some embodiments. The Fig. 13 to 18 show cross-sectional views of the fabrication of a semiconductor package with an interposer according to some embodiments. The Fig. 19 to 25 show cross-sectional views of the fabrication of a semiconductor package with an interposer according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0007] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0008] According to some embodiments, semiconductor devices may be bonded together to form a chip-on-wafer-on-substrate (CoWoS™) package with multiple dies bonded to an interposer. The interposer may include metallization layers plated in patterned photoresist masks, which are subsequently replaced by organic insulating layers. Optionally, the interposer may further include additional metallization layers formed in inorganic insulating materials using damascene processes. The use of metallization layers in organic insulating layers provides improved signal integrity and / or power integrity at high operating frequencies (e.g., higher than 20 GHz).Furthermore, embodiments with metallization layers formed in both organic and inorganic insulating materials can provide improved flexibility in processing and packaging design. Although embodiments are described herein in a specific context, namely a CoWoS packaging scheme, embodiments can also be used for other packaging schemes.

[0009] The Fig. 1 to 6 are cross-sectional views of intermediate steps of a method for forming an interposer 200 (see Fig. 6) According to some embodiments, the interposer may include metallization structures in organic insulating layers that provide improved signal / power integrity at high operating frequencies.

[0010] With reference to Fig. 1, an interposer 200 is shown in an intermediate stage of processing. The interposer 200 may be formed as part of a larger wafer. The interposer 200 may be processed according to suitable manufacturing processes for forming integrated circuits within the interposer 200. For example, the interposer 200 may include a semiconductor substrate 202 such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 may include other semiconductor materials such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used.

[0011] Active and / or passive devices such as transistors, diodes, capacitors, resistors, inductors, etc., may be formed in and / or on the semiconductor substrate 202. For example, the interposer 200 may include an integrated deep trench capacitor (iCAP) 204A having portions disposed on a top surface of the semiconductor substrate 202 as well as portions extending into the semiconductor substrate 202. Other types of capacitors, such as deep trench capacitors (DTCs) or the like, are also possible. In some embodiments, the interposer 200 is free of any active devices, and only passive devices are formed in and / or on the semiconductor substrate 202. In further embodiments, the interposer 200 may be free of both active and passive devices.

[0012] The devices may be connected by an interconnect structure 206, which may include, for example, metallization structures 206A in one or more dielectric layers 206B (also referred to as insulating material layers 206B) on the semiconductor substrate 202. The dielectric layers 206B may be formed from inorganic materials deposited by CVD processes and patterned using damascene processes (e.g., single damascene processes, dual damascene processes, or the like). As an example of a damascene process, a dielectric layer 206B may be deposited, and openings may be patterned in the dielectric layer 206B (e.g., by photolithography and / or etching). Subsequently, the openings in the dielectric layer 206B may be filled with a conductive material, and excess conductive material may be removed by a planarization process (e.g.,chemical mechanical polishing (CMP) or the like) to form a metallization structure 206A. The interconnect structures 206 electrically connect the devices on the substrate 202 to form one or more integrated circuits. In some embodiments, additional passive devices 204B (e.g., capacitors, resistors, inductors, etc.) may be formed in the interconnect structure 206. For example, the interconnect structure 206 may include a metal-insulator-metal (MIM) capacitor or the like. Although. Fig. 1 shows the interconnect structure 206 with two layers of metallization structures 206A, embodiments contemplate that the interconnect structure 206 may have any number of metallization structure layers, such as between one layer and five layers of metallization structures 206A.

[0013] The interposer 200 further includes vias 201 that may be electrically connected to the metallization structures 206A in the interconnect structure 206. The vias 201 may include a conductive material (e.g., copper or the like) and may extend from a metallization structure 206A into the substrate 202. One or more insulating barrier layers 203 may be formed around at least portions of the vias 201 in the substrate 202. The insulating barrier layers 203 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like and may be used to physically and electrically isolate the vias 201 from each other and from the substrate 202. In subsequent processing steps, the substrate 202 may be thinned to expose the vias 201 (see Fig. 15). After thinning, the vias 201 provide an electrical connection from a backside of the substrate 202 to a frontside of the substrate 202. In various embodiments, the backside of the substrate 202 may refer to a side of the substrate 202 opposite the devices and interconnect structure 206, while the frontside of the substrate 202 may refer to a side of the substrate 202 on which the devices and interconnect structure 206 are arranged.

[0014] In one embodiment, the interposer 200 further includes contact pads 208 that enable connections to be made to the interconnect structure 206 and the devices on the substrate 202. The contact pads 208 may include copper, aluminum (e.g., 28K aluminum), or another conductive material. The contact pads 208 are electrically connected to the metallization structures 206A of the interconnect structure 206. One or more passivation films may be disposed on the interconnect structure 206 and the contact pads 208. For example, the interconnect structure 206 may include passivation films 210 and 212. The passivation films 210 and 212 may each include an inorganic material, such as silicon oxide, silicon oxynitride, silicon nitride, or the like. In some embodiments, the materials of the passivation films 210 and 212 may be the same or different from each other.Furthermore, the materials of passivation films 210 and 212 may be the same as or different from the materials of dielectric layers 206B. In some embodiments, contact pads 208 extend over and cover edges of passivation film 210, and passivation film 212 extends over and cover edges of contact pads 208.

[0015] The interposer 200 may be formed as part of a larger wafer (e.g., connected to another interposer 200). In some embodiments, the interposers 200 may be separated from each other after packaging. For example, the interposer 200 may be packaged while still connected as part of a wafer. In some embodiments, a chip probe (CP) test may be applied to each of the interposers 200 (e.g., via the contact pads 208). The CP test verifies the electrical functionality of the interposer 200, and dies that pass the CP tests are referred to as known good dies (KGDs). Interposers 200 that fail the CP tests are discarded or repaired. In this way, KGDs are delivered for packaging, reducing scrap and the cost of packaging a faulty die.

[0016] In Fig. 2, conductive interconnects 214 are formed on contact pads 208. Conductive interconnects 214 may include a metal such as copper, titanium, tungsten, aluminum, or the like. As an example for forming conductive interconnects 214, a seed layer (not shown separately) may be deposited on exposed surfaces of passivation layer 212, sidewalls of passivation layer 210, and top surfaces of contact pads 208. In some embodiments, the seed layer is a metal layer, which may consist of a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using CVD, PVD, or the like. A photoresist (not shown) is formed and patterned on the seed layer.The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the conductive interconnects 214. The patterning forms one or more openings through the photoresist such that the seed layer is exposed. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer by plating, for example, electroplating or electroless plating or the like. The photoresist is then removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. Excess portions of the seed layer (e.g., portions not covered by the conductive material) may be removed by an etching process, and remaining portions of the seed layer and conductive material correspond to the conductive interconnects 214.

[0017] In Fig. 3, an insulating material 216 is deposited over the conductive interconnects 214. In some embodiments, the insulating material 216 is formed from an organic material such as a polymer, which may be comprised of a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. In some embodiments, the insulating material 216 has a relatively low dielectric constant and a relatively low dissipation factor. For example, a dielectric constant of the insulating material 216 may be lower than about 3.5, and a dissipation factor of the insulating material 216 may be lower than 0.03. The insulating material 216 may have a lower dissipation factor than a material of the dielectric layers 206B. The insulating material 216 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof.The insulating material 216 may cover the conductive connectors 214 such that an upper surface of the insulating material 216 overlies the upper surfaces of the conductive connectors 214.

[0018] In Fig. 4, the insulating material 216 is then patterned to form openings that expose portions of the conductive connectors 214. Patterning may be achieved by a suitable process, such as by exposing the insulating material 216 to light if the insulating material 216 is a photosensitive material, or by etching using, for example, an anisotropic etch. If the insulating material 216 is a photosensitive material, the insulating material 216 may be developed after exposure.

[0019] Then, the metallization structure 218 is formed. The metallization structure 218 has portions on the main surface of the insulating material 216 that extend along it. The metallization structure 218 further has portions that extend through the insulating material 216 so as to physically and electrically connect to the conductive connectors 214. The metallization structure 218 may be formed using a process other than the damascene processes used to form the metallization structures 206A in the interconnect structure 206. As an example for forming the metallization structure 218, a seed layer is formed over the insulating material 216 and in the openings that extend through the insulating material 216.In some embodiments, the seed layer is a metal layer, which may consist of a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 218. Patterning forms openings through the photoresist that expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer.The conductive material may be formed by plating, for example, electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying portions of the seed layer forms the metallization structure 218. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, for example, wet or dry etching.

[0020] The insulating material 220 is deposited on the metallization structure 218 and the insulating material 216. The insulating material 220 may be formed in a similar manner to the insulating material 216 and may be formed from a similar material to the insulating material 216. For example, the insulating material 220 may include an organic material that provides better signal integrity and power integrity in the interposer 200.

[0021] In Fig. 5, additional metallization layers are formed over the metallization structure 218 to form a redistribution structure 240. The redistribution structure 240 includes organic insulating material layers 216, 220, 224, 228, 232, and 236; the conductive interconnects 214; and metallization structures 218, 222, 226, 230, and 234. The metallization structures may also be referred to as redistribution layers or redistribution lines. Each of the metallization structure layers 222, 226, 230, and 234 may be formed by a substantially similar process and from a substantially similar material as the metallization structure 218 described above, and each of the organic insulating material layers 224, 228, 232, and 236 may be formed by a substantially similar process and from a substantially similar material as the insulating material 216 described above.Metallization structures 218, 222, 226, 230, and 234 collectively form functional circuits that provide, for example, signal and / or power routing to underlying metallization structures 206A, devices 204, and vias 201. For example, each of insulating materials 224, 228, 232, and 236 may have a relatively low dissipation factor (e.g., lower than that of dielectric layers 206B), enabling redistribution structure 240 to provide good signal and power integrity in interposer 200 even at relatively high operating frequencies.

[0022] In Fig. 6, UBMs 242 are formed for external connection to the redistribution structure 240. The UBMs 242 have bump portions and extend along the main surface of the insulating material 236 and have via portions that extend through the insulating material 236 to physically and electrically connect to the metallization structure 234. As a result, the UBMs 242 are electrically connected to the metallization structures 206A and the vias 201. The UBMs 242 may be formed from the same material as the metallization structure 218. In some embodiments, the UBMs 242 have a different size than the metallization structures 218, 222, 226, 230, and 234. Thus, an interposer 200 with relatively high signal integrity and power integrity is formed.

[0023] The Fig. 7 to 11 show cross-sectional views of intermediate steps for forming an interposer 200' according to some embodiments. The interposer 200' may be similar to the interposer 200, with like reference numerals denoting like elements formed by like processes. However, the interposer 200' may be free of any contact pads 208 connecting the metallization structures of the redistribution structure 240 to the metallization structures of the interconnect structure 206 (see Fig. 11).

[0024] In particular, with reference to Fig. 7, no contact pads 208 are formed over the metallization structures 206A of the interconnect structure 206. Rather, the passivation films 210 and 212 are patterned to include openings 250 that expose a top metallization structure 206A of the interconnect structure 206. The passivation films 210 and 212 may be patterned, for example, using a combination of lithography and etching.

[0025] Next, with reference to Fig. 8, the insulating material 216 is deposited over a top surface of the passivation film 212 and in the openings 250. As a result, the insulating material 216 may extend through the passivation films 210 and 212 to a topmost metallization structure 206A of the interconnect structure 206. In some embodiments, the insulating material 216 is formed from an organic material such as a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. In some embodiments, the insulating material 216 has a relatively low dielectric constant and a relatively low dissipation factor. For example, a dielectric constant of the insulating material 216 may be lower than about 3.5, and a dissipation factor of the insulating material 216 may be lower than about 0.03.The insulating material 216 may have a lower loss factor than a material of the dielectric layers 206B. The insulating material 216 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof.

[0026] In Fig. 9, the insulating material 216 is then patterned to form openings 252 that expose portions of the topmost metallization structure 206A of the interconnect structure 206. Patterning may be achieved by a suitable process, such as by exposing the insulating material 216 to light if the insulating material 216 is a photosensitive material, or by etching using, for example, an anisotropic etch. If the insulating material 216 is a photosensitive material, the insulating material 216 may be developed after exposure.

[0027] In Fig. 10, the metallization structure 218 is then formed. The metallization structure 218 has portions on the main surface of the insulating material 216 that extend along it. The metallization structure 218 further has portions that extend through the insulating material 216 such that they are physically and electrically connected to the topmost metallization structure 206A of the interconnect structure 206. As an example for forming the metallization structure 218, a seed layer is formed over the insulating material 216 and in the openings that extend through the insulating material 216. In some embodiments, the seed layer is a metal layer, which may consist of a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer.The seed layer may be formed, for example, using PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 218. The patterning forms openings through the photoresist, exposing the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying portions of the seed layer forms the metallization pattern 218.The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching.

[0028] In Fig. 11, additional metallization layers are formed over metallization structure 218 to form a redistribution structure 240 in interposer 200'. Redistribution structure 240 includes organic insulating material layers 216, 220, 224, 228, 232, and 236 and metallization structures 218, 222, 226, 230, and 234. The metallization structures may also be referred to as redistribution layers or redistribution lines. Each of the metallization structure layers 222, 226, 230, and 234 may be formed by a substantially similar process and from a substantially similar material as the metallization structure 218 described above, and each of the organic insulating material layers 224, 228, 232, and 236 may be formed by a substantially similar process and from a substantially similar material as the insulating material 216 described above.Metallization structures 218, 222, 226, 230, and 234 collectively form functional circuits that provide, for example, signal and / or power routing to underlying metallization structures 206A, devices 204, and vias 201. For example, each of insulating materials 224, 228, 232, and 236 may have a relatively low dissipation factor (e.g., lower than that of dielectric layers 206B), enabling redistribution structure 240 to provide good signal and power integrity in interposer 200 even at relatively high operating frequencies. In the interposer 200', the metallization structures 218, 222, 226, 230, and 234 of the redistribution structure 240 are directly connected to the metallization structures 206A of the interconnect structure 206 without any intervening contact pads or conductive connectors.

[0029] The redistribution structure 240 is shown as an example with five layers of metallization structures in the interposer 200'. More or fewer layers of insulating material layers and metallization structure layers may be formed in the redistribution structure 240. If fewer insulating material layers and metallization structure layers are to be formed, the steps and processes described herein may be omitted. If more insulating material layers and metallization structure layers are to be formed, the steps and processes described herein may be repeated.

[0030] Fig. 12 shows a cross-sectional view of an interposer 200" according to some embodiments. The interposer 200" may be similar to the interposer 200, with like reference numerals denoting like elements formed by like processes. As shown, the interposer 200" does not use the interconnect structure 206. For example, the interposer 200" may be free of any metallization structures formed by a damascene process and may further be free of any insulating layers formed from inorganic materials. Rather, the redistribution structure 240 in the interposer 200" may be formed directly on the substrate 202, such that the bottommost metallization structure 218 of the redistribution structure 240 may be directly connected to the vias 201 in the substrate 202.The redistribution structure 240 includes organic insulating material layers 216, 220, 224, 228, 232, and 236 and metallization structures 218, 222, 226, 230, and 234. The use of organic insulating materials provides good signal integrity and power integrity at relatively high operating frequencies. As shown in FIG. Fig. 12, the use of the interconnect structure 206 (e.g., comprising the passivation films 210 and 212, the dielectric layers 206B, and the metallization structures 206A) is optional.

[0031] The redistribution structure 240 is shown as an example with five layers of metallization structures in the interposer 200. More or fewer layers of insulating material layers and metallization structure layers may be formed in the redistribution structure 240. If fewer insulating material layers and metallization structure layers are to be formed, steps and processes described herein may be omitted. If more insulating material layers and metallization structure layers are to be formed, steps and processes described herein may be repeated.

[0032] The Fig. 13 to 18 show cross-sectional views for applying further processing steps for packaging the interposer 200 according to some embodiments. Although the interposer 200 is shown, it should be understood that the process steps of Fig. 13 to 18 can also be used to connect the interposer 200' from Fig. 11 and / or the Interposer 200" from Fig. 12 to pack.

[0033] In Fig. 13, integrated circuit dies 100 (e.g., a first integrated circuit die 100A and a plurality of second integrated circuit dies 100B) are attached to the interposer 200. The integrated circuit dies 100 can be attached to the interposer 200 in Fig. 1, wherein the integrated circuit dies 100 include active devices interconnected by an interconnect structure to form functional circuits. In the illustrated embodiment, multiple integrated circuit dies 100 are arranged side by side, for example, the first integrated circuit die 100A and the second integrated circuit dies 100B, with the first integrated circuit die 100A sandwiched between the second integrated circuit dies 100B. In some embodiments, the first integrated circuit die 100A consists of a logic device, such as a CPU, GPU, or the like, and the second integrated circuit dies 100B consist of memory devices, such as DRAM dies, HMC modules, HBM modules, or the like. In some embodiments, the first integrated circuit die 100A consists of the same device type (e.g., SoCs) as the second integrated circuit dies 100B.The integrated circuit dies 100 may be mounted on a front side of the interposer 200 such that the interconnect structure 206 and the redistribution structure 240 are each located between the semiconductor substrate 202 and the dies 100.

[0034] In the illustrated embodiment, the integrated circuit dies 100 are attached to the interposer 200 with solder connections, such as conductive connectors 102 on the UBMs 242 of the interposer 200. The integrated circuit dies 100 may be placed on the interconnect structure 206, for example, using a placement tool. The conductive connectors 102 may be formed from a conductive material that is reflowable, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 102 are formed by first forming a solder layer by methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a solder layer is formed on the structure, reflow may be performed to form the conductive connectors 102 into desired bump shapes.Attaching the integrated circuit dies 100 to the interposer 200 may include placing the integrated circuit dies 100 on the interposer 200 and reflowing the conductive connectors 102. The conductive connectors 102 form connections between the UBMs 242 of the interposer 200 and the conductive connectors 102 of the integrated circuit dies 100, thereby electrically connecting the interposer 200 to the integrated circuit dies 100.

[0035] In Fig. 14, an underfill 302 may be formed around the conductive interconnects 102 and between the interposer 200 and the integrated circuit dies 100. The underfill 302 may reduce stresses and protect the connections resulting from the reflow of the conductive interconnects 102. The underfill 302 may be formed from an underfill material such as a molding compound, epoxy, or the like. The underfill 302 may be formed by a capillary flow process after the integrated circuit dies 100 are attached to the interposer 200, or may be formed by a suitable deposition process before the integrated circuit dies 100 are attached to the interposer 200. The underfill 302 may be applied in liquid or semi-liquid form and subsequently cured.

[0036] In further embodiments (not shown separately), the integrated circuit dies 100 are attached to the interposer 200 using direct bonds. For example, fusion bonding, dielectric-to-dielectric direct bonding, metal-to-metal direct bonding, combinations thereof, or the like may be used to directly bond corresponding dielectric layers and / or die connectors of the integrated circuit dies 100 and the interposer 200 without the use of adhesive or solder. The underfill 302 may be omitted when direct bonding is used. Furthermore, a mixture of bonding techniques could be used; e.g., some integrated circuit dies 100 could be attached to the interposer 200 using solder connections, and other integrated circuit dies 100 could be attached to the interposer 200 using direct bonds.

[0037] Furthermore, Fig. 14, an encapsulation material 304 is formed on and around the integrated circuit dies 100. Once formed, the encapsulation material 304 encapsulates the integrated circuit dies 100 and the underfill 302 (if present) or the conductive interconnects 102. The encapsulation material 304 may be formed from a molding compound, an epoxy resin, or the like. The encapsulation material 304 may be deposited by compression molding, transfer molding, or the like and is formed over the interposer 200 such that the integrated circuit dies 100 are buried or covered, respectively. The encapsulation material 304 may be deposited in liquid or semi-liquid form and subsequently cured. The encapsulation material 304 may be thinned to expose the integrated circuit dies 100.The thinning process may consist of a grinding process, chemical mechanical polishing (CMP), etching back, combinations thereof, or the like. After the thinning process, the top surfaces of the integrated circuit dies 100 and the encapsulation material 304 are coplanar (within process variations), so that they are level with each other. Thinning is performed until a desired amount of the integrated circuit dies 100 and / or the encapsulation material 304 has been removed.

[0038] In Fig. 15, a backside of the substrate 202 is thinned to expose the vias 201. Exposing the vias 201 may be achieved by a thinning process such as a grinding process, chemical mechanical polishing (CMP), etching back, combinations thereof, or the like. In some embodiments (not separately shown), the thinning process for exposing the vias 201 includes CMP, and the vias 201 protrude from the backside of the interposer 200 as a result of dishing that occurs during the CMP. In such embodiments, an insulating layer (not separately shown) may optionally be formed on the back surface of the substrate 202 surrounding the protruding portions of the vias 201.The insulating layer may be formed from a silicon-containing insulator such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition process such as spin coating, CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), or the like. After the substrate 202 has been thinned, the exposed surfaces of the vias 201 and the insulating layer (if present) or the substrate 202 (within process variations) are coplanar, so that they are at the same height, and are exposed at the backside of the interposer 200.

[0039] In Fig. 16, a backside redistribution structure 306 and UBMs 308 are formed on the exposed surfaces of the vias 201 and the substrate 202. The redistribution structure 306 may be formed from similar materials and by similar processes as the redistribution structure 240 described above. For example, the redistribution structure 306 may include one or more metallization layers in organic insulating materials. Furthermore, the UBMs 308 may be formed from similar materials and by similar processes as the UBMs 242 described above.

[0040] Conductive interconnects 310 are formed on the UBMs 308. The conductive interconnects 310 may consist of ball grid array (BGA) interconnects, solder balls, metal pillars, flip-chip interconnect bumps (C4) bumps, bumps formed by ENEPIG (electroless nickel-electroless palladium-gold immersion) technology, or the like. The conductive interconnects 310 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 310 are formed by initially forming a solder layer by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After a solder layer is formed on the structure, reflow may be performed to form the material into the desired bump shape.In another embodiment, the conductive connectors 310 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or a combination thereof and may be formed by a plating process.

[0041] In Fig. 17, a singulation process is next performed by cutting along scribe line regions. The singulation process may include sawing, dicing, or the like. For example, the singulation process may include sawing the encapsulation material 304, the redistribution structure 240, the interconnect structure 206, and the substrate 202. The singulation process singulates each package 300 from adjacent packages 300. The singulation process forms the interposer 200 from the singulated portions of the interposer wafer. As a result of the singulation process, the outer sidewalls of the interposer 200 (including the interconnect structure 206, the passivation layers 210 / 212, and the redistribution structure 240) and the encapsulation material 304 are laterally flush (within process variations). Furthermore, the encapsulation material 304 may completely surround the integrated circuit dies 100 in a plan view.

[0042] In Fig. 18, the package 300 is attached to a package substrate 400, thereby completing the formation of the integrated circuit package. A single package component 300, a single package substrate 400, and a single integrated circuit package are shown. It should be understood that multiple package components may be processed simultaneously to form multiple integrated circuit packages.

[0043] The package 300 is attached to a package substrate 400 using the conductive connectors 310. In some embodiments, the package substrate 400 includes a substrate core, which may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, or the like may be used. Further, the substrate core may be made of an SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In another embodiment, the substrate core is made of an insulating core, such as a glass fiber reinforced resin core. An example of a core material is a glass fiber resin such as FR4.Alternatives for the core material include bismaleimide triazine resin (BT resin) or other printed circuit board (PCB) materials or films. For the substrate core, build-up films such as Ajinomoto build-up film (ABF) or other laminates can be used.

[0044] The substrate core may include active and passive devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to meet the structural and functional design requirements for the system. The devices may be fabricated using any suitable methods.

[0045] The substrate core may also include metallization layers and vias, and bond pads 402 over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and configured to connect the various devices to form functional circuits. The metallization layers may be formed from alternating layers of dielectric material (e.g., low-k dielectric) and conductive material (e.g., copper), with vias connecting the conductive material layers, and may be formed by any suitable process (such as deposition, damascene, or the like). In some embodiments, the substrate core is substantially free of active and passive devices.

[0046] The conductive connectors 310 are reflowed to attach the UBMs 308 to the bond pads 402. The conductive connectors 310 connect the interposer 200, such as the metallization structures of the redistribution structure 240 and the metallization structures of the interconnect structure 206, to the package substrate 400, such as the metallization layers of the substrate core. Thus, the package substrate 400 is electrically connected to the integrated circuit dies 100. In some embodiments, passive devices (e.g., surface-mounted devices (SMDs), not shown separately) may be attached to the interposer 200 (e.g., bonded to the UBMs 308) before it is mounted to the package substrate 400. In such embodiments, the passive devices may be bonded to a same surface of the package 300 as the conductive connectors 310. In some embodiments, passive devices (e.g.,SMDs, not shown separately) are attached to the package substrate 400, e.g., to the bond pads 402.

[0047] In some embodiments, an underfill (not shown separately) is formed between the package 300 and the package substrate 400, surrounding the conductive connectors 310. The underfill may be formed by a capillary flow process after the package 300 is attached, or may be formed by any suitable deposition method before the package component 300 is attached. The underfill may be comprised of a continuous material extending from the package substrate 400 to the redistribution structure 306.

[0048] The Fig. 13 to 18 show manufacturing steps for packaging the interposer 200 while it is part of a wafer and before a dicing process is performed on the interposer 200. The Fig. 19 to 25 show cross-sectional views of various intermediate steps for applying further processing steps for packaging the interposer 200 according to some embodiments. Fig. 19 to 25, the interposer 200 is packaged after being singulated and separated from other interposers in a wafer. Although the interposer 200 is shown, it is understood that the process steps of the Fig. 19 to 25 can also be used to connect the interposer 200' from Fig. 11 and / or the Interposer 200" from Fig. 12 to pack.

[0049] In Fig. 19, a carrier substrate 500 is provided, and a separation layer 502 is formed on the carrier substrate 500. The carrier substrate 500 may be made of a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 500 may be made of a wafer, so that multiple packages can be formed simultaneously on the carrier substrate 500.

[0050] The release layer 502 may be formed from a polymer-based material that can be removed along with the support substrate 500 from overlying structures formed in subsequent steps. In some embodiments, the release layer 502 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 502 may be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 502 may be dispensed and cured as a liquid, may consist of a laminate film laminated to the support substrate 500, or the like. The top surface of the release layer 502 may be planarized and have a high degree of planarity.

[0051] Vias 504 are formed on the support substrate 500. As an example for forming the vias 504, a seed layer (not shown) is formed over the support substrate 500 and on the separation layer 502. In some embodiments, the seed layer is a metal layer, which may consist of a single layer or a composite layer comprising multiple sublayers formed from different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the conductive vias.Patterning forms openings through the photoresist, exposing the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching.The remaining portions of the seed layer and conductive material form the vias 504.

[0052] In Fig. 20, singulated interposers 200 (labeled 200A and 200B) are adhered to the separation layer 502 with an adhesive (not shown separately). Each of the interposers 200 may be singulated, and a planarization process (e.g., a CMP process, an etch-back process, and / or the like) may be applied to a backside of the interposers 200 such that the vias 201 are exposed before the interposers 200 are attached to the carrier substrate 500. A desired type and quantity of interposers 200 are adhered to each region of the carrier substrate 500. In the illustrated embodiment, multiple interposers 200 are adhered adjacent to one another, such as the interposers 200A and the interposers 200B. The interposers 200A may include redistribution structures 240 with organic insulating layers (e.g., as described above in the Fig. 1 to 12), while the interposers 200B may be free of redistribution structures with organic insulating layers. Instead, the interposers 200B may include only the interconnect structure 206, and all metallization structures in the interposer 200B may be formed by damascene processes. In some embodiments, the interposers 200A may be referred to as local silicon interconnect (LSI) dies, and the interposers 200B may be referred to as local redistribution layer interconnect (LRI) dies. The interposers 200A and 200B may have different sizes (e.g., different heights and / or areas) or the same size (e.g., the same height and / or area).

[0053] In Fig. 21, an encapsulation material 506 is formed on and around the various components. Once formed, the encapsulation material 506 encapsulates the vias 504 and the interposers 200. The encapsulation material 506 may be made of a molding compound, an epoxy resin, or the like. The encapsulation material 506 may be deposited by compression molding, transfer molding, or the like and may be formed over the carrier substrate 500 such that the vias 504 and / or the interposers 200 are buried or covered. The encapsulation material 506 is further formed in gap regions between the interposers 200. The encapsulation material 506 may be deposited in liquid or semi-liquid form and subsequently cured.

[0054] The encapsulation material 506 may initially be deposited to bury the interposers 200 and the vias 504. A planarization process is performed on the encapsulation material 506 to expose the vias 504, the UBMs 242 of the interposers 200A, and the conductive interconnects 214 of the interposers 200B. The top surfaces of the vias 504, the UBMs 242, the conductive interconnects 214, and the encapsulation material 506 are substantially coplanar after the planarization process, subject to process variations. The planarization process may, for example, consist of a CMP, a grinding process, or the like.

[0055] In Fig. 22, a redistribution structure 508 is formed over the interposers 200, the vias 504, and the encapsulation material 506, and UBMs 510 may be formed over the redistribution structure 508. The redistribution structure 508 may be formed from similar materials and by similar processes as the redistribution structure 240 described above. For example, the redistribution structure 508 may include one or more metallization layers in organic insulating materials. Further, the UBMs 510 may be formed from similar materials and by similar processes as the UBMs 242 described above. In some embodiments, the UBMs 510 may each have a uniform size. In further embodiments (as shown), the UBMs 510 may have different sizes to enable the placement of different types of dies and / or die stacks over the UBMs 510.

[0056] In Fig. 23, integrated circuit dies 100 (e.g., a first integrated circuit die 100A and a plurality of second integrated circuit dies 100B) are attached to the redistribution structure 508. The integrated circuit dies 100 may be provided to the interposer 200 in Fig. 1, wherein the integrated circuit dies 100 include active devices interconnected by an interconnect structure to form functional circuits. In the illustrated embodiment, multiple integrated circuit dies 100 are arranged side by side, for example, the first integrated circuit die 100A and the second integrated circuit dies 100B, with the first integrated circuit die 100A sandwiched between the second integrated circuit dies 100B. In some embodiments, the first integrated circuit die 100A consists of a logic device, such as a CPU, GPU, or the like, and the second integrated circuit dies 100B consist of memory devices, such as DRAM dies, HMC modules, HBM modules, or the like. In some embodiments, the first integrated circuit die 100A consists of the same device type (e.g., SoCs) as the second integrated circuit dies 100B.In the illustrated embodiment, the integrated circuit dies 100 are attached to the redistribution structure 508 with solder connections such as conductive connectors 102 on the UBMs 510 in a manner similar to that described above. Thus, the redistribution structure 508 may electrically connect the integrated circuit dies 100 to the interposers 200 and the vias 504. In further embodiments, the integrated circuit dies 100 may be attached to the redistribution structure 508 using a different bonding technique. An underfill 302 may be formed around the conductive connectors 102, and an encapsulation material 304 is formed on and around the integrated circuit dies 100 as described above.

[0057] In Fig. 24, a carrier substrate debonding is performed to separate (or "debond") the carrier substrate 500 from the interposers 200 and the encapsulation material 506. According to some embodiments, the debonding includes projecting a light, such as a laser light or a UV light, onto the release layer 502 so that the release layer 502 decomposes under the heat of the light and the carrier substrate 500 can be removed. The structure is then flipped over and placed on a tape (not shown). After the carrier substrate 500 is removed, a backside redistribution structure 306 and UBMs 308 are formed on the exposed surfaces of the interposers 200 and the vias 504. The redistribution structure 306 may be formed from similar materials and by similar processes as the redistribution structure 240 described above.For example, the redistribution structure 306 may include one or more metallization layers in organic insulating materials. Furthermore, the UBMs 308 may be formed from similar materials and by similar processes as the UBMs 242 described above. Vias 504 establish interconnections between the redistribution structures 306 and 508.

[0058] In Fig.25, a singulation process is applied to separate individual packages 550 from other packages formed on the carrier substrate 500. The singulation process may include sawing, dicing, or the like. For example, the singulation process may include sawing the encapsulation material 304, the redistribution structure 508, the encapsulation material 506, and the redistribution structure 306. The singulation process singulates each package 550 from adjacent packages 550. As a result of the singulation process, the outer sidewalls of the encapsulation material 304, the redistribution structures 508 and 306, and the encapsulation material 506 are laterally flush (within process variations). The package 550 is then attached to a package substrate 400 in a manner similar to that described above, thereby completing the formation of the integrated circuit package.

[0059] According to some embodiments, semiconductor devices may be bonded together to fabricate a package comprising multiple dies bonded with an interposer. The interposer may include metallization layers plated in patterned photoresist masks, which are subsequently replaced with organic insulating layers. Optionally, the interposer may further include additional metallization layers formed in inorganic insulating materials using damascene processes. The use of metallization layers in organic insulating layers provides improved signal integrity and / or power integrity at high operating frequencies (e.g., higher than 20 GHz). Furthermore, embodiments with metallization layers formed in both organic and inorganic insulating materials may provide improved flexibility in terms of processing and packaging design.

[0060] In some embodiments, a device package includes an interposer comprising: a semiconductor substrate; first vias extending through the semiconductor substrate, the via protruding from a front surface of the semiconductor substrate; an interconnect structure over the front surface of the semiconductor substrate. The interconnect structure includes: a first metallization structure in an inorganic insulating material; and a passivation film over the first metallization structure. The interposer further includes a first redistribution structure over the passivation film, the first redistribution structure including a second metallization structure in an organic insulating material, the first redistribution structure being flush with the interconnect structure and the semiconductor substrate.The device package further includes an integrated circuit die over and attached to the interposer; and a first encapsulation material around the integrated circuit die. Optionally, in some embodiments, the interconnect structure further includes a contact pad in the passivation film, wherein the second metallization structure is electrically connected to the contact pad, and wherein the contact pad is made of a different material than the first metallization structure. Optionally, in some embodiments, the contact pad is made of aluminum. Optionally, in some embodiments, the second metallization structure extends through the passivation film of the first metallization structure. Optionally, in some embodiments, the organic insulating material extends through the passivation film. Optionally, in some embodiments, the interposer and the first encapsulation material are flush.Optionally, in some embodiments, the package further comprises a second encapsulation material around the interposer; and a second redistribution structure over the interposer and the second encapsulation material, the second redistribution structure electrically connecting the integrated circuit die to the interposer. Optionally, in some embodiments, the package further comprises second vias extending through the second encapsulation material. Optionally, in some embodiments, the package further comprises a third redistribution structure on a side opposite the integrated circuit die. Optionally, in some embodiments, the interposer is free of any active devices.

[0061] In some embodiments, a device package includes an interposer that is free of any active devices, the interposer comprising: a semiconductor substrate; an interconnect structure comprising a first metallization structure in a first insulating material; and a first redistribution structure comprising a second metallization structure in a second insulating material, wherein the second insulating material has a lower loss factor than the first insulating material.The device package further includes an integrated circuit die electrically connected to the interposer, wherein the interconnect structure and the first redistribution structure are each located between the integrated circuit die and the semiconductor substrate; a first encapsulation material around the integrated circuit die, wherein the first encapsulation material completely surrounds the integrated circuit die in a plan view, wherein outer sidewalls of the first encapsulation material are flush with outer sidewalls of the interposer; and a second redistribution structure on a side of the interposer opposite the integrated circuit die. Optionally, in some embodiments, the first insulating material is an inorganic material, and wherein the second insulating material is an organic material.Optionally, in some embodiments, the first metallization structure is electrically connected to the second metallization structure through an aluminum contact pad. Optionally, in some embodiments, the first metallization structure is in physical contact with the second metallization structure.

[0062] In some embodiments, a method comprises forming an interconnect structure on a substrate, the interconnect structure having a first metallization structure formed by a damascene process; forming a redistribution structure on the interconnect structure, the redistribution structure having a second metallization structure formed by a different type of process than the first metallization structure; bonding an integrated circuit die over the redistribution structure; encapsulating the integrated circuit die in an encapsulation material; and performing a singulation process. Performing the singulation process comprises singulating through the interconnect structure, the redistribution structure, and the encapsulation material.Optionally, in some embodiments, the damascene process comprises: patterning an opening in an inorganic dielectric layer; and plating the first metallization structure in the opening. Optionally, in some embodiments, forming the second metallization structure comprises: depositing a seed layer over the interconnect structure; patterning an opening in a photoresist over the seed layer; plating the second metallization structure in the opening; removing the photoresist; and depositing an organic insulating material around the second metallization structure. Optionally, in some embodiments, the method further comprises, after bonding the integrated circuit die, performing a singulation process on the interconnect structure, the redistribution structure, and the substrate.Optionally, in some embodiments, the method further comprises performing a singulation process on the interconnect structure, the redistribution structure, and the substrate prior to bonding the integrated circuit die. Optionally, in some embodiments, the method further comprises forming an aluminum contact pad over the first metallization structure, wherein the aluminum contact pad electrically connects the first metallization structure to the second metallization structure.

Claims

[1] Device package (300, 550), comprising: an interposer (200), comprising: a semiconductor substrate (202); first vias (201) extending through the semiconductor substrate (202), the vias (201) protruding from a front side of the semiconductor substrate (202); an interconnect structure (206) over the front side of the semiconductor substrate (202), the interconnect structure (206) comprising: a first metallization structure (206A) in an inorganic insulating material (206B); and a passivation film (210, 212) over the first metallization structure (206A); and a first redistribution structure (240) over the passivation film (210, 212), the first redistribution structure (240) comprising a second metallization structure (218, 222, 226, 230, 234) in an organic insulating material (216, 220, 224, 228, 232, 236), the first redistribution structure (240) being flush with the interconnect structure (206) and the semiconductor substrate (202); an integrated circuit die (100A) over and attached to the interposer (200); and a first encapsulation material (304) around the integrated circuit die (100A). [2] The device package (300, 550) of claim 1, wherein the interconnect structure (206) further comprises a contact pad (208) in the passivation film (210, 212), wherein the second metallization structure (218, 222, 226, 230, 234) is electrically connected to the contact pad (208), and wherein the contact pad (208) is made of a different material than the first metallization structure (206A). [3] The device package (300, 550) of claim 2, wherein the contact pad (208) is made of aluminum. [4] The device package (300, 550) of any preceding claim, wherein the second metallization structure (218) extends through the passivation film (210, 212) of the first metallization structure (206A). [5] The device package (300, 550) of claim 4, wherein the organic insulating material (216) extends through the passivation film (210, 212). [6] The device package (300, 550) of any preceding claim, wherein the interposer (200) and the first encapsulation material (304) are flush. [7] Device package (300, 550) according to one of the preceding claims, further comprising: a second encapsulation material (506) around the interposer (200); and a second redistribution structure (508) over the interposer (200) and the second encapsulation material, the second redistribution structure (508) electrically connecting the integrated circuit die (100A) to the interposer (200). [8] The device package (300, 550) of claim 7, further comprising second vias (504) extending through the second encapsulation material (506). [9] The device package (300, 550) of any preceding claim, further comprising a third redistribution structure (306) on a side of the interposer opposite the integrated circuit die (100A). [10] Device package (300, 550) according to one of the preceding claims, wherein the interposer (200) is free of any active devices. [11] Device package (300, 550), comprising: an interposer (200) which is free of any active devices, the interposer (200) comprising: a semiconductor substrate (202); an interconnect structure (206) having a first metallization structure (206A) in a first insulating material (206B); and a first redistribution structure (240) comprising a second metallization structure (218, 222, 226, 230, 234) in a second insulating material (216, 220, 224, 228, 232, 236), wherein the second insulating material (216, 220, 224, 228, 232, 236) has a lower loss factor than the first insulating material (206B); an integrated circuit die (100A) electrically connected to the interposer (200), wherein the interconnect structure (206) and the first redistribution structure (240) are each located between the integrated circuit die (100A) and the semiconductor substrate (202); a first encapsulation material (304) around the integrated circuit die (100A), wherein the first encapsulation material (304) completely surrounds the integrated circuit die (100A) in a plan view, wherein outer sidewalls of the first encapsulation material are flush with outer sidewalls of the interposer (200); and a second redistribution structure (306) on a side of the interposer (200) opposite the integrated circuit die (100A), wherein the first metallization structure (206A) is electrically connected to the second metallization structure (218, 222, 226, 230, 234) by an aluminum contact pad (208). [12] The device package (300, 550) of claim 11, wherein the first insulating material (206B) is an inorganic material, and wherein the second insulating material (216, 220, 224, 228, 232, 236) is an organic material. [13] The device package (300, 550) of claim 11 or 12, wherein the first metallization structure (206A) is in physical contact with the second metallization structure (218). [14] Method comprising: Forming an interconnect structure (206) on a substrate (202), the interconnect structure (206) having a first metallization structure (206A) formed by a damascene process; Forming a redistribution structure (240) on the interconnect structure (206), the redistribution structure (240) comprising a second metallization structure (218, 222, 226, 230, 234) formed by a different type of process than the first metallization structure (206A); Bonding an integrated circuit die (100A) over the redistribution structure (240); Encapsulating the integrated circuit die (100A) in an encapsulation material (304); and Performing a singulation process, wherein performing the singulation process comprises singulating through the interconnect structure (206), the redistribution structure (240) and the encapsulation material (304). [15] The method of claim 14, wherein the damascene process comprises: Structuring an opening in an inorganic dielectric layer (206B); and Plating the first metallization structure (206A) in the opening. [16] The method of claim 14 or 15, wherein forming the second metallization structure (218, 222, 226, 230, 234) comprises: depositing a seed layer over the interconnect structure (206); Patterning an opening in a photoresist over the seed layer; Plating the second metallization structure (218, 222, 226, 230, 234) in the opening. Removing the photoresist; and Depositing an organic insulating material (216, 220, 224, 228, 232, 236) around the second metallization structure (218, 222, 226, 230, 234). [17] The method of claim 16, further comprising, after bonding the integrated circuit die (100A), performing a singulation process on the interconnect structure (206), the redistribution structure (240), and the substrate (202). [18] The method of any one of claims 14 to 17, further comprising forming an aluminum contact pad over the first metallization structure (206A), the aluminum contact pad electrically connecting the first metallization structure (206A) to the second metallization structure (218, 222, 226, 230, 234).

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