Integrated chips with thermal barrier structures in phase-change material devices and their fabrication

Abstract

Integrated chip that features: a heating structure overlying a semiconductor substrate; a phase change element, PWE, arranged above the heating structure; a thermal barrier structure disposed between the heating structure and the PWE, wherein outer sidewalls of the PWE are laterally spaced between outer sidewalls of the thermal barrier structure; and a sidewall spacer structure disposed on the outer sidewalls of the PWE, the sidewall spacer structure contacting a top surface of the thermal barrier structure.

Description

BACKGROUND

[0001] Modern integrated circuits (ICs) comprise millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). ICs can use many different types of transistor devices depending on the application. In recent years, the growing market for cellular and radio frequency (RF) devices has led to a significant increase in demand for RF switching devices. A smartphone, for example, may have ten or more RF switching devices to switch a received signal to the correct bands.

[0002] The prior art relating to the subject matter of the invention can be found, for example, in the documents US 2020 / 0 058 856 A1 and US 2020 / 0 058 853 A1.

[0003] The task is to improve corresponding RF switching devices.

[0004] The object is achieved by the integrated chips according to patent claims 1 and 8 and the method according to patent claim 14. Further embodiments of the invention are disclosed in the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1A-1B illustrate various views of some embodiments of a phase change material (PWM) device having a thermal barrier structure configured to enhance performance of the PWM device. Fig. 2A-2C and 3A-3C illustrate various views of some other embodiments of the PWM device of the Fig. 1A-1B. Fig. 4A-4C illustrate various views of some alternative embodiments of the PWM device of the Fig. 1A-1B, wherein a sidewall spacer structure is disposed along sidewalls of a phase change element (PWE) of the PWM device. Fig. 5A-5B and 6A-6B illustrate various cross-sectional views of some other embodiments of the PWM device of the Fig. 4A-4C. Fig. 7A-7B illustrate various views of some embodiments of an integrated chip having a PWM device including a thermal barrier structure disposed within an interconnect structure. Fig. 8A-8B illustrate various cross-sectional views of some other embodiments of the integrated chip of the Fig. 7A-7B. Fig. 9A to 9C illustrate various views of some other embodiments of the integrated chip of the Fig. 7A to 7B, wherein a sidewall spacer structure is arranged along sidewalls of a PWE of the PWM device. Fig. 10A-10C illustrate various views of some other embodiments of the PWM device of the Fig. 4A-4C. Fig. 11A-11B and 12A-12B illustrate various cross-sectional views of some other embodiments of the PWM device of the Fig. 10A-10C. Fig. 13 illustrates a graph corresponding to some other embodiments of performance examples of a PWM device having a thermal barrier structure. Fig. Fig. 14A-14C to 23A-23C illustrate various views of some embodiments of a method of forming an integrated chip including a PWM device having a thermal barrier structure configured to enhance performance of the PWM device. Fig. 24 illustrates, in flowchart format, a methodology of some embodiments of a method for forming an integrated chip including a PWM device having a thermal barrier structure configured to enhance performance of the PWM device. Fig. Fig. 25A-25C to 31A-31C illustrate various views of some embodiments of a method of forming an integrated chip including a PWM device having a thermal barrier structure and a sidewall spacer structure configured to enhance performance of the PWM device. Fig. 32 illustrates, in flowchart format, a methodology of some embodiments of a method for forming an integrated chip including a PWM device having a thermal barrier structure and a sidewall spacer structure configured to enhance performance of the PWM device. DETAILED DESCRIPTION

[0006] The present disclosure provides many different embodiments or examples of implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments where the first and second structural elements are formed in direct contact, and may also include embodiments where additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] A phase-change material (PWM) device may include a phase-change element (PWE) disposed over a heater structure. The PWE has a crystalline phase and an amorphous phase with different values ​​of electrical resistivity, such that the PWM device is configured to switch between discrete resistive states. The heater structure is configured to generate heat during operation of the PWM device based on an applied switching signal (e.g., a voltage or current signal) that adjusts the phase of the PWE. For example, the PWM device may be switched to a first state (e.g., an "OFF" state) by heating the PWE to a high temperature (e.g., by applying a high current and / or high voltage to the heater structure) and then cooling the PWE after heating.Heating and cooling causes the PWE to be in the amorphous phase (corresponding, for example, to a high-resistance state). Furthermore, the PWM device can be switched to a second state (e.g., an "ON" state) by heating the PWE to a moderate temperature for an extended period of time (e.g., by applying a moderate voltage and / or current to the heating structure). This causes the PWE to be in the crystalline phase (corresponding, for example, to a low-resistance state). The switching operation of the PWM device thus depends on a temperature applied to the PWE by the heating structure.

[0009] The PWM device may further include a thermal barrier structure disposed between the PWE and the heater structure. The thermal barrier structure is configured to increase a distance between the heater structure and the PWE (i.e., increase the insulation between the PWE and the heater structure) and / or to distribute the heat generated by the heater structure more evenly across the PWE, thereby reducing damage to the PWE during switching operations. The PWE and the thermal barrier structure may be formed by a single etching process such that the outer sidewalls of the PWE are aligned with the outer sidewalls of the thermal barrier structure. The thermal barrier structure may adjust a breakdown voltage of the PWM device, for example, by adjusting a thickness, a layout, and / or a material of the thermal barrier structure.Additionally, the heater structure may include a central heater segment extending continuously between a first outer heater segment and a second outer heater segment. The PWE and the thermal barrier structure lie directly above the central heater segment such that the outer sidewalls of the PWE and the thermal barrier structure lie directly above outer regions of the central heater segment. During operation of the PWM device, a switching signal (e.g., a current and / or voltage signal) is applied to the central heater segment of the heater structure to heat the PWE and adjust its phase. However, significant heat can accumulate in the outer regions of the central heater segment.Because the outer sidewalls of the PWE and the thermal barrier structure at the outer regions of the center heater segment are aligned, the intense heat is not evenly distributed across the PWE, and the PWE may be damaged at relatively low voltages (e.g., approximately 7 volts). For example, the intense heat at the outer regions of the center heater segment may cause deformation, cracking, or delamination of the PWM and / or the thermal barrier structure around the outer sidewalls of the PWE, thereby reducing the breakdown voltage of the PWM device (e.g., the breakdown voltage is reduced to approximately 7 volts). As a result, the operating voltage range, stability, and overall performance of the PWM device are reduced.

[0010] Various embodiments of the present disclosure relate to a PWM device having a thermal barrier structure configured to enhance performance of the PWM device. The PWM device overlies a substrate. The PWM device includes a PWE and a heater structure having a central heater segment extending continuously between a first outer heater segment and a second outer heater segment. The PWE directly overlies the central heater segment and has outer sidewalls overlying outer regions of the central heater segment. Furthermore, a thermal barrier structure is disposed between the PWE and the heater structure. The outer sidewalls of the PWE are spaced between outer sidewalls of the heater barrier structure such that the thermal barrier structure extends outwardly from the outer sidewalls of the PWE.As a result, the thermal barrier structure strengthens the insulation between the heater structure and the PWE (e.g., at the outer regions of the central heater segment) and improves the even distribution of heat from the heater structure across the PWE. This prevents damage to the PWE during switching operations and increases the breakdown voltage of the PWM device (e.g., to above approximately 14 volts). Thus, the thermal barrier structure increases the operating voltage range, stability, robustness, and overall performance of the PWM device.

[0011] Fig. 1A and Fig. 1B illustrate various views of some embodiments of an integrated chip including a PWM device 104 having a thermal barrier structure 108 configured to enhance performance of the PWM device 104. Fig. 1A illustrates a cross-sectional view 100a corresponding to some embodiments of the integrated chip. Fig. 1B illustrates a top view 100b, corresponding to some embodiments of the integrated chip, taken along line AA' of the cross-sectional view 100a of Fig. 1A.

[0012] The integrated chip includes a PWM device 104 overlying a semiconductor substrate 102. In some embodiments, the PWM device 104 includes a heater structure 106, a thermal barrier structure 108, a phase change element (PWE) 110, and a hard mask 112. The thermal barrier structure 108 is disposed between the PWE 110 and the heater structure 106. The hard mask 112 overlies the PWE 110. A top dielectric layer 116 is disposed over and around the PWM device 104, and a cap layer 114 is disposed between the top dielectric layer 116 and the PWM device 104. The capping layer 114 extends continuously from outer sidewalls 1100s1, 1100s2 of the PWE 110 along outer sidewalls of the hard mask 112 to a top surface of the hard mask 112.

[0013] In some embodiments, the PWE 110 may include a PWM, such as one or more chalcogenide materials including at least one chalcogen ion (e.g., a chemical element in column VI of the periodic table), germanium antimony telluride (GST), another suitable phase-change alloy, or another suitable material. The PWE 110 may have a crystalline phase or an amorphous phase with different electrical resistivity values ​​that can be adjusted based on heat supplied to the PWE 110. The heater structure 106 is configured to generate heat during operation of the PWM device 104 based on an applied switching signal (e.g., a voltage or current signal) that adjusts the phase of the PWE 110.For example, the PWM device 104 may be switched to a first state (e.g., an "OFF" state) by heating the PWE 110 to a high temperature (e.g., about 700 degrees Celsius) and then cooling the PWE 110. Heating to the high temperature and then cooling causes the PWE 110 to be in the amorphous phase (e.g., corresponding to a high-resistance state). Furthermore, the PWM device 104 may be switched to a second state (e.g., an "ON" state) by heating the PWE 110 to a moderate temperature (e.g., above about 200 degrees Celsius or within a range of about 200 to 300 degrees Celsius) for an extended period of time. Heating at the moderate temperature causes the PWE 110 to be in the crystalline phase (e.g., corresponding to a low-resistance state).The switching operation of the PWM device 104 thus depends on a temperature applied to the PWE 110 by the heater structure 106. In some embodiments, the PWE 110 is referred to or configured as a switching layer, a data storage layer, or the like. In further embodiments, the PWM device 104 may be configured as a PWM switch, an RF switch, a PWM memory device, or the like.

[0014] The heater structure 106 includes a first outer heater segment 106a, a second outer heater segment 106b, and a middle heater segment 106c that extends continuously laterally between the first outer heater segment 106a and the second outer heater segment 106b. During operation of the PWM device 104, the switching signal is applied to the first outer heater segment 106a and / or the second outer heater segment 106b across the middle heater segment 106c, thereby generating heat at the middle heater segment 106c. At least a middle region of the PWE 110 lies directly above the middle heater segment 106c such that the heat generated at the middle heater segment 106c can adjust the phase of the PWE. The thermal barrier structure 108 is disposed vertically between the heater structure 106 and the PWE 110.The thermal barrier structure 108 is configured to increase a distance between the heater structure 106 and the PWE 110 and / or to distribute the heat generated by the heater structure 106 more evenly across the PWE 110, thereby reducing damage to the PWE 110 during switching operations. Furthermore, outer sidewalls of the thermal barrier structure 108 extend beyond the outer sidewalls 1100s1, 1100s2 of the PWE 110. In some embodiments, as shown in top view 100b of FIG. Fig. 1B, the thermal barrier structure 108 includes a similar shape to the heater structure 106 and is larger than the heater structure 106, directly overlying an outer periphery of the heater structure 106.

[0015] In various embodiments, during operation of the PWM device 104, significant heat (e.g., approximately 600 to 700 degrees Celsius or more) may accumulate at outer regions 130, 132 of the center heater segment 106c (e.g., during a switching operation). Because the outer sidewalls 1100s1, 1100s2 of the PWE 110 are disposed between the outer sidewalls of the thermal barrier structure 108, the thermal barrier structure 108 may provide greater insulation between the PWE 110 and the heater structure 106 at the outer regions 130, 132 of the center heater segment 106c. As a result, the thermal barrier structure 108 mitigates damage (e.g., deformation, cracking, delamination, etc.) to the PWM 110 during switching operations, thereby increasing the breakdown voltage of the PWM device 104 (e.g., to above about 14 volts). Thus, the thermal barrier structure 108 increases the stability, robustness, and overall performance of the PWM device 104.

[0016] With reference to plan view 100b of Fig. 1B, the PWM device 104 further comprises a first radio frequency (RF) structure 120 and a second RF structure 122. It can be seen that, for clarity, the PWE 110 is at least partially transparent, that an outer perimeter of the thermal barrier structure 108 is illustrated in dashed lines, and that the capping layer 114 in the top view 100b of Fig. 1B has been omitted. Furthermore, an etch stop layer 126 is arranged along top surfaces of the first and second RF structures 120, 122. The first and second RF structures 120, 122 are configured to perform a read operation on the PWM device 104. For example, the first RF structure 120 is configured to transmit an RF signal through the PWE 110 to the second RF structure 122. In various embodiments, a strength of the RF signal received by the second RF structure 122 depends on the phase of the PWE 110. For example, when the RF signal is transmitted from the first RF structure 120 through the PWE 110 while the PWE 110 is in the amorphous phase, a strength of the RF signal received at the second RF structure 122 (e.g., a signal reception strength) may be relatively low.In another example, a strength of the RF signal received at the second RF structure 122 may be relatively high when the RF signal is transmitted from the first RF structure 120 through the PWE 110 while the PWE is in the crystalline phase. In further embodiments, the RF signal may or may not pass through the PWE 110 depending on the phase of the PWE 110. In further embodiments, the second RF structure 122 may be configured to transmit the RF signal to the first RF structure 120, and the first RF structure 120 is configured to receive the RF signal. Accordingly, the first and second RF structures 120, 122 are configured to perform non-destructive read operations on the PWM device 104 and determine a state of the PWM device 104.

[0017] In further embodiments, due to a layout and / or proximity between the heater structure 106 and the first and / or second RF structures 120, 122, leakage currents may occur between the first and / or second RF structures 120, 122 and the heater structure 106 (e.g., the first and / or second outer heater segments 106a, 106b) during the read operation. This may partially lead to inaccurate read operations (e.g., because the heater structure 106 interferes with the RF signal). Due to a material, a layout, a thickness, and / or an area of ​​the thermal barrier structure 108, the thermal barrier structure 108 enhances the insulation between the first and / or second RF structure 120, 122 and the heater structure 106, thereby reducing leakage currents between the first and / or second RF structure 120, 122 and the heater structure 106.As a result, reading operations in the PWM device 104 can be performed precisely, thereby increasing an overall performance of the PWM device 104.

[0018] Fig. 2A-2C illustrate various views of some embodiments of an integrated chip including a PWM device 104 having a thermal barrier structure 108 configured to enhance performance of the PWM device 104. Fig. 2A illustrates a cross-sectional view 200a, corresponding to some embodiments of the integrated chip, along the line AA' of a top view 200c of Fig. 2C. Fig. Figure 2B illustrates a cross-sectional view 200b, corresponding to some embodiments of the integrated chip, taken along line BB' of the top view 200c of Fig. 2C.

[0019] The integrated chip includes a PWM device 104 overlying a semiconductor substrate 102. The semiconductor substrate 102 may be or comprise, for example, silicon, monocrystalline silicon, a bulk substrate, a silicon-on-insulator (SOI) substrate, another suitable substrate, or the like. The PWM device 104 includes a heater structure 106, a thermal barrier structure 108, a PWE 110, and a hard mask 112. The thermal barrier structure 108 is disposed vertically between the PWE 110 and the heater structure 106. The heater structure 106 may be or comprise, for example, tungsten, titanium, titanium nitride, molybdenum, another conductive material, or any combination of the foregoing. The thermal barrier structure 108 may be or include, for example, silicon nitride, silicon carbide, aluminum nitride, a high-k dielectric material, another suitable material, or any combination of the foregoing.As used herein, a high-k dielectric material is a dielectric material with a dielectric constant greater than 3.9. The hard mask 112 may be or include, for example, silicon nitride, silicon carbide, silicon dioxide, another dielectric material, or any combination of the foregoing. In further embodiments, the hard mask 112 may include a first hard mask layer (not shown) disposed on the PWE and a second hard mask layer (not shown) on top of the first hard mask layer. In such embodiments, the first hard mask layer may include a first dielectric material (e.g., silicon nitride, silicon carbide, etc.), and the second hard mask layer may include a second dielectric material (e.g., an oxide, silicon dioxide, etc.).

[0020] The heater structure 106 is disposed within a lower dielectric layer 202. Furthermore, an upper dielectric layer 116 overlies the PWM device 104. The lower dielectric layer 202 and the upper dielectric layer 116 may each be or comprise, for example, silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant of less than about 3.9. A capping layer 114 is disposed between the upper dielectric layer 116 and the PWM device 104. The capping layer 114 may comprise a non-oxygen-based dielectric material, another dielectric material, or any combination of the foregoing.The non-oxygen-based dielectric material may be, for example, silicon nitride, silicon carbide, or the like.

[0021] Furthermore, the heater structure 106 comprises a first outer heater segment 106a, a second outer heater segment 106b, and a middle heater segment 106c. The middle heater segment 106c is arranged laterally between the first outer heater segment 106a and the second outer heater segment 106b. The PWE 110 and the hard mask 112 lie directly above the middle heater segment 106c and are laterally spaced between the first and second outer heater segments 106a, 106b. Furthermore, a first radio frequency (RF) structure 120 and a second RF structure 122 are arranged within the lower dielectric layer 202. The middle heater segment 106c is arranged laterally between the first RF structure 120 and the second RF structure 122.The first and second RF structures 120, 122 may, for example, each be or comprise tungsten, aluminum, copper, titanium nitride, another conductive material, or any combination of the foregoing. In various embodiments, the heater structure 106 may comprise a first conductive material (e.g., tungsten), and the first and second RF structures 120, 122 may comprise a second conductive material (e.g., copper, aluminum, etc.) that is different from the first conductive material. Furthermore, an etch stop layer 126 directly overlies the first and second RF structures 120, 122. The etch stop layer 126 may, for example, be or comprise silicon nitride, silicon carbide, aluminum nitride, another dielectric material, or any combination of the foregoing.

[0022] With reference to the cross-sectional view 200a of Fig. 2A, in some embodiments, the thermal barrier structure 108 has a first length L1 that is greater than a second length L2 of the PWE 110. Furthermore, the heater structure 106 has a third length L3 that is less than the first length L1 and greater than the second length L2. In various embodiments, due to the fact that the thermal barrier structure 108 has the first length L1 that is greater than the second length L2 of the PWE 110, the thermal barrier structure 108 can provide greater insulation between the PWE 110 and the heater structure 106 (e.g., at outer regions of the central heater segment 106c). As a result, damage (e.g., peeling and / or lifting of outer edges of the PWE 110 under high heat) to the PWE 110 during operation of the PWM device 104 is reduced.

[0023] Furthermore, the thermal barrier structure 108 has a first thickness t1, which may, for example, be within a range of about 30.0 nm to about 60.0 nm or another suitable value. In various embodiments, when the first thickness t1 is sufficiently thick (for example, about 30.0 nm or more), the PWE 110 is sufficiently insulated from relatively high heat during operation of the PWM device 104, and / or the thermal barrier structure 108 may more effectively distribute heat more evenly across the PWE 110, thereby increasing a robustness (for example, a number of switching operations that can be performed) of the PWM device 104.In further embodiments, when the first thickness t1 is less than about 60.0 nm, a heat transfer efficiency between the heater structure 106 and the PWE 110 is increased, thereby reducing the current consumed during the reading and / or switching operations performed in the PWM device 104. In some embodiments, the PWE 110 has a second thickness t2, which may, for example, be within a range of about 50.0 nm to about 100.0 nm or another suitable value. In further embodiments, the first thickness t1 of the thermal barrier structure 108 is less than the second thickness t2 of the PWE 110. In further embodiments, the capping layer 114 has a third thickness t3, which may, for example, be within a range of about 10.0 nm to about 40.0 nm. In various embodiments, the third thickness t3 may be less than the first thickness t1 and may be less than the second thickness t2.

[0024] With reference to the cross-sectional view 200b of Fig. 2B, the thermal barrier structure 108 extends laterally beyond outer sidewalls of the middle heater segment 106c of the heater structure 106. Furthermore, the etch stop layer 126 overlies outer regions of the first and second RF structures 120, 122. In various embodiments, a thickness of the etch stop layer 126 is equal to the first thickness t1 of the thermal barrier structure 108. In some embodiments, the etch stop layer 126 comprises a same material as the thermal barrier structure 108. Furthermore, the PWE 110 may extend continuously from opposite sidewalls of the thermal barrier structure 108 to a top surface of the thermal barrier structure 108. A bottom surface of the PWE 110 may be aligned with a bottom surface of the thermal barrier structure 108. Additionally, the PWE 110 directly overlies portions of the first and second RF structures 120, 122.

[0025] With reference to plan view 200c of Fig. 2C, the thermal barrier structure 108 and the heater structure 106 have a similar shape and / or layout, with the thermal barrier structure 108 having a larger area in plan view than the heater structure 106. In such embodiments, the thermal barrier structure 108 extends continuously laterally outward from an outer perimeter of the heater structure 106. Furthermore, the first outer heater segment 106a has a first width W1, and the second outer heater segment 106b has a second width W2. The middle heater segment 106c has a third width W3, which may be smaller than the first width W1 and the second width W2.In various embodiments, due to the fact that the first and second widths W1, W2 are relatively large (e.g., at least twice as large as the third width W3), the first and second outer heater segments 106a, 106b may be sufficiently large to include one or more conductive vias (not shown) formed on the first and second outer heater segments 106a, 106b. Furthermore, the relatively large first and second widths W1, W2 facilitate receiving a sufficiently large voltage to induce current that generates heat. In various embodiments, the fact that the third width W3 is relatively small (e.g., at least half as large as the first or second widths W1, W2) ensures that the middle heater segment 106c can generate sufficient heat directed toward the PWE 110.In various embodiments, the third width W3 is used to control a region and / or an area of ​​the PWE 110 that undergoes the phase change (e.g., between the amorphous phase and the crystalline phase).

[0026] Fig. 3A-3C illustrate various views of some other embodiments of the integrated chip of the Fig. 2A-2C, wherein the thermal barrier structure 108 includes a first pair of opposing sidewalls 302a, 302b perpendicularly above a second pair of opposing sidewalls 304a, 304b. The first pair of opposing sidewalls 302a, 302b are laterally spaced between the second pair of opposing sidewalls 304a, 304b. Fig. 3A illustrates a cross-sectional view 300a, corresponding to some embodiments of the integrated chip, along the line AA' of a top view 300c of Fig. 3C. Fig. 3B illustrates a cross-sectional view 300b, corresponding to some embodiments of the integrated chip, taken along line BB' of the top view 300c of Fig. 3C.

[0027] Fig. 4A-4C illustrate various views of some other embodiments of the integrated chip of the Fig. 2A-2C, wherein a sidewall spacer structure 402 is disposed along outer sidewalls of the PWE 110. Fig. 4A illustrates a cross-sectional view 400a, corresponding to some embodiments of the integrated chip, along the line AA' of a top view 400c of Fig. 4C. Fig. 4B illustrates a cross-sectional view 400b, corresponding to some embodiments of the integrated chip, taken along line BB' of the top view 400c of Fig. 4C.

[0028] The sidewall spacer structure 402 extends continuously from a top surface of the thermal barrier structure 108 along outer sidewalls 1100s1, 1100s2 of the PWE 110 to opposite sidewalls of the hard mask 112. In various embodiments, the sidewall spacer structure 402 laterally wraps around an outer perimeter of the PWE 110. The sidewall spacer structure 402 has a fourth thickness t4, which may, for example, be within a range of about 20.0 nm to 60.0 nm or be another suitable value. Furthermore, the hard mask 112 has a fifth thickness t5, which may, for example, be within a range of about 30.0 nm to about 60.0 nm or be another suitable value. In some embodiments, the fourth thickness t4 may be less than the first thickness t1, the second thickness t2, and / or the fifth thickness t5. In further embodiments, the fourth thickness t4 may be greater than the third thickness t3.Furthermore, the sidewall spacer structure 402 may be or include, for example, silicon nitride, silicon carbide, a non-oxygen-based dielectric material, another dielectric material, or any combination of the foregoing. In some embodiments, due to the fact that the sidewall spacer structure 402 includes a non-oxygen-based dielectric material, oxidation of the PWE 110 during operation of the PWM device 104 is mitigated, thereby increasing overall performance (e.g., stability and robustness) of the PWM device 104. In some embodiments, the sidewall spacer structure 402 and the thermal barrier structure 108 may include a same material (such as silicon nitride, silicon carbide, a non-oxygen-based dielectric material, or another suitable material).In various embodiments, due to a layout, material, and / or thickness of the sidewall spacer structure 402, the sidewall spacer structure 402 enhances the insulation between the heater structure 106 and the PWE 110, thereby mitigating damage (e.g., delamination, cracks, etc.) to the PWE 110 during operation and / or manufacturing of the PWM device 104 (e.g., due to intense heat during switching operations and / or intense heat during processing steps). As a result, the sidewall spacer structure 402 increases stability, robustness, and overall performance of the PWM device 104.

[0029] In some embodiments, the thermal barrier structure 108 extends beyond outer sidewalls 1100s1, 1100s2 of the PWE 110 and is configured to further enhance the insulation between the PWE 110 and the heater structure 106, thereby further mitigating damage (e.g., peeling, cracking, etc.) to the PWE 110 during operation and / or manufacturing of the PWM device 104. As a result, the thermal barrier structure 108 further increases the stability, robustness, and overall performance of the PWM device 104. In various embodiments, as shown in plan view 400c of Fig. 4C, the thermal barrier structure 108 and the PWE 110 have a similar shape and / or layout, with the thermal barrier structure 108 having a larger area in plan view than the PWE 110. The thermal barrier structure 108 extends continuously laterally outward from an outer perimeter of the PWE 110. It can be seen that in further embodiments, the sidewall spacer structure 402 and the capping layer 114 in the plan view 400c of Fig. 4C have been omitted for clarity. In various embodiments, the sidewall spacer structure 402 extends continuously laterally from the outer perimeter of the PWE 110 to the outer perimeter of the thermal barrier structure 108. In further embodiments, the thermal barrier structure 108 lies at least directly over portions of the first and second RF structures 120, 122.

[0030] Fig. 5A and Fig. 5B illustrate cross-sectional views 500a and 500b of some other embodiments of the integrated chip of the Fig. 4A-4C, wherein outer sidewalls of the thermal barrier structure 108, outer sidewalls of the sidewall spacer structure 402, outer sidewalls of the PWE 110, and outer sidewalls of the hard mask 112 are inclined relative to a top surface of the semiconductor substrate 102. Fig. 5A illustrates the cross-sectional view 500a, corresponding to some embodiments of the integrated chip, along the line AA' of the top view 400c of Fig. 4C. Fig. 5B illustrates the cross-sectional view 500b, corresponding to some embodiments of the integrated chip, along the line BB' of the top view 400c of Fig. 4C.

[0031] Fig. 6A and Fig. 6B illustrate cross-sectional views 600a and 600b of some other embodiments of the integrated chip of the Fig. 4A-4C, wherein a top surface of the sidewall spacer structure 402 is aligned with and / or coplanar with a top surface of the hard mask 112. Fig. 6A illustrates the cross-sectional view 600a, corresponding to some embodiments of the integrated chip, along the line AA' of the top view 400c of Fig. 4C. Fig. 6B illustrates the cross-sectional view 600b, corresponding to some embodiments of the integrated chip, along the line BB' of the top view 400c of Fig. 4C.

[0032] Fig. 7A and Fig. 7B illustrate various views of some embodiments of an integrated chip having a PWM device 104 including a thermal barrier structure 108 disposed within an interconnect structure 701. Fig. 7A illustrates a cross-sectional view 700a, corresponding to some embodiments of the integrated chip, taken along line BB' of a top view 700b of Fig. 7B.

[0033] The integrated chip includes an interconnect structure 701 disposed over a semiconductor substrate 102. The semiconductor substrate 102 may be any type of semiconductor body, such as silicon, monocrystalline silicon, silicon germanium, etc., any other type of semiconductor and / or epitaxial layer(s), a silicon-on-insulator (SOI) substrate, another semiconductor body, or the like. A plurality of semiconductor devices 702 are disposed on and / or within a front surface 102f of the semiconductor substrate 102.The semiconductor devices may, for example, each be or include a metal-oxide-semiconductor field-effect transistor (MOSFET), a high-voltage transistor, a bipolar transistor (BJT), an n-channel metal-oxide-semiconductor transistor (nMOS transistor), a p-channel metal-oxide-semiconductor transistor (pMOS transistor), a gate-all-around FET (GAAFET), a gate-surrounding FET, a multi-bridge-channel FET (MBCFET), a nanowire FET, a nanoring FET, a nanolayer field-effect transistor (NSFET), or the like. It is understood that the plurality of semiconductor devices 702, each configured as a different semiconductor device, also fall within the scope of the disclosure.

[0034] The interconnect structure 701 includes a stack of dielectric layers and a plurality of metallization layers arranged within the stack of dielectric layers. In various embodiments, the plurality of metallization layers includes a plurality of conductive wires 710 and a plurality of conductive vias 712. Furthermore, the stack of dielectric layers includes an inter-layer dielectric (ILD) layer 704, a plurality of inter-metal dielectric (IMD) layers 706, and a plurality of dielectric protection layers 708. Furthermore, a PWM device 104 is arranged within the interconnect structure 701, stacked vertically between various metallization layers. In various embodiments, the PWM device 104 may be configured like the PWM device 104 of the Fig. 1A-1B, 2A-2C, or 3A-3C. In some embodiments, the PWM device 104 includes a heater structure 106, a PWE 110, a thermal barrier structure 108, a hard mask 112, a cap layer 114, a first RF structure 120, and a second RF structure 122.

[0035] The conductive wires and vias 710, 712 are configured to facilitate electrical connections between the PWM device 104 and other semiconductor devices and / or structures (e.g., the semiconductor devices 702) disposed in and / or on the semiconductor substrate 102. In some embodiments, one or more conductive vias within the plurality of conductive vias 712 contact the first and second RF structures 120, 122 and the heater structure 106 and are configured to facilitate the application of read and / or switching signals to the first and second RF structures 120, 122 and the heater structure 106. The plurality of conductive wires and vias 710, 712 may be or include, for example, copper, aluminum, ruthenium, titanium, tantalum, tungsten, another conductive material, or any combination of the foregoing.The ILD and IMD layers 704, 706 may be or include, for example, silicon dioxide, doped silicon dioxide (e.g., carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), another low-k dielectric material, or any combination of the foregoing. Furthermore, the dielectric protection layers 708 may be configured as an etch stop layer and may be or include, for example, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, another dielectric material, or the like. In various embodiments, the metallization layers may further include a top conductive structure 710a disposed over the PWE 110 of the PWM device 104. In such embodiments, the top conductive structure 710a may be configured as a top electrode.In further embodiments, the upper conductive structure 710a may be omitted (not shown).

[0036] Fig. 8A and Fig. 8B illustrate cross-sectional views 800a and 800b of some embodiments of an integrated chip that are similar to some other embodiments of the integrated chip of the Fig. 7A-7B, wherein a first dielectric layer 802 and a second dielectric layer 804 are stacked vertically and underlying the heater structure 106. Fig. 8A illustrates the cross-sectional view 800a, corresponding to some embodiments of the integrated chip, along the line AA' of the top view 700b of Fig. 7B. Fig. 8B illustrates the cross-sectional view 800b corresponding to some embodiments of the integrated chip, taken along the line BB' of the top view 700b of Fig. 7B.

[0037] Furthermore, the hard mask 112 comprises a first hard mask layer 806 and a second hard mask layer 808. In some embodiments, the first hard mask layer 806 comprises a first dielectric material (e.g., silicon nitride, silicon carbide, etc.), and the second hard mask layer 808 comprises a second dielectric material (e.g., an oxide, silicon dioxide, etc.) that is different from the first dielectric material. In some embodiments, the second dielectric layer 804 extends continuously along and directly contacts an entire bottom surface of the heater structure 106, an entire bottom surface of the first RF structure 120, and / or an entire bottom surface of the second RF structure 122. In such embodiments, the metallization layers in the interconnect structure 701 may be offset from the bottom surfaces of the heater structure 106 and the first and second RF structures 120, 122.

[0038] Fig. 9A-9C illustrate various views of some embodiments of an integrated chip that are similar to some other embodiments of the integrated chip of the Fig. 7A and Fig. 7B, wherein the PWM device 104 includes a sidewall spacer structure 402 laterally enclosing outer sidewalls of the PWE 110. In various embodiments, the PWM device 104 may be configured as shown in FIGS. Fig. 4A-4C, 5A-5B or 6A-6B. Fig. 9A illustrates a cross-sectional view 900a, corresponding to some embodiments of the integrated chip, taken along line AA' of a top view 900c of Fig. 9C. Fig. 9B illustrates a cross-sectional view 900b, corresponding to some embodiments of the integrated chip, taken along line BB' of the top view 900c of Fig. 9C. It can be seen that the PWE 110 and the sidewall spacer structure 402 are at least partially transparent for the sake of clarity and the capping layer 114 in the top view 900c of Fig. 9C was omitted.

[0039] Fig. 10A-10C illustrate various views of some other embodiments of the integrated chip of the Fig. 4A-4C, wherein the PWE 110 extends along opposite sidewalls of the thermal barrier structure 108. Fig. 10A illustrates a cross-sectional view 1000a, corresponding to some embodiments of the integrated chip, along the line AA' of a top view 1000c of Fig. 10C. Fig. 10B illustrates a cross-sectional view 1000b, corresponding to some embodiments of the integrated chip, taken along line BB' of the top view 1000c of Fig. 10C. It can be seen that, for the sake of clarity, the capping layer 114 and the upper dielectric layer 116 in the top view 1000c of Fig. 10C and that the PWE 110 and the sidewall spacer structure 402 in the plan view 1000c of Fig. 10C are at least partially transparent.

[0040] In various embodiments, as shown in cross-sectional view 1000b of Fig. 10B, a bottom surface of the sidewall spacer structure 402 and a bottom surface of the PWE 110 are aligned with a bottom surface of the thermal barrier structure 108. In further embodiments, as shown in top view 1000c of Fig. As illustrated in Figure 10C, the thermal barrier structure 108 has a greater width than the central heater segment 106c.

[0041] Fig. 11A and Fig. 11B illustrate cross-sectional views 1100a and 1100b of some other embodiments of the integrated chip of the Fig. 10A-10C, wherein outer sidewalls of the thermal barrier structure 108, outer sidewalls of the sidewall spacer structure 402, outer sidewalls of the PWE 110, and outer sidewalls of the hard mask 112 are inclined relative to a top surface of the semiconductor substrate 102. Fig. 11A illustrates the cross-sectional view 1100a, corresponding to some embodiments of the integrated chip, along the line AA' of the top view 1000c of Fig. 10C. Fig. 11B illustrates the cross-sectional view 1100b, corresponding to some embodiments of the integrated chip, along the line BB' of the top view 1000c of Fig. 10C.

[0042] Fig. 12A and Fig. 12B illustrate cross-sectional views 1200a and 1200b of some other embodiments of the integrated chip of the Fig. 10A-10C, wherein a top surface of the sidewall spacer structure 402 is aligned with and / or coplanar with a top surface of the hard mask 112. Fig. 12A illustrates the cross-sectional view 1200a, corresponding to some embodiments of the integrated chip, along the line AA' of the top view 1000c of Fig. 10C. Fig. 12B illustrates the cross-sectional view 1200b, corresponding to some embodiments of the integrated chip, along the line BB' of the top view 1000c of Fig. 10C.

[0043] Fig. 13 illustrates a graph 1300 including resistance curves 1310, 1312 of some other embodiments of a PWM device having a thermal barrier structure. For example, resistance curve 1312 may correspond to the operation of the PWM device as previously described in FIGS. Fig. 1A-1B. These resistance curves 1310, 1312 reflect varying switching operations performed at different voltages in the PWM device. During the switching operations, for example, a voltage (e.g., a switching signal) is applied to the first and / or second outer heater segments 106a-b to generate a heating current across the middle heater segment 106c.

[0044] In various embodiments, a first resistance curve 1310 represents some embodiments of operating conditions of a second PWM device including a PWE having outer sidewalls aligned with outer sidewalls of the thermal barrier structure (e.g., a length of the thermal barrier structure need not be greater than a length of the PWE). The first resistance curve 1310 represents a resistance between the heater structure of the second PWM device and RF structures of the second PWM device. In some embodiments, the resistance between the heater structure and the RF structures of the second PWM device decreases below a first resistance value 1302 after one or more voltages greater than a first voltage 1306 are applied to the heater structure of the second PWM device.Because the thermal barrier structure of the second PWM device does not sufficiently enhance the insulation between the heater structure and the RF structures, the first voltage 1306 is relatively small, such that breakdown of the second PWM device may occur at relatively low voltages (for example, at about 7 volts).

[0045] In some embodiments, a second resistance curve 1312 illustrates some embodiments of operating conditions of a PWM device according to the present disclosure, wherein outer sidewalls of the PWE are laterally spaced between outer sidewalls of the thermal barrier structure. In some embodiments, the second resistance curve 1312 illustrates a resistance between the heater structure (e.g., 106 of the Fig. 1A-1B) and the first and / or second RF structure (for example 120, 122 of the Fig. 1B). In some embodiments, the resistance between the heater structure and the first and / or second RF structure decreases below a second resistance value 1304 after one or more voltages greater than a second voltage 1308 are applied to the heater structure (e.g., 106 of the Fig. 1A-1B) of the PWM device. Since the thermal barrier structure (for example, 108 of the Fig. 1A-1B) enhances the insulation between the heater structure and the first and / or second RF structure, the second voltage 1308 is relatively high, such that breakdown of the PWM device may occur at relatively high voltages (e.g., at about 14 volts or more). As can be seen from a comparison of curves 1310, 1312, the layout, material, and / or thickness of the thermal barrier structure 108, as illustrated and / or described in embodiments according to the present disclosure, enhances the insulation between conductive structures of the PWM device 104 and / or between the heater structure 106 and the PWE 110. As a result, a breakdown voltage, robustness, and stability of the PWM device 104 are increased.

[0046] Fig. Fig. 14A-14C to 23A-23C illustrate a series of different views of some embodiments of a method for forming an integrated chip including a PWM device having a thermal barrier structure configured to enhance performance of the PWM device. Figures with a suffix "A" illustrate a cross-sectional view of the integrated chip during various formation processes along line AA' of figures with a suffix "C." Figures with a suffix "B" illustrate a cross-sectional view along line BB' of figures with a suffix "C." Figures with a suffix "C" illustrate a top view of the integrated chip during various formation processes. Although the Fig. 14A-14C to 23A-23C are described with reference to a method of forming the integrated chip, it is understood that the Fig. 14A-14C to 23A-23C are not limited to the formation process, but rather can be independent and separate from this process.

[0047] As shown in cross-sectional views 1400a-b and plan view 1400c of Fig. 14A-14C, a semiconductor substrate 102 is provided, and a first dielectric layer 802, a second dielectric layer 804, and a conductive layer 1402 are formed over the semiconductor substrate 102. In some embodiments, the first dielectric layer 802 and the second dielectric layer 804 may each be formed over the semiconductor substrate 102 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process. The conductive layer 1402 may be formed, for example, by CVD, PVD, ALD, electroplating, electroless plating, or another suitable growth or deposition process.The conductive layer 1402 may be or include, for example, tungsten, titanium, titanium nitride, molybdenum, another conductive material, or any combination of the foregoing.

[0048] As shown in cross-sectional views 1500a-b and plan view 1500c of Fig. 15A-15C, an etching process is performed on the conductive layer (1402 of the Fig. 14A-14C) to define a first radio frequency (RF) structure 120, a second RF structure 122, and a heater structure 106. In various embodiments, the heater structure 106 is formed such that the heater structure 106 includes a first outer heater segment 106a, a second outer heater segment 106b, and a middle heater segment 106c. In some embodiments, the etching process includes: forming a patterned mask (not shown) over the conductive layer (1402 of the Fig. 14A-14C); contacting the conductive layer (1402 of the Fig. 14A-14C) with one or more etchants while the patterned mask is in place, thereby exposing unmasked regions of the conductive layer (1402 of Fig. 14A-14C); and performing a removal process to remove the patterned mask. In some embodiments, the etching process comprises a wet etch, a dry etch, or a combination of the foregoing. In further embodiments, the heater structure 106 is formed such that the first and second outer heater segments 106a, 106b each have one or more widths that are greater than a width of the middle heater segment 106c. In some embodiments, the first RF structure 120, the second RF structure 122, and the heater structure 106 are formed simultaneously with one another.

[0049] As shown in cross-sectional views 1600a-b and plan view 1600c of Fig. 16A-16C, a bottom dielectric layer 202 is formed over the second dielectric layer 804. The bottom dielectric layer 202 may be formed, for example, by CVD, PVD, ALD, or another suitable deposition or growth process. In further embodiments, after depositing the bottom dielectric layer 202, a planarization process (e.g., a chemical mechanical planarization (CMP) process, an etch process, etc.) may be performed on the bottom dielectric layer 202 such that a top surface of the bottom dielectric layer 202 is coplanar with a top surface of the heater structure 106, a top surface of the first RF structure 120, and / or a top surface of the second RF structure 122.

[0050] As shown in cross-sectional views 1700a-b and plan view 1700c of Fig. 17A-17C, a thermal barrier layer 1702 is formed over the heater structure 106 and the first and second RF structures 120, 122. The thermal barrier layer 1702 may be or include, for example, silicon nitride, silicon carbide, aluminum nitride, a non-oxygen-based dielectric material, a high-k dielectric material, another suitable material, or any combination of the foregoing. The thermal barrier layer 1702 may be formed, for example, by CVD, PVD, ALD, or another suitable deposition or growth process. In some embodiments, the thermal barrier layer 1702 may be formed to a thickness within a range of about 30.0 nm to about 60.0 nm, or to another suitable thickness.

[0051] As shown in cross-sectional views 1800a-b and plan view 1800c of Fig. 18A-18C, an etching process is performed on the thermal barrier layer (1702 of the Fig. 17A-17C) to define a thermal barrier structure 108 and an etch stop layer 126. In some embodiments, the thermal barrier structure 108 is formed such that the heater structure 106 and the thermal barrier structure 108 have a similar shape and / or layout. In such embodiments, the thermal barrier structure 108 extends continuously laterally outward from an outer perimeter of the heater structure 106, wherein the thermal barrier structure 108 has a larger area in plan view than the heater structure 106. In some embodiments, the etching process includes: forming a patterned mask (not shown) over the thermal barrier layer (1702 of Fig. 17A-17C); contacting the thermal barrier layer (1702 of the Fig. 17A-17C) with one or more etchants while the patterned mask is in place, thereby exposing unmasked regions of the thermal barrier layer (1702 of the Fig. 17A-17C); and performing a removal process to remove the patterned mask. In various embodiments, the etching process includes a wet etch, a dry etch, or a combination of the foregoing. In some embodiments, the thermal barrier structure 108 and the etch stop layer 126 are formed simultaneously with each other.

[0052] As shown in cross-sectional views 1900a-b and plan view 1900c of Fig. 19A-19C, a stack of layers 1902-1906 is formed over the heater structure 106. In some embodiments, the stack of layers 1902-1906 includes a PWE layer 1902, a first mask layer 1904, and a second mask layer 1906. In various embodiments, the PWE layer 1902, the first mask layer 1904, and the second mask layer 1906 may each be formed by an individual deposition process, such as a CVD process, a PVD process, an ALD process, or another suitable deposition or growth process. The PWE layer 1902 may, for example, be or comprise a PWM, such as one or more chalcogenide materials comprising at least one chalcogen ion (e.g., a chemical element in column VI of the periodic table), germanium antimony telluride (GST), another suitable phase change alloy, or another suitable material.Furthermore, the PWE layer 1902 may be formed, for example, to a thickness in the range of about 50.0 nm to about 100.0 nm or another suitable thickness value.

[0053] As shown in the cross-sectional views 2000a-b and the plan view 2000c of the Fig. 20A-20C, a first patterning process is performed on the first and second mask layers (1904 and 1906 of the Fig. 19A-C) to define a hard mask 112 comprising a first hard mask layer 806 and a second hard mask layer 808. In some embodiments, the first patterning process includes: forming a first mask (not shown) over the first and second mask layers (1904 and 1906 of Fig. 19A-C); contacting the first and second mask layers (1904 and 1906 of the Fig. 19A-C) with one or more etchants while the first mask is in place, thereby exposing unmasked regions of the first and second mask layers (1904 and 1906 of the Fig. 19A-C); and performing a removal process to remove the first mask. In various embodiments, the first patterning process comprises a wet etch, a dry etch, or a combination of the foregoing.

[0054] As shown in cross-sectional views 2100a-b and plan view 2100c of Fig. As shown in Figures 21A-21C, a second patterning process is performed on the PWE layer (1902 of the Fig. 20A-C) to define a PWE 110 and a PWM device 104 over the heater structure 106. In some embodiments, the second patterning process includes contacting the PWE layer (1902 of Fig. 20A-C) with one or more etchants while the hard mask 112 is in place, thereby exposing unmasked regions of the PWE layer (1902 of the Fig. 20A-C). In various embodiments, the second patterning process comprises a wet etch, a dry etch, or a combination of the above. In further embodiments, the second patterning process differs from the first patterning process of the Fig. 20A-20C.

[0055] As shown in cross-sectional views 2200a-b and plan view 2200c of Fig. 22A-22C, a cap layer 114 and a top dielectric layer 116 are formed over the PWM device 104. In some embodiments, the cap layer 114 and the top dielectric layer 116 may, for example, each be formed by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. It should be noted that, for clarity, the cap layer 114 and the top dielectric layer 116 are not shown in the top view 2200c of Fig. 22C have been omitted. In various embodiments, the capping layer 114 may be formed to a thickness within a range of about 10.0 nm to about 40.0 nm or another suitable thickness value.

[0056] As shown in cross-sectional views 2300a-b and plan view 2300c of Fig. 23A-23C, a plurality of conductive vias 712 and a plurality of conductive wires 710 are formed over the PWM device 104. It can be seen that, for clarity, the cap layer 114 and the upper dielectric layer 116 are shown in the top view 2300c of Fig. 23C have been omitted. The conductive wires and vias 710, 712 may be formed, for example, by one or more deposition processes, one or more patterning processes, one or more planarization processes, one or more other suitable manufacturing processes, or any combination of the foregoing.In some embodiments, a process for forming the conductive wires and vias 710, 712 includes: patterning the upper dielectric layer 116, the cap layer 114, the thermal barrier structure 108, and / or the etch stop layer 126 to form a plurality of metallization openings above the heater structure 106 and the first and second RF structures 120, 122; filling the plurality of metallization openings with a conductive material (e.g., copper, aluminum, titanium nitride, tantalum nitride, ruthenium, another metal material, or any combination of the foregoing); and performing a planarization process (e.g., a CMP process, an etch process, etc.) on the conductive material.

[0057] Fig. 24 illustrates a flowchart of some embodiments of a method 2400 for forming an integrated chip including a PWM device having a thermal barrier structure configured to enhance performance of the PWM device. While the method 2400 is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Thus, in some embodiments, the actions may be performed in different orders than those depicted and / or concurrently. Furthermore, in some embodiments, the illustrated actions or events may be divided into multiple actions or events that may be performed at different times or concurrently with other actions or sub-actions.In some embodiments, some illustrated actions or events may be omitted, and other non-illustrated actions or events may be included.

[0058] In operation 2402, a heater structure is formed over a semiconductor substrate. The heater structure includes a central heater segment that extends continuously laterally from a first outer heater segment to a second outer heater segment. Fig. 14A-14C through 15A-15C illustrate various views corresponding to some embodiments of action 2402.

[0059] In action 2404, a first radio frequency (RF) structure and a second RF structure are formed over the semiconductor substrate, with the first and second RF structures disposed on opposite sides of the central heater segment. Fig. 14A-14C through 15A-15C illustrate various views corresponding to some embodiments of action 2404.

[0060] In action 2406, a thermal barrier structure is formed over the heater structure. In plan view, the thermal barrier structure and the heater structure have a similar or identical shape, and the thermal barrier structure has a larger area than the heater structure. Fig. 17A-17C through 18A-18C illustrate various views corresponding to some embodiments of action 2406.

[0061] At action 2408, a phase change element (PWE) is formed directly overlying the center heater segment, thereby defining a PWM device, with outer sidewalls of the PWE laterally spaced between outer sidewalls of the thermal barrier structure. Fig. 19A-19C through 21A-21C illustrate various views corresponding to some embodiments of action 2408.

[0062] In Action 2410, a capping layer is formed over the PWE and the thermal barrier structure. Fig. 22A-22C illustrate various views corresponding to some embodiments of action 2410.

[0063] In action 2412, a plurality of conductive vias are formed over the first and second RF structures and the first and second outer heater segments. Fig. 23A-C illustrate various views corresponding to some embodiments of action 2412.

[0064] Fig. Fig. 25A-25C to 31A-31C illustrate a series of different views of some embodiments of a method for forming an integrated chip including a PWM device having a thermal barrier structure and a sidewall spacer structure configured to enhance performance of the PWM device. Figures with a suffix "A" illustrate a cross-sectional view of the integrated chip during various formation processes along line AA' of figures with a suffix "C." Figures with a suffix "B" illustrate a cross-sectional view along line BB' of figures with a suffix "C." Figures with a suffix "C" illustrate a top view of the integrated chip during various formation processes. Although the Fig. 25A-25C to 31A-31C are described with reference to a method of forming the integrated chip, it is understood that the Fig. 25A-25C to 31A-31C are not limited to the formation process, but rather can be independent and separate from this process.

[0065] As shown in cross-sectional views 2500a-b and plan view 2500c of the Fig. 25A-25C, a semiconductor substrate 102 is provided, and a first dielectric layer 802, a second dielectric layer 804, a heater structure 106, a first RF structure 120, a second RF structure 122, and a bottom dielectric layer 202 are formed over the semiconductor substrate 102. In various embodiments, the first and second dielectric layers 802, 804, the heater structure 106, the first and second RF structures 120, 122, and the bottom dielectric layer 202 are formed, for example, as shown in FIGS. Fig. 14A-14C to 16A-16C. Further, a thermal barrier layer 2502 is formed over the heater structure 106 and the first and second RF structures 120, 122. The thermal barrier layer 2502 may be or include, for example, silicon nitride, silicon carbide, aluminum nitride, a non-oxygen-based dielectric material, a high-k dielectric material, another suitable material, or any combination of the foregoing. The thermal barrier layer 2502 may be formed, for example, by CVD, PVD, ALD, or another suitable deposition or growth process. In some embodiments, the thermal barrier layer 2502 may be formed to a thickness within a range of about 30.0 nm to about 60.0 nm, or to another suitable thickness. It can be seen that in the interest of better clarity, the thermal barrier layer 2502 in the plan view 2500c of Fig. 25C is partially transparent.

[0066] As shown in cross-sectional views 2600a-b and plan view 2600c of Fig. 26A-26C, an etching process is performed on the thermal barrier layer 2502 to define a thermal barrier structure 108 over the heater structure 106. In some embodiments, the etching process includes: forming a patterned mask (not shown) over the thermal barrier layer 2502; contacting the thermal barrier layer 2502 with one or more etchants while the patterned mask is in place, thereby removing unmasked regions of the thermal barrier layer 2502; and performing a removal process to remove the patterned mask. In various embodiments, the etching process includes a wet etch, a dry etch, or a combination of the foregoing. It should be noted that, for clarity, the thermal barrier layer 2502 and the thermal barrier structure 108 are shown in plan view 2600c of Fig. 26C are partially transparent.

[0067] As shown in cross-sectional views 2700a-b and plan view 2700c of Fig. 27A-27C, a stack of layers 2702-2706 is formed over the heater structure 106. In some embodiments, the stack of layers 2702-2706 includes a PWE layer 2702, a first mask layer 2704, and a second mask layer 2706. In various embodiments, the PWE layer 2702, the first mask layer 2704, and the second mask layer 2706 may each be formed by an individual deposition process, such as a CVD process, a PVD process, an ALD process, or another suitable deposition or growth process. The PWE layer 2702 may, for example, be or comprise a PWM, such as one or more chalcogenide materials comprising at least one chalcogen ion (e.g., a chemical element in column VI of the periodic table), germanium antimony telluride (GST), another suitable phase change alloy, or another suitable material.Furthermore, the PWE layer 2702 may be formed, for example, to a thickness in the range of about 50.0 nm to about 100.0 nm, or any other suitable thickness. It should be noted that, for clarity, the thermal barrier layer 2502, the thermal barrier structure 108, and the PWE layer 2702 are shown in plan view 2700c of FIG. Fig. 27C are partially transparent.

[0068] As shown in cross-sectional views 2800a-b and plan view 2800c of Fig. 28A-28C, a first patterning process is performed on the stack of layers (2702-2706 of the Fig. 27A-27C) to define a PWM device 104, a hard mask 112 comprising a first hard mask layer 806 and a second hard mask layer 808, and a PWE 110. In some embodiments, the first patterning process includes: forming a first mask (not shown) over the stack of layers (2702-2706 of Fig. 27A-27C); contacting the stack of layers (2702-2706 of Fig. 27A-27C) with one or more etchants while the first mask is in place, thereby exposing unmasked regions of the stack of layers (2702-2706 of Fig. 27A-27C); and performing a removal process to remove the first mask. In various embodiments, the first patterning process comprises a wet etch, a dry etch, or a combination of the foregoing. It can be seen that, for the sake of clarity, the thermal barrier layer 2502, the thermal barrier structure 108, and the PWE 110 are shown in plan view 2800c of Fig. 28C are partially transparent.

[0069] As shown in cross-sectional views 2900a-b and plan view 2900c of Fig. 29A-29C, a sidewall spacer structure 402 is formed along outer opposing sidewalls of the PWE 110. The sidewall spacer structure 402 has a fourth thickness t4, which may, for example, be within a range of about 20.0 nm to 60.0 nm or may be another suitable value. The sidewall spacer structure 402 may, for example, be or include silicon nitride, silicon carbide, a non-oxygen-based dielectric material, another dielectric material, or any combination of the foregoing. In some embodiments, a process for forming the sidewall spacer structure 402 includes: depositing (e.g., by CVD, PVD, ALD, etc.) a sidewall spacer layer over the PWM device 104; and performing an etch process on the sidewall spacer layer, the thermal barrier structure 108, and the thermal barrier layer (2502 of the Fig. 28A-28C). In various embodiments, the etching process comprises a dry etch, a wet etch, or any combination of the foregoing. In further embodiments, the etching process removes the thermal barrier layer (2502 of Fig. 28A-28C) from above the first and second RF structures 120, 122. It can be seen that, for clarity, the sidewall spacer structure 402 and the PWE 110 in the top view 2900c of Fig. 29C are partially transparent.

[0070] As shown in cross-sectional views 3000a-b and plan view 3000c of the Fig. 30A-30C, a cap layer 114 and a top dielectric layer 116 are formed over the PWM device 104. In some embodiments, the cap layer 114 and the top dielectric layer 116 may, for example, each be formed by a CVD process, a PVD process, an ALD process, or other suitable growth or deposition process. It should be noted that for clarity, the cap layer 114 and the top dielectric layer 116 are shown in plan view 3000c of Fig. 30C have been omitted. In various embodiments, the capping layer 114 may be formed to a thickness within a range of about 10.0 nm to about 40.0 nm or another suitable thickness value.

[0071] As shown in cross-sectional views 3100a-b and plan view 3100c of Fig. As shown in Figures 31A-31C, a plurality of conductive vias 712 and a plurality of conductive wires 710 are formed over the PWM device 104. The conductive wires and vias 710, 712 may be formed, for example, by one or more deposition processes, one or more patterning processes, one or more planarization processes, one or more other suitable manufacturing processes, or any combination of the foregoing.In some embodiments, a process for forming the conductive wires and vias 710, 712 includes: patterning the upper dielectric layer 116 and / or the cap layer 114 to form a plurality of metallization openings above the heater structure 106 and the first and second RF structures 120, 122; filling the plurality of metallization openings with a conductive material (e.g., copper, aluminum, titanium nitride, tantalum nitride, ruthenium, another metal material, or any combination of the foregoing); and performing a planarization process (e.g., a CMP process, an etch process, etc.) on the conductive material.

[0072] Fig. 32 illustrates a flowchart of some embodiments of a method 3200 for forming an integrated chip including a PWM device having a thermal barrier structure and a sidewall spacer structure configured to enhance performance of the PWM device. While the method 3200 is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Thus, in some embodiments, the actions may be performed in different orders than those depicted and / or concurrently. Furthermore, in some embodiments, the illustrated actions or events may be divided into multiple actions or events that may be performed at different times or concurrently with other actions or sub-actions.In some embodiments, some illustrated actions or events may be omitted, and other non-illustrated actions or events may be included.

[0073] In action 3202, a heater structure is formed over a semiconductor substrate. The heater structure includes a central heater segment that extends continuously laterally from a first outer heater segment to a second outer heater segment. Fig. 25A-25C illustrate various views corresponding to some embodiments of action 3202.

[0074] In action 3204, a first radio frequency (RF) structure and a second RF structure are formed over the semiconductor substrate, wherein the first and second RF structures are disposed on opposite sides of the central heater segment. Fig. 25A-25C illustrate various views corresponding to some embodiments of action 3204.

[0075] In action 3206, a thermal barrier structure is formed over the heating structure. Fig. 25A-25C through 26A-26C illustrate various views corresponding to some embodiments of action 3206.

[0076] At action 3208, a phase change element (PWE) is formed directly overlying the center heater segment, thereby defining a PWM device, with outer sidewalls of the PWE laterally spaced between outer sidewalls of the thermal barrier structure. Fig. 27A-27C through 28A-28C illustrate various views corresponding to some embodiments of action 3208.

[0077] In action 3210, a sidewall spacer structure is formed along outer sidewalls of the PWE. Fig. 29A-29C illustrate various views corresponding to some embodiments of action 3210.

[0078] In Action 3212, a cap layer is formed over the PWE, the thermal barrier structure and the sidewall spacer structure. Fig. 30A-30C illustrate various views corresponding to some embodiments of action 3212.

[0079] In action 3214, a plurality of conductive vias are formed over the first and second RF structures and the first and second outer heater segments. Fig. 31A-C illustrate various views corresponding to some embodiments of action 3214.

[0080] Accordingly, in some embodiments, the present application relates to a PWM device comprising a thermal barrier structure disposed between a heater structure and a PWE, wherein outer sidewalls of the PWE are laterally spaced between outer sidewalls of the thermal barrier structure.

[0081] In various embodiments, the present application provides an integrated chip comprising: a heater structure overlying a semiconductor substrate; a phase change element (PWE) disposed over the heater structure; and a thermal barrier structure disposed between the heater structure and the PWE, wherein outer sidewalls of the PWE are laterally spaced between outer sidewalls of the thermal barrier structure. In one embodiment, the thermal barrier structure comprises a first outer heater segment, a second outer heater segment, and a middle heater segment continuously extending laterally from the first outer heater segment to the second outer heater segment, wherein widths of the first and second outer heater segments are greater than a width of the middle heater segment.In one embodiment, the PWE lies directly above the central heater segment, and wherein a length of the central heater segment is greater than a length of the PWE. In one embodiment, a width of the PWE is greater than a width of the central heater segment. In one embodiment, the integrated chip further comprises: a first radio frequency (RF) structure lying above the semiconductor substrate; and a second RF structure lying above the semiconductor substrate, wherein the first and second RF structures are arranged on opposite sides of the central heater segment, wherein the PWE lies directly above outer regions of the first and second RF structures. In one embodiment, the heater structure and the thermal barrier structure have a first shape in plan view, and the PWE has a second shape different from the first shape, wherein an area of ​​the heater structure is greater than an area of ​​the thermal barrier structure.In one embodiment, the integrated chip further comprises: a sidewall spacer structure disposed on the outer sidewalls of the PWE, wherein the sidewall spacer structure contacts a top surface of the thermal barrier structure. In one embodiment, the sidewall spacer structure and the thermal barrier structure each comprise a non-oxygen-based dielectric material.

[0082] In various embodiments, the present application provides an integrated chip comprising: a bottom dielectric layer overlying a semiconductor substrate; a heater structure disposed within the bottom dielectric layer, the heater structure comprising a central heater segment; a phase change element (PWE) overlying the heater structure; and a thermal barrier structure vertically between the heater structure and the PWE, the thermal barrier structure extending continuously laterally from an outer edge of the PWE to directly over an outer region of the central heater segment. In one embodiment, the integrated chip further comprises: a sidewall spacer structure laterally wrapping around the PWE, the sidewall spacer structure directly overlying at least a portion of the outer region of the central heater segment.In one embodiment, the integrated chip further comprises: a cap layer overlying the PWE, wherein the cap layer extends continuously from over the PWE along sidewalls of the sidewall spacer structure to a top surface of the heater structure. In one embodiment, the integrated chip further comprises: a hard mask disposed on the PWE, wherein the sidewall spacer structure extends continuously from opposite sidewalls of the PWE to opposite sidewalls of the hard mask. In one embodiment, a top surface of the hard mask is aligned with a top surface of the sidewall spacer structure. In one embodiment, the PWE and the thermal barrier structure have a first shape in plan view, and the heater structure has a second shape different from the first shape, wherein an area of ​​the heater structure is larger than an area of ​​the PWE.In one embodiment, the heater structure further comprises a first outer heater segment and a second outer heater segment disposed on opposite sides of the central heater segment, wherein the first and second outer heater segments each have two or more discrete widths that are greater than a width of the central heater segment.

[0083] In various embodiments, the present application provides a method of forming an integrated chip, the method comprising: forming a heater structure over a semiconductor substrate; depositing a thermal barrier layer over the heater structure; performing a first patterning process on the thermal barrier layer to form a thermal barrier structure over the heater structure; depositing a phase change element (PWE) layer over the thermal barrier structure; and performing a second patterning process on the PWE layer to form a PWE over the thermal barrier structure, wherein a length of the thermal barrier structure is greater than a length of the PWE. In one embodiment, the first patterning process is different from the second patterning process.In one embodiment, the first patterning process comprises forming a first mask over the thermal barrier layer, and the second patterning process comprises forming a second mask over the PWE layer, wherein the first mask is different from the second mask. In one embodiment, the method further comprises forming a first radio frequency (RF) structure and a second RF structure over the semiconductor substrate, wherein the heater structure is laterally spaced between the first and second RF structures, wherein the heater structure and the first and second RF structures are formed simultaneously with each other.In one embodiment, the method further comprises forming a sidewall spacer structure along outer opposing sidewalls of the PWE, wherein the sidewall spacer structure extends continuously from a top surface of the thermal barrier structure to the outer opposing sidewalls of the PWE.

Claims

[1] Integrated chip that has: a heating structure overlying a semiconductor substrate; a phase change element, PWE, arranged above the heating structure; a thermal barrier structure disposed between the heating structure and the PWE, wherein outer sidewalls of the PWE are laterally spaced between outer sidewalls of the thermal barrier structure; and a sidewall spacer structure disposed on the outer sidewalls of the PWE, the sidewall spacer structure contacting a top surface of the thermal barrier structure. [2] The integrated chip of claim 1, wherein the thermal barrier structure comprises a first outer heating segment, a second outer heating segment, and a middle heating segment continuously extending laterally from the first outer heating segment to the second outer heating segment, wherein widths of the first and second outer heating segments are greater than a width of the middle heating segment. [3] The integrated chip of claim 2, wherein the PWE is located directly above the center heater segment, and wherein a length of the center heater segment is greater than a length of the PWE. [4] The integrated chip of claim 3, wherein a width of the PWE is greater than a width of the central heater segment. [5] Integrated chip according to one of claims 2 to 4, further comprising: a first radio frequency structure, RF structure, lying above the semiconductor substrate; and a second RF structure overlying the semiconductor substrate, the first and second RF structures being disposed on opposite sides of the central heater segment, the PWE directly overlying outer regions of the first and second RF structures. [6] The integrated chip according to any one of claims 1 to 5, wherein the heater structure and the thermal barrier structure have a first shape in plan view and the PWE has a second shape different from the first shape, wherein an area of ​​the thermal barrier structure is larger than an area of ​​the heater structure. [7] The integrated chip of any one of claims 1 to 6, wherein the sidewall spacer structure and the thermal barrier structure each comprise a non-oxygen-based dielectric material. [8] Integrated chip that has: a lower dielectric layer overlying a semiconductor substrate; a heating structure disposed within the lower dielectric layer, the heating structure having a central heating segment; a phase change element, PWE, located above the heating structure; a thermal barrier structure vertically between the heating structure and the PWE, the thermal barrier structure extending continuously laterally from an outer edge of the PWE to directly over an outer region of the central heating segment; and a sidewall spacer structure laterally surrounding the PWE, the sidewall spacer structure directly overlying at least a portion of the outer region of the central heater segment. [9] The integrated chip of claim 8, further comprising: a capping layer overlying the PWE, the capping layer extending continuously from over the PWE along sidewalls of the sidewall spacer structure to a top surface of the heater structure. [10] The integrated chip of claim 8, further comprising: a hard mask disposed on the PWE, wherein the sidewall spacer structure extends continuously from opposite sidewalls of the PWE to opposite sidewalls of the hard mask. [11] The integrated chip of claim 10, wherein a top surface of the hard mask is aligned with a top surface of the sidewall spacer structure. [12] The integrated chip according to any one of claims 8 to 11, wherein the PWE and the thermal barrier structure have a first shape in plan view and the heater structure has a second shape different from the first shape, wherein an area of ​​the heater structure is larger than an area of ​​the PWE. [13] The integrated chip of any one of claims 8 to 12, wherein the heating structure further comprises a first outer heating segment and a second outer heating segment disposed on opposite sides of the central heating segment, the first and second outer heating segments each having two or more discrete widths greater than a width of the central heating segment. [14] A method of forming an integrated chip, the method comprising: Forming a heater structure over a semiconductor substrate; Depositing a thermal barrier layer over the heating structure; performing a first patterning process on the thermal barrier layer to form a thermal barrier structure over the heater structure; Depositing a phase change element (PWE) layer over the thermal barrier structure; Performing a second patterning process on the PWE layer to form a PWE over the thermal barrier structure, wherein a length of the thermal barrier structure is greater than a length of the PWE; and Forming a sidewall spacer structure along outer opposing sidewalls of the PWE, the sidewall spacer structure extending continuously from a top surface of the thermal barrier structure to the outer opposing sidewalls of the PWE. [15] The method of claim 14, wherein the first patterning process is different from the second patterning process. [16] The method of claim 15, wherein the first patterning process comprises forming a first mask over the thermal barrier layer and the second patterning process comprises forming a second mask over the PWE layer, the first mask being different from the second mask. [17] A method according to any one of claims 14 to 16, further comprising: Forming a first radio frequency structure, RF structure, and a second RF structure over the semiconductor substrate, wherein the heater structure is laterally spaced between the first and second RF structures, wherein the heater structure and the first and second RF structures are formed simultaneously with each other.

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