METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION PROCESSES

Abstract

A method for manufacturing a semiconductor device, wherein the method comprises: Forming a doped region (102) in a semiconductor body (104), wherein forming the doped region (102) comprises: Introducing first dopants (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1); thereafter Applying a first heat treatment (T1) to the semiconductor body (104); and then Introducing a second dopant (1082) through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by means of a second ion implantation process (I2-2), wherein an atomic number of the first dopant (1081) is equal to an atomic number of the second dopant (1082), an ion implantation energy (E2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation energy (E1) of the first ion implantation process (I2-1), and an ion implantation dose (D2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation dose (D1) of the first ion implantation process (I2-1).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, in particular to a method comprising the formation of a doped region in a semiconductor body by means of ion implantation processes. BACKGROUND

[0002] The technological development of newer generations of power semiconductor devices, such as insulated-gate field-effect transistors (IGFETs) like metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), or junction / barrel field-effect transistors (JFETs) or freewheeling diodes, aims to improve the electrical device characteristics, e.g., the area-specific on-resistance. By adjusting or tailoring the properties of doped semiconductor regions, such as peaks, slopes, and extents, the electrical device characteristics can be adapted to the specific requirements of the semiconductor device. For examples, reference is made to the semiconductor devices and manufacturing processes described in German patent application DE 10 2021 125 290 A1.

[0003] There is a constant need to improve the flexibility in forming doped semiconductor regions. SUMMARY

[0004] An example in the present disclosure relates to a method for manufacturing a semiconductor device. The method comprises forming a doped region in a semiconductor body. Forming the doped region includes introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by means of an ion implantation process. A first heat treatment is then applied to the semiconductor body. Subsequently, second dopants are introduced through the first surface of the semiconductor body at the first vertical reference level by means of a second ion implantation process. The atomic number of the first dopants is equal to the atomic number of the second dopants. The ion implantation energy of the second ion implantation process differs by less than 20% from the ion implantation energy of the first ion implantation process.The ion implantation dose of the second ion implantation process differs by less than 20% from the ion implantation dose of the first ion implantation process.

[0005] Another example in the present disclosure relates to a further method for fabricating a semiconductor device. The method comprises forming a doped region in a semiconductor body. Forming the doped region includes introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by means of a first ion implantation process. The first dopants are implanted along a beam axis that deviates by at most 1.5° from a principal crystal axis of the semiconductor body, along which channeling takes place. Thereafter, a first heat treatment is applied to the semiconductor body. Subsequently, second dopants are introduced through the first surface of the semiconductor body at the first vertical reference level by means of a second ion implantation process.The second dopants are implanted along a beam axis that deviates by no more than 1.5° from a main crystal axis of the semiconductor body, along which channeling takes place.

[0006] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are enclosed to provide a further understanding of the embodiments and are incorporated into and form part of this description. The drawings illustrate examples of features of a processing of the semiconductor device and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and the claims. Fig. Figures 1A to 1C are schematic cross-sectional views to illustrate process features of a method for manufacturing a semiconductor device that includes forming a doped region. Fig. Figure 2 is a schematic cross-sectional view to illustrate a process feature of the electrical activation of dopants in the doped region. Fig. Figures 3A to 3C are schematic cross-sectional views to illustrate further process features of a method for manufacturing a semiconductor device that includes forming a doped region. Fig. 4 and Fig. Figure 5 shows schematic cross-sectional views to illustrate configuration examples of a semiconductor device containing a doped region defined by the reference to Fig. The process characteristics described in sections 1A to 1C were developed. Fig. Figure 6 is a schematic illustration of simulated channeling profiles. DETAILED DESCRIPTION

[0008] The following detailed description refers to the accompanying drawings, which form part of this document and illustrate specific examples of semiconductor substrate processing. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are identified by the same reference symbols in the various drawings unless otherwise noted.

[0009] The terms "have," "contain," "comprise," "exhibit," and the like are open terms, indicating the presence of the identified structures, elements, or features, but not excluding the presence of additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise.

[0010] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" implies that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0011] When two elements A and B are combined with an "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies analogously to combinations of more than two elements.

[0012] For physical dimensions, specified ranges include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least".

[0013] The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0014] The term "on" should not be interpreted as meaning only "directly on". Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" the substrate).

[0015] An example of a process for fabricating a semiconductor device involves forming a doped region in a semiconductor body. Forming the doped region can include introducing initial dopants through a first surface of the semiconductor body at a first vertical reference level by means of a first ion implantation process. Subsequently, a first heat treatment is applied to the semiconductor body. Then, second dopants can be introduced through the first surface of the semiconductor body at the first vertical reference level by means of a second ion implantation process. The atomic number of the first dopants can be equal to the atomic number of the second dopants. The ion implantation energy of the second ion implantation process can differ from that of the first ion implantation process by less than 20%, less than 10%, or even less than 5%.The ion implantation dose of the second ion implantation process may differ by less than 20%, or less than 10%, or even less than 5% from the ion implantation dose of the first ion implantation process.

[0016] The semiconductor material can have a crystal lattice suitable for ion channeling. Typically, in some crystal directions of single-crystal materials, open spaces extend straight into the crystal. These open spaces form channels through which ions migrate with less interaction with the atoms of the crystal lattice than outside the channels. The channels control the movement of the ions, with ions entering through such channels exhibiting a delay pattern that differs from the delay pattern for ions entering the semiconductor material outside the channels. In other words, in some crystal directions of single-crystal materials, the atoms align themselves in such a way that they form so-called channels in which the incoming ion flow is restricted. The channel directions coincide with principal crystal directions.

[0017] The first and second dopants can be implanted into the semiconductor body, for example, via ions of the respective element or element compound. For instance, no further ion implantation can be performed between the ion implantation of the first and second dopants. In addition to the first and second ion implantation processes, further ion implantation processes can be performed to form the doped region. For example, each of the further ion implantation processes can be performed either before or after the first ion implantation process. Further heat treatment can be performed after each or some of the additional ion implantation processes.A sequence of n ion implantations, followed by crystal damage repair, can be performed to form the doped region, where n is an integer equal to or greater than 2, e.g., 3, 4, 5, 6, 7, 8, 9, 10, or even larger. Between ion implantation processes, a semiconductor layer can be formed on a surface of the semiconductor body, from which dopants enter or migrate into the semiconductor body via the ion implantation processes. This can allow for an increase in the lateral extent of the doped region. Parameters of the additional ion implantation processes, e.g., ion implantation energy and / or ion implantation dose and / or ion implantation inclination angle with respect to the vertical axis on the first surface, can be similar to those of the first and / or second ion implantation process.

[0018] The first vertical reference level is measured with respect to a fixed vertical position within the semiconductor body and can define an outer surface of the semiconductor body. If a semiconductor layer is deposited on the first surface at the first reference level by a semiconductor deposition process, followed by a subsequent ion implantation process into the deposited semiconductor layer, the subsequent ion implantation process will introduce dopants through a surface of the deposited semiconductor layer that lies at a second vertical reference level, which differs from the first vertical reference level. While the first vertical reference level can define the outer surface of the semiconductor layer before the deposition process, the second vertical reference level can define the outer surface of the semiconductor body plus the deposited semiconductor layer.

[0019] The first heat treatment can be performed to cure the semiconductor body. This initial heat treatment can be carried out using a furnace process or rapid thermal processing (RTP). Additionally, or as an alternative, curing can be performed by laser thermal annealing (LTA), with or without melting. By ensuring a suitable heat balance for the curing process, this can reduce or minimize crystal damage in the irradiated zone. This, in turn, can reduce or minimize the degradation of channeling performance or de-channeling of subsequent ion implantation of dopants, such as in a second ion implantation process, due to crystal damage from the first ion implantation process. This can, for example, improve the tuning of a vertical dopant concentration profile.

[0020] The semiconductor device can be, for example, an integrated circuit, a discrete semiconductor device, or a semiconductor module. The semiconductor device can be, or contain, a power semiconductor device, such as a vertical power semiconductor device with a load current flowing between a first surface and a second surface. The semiconductor device can be, or contain, a power semiconductor IGFET, such as a power semiconductor MOSFET, or a power semiconductor IGBT. The power semiconductor device can be configured to conduct currents greater than 1 A, 10 A, or even 30 A, and can further be configured to generate voltages between load electrodes, such as between the emitter and collector of an IGBT or between the drain and source of a MOSFET, in the range of a few hundred to a few thousand volts.400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV blocking voltage. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device.

[0021] For example, the semiconductor body can be or contain a crystalline SiC semiconductor substrate. The crystalline SiC semiconductor substrate can, for example, have a hexagonal polytype, e.g., 4H or 6H. The semiconductor body can be homogeneously doped or can consist of differently doped SiC layer regions, e.g., with a doping concentration of at least 2 × 10⁻⁶. 17 cm -3 and at most 1×10 19 cm -3 , for example at least 5×10 17 cm -3 and at most 1×10 19 cm -3 , include or can be nominally undoped (e.g., with a doping concentration of at most 1×10 17 cm -3 or of at most 1×10 15 cm -3; so-called "unintentionally doped silicon carbide"). For example, the semiconductor body may comprise, e.g., differently doped SiC layer regions, an essentially homogeneously doped SiC semiconductor substrate, and an epitaxial buffer layer on the SiC semiconductor substrate. The semiconductor body may, for example, contain one or more layers of another material with a melting point close to or higher than crystalline silicon carbide. For example, the layers of another material may be embedded in the crystalline SiC semiconductor substrate. The crystalline SiC semiconductor substrate may have two essentially parallel main surfaces of the same shape and size and a lateral surface region connecting the edges of the two main surfaces.For example, the silicon carbide semiconductor substrate can be a rectangular prism with or without rounded edges, or a right cylinder, or a slightly inclined cylinder (e.g., with sides inclined at an angle of at most 8°, 5°, or 3°, respectively) with or without one or more flats or notches along the outer circumference. As an alternative to SiC, a wafer made of a wide-bandgap semiconductor, such as a non-silicon carbide wide-bandgap semiconductor material, can be processed. The wide-bandgap semiconductor wafer can have a larger bandgap than that of silicon (1.1 eV). For example, the wide-bandgap semiconductor wafer can be a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer.As an alternative to SiC and wide-bandgap materials, a silicon semiconductor body can also be used. For example, the semiconductor body can have a cubic diamond crystal lattice like silicon (Si). In the case of a cubic diamond crystal lattice, a surface of the semiconductor body can coincide with a {100} crystal face, can be inclined by at most ±2 degrees to the {100} crystal face, or can be any other surface suitable for channeling. Accordingly, a <100> -Crystal direction, which is one of several principal crystal directions along which channeling takes place, or any other suitable direction perpendicular to the process surface.

[0022] By dividing the ion implantation dose of a single ion implantation process into multiple, lower-dose ion implantations with intervening heat treatments to heal crystal damage caused by the previous implantation, the resulting ion implantation profile of the multiple implantations can offer greater flexibility in shaping profiles compared to a single ion implantation process or fewer ion implantation processes with the same total dose. The intervening heat treatments to heal the crystal damage from the previous ion implantation process improve ion implantations through channeling of subsequent ion implantations by reducing de-channeling or the effects of channeling degradation.More precisely, the concentration of implanted ions in the channeling extension region can be increased as a consequence of reduced crystal damage through the application of intermediate heat treatments.

[0023] For example, the first and / or second dopants can be implanted along a beam axis that deviates by no more than 1.5°, 1.0°, 0.5°, 0.3°, or 0.1° from a principal crystal axis of the semiconductor body along which channeling occurs. For example, a maximum inclination angle between a principal beam direction and the principal crystal direction along which ion channeling occurs, as well as a variability of the incidence angle of an implantation beam of no more than ±0.5 degrees for at least 80% of the surface of the semiconductor body, can apply.

[0024] Details regarding the process features described above apply equally to another example of a method for fabricating a semiconductor device. This method involves forming a doped region within a semiconductor body. The formation of the doped region can include the introduction of initial dopants through a first surface of the semiconductor body at a first vertical reference level by means of a first ion implantation process. The initial dopants can be implanted along a beam axis that deviates by no more than 1.5° from a principal crystal axis of the semiconductor body, along which channeling occurs. Subsequently, a first heat treatment can be applied to the semiconductor body. Then, a second set of dopants can be introduced through the first surface of the semiconductor body at the first vertical reference level by means of a second ion implantation process.The second dopants can be implanted along a beam axis that deviates by no more than 1.5° from a principal crystal axis of the semiconductor body along which channeling occurs. For example, the semiconductor body can be a SiC semiconductor body, and the principal crystal axis can be the c-axis. The atomic number of the first dopants can differ from the atomic number of the second dopants. Alternatively, or in addition, the ion implantation energy of the second ion implantation process can differ by less than 20%, less than 10%, or even less than 5% from the ion implantation energy of the first ion implantation process. Additionally, or in addition, the ion implantation dose of the second ion implantation process can differ by less than 20% from the ion implantation dose of the first ion implantation process.

[0025] The second ion implantation energy can, for example, be lower than the first ion implantation energy.

[0026] The second ion implantation dose can, for example, be lower than the first ion implantation dose.

[0027] For example, an ion implantation mask from the first ion implantation process can be reused for the second ion implantation process.

[0028] The process can further include, for example, applying an activation heat treatment to the semiconductor body after the second ion implantation process. The activation heat treatment can be configured to electrically activate the first and second dopants. The maximum temperature of the activation heat treatment can be higher than the maximum temperature of the first heat treatment.

[0029] The maximum temperature of the activation heat treatment can be more than 400 K, 500 K, or even 600 K higher than the maximum temperature of the initial heat treatment. For example, the temperature of the initial heat treatment might range from 600°C to 1000°C, and the temperature of the activation heat treatment might range from 1600°C to 1900°C.

[0030] The maximum temperature of the first heat treatment can, for example, be configured to heal any crystal damage caused by the first ion implantation process.

[0031] The semiconductor body could, for example, be a SiC semiconductor body. The maximum temperature of the first heat treatment could, for example, be between 600°C and 1200°C, between 600°C and 1000°C, or between 700°C and 900°C.

[0032] The process can, for example, include additional ion implantation processes beyond the first and second ion implantation processes. Each of these additional ion implantation processes can be performed either before or after the first ion implantation process. Heat treatments to repair crystal damage can be performed between subsequent ion implantation processes that include at least one of the additional ion implantation processes. The atomic number of the dopants used for the additional ion implantation processes to form the doped region can, for example, be the same as or different from the atomic number of the first / second dopants.

[0033] The doped region can, for example, be a p-doped region or an n-doped region of a superjunction structure with the p-doped region laterally adjacent to the n-doped region.

[0034] For example, forming the superjunction structure can further include forming a semiconductor layer on the first surface of the semiconductor body. Forming the superjunction structure can also include introducing third dopants through a surface of the semiconductor layer at a second vertical reference level using a third ion implantation process. Subsequently, a second heat treatment can be applied to the semiconductor body and the semiconductor layer. Finally, fourth dopants can be introduced through the surface of the semiconductor layer at the second vertical reference level using a fourth ion implantation process. The atomic number of one of the third dopants can be equal to the atomic number of one of the fourth dopants.The ion implantation energy of the fourth ion implantation process may differ from that of the third ion implantation process by less than 20%, less than 10%, or even less than 5%. Similarly, the ion implantation dose of the fourth ion implantation process may differ from that of the third ion implantation process by less than 20%, less than 10%, or even less than 5%.

[0035] For example, the formation of the superjunction structure can further involve the formation of a semiconductor layer on the first surface of the semiconductor body. The formation of the superjunction structure can also include the introduction of third dopants through a surface of the semiconductor layer at a second vertical reference level by means of a third ion implantation process, and the introduction of fourth dopants through the surface of the semiconductor layer at the second vertical reference level by means of a fourth ion implantation process. The introduction of both the first and third dopants can be performed before the first heat treatment, and the introduction of both the second and fourth dopants can be performed after the first heat treatment.For example, the atomic number of the third dopants is equal to the atomic number of the fourth dopants and / or the ion implantation energy of the fourth ion implantation process differs by less than 20% from the ion implantation energy of the third ion implantation process and / or the ion implantation dose of the fourth ion implantation process differs by less than 20% from the ion implantation dose of the third ion implantation process.

[0036] For example, both the first and second dopants form the n-doped region or an n-doped column of the superjunction structure, and both the third and fourth dopants form the p-doped region or a p-doped column of the superjunction structure. In other words, the n-doped and p-doped regions of the superjunction structure can each be formed in at least two ion implantation steps along the channeling axis. Between each ion implantation step, a heat treatment can be performed to heal the crystal lattice and thus improve channeling in the subsequent ion implantation step.

[0037] The doped region can be an n-doped current spread region of a power semiconductor device containing gate trenches. The current spread region can be adjacent to a bottom surface of the gate trenches. Furthermore, the current spread region can be adjacent to a channel end opposite another channel end that borders the source region.

[0038] For example, both the ion implantation energy of the first ion implantation process and the ion implantation energy of the second ion implantation process can each be greater than 1000 keV.

[0039] The semiconductor device may, for example, include a doped region formed by the method of one of the examples disclosed herein. The semiconductor device may be a vertical power semiconductor device, which may, for example, be part of an integrated circuit, a discrete semiconductor device, or a semiconductor module, or at least one of these. The semiconductor device may be used in applications relating to power transmission and distribution, automotive and transportation, renewable energy, consumer electronics, and other industrial applications. The vertical power semiconductor device may, for example, be or include an insulated-gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a junction field-effect transistor (JFET).For semiconductor devices based on substrate materials that allow only low diffusion of dopants, such as SiC, the examples described herein can provide greater flexibility in shaping doping concentration profiles. For example, higher concentrations at greater depths and box-shaped profiles can be achieved in such substrate materials. Doped regions requiring greater depths to fulfill their intended purpose can benefit from the examples disclosed herein. The doped region can, for example, be an n-doped current-spreading region of an n-channel MOSFET. The doped region can also be, for example, a portion, such as an n-doped or p-doped section in the form of a column, a superjunction, or an SJ structure of a superjunction MOSFET.

[0040] More details and aspects are provided in connection with the examples described above or below. The processing of the semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more of the examples described above or below.

[0041] The aspects and features that have been listed and described together with one or more of the previously described examples and illustrations can also be combined with one or more of the other examples to replace an identical feature of the other example or to additionally introduce the feature into the other example.

[0042] The functional and structural details described in relation to the examples above shall apply equally to the examples illustrated in the figures and further described below.

[0043] Referring to the schematic cross-sectional views of the Fig. Sections 1A to 1C illustrate exemplary process features for manufacturing a semiconductor device.

[0044] The illustrated process features of the method illustrate exemplary process features for forming a doped region 102 in a semiconductor body 104.

[0045] Referring to Fig. In step 1A, first dopants 1081 are introduced through a first surface 106 of the semiconductor body 104 at a first vertical reference level L1 by means of a first ion implantation process I2-1. The first vertical reference level L1 refers to a predetermined vertical position within the semiconductor body 104. The first dopants 1081 are implanted along a beam axis 1101 at an angle α1 with respect to a vertical axis of the first surface 106. For example, the angle α1 can deviate by a maximum of 1.5° from a main crystal axis of the semiconductor body along which channeling takes place, e.g., the c-axis in a SiC semiconductor body. The first ion implantation process I2-1 is based on an ion implantation energy E1 and an ion implantation dose D1.

[0046] Referring to Fig. In step 1B, a first heat treatment T1 is applied to the semiconductor body 104. For example, the first heat treatment G1 can include curing the semiconductor body 104 using a furnace process or rapid thermal processing (RTP). Additionally or alternatively, curing can be performed by laser thermal annealing (LTA), with or without melting. This can enable a reduction or minimization of crystal damage in the irradiated zone through appropriate curing.

[0047] Referring to Fig. Following the first heat treatment T1, second dopants 1082 are introduced through the first surface 106 of the semiconductor body 104 at the first vertical reference level L1 by means of a second ion implantation process I2-2. The second dopants 1082 are implanted along a beam axis 1102 at an angle α2 with respect to the vertical axis on the first surface 106. For example, the angle α2 can deviate by a maximum of 1.5° from a main crystal axis of the semiconductor body 104, along which channeling takes place, e.g., the c-axis in a SiC semiconductor body. The second ion implantation process I2-2 is based on an ion implantation energy E2 and an ion implantation dose D2. An atomic number of 1081 for the first dopants is equal to an atomic number of 1082 for the second dopants. For example, the first and second dopants could be Al for p-type doping, e.g.in a semiconductor body made of SiC or Si. The first and second dopants can be, for example, P for n-type doping, e.g., in a semiconductor body made of SiC or Si. The ion implantation energy E2 of the second ion implantation process I2-2 differs by less than 20%, less than 10%, or less than 5% from the ion implantation energy E1 of the first ion implantation process I2-1. The ion implantation dose D2 of the second ion implantation process I2-2 differs by less than 20%, less than 10%, or less than 5% from the ion implantation dose D1 of the first ion implantation process I2-1.

[0048] Other process characteristics can include, for example, before, after, or between the processes related to Fig. 1A, Fig. 1B, Fig. The process features illustrated in Figure 1C are carried out. Examples of further process features include deposition processes for forming insulating layers or semiconductor layers or conductive layers, etching processes, e.g., via a lithographic etch mask(s), for structuring structures, and doping processes for forming further doped regions in the semiconductor body 104. Exemplary doped regions include source and drain regions or emitter and collector regions, a body region(s), a body contact region(s), a current spreading region(s), a shielding region(s) configured to shield a gate dielectric against high electric fields, and a field stopping region(s). Exemplary insulating layers include a gate dielectric(s) and an interlayer insulating dielectric(s) in a wiring region above the semiconductor body 104.Examples of semiconducting layers include gate electrode(s), field electrode(s), and floating or potential-free electrode(s) formed from highly doped semiconductor materials. Examples of conductive layers include structured wiring layer(s), such as structured metal wiring layer(s), contact holes, contact plugs, and bond pad(s).

[0049] In the Fig. In the examples 1A to 1C, the formation of the doped region 102 based on two ion implantation processes I2-1 and I2-2 was illustrated. These two ion implantation processes I2-1 and I2-2 for forming the doped region 102 are merely exemplary and in no way limiting. Additional ion implantation processes beyond the first and second I2-1 and I2-2 can be performed to form the doped region 102. For example, each of the additional ion implantation processes can be performed either before the first I2-1 or after the second I2-2. Parameters of the additional ion implantation processes, e.g.,The ion implantation energy and / or ion implantation dose and / or inclination angle of the ion implantation with respect to the vertical axis on the first surface 106 may be similar to the first and / or second ion implantation process I2-1, I2-2.

[0050] Referring to the schematic cross-sectional view of Fig. 2. The method for forming the doped region 102 can further comprise a heat treatment Ta applied to the semiconductor body 104 after the second ion implantation process I2-2 for activation. The heat treatment for activation is configured to electrically activate the first and second dopants 1081, 1082.

[0051] The method for forming the doped area 102 can further be described in relation to the schematic cross-sectional views of the Fig. The process characteristics described in sections 3A to 3C include further process characteristics. These process characteristics can be categorized, for example, according to the criteria in Fig. 1C and / or Fig. 2 illustrated process characteristics or according to the process characteristics of Fig. 1C and before the process characteristics of Fig. 2 will be executed.

[0052] Referring to Fig. Step 3A comprises the formation of the doped region 102 and the formation of a semiconductor layer 1041 on the first surface 106 of the semiconductor body 104. Third dopants 1083 are introduced through a surface 1061 of the semiconductor layer 1041 at a second vertical reference level L2 by means of a third ion implantation process I2-3. The third dopants 1083 are implanted along a beam axis 1103 at an angle α3 with respect to the vertical axis on the surface 1061. For example, the angle α3 can deviate by a maximum of 1.5° from a principal crystal axis of the semiconductor body 104 along which channeling takes place, e.g., the c-axis in a SiC semiconductor body. The third ion implantation process I2-3 is based on an ion implantation energy E3 and an ion implantation dose D3.

[0053] Referring to Fig. 3B includes forming the doped area 102 and applying a second heat treatment T2 to the semiconductor body 104 and the semiconductor layer 1041.

[0054] Referring to Fig. In step 3C, fourth dopants 1084 are introduced through the surface 1061 of the semiconductor layer 1041 at the second vertical reference level L2 by means of a fourth ion implantation process I2-4. The fourth dopants 1084 are implanted along the beam axis 1104 at an angle α4 with respect to the vertical axis on the surface 1061. For example, the angle α4 can deviate by a maximum of 1.5° from a principal crystal axis of the semiconductor body 104, along which channeling takes place, e.g., the c-axis in a SiC semiconductor body. The fourth ion implantation process I2-4 is based on an ion implantation energy E4 and an ion implantation dose D4. An atomic number of the third dopants 1083 can be equal to an atomic number of the fourth dopants 1084.An ion implantation energy E4 of the fourth ion implantation process I2-4 differs by less than 20%, less than 10%, or less than 5% from an ion implantation energy E3 of the third ion implantation process I2-3. An ion implantation dose D4 of the fourth ion implantation process I2-4 differs by less than 20%, less than 10%, or less than 5% from an ion implantation dose D3 of the third ion implantation process I2-3.

[0055] In the Fig. 1A to 1C in combination with Fig. In the examples illustrated in Figures 3A to 3C, the formation of the doped region 102 was demonstrated based on four ion implantation processes I2-1, I2-2, I2-3, and I2-4. These four ion implantation processes for forming the doped region 102 are merely examples and are in no way limiting. Additional ion implantation processes beyond the first four I2-1, I2-2, I2-3, and I2-4 can be performed to form the doped region 102. The additional ion implantation process(s) can be performed before, between, or after the I2-1, I2-2, I2-3, and I2-4 processes.For example, one or more semiconductor layers can be formed on the surface 1061 of semiconductor layer 1041, and two or more additional ion implantation processes can be performed to introduce dopants into each of the one or more semiconductor layers on semiconductor layer 1041. This allows, for example, a flexible design of a vertical doping concentration profile with respect to profile depth and profile shape. Parameters of the additional ion implantation processes, e.g., ion implantation energy and / or ion implantation dose and / or inclination angle of an ion implantation with respect to the vertical axis, can be similar to those of the first to fourth ion implantation processes I2-1, I2-2, I2-3, I2-4.

[0056] The schematic cross-sectional view of Fig. Figure 4 illustrates a configuration example of a semiconductor device 100, which includes a superjunction structure SJ with an n-doped region 1021 laterally adjacent to a p-doped region 1022. The n-doped region 1021 and / or the p-doped region 1022 can be formed by the process examples described herein for forming the doped region 102. The semiconductor device 100 is schematically illustrated as a vertical power semiconductor device, which includes a first load contact LC1, e.g., a source or emitter electrode, electrically coupled via a first side 1151 of the semiconductor device 100 to a transistor cell region 114. The transistor cell region 114 is simplified by a dashed box, which can enclose any transistor cell configuration, e.g., planar or trench-gate configurations.The superjunction structure SJ is arranged between the transistor cell area 114 and a second side 1152 of the semiconductor device 100. A control electrode contact C, e.g., a gate pad, is electrically coupled to the transistor cell area via the first side 1051 of the semiconductor device 100. A second load contact LC2, e.g., a drain or collector electrode, is electrically coupled to the semiconductor body 104 via the second side 1152 of the semiconductor device 100.

[0057] The schematic cross-sectional view of Fig. Figure 5 illustrates another example of a semiconductor device 100 configured as an n-channel trench-gate MOSFET, which includes an n-doped current-spreading region 116 adjacent to a trench-gate structure 118 comprising a gate dielectric 1181 and a gate electrode 1182. The gate electrode 1182 is electrically connected to the control contact C. The first load contact LC1, e.g., a source contact, is connected via the first side 1151 of the semiconductor device 100 to an n + The -doped source region 120 and a p-doped body region 122 are electrically coupled. The second load contact LC2, e.g. a drain electrode, is electrically coupled to the semiconductor body 104 via a second side 1152 of the semiconductor device 100.

[0058] Fig.Figure 6 is a schematic illustration of simulated channeling profiles of aluminum at an ion implantation energy of 60 keV into the c-axis of a SiC semiconductor body. A concentration profile C1 results from a high-dose implantation (1 × 10⁻¹⁵ cm⁻¹). -2 ) and shows a pronounced de-channeling peak at a depth of approximately 90 nm. A concentration profile C3 is based on the same simulation parameters as the concentration profile C1, but at a 10-fold lower dose (e.g., 1 x 14 cm³). -2 A more plateau-like profile is achieved here. A concentration profile C2 is based on the concentration profile C3, but multiplied by a factor of 10. Here, it is assumed that the ion implantation is performed with a dose of 1E14 cm. -2The implantation process is repeated 10 times, with crystal healing performed between each implantation to maintain the crystal structure and ensure consistent channeling performance. The hatched area indicates the significantly higher aluminum concentration at greater depths, while the checkerboard pattern shows the reduction in concentration at random depths compared to the C1 concentration profile. The illustrated division into ten consecutive implantation and healing steps is for illustrative purposes only. The number of times the channeling implantation is subdivided into individual steps depends, for example, on the specific requirements of the technology itself.

[0059] The description and drawings only illustrate the principles of revelation.

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Forming a doped region (102) in a semiconductor body (104), wherein forming the doped region (102) comprises: Introducing first dopants (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1); thereafter Applying a first heat treatment (T1) to the semiconductor body (104); and then Introducing a second dopant (1082) through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by means of a second ion implantation process (I2-2), wherein an atomic number of the first dopant (1081) is equal to an atomic number of the second dopant (1082), an ion implantation energy (E2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation energy (E1) of the first ion implantation process (I2-1), and an ion implantation dose (D2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation dose (D1) of the first ion implantation process (I2-1). [2] Method according to the preceding claim, wherein the second dopants (1082) are implanted along a beam axis (1102) which deviates by no more than 1.5° from a main crystal axis of the semiconductor body (104) along which channeling takes place. [3] Method according to one of the preceding claims, wherein the first dopants (1081) are implanted along a beam axis (1101) which deviates by no more than 1.5° from a main crystal axis of the semiconductor body (104) along which channeling takes place. [4] Method for manufacturing a semiconductor device, wherein the method comprises: Forming a doped region (102) in a semiconductor body (104), wherein forming the doped region (102) comprises: Introducing first dopants (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1), wherein the first dopants (1081) are implanted along a beam axis (1101) that deviates by no more than 1.5° from a principal crystal axis of the semiconductor body (104), along which channeling takes place; thereafter Applying a first heat treatment (T1) to the semiconductor body (104); and then Introducing second dopants (1082) through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by means of a second ion implantation process (I2-2), wherein the second dopants (1082) are implanted along a beam axis (1102) which deviates by no more than 1.5° from a main crystal axis of the semiconductor body (104), along which channeling takes place. [5] Method according to any one of the preceding claims 2 to 4, wherein the semiconductor body is a SiC semiconductor body and the main crystal axis is the c-axis. [6] Method according to claim 4 or claim 5 in relation to claim 4, wherein the atomic number of the first dopants (1081) differs from the atomic number of the second dopants (1082) and / or an ion implantation energy (E2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation energy (E1) of the first ion implantation process (I2-1) and / or an ion implantation dose (D2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation dose (D1) of the first ion implantation process (I2-1). [7] Method according to any of the preceding claims, wherein the second ion implantation energy (E2) is lower than the first ion implantation energy (E1). [8] Method according to any of the preceding claims, wherein the second ion implantation dose (D2) is less than the first ion implantation dose (D1). [9] Method according to any of the preceding claims, wherein an ion implantation mask from the first ion implantation process (I2-1) is reused for the second ion implantation process (I2-2). [10] Method according to any of the preceding claims, further comprising: Applying an activation heat treatment to the semiconductor body (104) after the second ion implantation process (I2-2), wherein the activation heat treatment is configured to electrically activate the first and second dopants (1081, 1082), and wherein a maximum temperature of the activation heat treatment is higher than a maximum temperature of the first heat treatment (T1). [11] Method according to the preceding claim, wherein the maximum temperature of the heat treatment for activation is more than 400 K higher than the maximum temperature of the first heat treatment. [12] Method according to any of the preceding claims, wherein the maximum temperature of the first heat treatment is configured to heal any crystal damage caused by the first ion implantation process (I2-1). [13] Method according to any of the preceding claims, wherein the semiconductor body (104) is a SiC semiconductor body and the maximum temperature of the first heat treatment (T1) is between 600°C and 1200°C. [14] Method according to any of the preceding claims, further comprising ion implantation processes in addition to the first and second ion implantation processes (I2-1, I2-2), wherein each of the ion implantation processes in addition to the first and second ion implantation processes (I2-1, I2-2) is carried out either before the first ion implantation process (I2-1) or after the second ion implantation process (I2-2). [15] Method according to any of the preceding claims, wherein the doped region (102) is a p-doped region (1022) or an n-doped region (1021) of a superjunction structure (SJ) having the p-doped region (1022) bordering laterally on the n-doped region (1021). [16] Method according to the preceding claim, wherein the formation of the superjunction structure (SJ) further comprises: Forming a semiconductor layer (1041) on the first surface (106) of the semiconductor body (104); and Introducing a third dopant (1083) through a surface (1061) of the semiconductor layer (1041) at a second vertical reference level (L2) by means of a third ion implantation process (I2-3); thereafter Applying a second heat treatment (T2) to the semiconductor body (104) and the semiconductor layer (1041); and thereafter Introducing fourth dopants (1084) through the surface (1061) of the semiconductor layer (1041) at the second vertical reference level (L2) by means of a fourth ion implantation process (I2-4), wherein an atomic number of the third dopants (1083) is equal to an atomic number of the fourth dopants (1084), an ion implantation energy (E4) of the fourth ion implantation process (I2-4) differs by less than 20% from an ion implantation energy (E3) of the third ion implantation process (I2-3), and an ion implantation dose (D4) of the fourth ion implantation process (I2-4) differs by less than 20% from an ion implantation dose (D3) of the third ion implantation process (I2-3). [17] Method according to claim 15, wherein forming the superjunction structure (SJ) further comprises: Forming a semiconductor layer (1041) on the first surface (106) of the semiconductor body (104); and Introducing third dopants (1083) through a surface (1061) of the semiconductor layer (1041) at a second vertical reference level (L2) by means of a third ion implantation process (I2-3); and Introducing fourth dopants (1084) through the surface (1061) of the semiconductor layer (1041) at the second vertical reference level (L2) by means of a fourth ion implantation process (I2-4), wherein the introduction of both the first dopants (1081) and the third dopants (1083) is carried out before the first heat treatment (T1) and wherein the introduction of both the second dopants (1082) and the fourth dopants (1084) is carried out after the first heat treatment (T1). [18] Method according to one of the preceding claims 16 or 17, wherein both the first dopants (1081) and the second dopants (1082) form the n-doped region (1021) of the superjunction structure (SJ); and Both the third dopants (1083) and the fourth dopants (1084) form the p-doped region (1022) of the superjunction structure (SJ). [19] Method according to any one of claims 1 to 14, wherein the doped region (102) is an n-doped current spreading region (116) of a power semiconductor device containing gate trenches, wherein the current spreading region borders a bottom side of the gate trenches. [20] Method according to any of the preceding claims, wherein each of the ion implantation energy (E1) of the first ion implantation process (I2-1) and the ion implantation energy (E2) of the second ion implantation process (I2-2) is greater than 1000 keV.

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