METHOD FOR PRODUCING AN ARRANGEMENT OF AT LEAST TWO ION TRAP CHIPS AND ARRANGEMENT

Abstract

Method for producing an arrangement (1) of at least two ion trap chips, comprising a first ion trap chip (25) and a second ion trap chip (26), with - Providing a holder (2) having a first main surface (5) with a first region (3) and a second region (4), - arranging a first transparent layer (22) on which the first ion trap chip (25) is arranged on the first region (3), - providing a second transparent layer (23) on which the second ion trap chip (26) is arranged in the second region (4), - aligning the first ion trap chip (25) and the second ion trap chip (26) in the vertical direction so that the main extension planes of the first ion trap chip (25) and the second ion trap chip (26) extend within a common plane (27) extending in lateral directions, - providing a spacer layer (12) with a predetermined thickness in the vertical direction depending on the orientation, - arranging the spacer layer (12) on the second region (4), - Arranging the second transparent layer (23) on the spacer layer (12) such that the main extension planes of the first ion trap chip (25) and the second ion trap chip (26) extend within the common plane (27).

Description

The present disclosure relates to a method for manufacturing an array of at least two ion trap chips and an array.Quantum computers with trapped ions are limited in size by the number of ions that can be trapped by a single ion trap chip. One possibility is to establish a physical connection between a plurality of ion trap chips by positioning them close to one another and moving the ions back and forth between them, in particular in lateral directions. However, mechanical alignment must be precise and is typically performed with large translation motion tables that are not compatible with scaling of the ion trap chips.WO 2022 / 090729, A1, describes a chip arrangement and a method for producing a chip arrangement.One object to be achieved is to provide a method with which two ion trap chips can be aligned particularly precisely with respect to one another. Furthermore, such an arrangement is intended to be provided.The object is achieved by the subject matter of the independent claims. Advantageous embodiments, implementations and further developments are the subject matter of the respective dependent claims.The method of manufacturing an array of at least two ion trap chips is described, comprising a first ion trap chip and a second ion trap chip. In particular, each of the ion trap chips is configured to include at least one ion and / or to change an electronic state of the at least one ion, in particular to perform a quantum calculation. Each of the ion trap chips is in particular a surface ion trap and / or a multilayer ion trap.For example, each of the ion trap chips includes a set of electrodes provided on a substrate. For example, a high-frequency voltage is applied to at least some of the electrodes, such that a time-varying electric field is provided, which is designed to confine and / or modify the ion. In particular, the ion or ions are located in a processing area of each of the ion trap chips.A mount having a first major surface with a first region and a second region is provided. In particular, the holder comprises the first main surface, which is e.g. a top surface, opposite a second main surface, which is e.g. a bottom surface. For example, the holder, in particular the second main surface, is arranged on a carrier, which is in particular a stable platform for the holder. The mount is formed with, for example, a material compatible with a vacuum environment and / or a cryogenic environment. The material of the holder comprises, for example, at least one of the materials steel, in particular a stainless steel alloy, aluminum, copper, titanium, ceramic. The holder is, for example, monolithically formed.A first transparent layer is disposed on the first region, and the first ion trap chip is disposed on the first transparent layer. For example, the first transparent layer and the first ion trap chip are mechanically stably fixed on the first region. This means that the first ion chip is mechanically stably connected to the first region.For example, the first transparent layer comprises a top surface and a bottom surface opposite the top surface, wherein the top surface and the bottom surface are connected to a side surface. The bottom surface of the first transparent layer faces the first region, for example. The first ion trap chip is arranged, for example, on the top surface of the first transparent layer.The first transparent layer is formed, for example, with a material which is transmissive, in particular for ultraviolet light (UV) and / or visible light. For example, the first transparent layer is configured to transmit light. The light is, for example, characteristic of electromagnetic radiation in a UV wavelength range, e.g. at least 100 nm and at most 380 nm, and / or characteristic of electromagnetic radiation in a visible wavelength range, e.g. at least 380 nm and at most 780 nm. The first transparent layer has a light transmittance of at least 80% or at least 90%. The material of the first transparent layer comprises, for example, a glass material. The glass material comprises, for example, at least one of the following materials: borosilicate glass, quartz glass.A second transparent layer is provided in the second region, wherein the second ion trap chip is arranged on the second transparent layer. In particular, the second ion trap chip is arranged on the second transparent layer and subsequently the second transparent layer with the second ion trap is positioned in the second region. For example, the second transparent layer and the second ion trap chip are provided in the second region without being mechanically stably fixed on the second region.For example, the second transparent layer with the second ion trap in the second region is provided with a precision movement device, which is in particular a five- or six-dimensional movement table. The precision moving device is specifically configured to move in the vertical direction and in lateral directions, and is configured to adjust a degree of inclination and a degree of yaw. Moreover, the precision movement device is designed, for example, to set a rotation in lateral directions. In particular, the second ion trap chip faces the precision moving device and the second transparent layer faces the holder.Alternatively, the holder is arranged on a first precision movement device, which is a two- or three-dimensional movement table configured to move in the vertical direction and / or in lateral directions, and the second transparent layer is arranged on a second precision movement device configured to adjust a degree of inclination and a degree of yaw and optionally a rotation in lateral directions.For example, the second transparent layer comprises a top surface and a bottom surface opposite the top surface, wherein the top surface and the bottom surface are connected to a side surface. The bottom surface of the second transparent layer is arranged, for example, directly opposite the second region. For example, the bottom surface of the second transparent layer is spaced apart from the second region in the vertical direction.The second transparent layer having the second ion trap is provided in the second region such that the side surfaces of the first transparent layer and the second transparent layer face each other. For example, the mutually facing side surfaces of the first transparent layer and of the second transparent layer are spaced apart from one another in lateral directions. A distance of the mutually facing side surfaces of the first transparent layer and the second transparent layer is, for example, at least 100 μm, at least 200 μm or at least 300 μm and / or at most 600 μm, at most 500 μm or at most 400 μm, for example, approximately 200 μm. The distance is in particular a minimum distance in lateral directions of the mutually facing side surfaces of the first transparent layer and of the second transparent layer.The second transparent layer is formed of the same material as the first transparent layer, for example. The features in connection with the first transparent layer also apply in connection with the second transparent layer.The first ion chip and the second ion chip are aligned in the vertical direction such that the main extension planes of the first ion chip and the second ion chip extend in a common plane extending in lateral directions. In addition, the first ion chip and the second ion chip are oriented such that the mutually facing side surfaces of the first ion chip and of the second ion chip extend parallel to one another. For example, the holder has a main extension plane in lateral directions. Vertical directions are oriented perpendicular to the lateral directions. In particular, the first ion chip, the second ion chip, the first transparent layer and the second transparent layer each have a main extension plane in lateral directions. For example, alignment marks, e.g., certain features on the first ion chip and the second ion chip, are used to verify the correct alignment. In particular, the alignment marks may be a visible part of the first ion chip and the second ion chip, e.g. at least one particular electrode or wire.In the aligned state, the first transparent layer and the first ion chip are fastened to the holder and the second transparent layer and the second ion chip are spaced apart from the first main surface in the vertical direction by a distance such that the main extension planes of the first ion chip and of the second ion chip extend in lateral directions within the common plane. In particular, the mutually facing side surfaces of the first ion chip and of the second ion chip extend parallel to one another in the aligned state. For example, a position of the substrate of the second ion chip is oriented such that a position of the substrate of the second ion chip in lateral directions are approximately the same, e.g. the positions in lateral directions differ by at most 1 μm or at most 0.5 μm.For example, the mutually facing side surfaces of the first ion chip and of the second ion chip are spaced apart from one another in lateral directions, wherein a distance between the mutually facing side surfaces of the first ion chip and of the second ion chip is smaller, in particular at least 10% or at least 50% smaller, than the distance of the mutually facing side surfaces of the first transparent layer and of the second transparent layer.For example, the alignment is performed by the precision moving device on which the second transparent layer and the second ion trap chip are disposed.A spacer layer is provided, the spacer layer having a predetermined thickness in the vertical direction depending on the orientation. For example, the predetermined thickness in the vertical direction is characteristic of the distance between the second transparent layer and the second region in the vertical direction. In particular, the predefined thickness is smaller than the distance between the second transparent layer and the second region or between the second transparent layer and a further element arranged on the second region for compensating variations in the spacer layer and / or, for example, for compensating adhesive layers.The spacer layer is formed, for example, with a material having a comparatively low coefficient of thermal expansion. The material of the spacer layer comprises, for example, quartz. The spacer layer is, for example, monolithically formed. The predetermined thickness of the spacer layer is produced, for example, by a mechanical material removal, such as, for example, mechanical polishing, of an initial spacer layer.The predefined thickness is, for example, at least 20 μm or at least 30 μm and / or at most 500 μm, at most 300 μm or at most 100 μm. The predetermined thickness is uniform, for example, over the entire spacer layer, within the limits of manufacturing tolerances. The spacer layer has, for example, the manufacturing tolerance related to a variation in thickness. The deviation is in particular at most 10 μm, at most 3 μm or at most 2 μm.The spacer layer is disposed on the second region. For example, the spacer layer is mechanically stably fixed on the second region.The second transparent layer is arranged on the spacer layer in such a way that the main extension planes of the first ion trap chip and of the second ion trap chip extend within the common plane. For example, the second transparent layer and the second ion trap chip are directly mechanically stably fixed to the spacer layer. This means that the second ion trap chip is mechanically stably connected to the second region.After the alignment, the processing regions of the first ion trap chip and the second ion trap chip are aligned in the vertical direction on the same plane. In particular, the processing regions overlap spatially in the lateral and vertical directions. In this way, a physical connection is established between the first ion trap chip and the second ion trap chip, and ions can be reciprocated between the ion chips.The method described here is carried out, for example, in the sequence indicated. The method described here is, for example, at least partially a computer-implemented method.One concept of the method described here is, inter alia, to use the first transparent layer and the second transparent layer and the spacer layer for aligning the two ion trap chips. The first transparent layer and the second transparent layer advantageously provide an optical access for aligning the two ion trap chips in the vertical direction. Depending on such a particularly precise alignment, the thickness of the spacer layer can advantageously be precisely predefined.According to at least one embodiment of the method, during the alignment a distance between the second transparent layer and the holder in the vertical direction is determined. In particular, the predefined thickness of the spacer layer is determined as a function of the distance between the second transparent layer and the second region in the vertical direction, in particular between the bottom surface of the second transparent layer and a further element arranged on the second region in the vertical direction.During the alignment, the second transparent layer is moved in the vertical direction towards the second region in such a way that the second transparent layer, in particular the base surface, is in direct contact with the second region or the further element arranged on the second region. Subsequently, the second transparent layer is moved away from the second region in the vertical direction until the main extension planes of the first ion trap chip and of the second ion trap chip extend in a common plane. With such a movement, the distance between the second transparent layer and the holder in the vertical direction is advantageously determined accurately.According to at least one embodiment of the method, a first piezoelectric element is arranged on the holder in the first region. For example, the first piezoelectric element is mechanically fixed in a stable manner on the first region. In particular, before arranging the first transparent layer with the first ion trap chip on the first region, the first piezo element is arranged on the holder in the first region.According to at least one embodiment of the method, a second piezoelectric element is arranged on the holder in the second region. For example, the second piezoelectric element is mechanically fixed in a stable manner on the second region. In particular, before the provision of the second transparent layer with the second ion trap chip in the second region, the second piezoelement is arranged on the holder in the second region.In particular, during the alignment, the distance between the second transparent layer and the second piezoelectric element is determined in the vertical direction. For example, the predefined thickness is characteristic of the distance between the second transparent layer and the second piezoelectric element in the vertical direction. The distance is a minimum distance in the vertical direction between two surfaces of the second transparent layer and the second piezoelectric element facing each other.In particular, the first piezoelectric element and / or the second piezoelectric element are designed to convert electrical energy into mechanical energy on the basis of the piezoelectric effect, and vice versa. For example, the first piezoelectric element and / or the second piezoelectric element are designed to change the thickness in the vertical direction and / or shear along lateral directions as a function of an applied electrical energy, e.g. a voltage applied to the first piezoelectric element and / or the second piezoelectric element. By using the first piezoelectric element and / or the second piezoelectric element, an active position stabilization and / or a passive position stabilization of the first ion trap chip and / or of the second ion trap chip on the picometer level can be advantageously achieved. In particular, a position of the first ion trap chip and / or of the second ion trap chip can be moved, i.e. adjusted and / or stabilized, in the vertical direction and / or in lateral directions with an accuracy of at most 1 nm or at most 100 pm using the first piezoelectric element and / or the second piezoelectric element.According to at least one embodiment of the method, the first transparent layer is arranged on the first piezoelectric element. For example, following the arrangement of the first piezoelectric element on the holder in the first region, the first transparent layer with the first ion trap chip is arranged on the first piezoelectric element. For example, the first transparent layer is mechanically stably fixed on the first piezo element. In particular, the holder, the first piezoelectric element, the first transparent layer and the first ion trap chip are stacked one above the other in the vertical direction, in particular in the stated sequence.According to at least one embodiment of the method, the spacer layer is arranged on the second piezoelectric element. For example, the spacer layer is fastened mechanically stably on the second piezoelectric element. In particular, before the provision of the second transparent layer with the second ion trap chip in the second region, the spacer layer is arranged on the second piezoelectric element in the second region.According to at least one embodiment of the method, a further spacer layer is arranged on the first piezoelectric element. In particular, the spacer layer has a further predetermined thickness in the vertical direction. For example, the further spacer layer is fastened mechanically stably on the first piezoelectric element. In particular, before arranging the first transparent layer with the first ion trap chip on the second region, the further spacer layer is arranged on the first piezoelement in the first region.The further spacer layer is formed, for example, with the same material as the spacer layer. In particular, the features in connection with the spacer layer also apply in connection with the further spacer layer and vice versa. The further spacer layer and the spacer layer can be of different thicknesses in the vertical direction. With such a further spacer layer, the ion trap chips can advantageously be aligned particularly precisely in the vertical direction.According to at least one embodiment of the method, the holder has a through hole. The through hole extends completely through the holder in the vertical direction. The through hole advantageously provides an optical access for aligning the two ion trap chips in the vertical direction.According to at least one embodiment of the method, the first region is spaced apart from the second region in lateral directions by the through hole. The through hole extends in lateral directions along a length and a width, wherein the length is in particular greater than the width and the length runs perpendicular to the width.According to at least one embodiment of the method, cross sections in lateral directions of the through hole taper towards the first main surface. Advantageously, the electromagnetic radiation can be advantageously focused through the tapering through-hole.According to at least one embodiment of the method, a side surface of the first transparent layer facing the second transparent layer is inclined with respect to the first main surface. In particular, the first main surface facing the side surface of the first transparent layer facing the second transparent layer and the side surface of the first transparent layer facing the second transparent layer enclose an angle of at most 80° and at least 10°, e.g. about 45° or 60°.According to at least one embodiment of the method, a side surface of the second transparent layer facing the first transparent layer is inclined with respect to the first main surface. In particular, the first main surface facing the side surface of the second transparent layer facing the first transparent layer and the side surface of the second transparent layer facing the first transparent layer enclose an angle of at most 80° and at least 10°, e.g. about 45° or 60°. The angles of the side surfaces facing each other are, for example, of the same size.For example, the mutually facing side surfaces of the first transparent layer and the second transparent layer form a further through hole. In particular, cross sections in lateral directions of the further through hole taper in the direction of the first ion trap chip and of the second ion trap chip. For example, the distance in lateral directions of the mutually facing side surfaces of the first transparent layer and the second transparent layer is smaller than an extension in lateral directions of the through hole.According to at least one embodiment of the method, in plan view, the first piezoelectric element and / or the second piezoelectric element do not overlap with an opening of the through hole on the first main surface in lateral directions. The plan view is along the vertical direction to the first main surface. The through hole has, for example, the opening in the first main surface and another opening in the second main surface. Since the through hole tapers towards the first main surface, the opening is in particular larger than the further opening.For example, the first piezoelectric element and / or the second piezoelectric element extends in lateral directions at most up to an edge of the opening. In particular, a bottom surface of the first piezoelectric element is arranged over the full surface on the first region and / or a bottom surface of the second piezoelectric element is arranged over the full surface on the second region.According to at least one embodiment of the method, in plan view, the first transparent layer and the second transparent layer are partially overlapping in lateral directions with the opening of the through hole at the first main surface. For example, the first transparent layer and / or the second transparent layer protrudes beyond the edge of the opening in lateral directions up to at least 10%, at least 20% or at least 30% and / or at most 45%, at most 40% or at most 35% of the width of the opening. For example, the first transparent layer and / or the second transparent layer protrudes beyond the edge of the opening by at most 800 μm or at most 400 μm in lateral directions.For example, in a cross-sectional view along the width of the opening and in the vertical direction, a corner of the first transparent layer, which is located on the top surface of the first transparent layer, protrudes beyond the edge of the opening in the lateral direction. A further corner of the first transparent layer, which is located on the bottom surface of the first transparent layer, does not project beyond the edge of the opening in the lateral direction. For example, in a cross-sectional view along the width of the opening and in the vertical direction, a corner of the second transparent layer, which is located on the top surface of the second transparent layer, protrudes beyond the edge of the opening in the lateral direction. A further corner of the second transparent layer, which is located on the bottom surface of the second transparent layer, does not project beyond the edge of the opening in the lateral direction, for example. With such an overlap of the first transparent layer and / or the second transparent layer, the optical access is advantageously established.According to at least one embodiment of the method, the first ion trap chip and the second ion trap chip overlap with the opening of the through hole at the first main surface. For example, the first ion trap chip protrudes in lateral directions beyond the side surface of the first transparent layer that faces the side surface of the second transparent layer. The second ion trap chip protrudes, for example, in lateral directions beyond the side surface of the second transparent layer that faces the side surface of the first transparent layer. The overlap of the transparent layers and the overlap of the ion trap chip advantageously produce optical access and enable a mechanically stable attachment of the ion chips.According to at least one embodiment of the method, a first adhesive layer is formed on the first region, on which the first piezoelectric element is arranged. In particular, the first piezoelectric element is fastened mechanically stably to the first region by the first adhesive layer.According to at least one embodiment of the method, a second adhesive layer is formed on the first piezoelectric element, on which the further spacer layer is arranged. In particular, the further spacer layer is fastened mechanically stably to the first piezoelectric element by the second adhesive layer.According to at least one embodiment of the method, a third adhesive layer is arranged on the further spacer layer, on which the first transparent layer is arranged. In particular, the first transparent layer is fastened mechanically stably to the further spacer layer by the third adhesive layer.According to at least one embodiment of the method, a fourth adhesive layer is formed on the first transparent layer, on which the first ion trap chip is arranged. In particular, the first ion trap chip is mechanically stably attached to the first transparent layer by the fourth adhesive layer.According to at least one embodiment of the method, a fifth adhesive layer is formed on the second region, on which the second piezoelectric element is arranged. In particular, the second piezoelectric element is fastened mechanically stably to the second region by the fifth adhesive layer.According to at least one embodiment of the method, a sixth adhesive layer is formed on the second piezoelectric element, on which the spacer layer is arranged. In particular, the spacer layer is fastened mechanically stably to the second piezoelectric element by the sixth adhesive layer.According to at least one embodiment of the method, a seventh adhesive layer is arranged on the spacer layer, on which the second transparent layer is arranged. In particular, the second transparent layer is mechanically stably fastened to the spacer layer by the seventh adhesive layer.For example, the first adhesive layer, the second adhesive layer and / or the fifth adhesive layer, the sixth adhesive layer, are each formed from an epoxy, in particular a thermosetting epoxy.According to at least one embodiment of the method, an eighth adhesive layer is arranged on the second transparent layer, on which adhesive layer the second ion trap chip is arranged. In particular, the second ion trap chip is mechanically stably attached to the second transparent layer by the eighth adhesive layer.For example, the third adhesive layer and the fourth adhesive layer and / or the seventh adhesive layer and the eighth adhesive layer are each formed from an epoxy, in particular a UV-curing epoxy. The UV light used for curing can be supplied to the epoxy resin via side surfaces of the first transparent layer and / or the second transparent layer. Thus, a direct line of sight for the UV light is advantageously provided on the epoxy resin by the side surfaces. Furthermore, the through-hole and the further through-hole for the electromagnetic UV radiation are advantageously used for curing the fourth adhesive layer.It is advantageous that epoxy shrinkage is minimized by the particular sequence of at least some of the adhesive layers. In addition, a number of the adhesive layers can be minimized.Further, an arrangement will be described. The arrangement is produced in particular by the method described here. Therefore, all features and embodiments disclosed in connection with the method are also disclosed in connection with the arrangement and vice versa.The arrangement comprises a holder having a first main surface with a first region and a second region, a first transparent layer arranged on the first region, a first ion trap chip arranged on the first transparent layer, a spacer layer arranged on the second region, a second transparent layer arranged on the spacer layer and a second ion trap chip arranged on the second transparent layer. According to at least one embodiment of the arrangement, the main extension planes of the first ion trap chip and of the second ion trap chip extend in lateral directions in a common plane.According to at least one embodiment of the arrangement, the mutually facing side surfaces of the first transparent layer and the second transparent layer delimit the further through-hole, and cross sections in lateral directions of the further through-hole widen in the direction of the holder.The method and the ion trap are explained in more detail below with reference to exemplary embodiments and the associated figures.FIGS. 1 to 9 show the method steps of the method according to one exemplary embodiment. FIG. 10 shows an arrangement according to an exemplary embodiment.Elements that are identical or similar or have the same effect are provided with the same reference numerals in the figures. The figures and the proportions of the elements shown in the figures are not to be considered true to scale. Rather, for improved clarity and / or for improved understanding, individual elements may be represented with an exaggerated size.In the process stage according to the exemplary embodiment of FIG. 1, a holder 2 is provided. The holder 2 has a first main surface 5 with a first region 3 and a second region 4 and a second main surface 6 opposite the first main surface 5. The first main surface 5 and the second main surface 6 both extend in lateral directions. The holder 2 has a through hole 7 which tapers in the direction of the first main surface 5. The through hole 7 comprises an opening 8 in the first main surface 5 and a further opening 9 in the second main surface 6.Subsequently, in the method step according to FIG. 2, a first piezoelectric element 10 is arranged on the first region 3 by a first adhesive layer 14 and a second piezoelectric element 11 is arranged on the second region 4 by a fifth adhesive layer 18. A further spacer layer 13 is arranged on the first piezoelectric element 10 by a second adhesive layer 15. In a plan view of the first main surface 5 in the vertical direction perpendicular to the lateral directions, the first piezoelement 10 and the further spacer layer 13 do not overlap with the opening 8.In a next method step according to FIG. 3, a first transparent layer 22 is arranged on the further spacer layer 13 by a third adhesive layer 16. The first transparent layer 22 has a side surface 24 facing the second region 4 which is inclined with respect to the first main surface 5. The side surface 24 of the first transparent layer 22 facing the second region 4 partially overlaps with the opening 8 in plan view. the side surface 24 of the first transparent layer 22 facing the second region 4 is at most 300 μm apart, e.g. about 200 μm apart from a central position of the through hole 7, as indicated by the dashed line, as indicated by the two arrows. Since the side surface 24 is inclined, the first transparent layer 22 tapers towards the first main surface 5.Subsequently, in the process stage according to FIG. 4, a first ion trap chip 25 is arranged on the further spacer layer 13 by a fourth adhesive layer 17. The first ion trap chip 25 partially overlaps with the opening 8 in plan view. the first ion trap chip 25 protrudes in lateral directions beyond the side surface 24 of the first transparent layer 22 facing the second region 4. The first ion trap chip 25 is arranged in lateral directions up to the central position of the through hole 7 at most.In a next step of the process of Fig. 5, the holder 2 is rotated about the central position to prepare for the insertion of a second ion trap chip 26.In the process stage according to FIG. 6, the second ion trap chip 26 is arranged on a second transparent layer 23 by an eighth adhesive layer 21. The second transparent layer 23 is shaped like the first transparent layer 22.Subsequently, in the method step according to FIG. 7, the second transparent layer 23 with the second ion trap chip 26 is positioned in the second region 4, wherein the second transparent layer 23 faces the holder 2 and the second ion trap chip 26 faces away from the holder 2. The second transparent layer 23 has a side surface 24 facing the first region 3, which, like the first transparent layer 22, is inclined with respect to the first main surface 5. The second transparent layer 23 with the second ion trap chip 26 corresponds in shape and position to the first transparent layer 22 with the first ion trap chip 25, mirrored on the central position line shown in FIG. 3.The holder 2 is placed upside down and the first ion chip and the second ion chip are aligned in the vertical direction such that the main extension planes of the first ion chip and the second ion chip extend in a common plane 27 extending in the lateral direction. A distance δ between the second transparent layer 23 and the second piezoelectric element 11 is determined by the alignment.In the process stage according to FIG. 8, a spacer layer 12 having a predefined thickness Δ is provided in the vertical direction as a function of the alignment, in particular as a function of the distance δ. In particular, the predefined thickness Δ is smaller than the distance δ for compensating further adhesive layers, e.g. a sixth adhesive layer 19 and a seventh adhesive layer 20.The spacer layer 12 is arranged on the second piezoelectric element 11 by the sixth adhesive layer 19. Specifically, the sixth adhesive layer 19 is applied to the second piezoelectric element 11 while being in the inverted configuration so that a gravitational force acts in a direction away from the first main surface 5 of the holder 2.Subsequently, in the process step according to FIG. 9, the second transparent layer 23 is arranged on the spacer layer 12 by a seventh adhesive layer 20, in particular in the reversed configuration.The arrangement 1 according to the exemplary embodiment of FIG. 10 is produced in particular by the method steps according to FIGS. 1 to 9. The mutually facing side surfaces 24 of the first transparent layer 22 and of the second transparent layer 23 delimit a further through-hole 28.Reference numerals denote reference numerals1 Arrangement 2 Holder 3 First region 4 Second region 5 First main surface 6 Second main surface 7 Through hole 8 Opening 9 Further opening 10 First piezoelement 11 Second piezoelement 12 Spacer layer 13 Further spacer layer 14 First adhesive layer 15 Second adhesive layer 16 Third adhesive layer 17 Fourth adhesive layer 18 Fifth adhesive layer 19 Sixth adhesive layer 20 Seventh adhesive layer 21 Eighth adhesive layer 22 First transparent layer 23 Second transparent layer 24 Side surface 25 First ion trap chip 26 Second ion trap chip 27 Common plane 28 Further through hole

Claims

Method for producing an arrangement (1) of at least two ion trap chips comprising a first ion trap chip (25) and a second ion trap chip (26), comprising - providing a holder (2) having a first main surface (5) with a first region (3) and a second region (4), - arranging a first transparent layer (22), on which the first ion trap chip (25) is arranged, on the first region (3), - providing a second transparent layer (23), on which the second ion trap chip (26) is arranged, in the second region (4), - aligning the first ion trap chip (25) and the second ion trap chip (26) in the vertical direction, such that the main extension planes of the first ion trap chip (25) and the second ion trap chip (26) extend within a common plane (27) extending in lateral directions, providing a spacer layer (12) having a predetermined thickness in the vertical direction depending on the alignment, arranging the spacer layer (12) on the second region (4), arranging the second transparent layer (23) on the spacer layer (12) such that the main extension planes of the first ion trap chip (25) and the second ion trap chip (26) extend within the common plane (27).Method according to Claim 1, wherein - during the alignment a distance between the second transparent layer (23) and the holder (2) in the vertical direction is determined.Method according to either of Claims 1 and 2, wherein - a first piezoelement (10) is arranged on the holder (2) in the first region (3), and / or - a second piezoelement (11) is arranged on the holder (2) in the second region (4).Method according to Claim 3, wherein - the first transparent layer (22) is arranged on the first piezoelectric element (10), and / or - the spacer layer (12) is arranged on the second piezoelectric element (11).Method according to either of Claims 2 and 3, wherein - a further spacer layer (13) is arranged on the first piezoelectric element (10).Method according to one of claims 1 to 5, wherein - the holder (2) has a through hole (7), and - the first region (3) is spaced apart from the second region (4) in lateral directions by the through hole (7).Method according to claim 6, wherein - cross sections in lateral directions of the through hole (7) taper towards the first main surface (5).Method according to either of Claims 6 and 7, wherein - a side face (24) of the first transparent layer (22) facing the second transparent layer (23) is inclined with respect to the first main face (5), and - a side face (24) of the second transparent layer (23) facing the first transparent layer (22) is inclined with respect to the first main face (5).Method according to any one of claims 3 and 7 to 8, wherein - in plan view, the first piezo element (10) and / or the second piezo element (11) do not overlap in lateral directions with an opening (8) of the through hole (7) on the first main surface (5), and - in plan view, the first transparent layer (22) and the second transparent layer (23) partially overlap in lateral directions with the opening (8) of the through hole (7) on the first main surface (5).The method according to claim 9, wherein - the first ion trap chip (25) and the second ion trap chip (26) overlap with the opening (8) of the through hole (7) at the first main surface (5).Method according to one of Claims 3 to 10, wherein - a first adhesive layer (14) is formed on the first region (3), on which the first piezoelectric element (10) is arranged, - a second adhesive layer (15) is formed on the first piezoelectric element (10), on which the further spacer layer (13) is arranged, - a third adhesive layer (16) is arranged on the further spacer layer (13), on which third adhesive layer the first transparent layer (22) is arranged, and / or - a fourth adhesive layer (17) is formed on the first transparent layer (22), on which fourth adhesive layer the first ion trap chip (25) is arranged.Method according to one of Claims 3 to 11, wherein - a fifth adhesive layer (18) on which the second piezoelement (11) is arranged is formed on the second region (4), - a sixth adhesive layer (19) on which the spacer layer (12) is arranged is formed on the second piezoelement (11), - a seventh adhesive layer (20) on which the second transparent layer (23) is arranged is arranged on the spacer layer (12), and / or - an eighth adhesive layer (21) is arranged on the second transparent layer (23) on which the second ion trap chip (26) is arranged.Arrangement (1) of at least two ion trap chips, comprising - a holder (2) having a first main surface (5) with a first region (3) and a second region (4), - a first transparent layer (22) arranged on the first region (3), - a first ion trap chip (25) arranged on the first transparent layer (22), - a spacer layer (12) arranged on the second region (4), - a second transparent layer (23) arranged on the spacer layer (12), and - a second ion trap chip (26) arranged on the second transparent layer (23), wherein - main extension planes of the first ion trap chip (25) and the second ion trap chip (26) extend within a common plane (27) in lateral directions.Arrangement (1) according to claim 13, wherein - the side surfaces (24) of the first transparent layer (22) and the second transparent layer (23) facing each other delimit a further through hole (28), and - cross sections in the lateral directions of the further through hole (28) widen towards the holder (2).

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