Semiconductor device with gate structure and current distribution area and associated manufacturing process

Abstract

Method for manufacturing a semiconductor device, comprising: Performing one or more first implantation processes to form an implanted area (116, 130, 146) of a first conductivity type in a semiconductor body (102); Forming a trench (170) in the semiconductor body (102); Performing, after forming the trench (170), a second implantation process to form a current propagation region of a second conductivity type in the semiconductor body (102), wherein the second implantation process has: Implanting the first dopants through an upper surface of the semiconductor body to form a first region (180A, 182A) of the current propagation domain; and Implanting a second dopant through a bottom of the trench (170) to form a second area (180B, 182B) of the stream propagation area; and Forming a gate structure (101) in the trench (170), wherein a vertical position of the first area (180A, 182A) of the current propagation area corresponds to a vertical position of the gate structure (101) and the second area (180B, 182B) of the current propagation area lies below the gate structure (101).

Description

TECHNICAL AREA

[0001] The present disclosure relates to semiconductor elements or devices. BACKGROUND

[0002] A semiconductor device can be used in mobile phones, laptops, desktops, tablets, watches, gaming systems, industrial electronics, commercial electronics, and / or consumer electronics. A semiconductor device may have an electrical contact between a semiconductor and a metal, which can be used to connect a component within the semiconductor device to an external circuit arrangement. An example of a semiconductor device is known from publication CN 1 14 038 908 A. SUMMARY

[0003] This summary is provided to introduce a selection of concepts in simplified form, which are further described in detail below.

[0004] The invention is defined in the independent claims. Further embodiments are defined in the dependent claims. In one embodiment, a method for fabricating a semiconductor device is provided. One or more first implantation processes can be performed to form an implanted region of a first conductivity type in a semiconductor body. A trench can be formed in the semiconductor body. After forming the trench, a second implantation process can be performed to form a current-propagation region of a second conductivity type in the semiconductor body. The second implantation process can comprise implanting first dopants through an upper surface of the semiconductor body to form a first region of the current-propagation region, and implanting second dopants through a bottom of the trench to form a second region of the current-propagation region.A gate structure can form in the trench. A vertical position of the first region of the current propagation area corresponds to a vertical position of the gate structure. The second region of the current propagation area lies below the gate structure.

[0005] In one embodiment, a method for fabricating a semiconductor device is provided. One or more first implantation processes are performed to form an implanted region of a first conductivity type in a semiconductor body. A second implantation process is then performed. This second implantation process comprises implanting first dopants of a second conductivity type through an upper surface of the semiconductor body to form a first region of a current propagation region. After performing the second implantation process, a trench can be formed in the semiconductor body. After forming the trench, a third implantation process can be performed. This third implantation process comprises implanting second dopants of a second conductivity type through the bottom of the trench to form a second region of the current propagation region. A gate structure is formed in the trench.A vertical position of the first region of the current propagation domain corresponds to a vertical position of the gate structure. The second region of the current propagation domain lies below the gate structure.

[0006] In one embodiment, a semiconductor device is provided. The semiconductor device may have a semiconductor body comprising a body region of a first conductivity type, a current-propagation region of a second conductivity type, and an implanted region of the first conductivity type. The semiconductor device may have a trench-gate structure within the semiconductor body, comprising a gate electrode and a gate dielectric layer that separates the gate electrode from the semiconductor body. The implanted region and the current-propagation region form a pn junction. A vertical position of a first region of the current-propagation region corresponds to a vertical position of the trench-gate structure, and the first region of the current-propagation region borders a first side wall of the trench-gate structure. A second region of the current-propagation region lies beneath the trench-gate structure.The difference between a first vertical distance and a second vertical distance is at most 200 nanometers. The first vertical distance corresponds to the distance between a vertical position of the top surface of the first region of the current propagation domain and a vertical position of the top surface of the semiconductor body. The second vertical distance corresponds to the distance between a vertical position of the top surface of the second region of the current propagation domain and a vertical position of the bottom surface of the trench-gate structure.

[0007] To achieve the preceding and related objectives, the following description and accompanying drawings present certain illustrative aspects and implementations. These indicate only some of the various ways in which one or more aspects may be used. Further aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. DESCRIPTION OF THE DRAWINGS Fig. Figure 1A schematically illustrates processes for manufacturing a semiconductor device according to various examples. Fig. Figure 1B schematically illustrates a process for manufacturing a semiconductor device according to various examples. Fig. 1C illustrates a semiconductor device according to various examples. Fig. Figure 1D schematically illustrates a process for manufacturing a semiconductor device according to various examples. Fig. Figure 1E schematically illustrates processes for manufacturing a semiconductor device according to various examples. Fig. Figure 1F schematically illustrates processes for manufacturing a semiconductor device according to various examples. Fig. Figure 1G schematically illustrates processes for manufacturing a semiconductor device according to various examples. Fig. Figure 1H schematically illustrates processes for manufacturing a semiconductor device according to various examples. Fig. Figure 2 illustrates a semiconductor device according to various examples. Fig. Figure 3A illustrates a semiconductor device according to various examples. Fig. Figure 3B illustrates a semiconductor device according to various examples. Fig. Figure 4 illustrates an exemplary procedure according to the techniques presented herein. Fig. Figure 5 is an illustration of an exemplary procedure according to the techniques presented herein. DETAILED DESCRIPTION

[0008] The claimed subject matter is now described with reference to the drawings, using the same reference numerals throughout to refer to the same elements. For explanatory purposes, numerous specific details are set forth in the following description to enable a comprehensive understanding of the claimed subject matter. However, it should be obvious that the claimed subject matter can be implemented in practice without these specific details. In other cases, well-known structures and devices are presented in the form of a block diagram to facilitate the description of the claimed subject matter.

[0009] The drawings are to be regarded as schematic representations, and the elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are depicted in such a way that their function and general purpose become apparent.

[0010] All numerical values ​​within the detailed description and claims herein are modified by “about” or “approximately” the stated value and take into account experimental errors and deviations that a person skilled in the art would expect.

[0011] The terms "above" and / or "overlying" should not be understood to mean only "directly above" and / or "in direct contact with". Rather, if an element is "above" another element and / or "lies" above such an element (e.g., a region lies above another region), another element (e.g., another region) may be positioned between the two elements (e.g., another region may be positioned between a first region and a second region if the first region is "above" the second region and / or "lies" above it). If a first element is "above" a second element and / or "lies" above it, at least some part of the first element may coincide vertically with the second element such that a vertical line can intersect the first and second elements.

[0012] The semiconductor substrate or semiconductor body may extend along a principal extension plane. The term "horizontal," as used in this description, is intended to describe an orientation substantially parallel to the principal extension plane. A first or principal horizontal side of the semiconductor substrate or semiconductor body may be substantially parallel to horizontal directions or may have surface sections that form an angle of at most 8 degrees (or at most 6 degrees) with the principal extension plane. The first or principal horizontal side may, for example, be the surface of a wafer or a die. Sometimes the horizontal direction is also referred to as the lateral direction.

[0013] The term “vertical”, as used in this description, is intended to describe an orientation that is essentially perpendicular to the horizontal direction (parallel to the direction of the normal of the first side of the semiconductor substrate or semiconductor body, or parallel to the direction of the normal of a surface section of the first side of the semiconductor substrate or body).

[0014] A semiconductor device, such as a transistor, can have one or more doped regions and a gate structure, such as a trench-gate structure. In some embodiments, the gate structure is formed by creating a trench in a semiconductor body and forming the trench structure within the trench. The one or more doped regions can have one or more first regions of a first conductivity type (e.g., a p-type) and / or a current-propagation region of a second conductivity type (e.g., an n-type). In some embodiments, a vertical position of a first region of the current-propagation region corresponds to a vertical position of the gate structure (e.g., a vertical position of at least some part of the first region of the current-propagation region corresponds to a vertical position of at least some part of the gate structure).A second region of the current propagation domain lies beneath the gate structure. The positions of the first and / or second region of the current propagation domain relative to the gate structure can improve the electrical performance of the semiconductor device, such as its on-resistance (RonxA). In some systems, an implantation process to form the current propagation domain within the semiconductor body is performed prior to trench formation. Therefore, a high implantation energy level may be required to implant dopants (of the second conductivity type) to a desired depth (e.g., beneath the subsequently formed gate structure) within the semiconductor body.

[0015] According to the present disclosure, a semiconductor device and a method for fabricating the semiconductor device are provided. In some embodiments, the semiconductor device may include a transistor such as a field-effect transistor (FET), a metal-oxide-semiconductor FET (MOSFET), an insulated-gate bipolar transistor (IGBT), and / or another type of transistor. In one example, the transistor is a MOSFET (e.g., a vertical MOSFET). The semiconductor device may include a current-propagation region and / or a gate structure such as a trench-gate structure. In some examples, a trench may be formed in a semiconductor body, and the gate structure may be formed within the trench.In some examples, an implantation process can be carried out after the formation of the trench and before the formation of the gate structure in order to form at least a certain part of the current propagation domain, such as at least a region of the current propagation domain that lies beneath the subsequently formed gate structure (e.g., dopants of the second conductivity type can be implanted through the bottom of the trench). In one example, the implantation process can be a surface implantation (i.e.,: blanket implantation) (which extends, for example, horizontally over at least one region of the semiconductor body), in which first dopants of the second conductivity type are implanted through the upper surface of the semiconductor body to form a first region of the current propagation region which has a vertical position corresponding to a vertical position of the subsequently formed gate structure, and second dopants of the second conductivity type are implanted through the bottom of the trench to form a second region of the current propagation region which lies below the subsequently formed gate structure.Accordingly, by performing the implantation process after trench formation and before gate structure formation, the current propagation area can be automatically aligned with the subsequently formed gate structure such that a vertical position of the first area corresponds to a vertical position of the gate structure, and that the second area lies beneath the gate structure. Alternatively and / or additionally, since the second area is formed by implanting dopants through the bottom of the trench, the implantation energy level required to implant dopants to a desired depth beneath the subsequently formed gate structure is reduced.The reduced implantation energy level of the implantation process can result in: (i) reduced power consumption for forming the current spread region; (ii) increased ion flux and / or reduced implantation time; and / or (iii) the ability to use a greater variety of dopants implanting tools to perform the implantation process to form the current spread region (e.g., because the implantation energy level is lower, more dopants implanting tools are available that can perform an implantation shot at the implantation energy level), thereby improving tool redundancy.

[0016] In one embodiment of the presently disclosed embodiments, a method for fabricating a semiconductor device is provided. The method may include performing one or more first implantation processes to form an implanted region of a first conductivity type in a semiconductor body. In some examples, the first conductivity type is a p-type. The implanted region may correspond to a shielding region, such as a region configured to provide shielding for a gate structure of the semiconductor device. In some examples, the implanted region (e.g., the shielding region) may include a bury region (e.g., a p-bury region) and / or a p-top region. In some examples, the semiconductor body has a semiconductor substrate, such as a silicon carbide (SiC) substrate.The semiconductor body can have one or more epitaxial layers located above the semiconductor substrate. These epitaxial layers can include an epitaxial SiC layer. The epitaxial layers can be grown on the semiconductor substrate.

[0017] The process can involve forming a trench in the semiconductor body. An etching process can be performed to form the trench. In some examples, a structured mask is formed over the top surface of the semiconductor body. The trench can be formed by utilizing the structured mask.

[0018] The method may include performing a second implantation process to form a current propagation region of a second conductivity type within the semiconductor body. In some examples, the second conductivity type is an n-type. Although examples are provided herein where the first conductivity type is the p-type and the second conductivity type is the n-type, embodiments are conceivable where the first conductivity type is the n-type and the second conductivity type is the p-type.

[0019] The second implantation process can be performed after the trench has been formed. This process may involve implanting first dopants through an upper surface of the semiconductor body to form a first region of the current propagation domain, and implanting second dopants through the bottom of the trench to form a second region. In some examples, the first and second dopants are implanted simultaneously, such as through a surface-wide implantation during the second implantation process.

[0020] In some examples, the structured mask (used to form the trench) is removed before the second implantation process.

[0021] The method can involve forming a gate structure in the trench. A vertical position of the first region of the stream propagation area corresponds to a vertical position of the gate structure (e.g., a vertical position of at least a certain part of the first region of the stream propagation area corresponds to a vertical position of at least a certain part of the gate structure). The second region of the stream propagation area lies below the gate structure.

[0022] In some examples, the formation of the gate structure involves forming a gate dielectric layer in the trench and / or forming a gate electrode in the trench. The gate dielectric layer can separate the gate electrode from the semiconductor body.

[0023] In some examples, the first region of the current propagation domain borders a first sidewall of the gate structure. The implanted region of the first conductivity type may border a second sidewall of the gate structure, which is opposite to the first sidewall of the gate structure.

[0024] In some examples, the maximum implantation energy level of the second implantation process may be at most 2000 kiloelectronvolts (keV). In some embodiments or implementations where the current propagation domain is formed via an implantation process performed before the trench is formed, the required maximum implantation energy level of the implantation process may exceed the maximum implantation energy level of the second implantation process (e.g., the required maximum implantation energy level of the implantation process may be more than 2000 keV, such as up to 4000 keV) in order to implant dopants deep enough to achieve a desired depth below the subsequently formed gate structure.

[0025] In some examples, the difference between a first vertical distance and a second vertical distance is at most 200 nanometers, such as at most 100 nanometers, at most 50 nanometers, and / or at most 10 nanometers (and / or the first vertical distance may be approximately equal to the second vertical distance). The first vertical distance corresponds to a distance between a vertical position of the top surface of the semiconductor body (through which dopants are implanted in the second implantation process to form the first region of the current propagation domain) and a vertical position of a top surface of the first region of the current propagation domain. The second vertical distance corresponds to a distance between a vertical position of a bottom surface of the gate structure and a vertical position of a top surface of the second region of the current propagation domain.

[0026] The method may involve performing a third implantation process to form a first-type conductivity body region within the semiconductor body. At least one region of the body region lies above the first current-propagation region and / or borders the first sidewall of the gate structure. In some examples, the body region defines a channel within the semiconductor device, such as a channel between a source region (which, for example, lies above the body region) and the current-propagation region.

[0027] In some examples, the implanted area of ​​the first conductivity type (e.g., the shielding area) and the current propagation area form a pn junction.

[0028] In some examples, one or more parameters (e.g., a number of implantation shots, an implantation energy level, and / or an ion implantation dose) associated with the top of the first region of the current propagation area adjacent to the body region are selected, and the second implantation process is performed using one or more of these parameters. For example, the one or more parameters (of the second implantation process) can be selected such that the top of the first region of the current propagation area is adjacent to the body region.

[0029] In some examples, one or more parameters (e.g., a number of implantation shots, an implantation energy level, and / or an ion implantation dose) are selected that are associated with a vertical position of the underside of the first region of the current propagation domain that is lower than or equal to the vertical position of the topside of the second region of the current propagation domain. The second implantation process is then performed using this one or more parameters. For example, the one or more parameters (of the second implantation process) can be selected such that the vertical position of the underside of the first region of the current propagation domain is lower than or equal to the vertical position of the topside of the second region of the current propagation domain.

[0030] In some examples, one or more parameters (e.g., a number of implantation shots, an implantation energy level, and / or an ion implantation dose) associated with forming the first area of ​​the current propagation domain are selected such that it extends from a vertical position higher than a vertical position of the trench floor to a second vertical position that is the same as or lower than the vertical position of the trench floor, with the second implantation process being carried out using the one or more parameters.For example, one or more parameters (of the second implantation process) can be selected such that the first area of ​​the current propagation region extends from the first vertical position, which is higher than the vertical position of the bottom of the trench, to the second vertical position, which is the same as or lower than the vertical position of the bottom of the trench.

[0031] In some examples, the third implantation process is performed after the trench has formed. In one example, the third implantation process might involve implanting third-type dopants through the top surface of the semiconductor body to form the body region and implanting fourth-type dopants through the bottom of the trench to form a first-type conductivity region. In some examples, the third- and fourth-type dopants might be implanted simultaneously, as in a full-surface implantation of the third implantation process. In some examples, the first-type conductivity region might correspond to a portion of the shielding region. In some examples, the body region lies above the first region of the current propagation region. In some examples, the first-type conductivity region lies above the second region of the current propagation region (e.g.,The area of ​​the first conductivity type can lie between the second area of ​​the current propagation region and the gate structure).

[0032] In some examples, the third implantation process is performed before the trench is formed.

[0033] In some examples, the first region of the current propagation region is formed via an implantation process performed before the trench is formed (e.g., the implantation process may involve implanting dopants through the top surface of the semiconductor body to form the first region of the current propagation region, which has a vertical position corresponding to a vertical position of the subsequently formed gate structure), and the second region of the current propagation region is formed via an implantation process performed after the trench is formed (e.g., the implantation process may involve implanting dopants through the bottom of the trench to form the second region of the current propagation region, which lies below the subsequently formed gate structure).

[0034] In one embodiment of the presently disclosed embodiments, a semiconductor device is provided. The semiconductor device can have a semiconductor body comprising a body region of the first conductivity type, a current-propagation region of the second conductivity type, and an implanted region (e.g., a shielding region) of the first conductivity type. The semiconductor device can have a trench-gate structure in the semiconductor body, comprising a gate structure and a gate dielectric layer that separates the gate electrode from the semiconductor body. The implanted region and the current-propagation region form a pn junction. A vertical position of a first region of the current-propagation region corresponds to a vertical position of the trench-gate structure, and the first region of the current-propagation region borders a first side wall of the trench-gate structure.A second region of the current propagation domain lies beneath the trench-gate structure. The difference between a first vertical distance and a second vertical distance is at most 200 nanometers, such as at most 100 nanometers, at most 50 nanometers, and / or at most 10 nanometers (and / or the first vertical distance may be approximately equal to the second vertical distance). The first vertical distance corresponds to the distance between a vertical position of a top surface of the first region of the current propagation domain and a vertical position of a top surface of the semiconductor body. The second vertical distance corresponds to the distance between a vertical position of a top surface of the second region of the current propagation domain and a vertical position of a bottom surface of the trench-gate structure.

[0035] In some examples, the semiconductor body has a semiconductor substrate, such as a SiC substrate. The semiconductor body may have one or more epitaxial layers located above the semiconductor substrate. The one or more epitaxial layers may include an epitaxial SiC layer. The one or more epitaxial layers may be grown on the semiconductor substrate.

[0036] In some examples, the implanted area borders the second side wall of the trench-gate structure, opposite the first side wall of the trench-gate structure.

[0037] In some examples, the upper surface of the first region of the stream propagation area borders the body region.

[0038] Fig. Figures 1A-1G illustrate aspects relating to the fabrication of a semiconductor device according to various examples in the present disclosure. In 1001 (illustrated in Fig. 1A) A semiconductor body 102 is provided. The semiconductor body 102 may comprise crystalline semiconductor material. The semiconductor body 102 may comprise a semiconductor element (e.g., silicon, germanium, and / or another semiconductor element) and / or a semiconductor compound (e.g., SiC, silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), and / or another semiconductor compound). In some examples, the semiconductor body 102 may contain defects or impurities (e.g., hydrogen, fluorine, oxygen, and / or other impurities).

[0039] In some examples, the semiconductor body 102 has a semiconductor substrate, such as a SiC substrate. The semiconductor body 102 may have one or more epitaxial layers located above the semiconductor substrate. The one or more epitaxial layers may include an epitaxial SiC layer. In some examples, one epitaxial layer (e.g., the epitaxial SiC layer) of the one or more epitaxial layers is grown onto the semiconductor substrate. In some examples, the semiconductor device has a buffer layer between the semiconductor substrate and the one or more epitaxial layers. In some examples, the one or more epitaxial layers have multiple epitaxial layers (e.g., to form a superjunction of the semiconductor device). In some examples, the semiconductor body 102 (e.g.,The semiconductor substrate, one or more epitaxial layers, and / or the buffer layer) contains dopants (e.g., nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), gallium (Ga), and / or other dopants). Semiconductor body 102, for example, contains n-type dopants such as nitrogen dopants (and / or other n-type dopants).

[0040] In 1002 (illustrated in Fig. 1A) A structured mask layer 106 and / or a first screen layer 108 are formed over the semiconductor body 102. The first structured mask layer 106 can comprise an oxide material (e.g., silicon dioxide (SiO2)) and / or one or more other materials. The first screen layer 108 (e.g., scattering oxide layer) can comprise an oxide material (e.g., SiO2) and / or one or more other materials. The material composition of the first structured mask layer 106 can be the same as that of the first screen layer 108 or different from it.

[0041] In some examples, a first mask layer (not shown), such as a hard mask, can be formed over the semiconductor body 102. The first mask layer can be built up (e.g., structured) to form the first structured mask layer 106 such that it has openings exposing areas of an upper surface of the semiconductor body 102. The first screen layer 108 can be formed (for example, after building up the first mask layer to form the first structured mask layer 106) over the exposed areas of the upper surface of the semiconductor body 102 and / or the first structured mask layer 106, so that the exposed areas of the upper surface of the semiconductor body 102 are covered by the first screen layer 108 (e.g.,The exposed areas of the upper surface of the semiconductor body 102 can correspond to areas of the upper surface of the semiconductor body 102 that are laterally offset from areas of the first structured mask layer 106 (which are not removed by the structure of the first mask layer 106). Areas 109A of the upper surface of the semiconductor body 102 lie beneath areas of the first structured mask layer 106 (and / or are covered by them). Areas 109B of the upper surface of the semiconductor body 102 that are not covered by the first structured mask layer 106 can lie beneath at least the first screen layer 108 (and / or can be covered by it).

[0042] In some examples, the first structured mask layer 106 has a thickness 112 in the range of at least 1 micrometer to at most 10 micrometers, in the range of at least 2 micrometers to at most 4 micrometers, and / or in the range of at least 2.5 micrometers to at most 3.5 micrometers. In some examples, the first screen layer 108 has a thickness 110 in the range of 10 nanometers to at most 500 nanometers and / or in the range of at least 25 nanometers to at most 75 nanometers.

[0043] In 1003 (illustrated in Fig. 1B) A first implantation process is performed to form one or more burial areas 116 of a first conductivity type in the semiconductor body 102 (e.g., the one or more burial areas may comprise a first burial area 116A, a second burial area 116B, etc.). The first implantation process (e.g., an ion implantation process) may involve the implantation of dopants of the first conductivity type through one or more regions of the upper surface of the semiconductor body 102 that are laterally offset from regions of the first structured mask layer 106.By performing the first implantation process, for example, dopants can be implanted into the semiconductor body 102 through the first screen layer 108 and the areas 109B of the upper surface of the semiconductor body 102 that are not covered by the first structured mask layer 106, in order to form the one or more burial sites 116. In one example, the first conductivity type is a p-type (e.g., the one or more burial sites 116 can be one or more p-type burial sites) and the dopants implanted via the first implantation process include p-type dopants such as aluminum dopants, boron dopants, gallium dopants, beryllium dopants, and / or other p-type dopants.In some examples, when dopants are implanted via the first implantation process, the first screen layer 108 can scatter ion beams from the first implantation process, attenuate and / or prevent channeling of the implanted dopants (so that, for example, dopants do not penetrate deeper than a desired depth into the semiconductor body 102) and / or attenuate and / or prevent damage to the upper surface of the semiconductor body 102 (e.g., the first screen layer 108 can attenuate and / or prevent damage that could otherwise be caused by ion beams from the first implantation process without the first screen layer 108).

[0044] In one example, the first implantation process may comprise one or more implantation shots, in which ions, such as high-energy ions, are injected through the first screen layer 108 into the semiconductor body 102. In some examples, the one or more implantation shots comprise only a single ion implantation shot (e.g., the one or more burial areas 116 may be formed by performing only the single implantation shot). In some examples, the depth and / or concentration of dopants (of the first conductivity type) of the one or more burial areas 116 depends on one or more parameters of the one or more implantation shots, such as an implantation energy level of the one or more implantation shots, an ion implantation dose of the one or more implantation shots, and / or another parameter.In some examples, the ion implantation level of one or more implantation shots can be in the range of at least 100 kiloelectron volts (keV) to a maximum of 6000 keV and / or in the range of at least 1000 keV to a maximum of 2500 keV. In some examples, the implantation dose of the implantation shot can be in the range of at least 0.5 × 10⁻⁶. 14 centimeter -2 (cm -2 ) up to a maximum of 3.50×10 14 cm -2 lay.

[0045] In some examples, after performing the first implantation process to form the one or more burial areas 116, the first structured mask layer 106 and / or the first screen layer 108 can be removed. The first structured mask layer 106 and / or the first screen layer 108 can be removed by applying an etching process such as a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, and / or another suitable etching process. In one example, the etching process utilizes hydrogen chloride (HCl) (e.g., hydrochloric acid), hydrogen fluoride (HF) (e.g., hydrofluoric acid), and / or one or more other chemicals.

[0046] In 1004 (illustrated in Fig. 1B) A first structured photoresist 120 and / or a second screen layer 122 is formed over the semiconductor body 102. The second screen layer 122 (e.g., scattering oxide layer) can comprise an oxide material (e.g., SiO2) and / or one or more other materials. In some examples, the second screen layer 122 is formed over the semiconductor body 102, and the first structured photoresist 120 can be formed over the second screen layer 122.

[0047] In some examples, a first photoresist (not shown) can be formed over the semiconductor body 102 (e.g., over the second screen layer 122). The first photoresist can be built up (e.g., structured) to form the first structured photoresist 120 such that it has openings exposing areas of the upper surface of the semiconductor body 102. In some examples, the first photoresist is a photosensitive material, in which properties such as the solubility of the first photoresist are influenced by light. The first photoresist is either a negative photoresist or a positive photoresist.In an example where the first photoresist is a negative photoresist, areas of the first photoresist become insoluble when illuminated by a light source. Therefore, the application of a solvent to the first photoresist during a subsequent development stage removes unexposed areas of the first photoresist to form the first structured photoresist 120. Accordingly, the first structured photoresist 120 formed from the first photoresist (e.g., the negative photoresist) can correspond to a negative image of a pattern or structure defined by opaque areas of a stencil, such as a mask, between the light source and the first photoresist. In an example where the first photoresist is a positive photoresist, illuminated areas of the first photoresist become soluble and are removed by the application of a solvent during development. Thus, the first structured photoresist 120 formed from the first photoresist (e.g.,The first structured photoresist formed by the positive photoresist 120 corresponds to a positive image of opaque areas of the stencil, such as a mask between the light source and the first photoresist.

[0048] One or more regions 117A of the upper surface of the semiconductor body 102 lie beneath (and / or are covered by) one or more regions of the first structured photoresist 120. In some examples, the one or more regions 117A may have boundary regions (e.g., edge regions) of the upper surface of the semiconductor body 102. One or more regions 117B of the upper surface of the semiconductor body 102 that are not covered by the first structured photoresist 120 may lie beneath (and / or be covered by) at least the second screen layer 122. In some examples, the one or more regions 117B may have a central region of the upper surface of the semiconductor body 102 between boundary regions (e.g., edge regions) of the upper surface of the semiconductor body 102.

[0049] In some examples, the second screen layer 122 has a thickness 126 in the range of at least 10 nanometers to at most 500 nanometers and / or in the range of at least 25 nanometers to at most 75 nanometers.

[0050] In 1005 (illustrated in Fig. 1C) A second implantation process is performed to form a body region 130 (e.g., a channel region) of the first conductivity type in the semiconductor body 102. The second implantation process (e.g., an ion implantation process) may involve the implantation of dopants of the first conductivity type through one or more regions of the upper surface of the semiconductor body 102 that are laterally offset from the first structured photoresist 120. In one example, the second implantation process involves an area-wide implantation extending horizontally over at least one region of the semiconductor body 102.By performing the second implantation process, for example, dopants can be implanted into the semiconductor body 102 through the second screen layer 122 and the one or more areas 117B of the upper surface of the semiconductor body 102 that are not covered by the first structured photoresist 120, in order to form the body region 130. In one example, the body region 130 can be a p-body region and the dopants implanted via the second implantation process include p-type dopants such as aluminum dopants, boron dopants, gallium dopants, beryllium dopants, and / or other p-type dopants.In some examples, when dopants are implanted via the second implantation process, the second screen layer 122 can scatter ion beams from the second implantation process, attenuate and / or prevent the channeling of implanted dopants and / or attenuate and / or prevent damage to the upper surface of the semiconductor body 102.

[0051] In one example, the second implantation process can comprise one or more implantation shots in which ions are injected through the second screen layer 122 into the semiconductor body 102. The one or more implantation shots can differ in their implantation energy level and / or implantation dose.

[0052] In some examples, after performing the second implantation process to form body area 130, the first structured photoresist 120 and / or the second screen layer 122 can be removed. The first structured photoresist 120 and / or the second screen layer 122 can be removed using an etching process.

[0053] In 1006 (illustrated in Fig. 1C) A second structured mask layer 136 and / or a third screen layer 138 is formed over the semiconductor body 102. The second structured mask layer 136 can comprise an oxide material (e.g., SiO2) and / or one or more other materials. The third screen layer 138 (e.g., scattering oxide layer) can comprise an oxide material (e.g., SiO2) and / or one or more other materials. The material composition of the second structured mask layer 136 can be the same as that of the third screen layer 138 or different from it.

[0054] In some examples, a second mask layer (not shown), such as a hard mask, can be formed over the semiconductor body 102. The second mask layer can be built up (e.g., structured) to form the second structured mask layer 136 such that it has openings exposing areas of an upper surface of the semiconductor body 102. The third screen layer 138 can be formed (for example, after the second mask layer has been built up to form the second structured mask layer 136) over the exposed areas of the upper surface of the semiconductor body 102 and / or the second structured mask layer 136, so that the exposed areas of the upper surface of the semiconductor body 102 are covered by the third screen layer 138 (e.g.,The exposed areas of the upper surface of the semiconductor body 102 can correspond to areas of the upper surface of the semiconductor body 102 that are laterally offset from areas of the second structured mask layer 136 that are not removed during the build-up of the second mask layer. Areas 139A of the upper surface of the semiconductor body 102 lie beneath (and / or are covered by) areas of the second structured mask layer 136. Areas 139B of the upper surface of the semiconductor body 102 that are not covered by the second structured mask layer 136 can lie beneath (and / or be covered by) at least the third screen layer 138.

[0055] In some examples, the second structured mask layer 136 has a thickness 140 in the range of at least 1 micrometer to at most 10 micrometers, in the range of at least 2 micrometers to at most 4 micrometers, and / or in the range of at least 2.5 micrometers to at most 3.5 micrometers. In some examples, the third screen layer 138 has a thickness 142 in the range of at least 10 nanometers to at most 500 nanometers and / or in the range of at least 25 nanometers to at most 75 nanometers.

[0056] In 1007 (illustrated in Fig. 1D) A third implantation process is performed to form one or more first-type conductivity regions 146 in the semiconductor body 102 (e.g., the one or more regions 146 may comprise a first region 146A, a second region 146B, etc.). The third implantation process (e.g., an ion implantation process) may involve implanting first-type conductivity dopants through one or more regions of the top surface of the semiconductor body 102 that are laterally offset from regions of the second structured mask layer 136. By performing the third implantation process, for example, the dopants may be implanted into the semiconductor body 102 through the third screen layer 138 and the regions 139B of the top surface of the semiconductor body 102 that are not covered by the second structured mask layer 136 to form the one or more regions 146.In one example, the one or more regions 146 can be one or more upper p-regions and include the dopants implanted via the third implantation process. These dopants may be p-type, such as aluminum, boron, gallium, beryllium, and / or other p-type dopants. In some examples, when the dopants are implanted via the third implantation process, the third screen layer 138 can scatter ion beams from the third implantation process, attenuate and / or prevent the channeling of implanted dopants, and / or attenuate and / or prevent damage to the upper surface of the semiconductor body 102.

[0057] In one example, the third implantation process can comprise one or more implantation shots in which ions are injected through the third screen layer 138 into the semiconductor body 102. The one or more implantation shots can differ in their implantation energy level and / or implantation dose.

[0058] In some examples, after performing the third implantation process to form one or more areas 146, the second structured mask layer 136 and / or the third screen layer 138 can be removed. The second structured mask layer 136 and / or the third screen layer 138 can be removed by applying an etching process.

[0059] In 1008 (illustrated in Fig. 1D) A second structured photoresist 150 and / or a fourth screen layer 152 is formed over the semiconductor body 102. The fourth screen layer 152 (e.g., scattering oxide layer) can comprise an oxide material (e.g., SiO2) and / or one or more other materials. In some examples, the fourth screen layer 152 is formed over the semiconductor body 102, and the second structured photoresist 150 can be formed over the fourth screen layer 152.

[0060] In some examples, a second photoresist (not shown) can be formed above the semiconductor body 102 (e.g., above the fourth screen layer 152). The second photoresist can be constructed (e.g., structured) to form the second structured photoresist 150 such that it has openings exposing areas of the upper surface of the semiconductor body 102. Areas 151A of the upper surface of the semiconductor body 102 lie beneath (and / or are covered by) areas of the second structured photoresist 150. Areas 151B of the upper surface of the semiconductor body 102 that are not covered by the second structured photoresist 150 may lie beneath (and / or be covered by) at least the fourth screen layer 152.

[0061] In some examples, the fourth screen layer 152 has a thickness 156 in the range of at least 10 nanometers to at most 500 nanometers and / or in the range of at least 25 nanometers to at most 75 nanometers.

[0062] In 1009 (illustrated in Fig. 1E) A fourth implantation process is performed to form one or more source regions 160 of a second conductivity type, different from the first conductivity type, in the semiconductor body 102 (e.g., the one or more source regions 160 may comprise at least one of a first source region 160A, a second source region 160B, a third source region 160C, etc.). The fourth implantation process (e.g., an implantation process) may involve the implantation of dopants of the second conductivity type through one or more regions of the upper surface of the semiconductor body 102 that are laterally offset from the second structured photoresist 150.By performing the fourth implantation process, dopants can, for example, be implanted into the semiconductor body 102 through the fourth screen layer 152 and the areas 151B of the upper surface of the semiconductor body 102 that are not covered by the second structured photoresist 150, in order to form the one or more source regions 160. In some examples, the second conductivity type is an n-type (e.g., the one or more source regions can be (n+)-source regions). The dopants implanted via the fourth implantation process can include n-type dopants such as nitrogen dopants, phosphorus dopants, and / or other n-type dopants.In some examples, when dopants are implanted via the fourth implantation process, the fourth screen layer 152 can scatter ion beams of the fourth implantation process, attenuate and / or prevent the channeling of implanted dopants and attenuate and / or prevent damage to the top surface of the semiconductor body 102.

[0063] In one example, the fourth implantation process can comprise one or more implantation shots in which ions are injected through the fourth screen layer 152 into the semiconductor body 102. The one or more implantation shots can differ in their implantation energy level and / or implantation dose.

[0064] In some examples, after performing the fourth implantation process to form one or more source regions 160, the second structured photoresist 150 and / or the fourth screen layer 152 can be removed. The second structured photoresist 150 and / or the fourth screen layer 152 can be removed by applying an etching process.

[0065] In 1010 (illustrated in Fig. 1E) A third structured mask layer 166 is formed over the semiconductor body 102. The third structured mask layer 166 can comprise an oxide material (e.g., SiO2) and one or more other materials. In some examples, a third mask layer (not shown), such as a hard mask, can be formed over the semiconductor body 102. The third mask layer can be built up (e.g., structured) to form the third structured mask layer 166 such that it has openings exposing areas of the top surface of the semiconductor body 102. Areas 167A of the top surface of the semiconductor body 102 lie beneath (and / or are covered by) areas of the third structured mask layer 166. Areas 167B of the top surface of the semiconductor body 102 are not covered by the third structured mask layer 166.

[0066] In some examples, the third structured mask layer 166 has a thickness 164 in the range of at least 100 nanometers to at most 10 micrometers, in the range of at least 2 micrometers to at most 4 micrometers and / or in the range of at least 2.5 micrometers to at most 3.5 micrometers.

[0067] In 1011 (illustrated in Fig. 1F) One or more trenches 170 are formed in the semiconductor body 102 (e.g., the one or more trenches may include at least one of a first trench 170A, a second trench 170B, etc.). The one or more trenches 170 can be formed by utilizing the third structured mask layer 166. In some examples, an etching process is performed to form the trenches 170, where openings in the third structured mask layer 166 allow one or more etchants applied during the etching process to remove areas of the semiconductor body 102, while the third structured mask layer 166 protects or shields areas of the semiconductor body 102 covered by the third structured mask layer 166. The etching process is a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process and / or any other suitable etching process.In one example, the etching process uses hydrogen chloride (e.g., hydrochloric acid), hydrogen fluoride (e.g., hydrofluoric acid) and / or one or more other chemicals.

[0068] In some examples, a trench (e.g., the first trench 170A, the second trench 170B, etc.) of one or more trenches 170 can be configured to have a rounded corner 174. The rounded corner 174 can be formed by treatment with hydrogen (e.g., H₂). Alternatively and / or additionally, a trench (e.g., the first trench 170A, the second trench 170B, etc.) of one or more trenches 170 can be configured such that a side wall 172 of the semiconductor body 102, defining the trench, is chamfered at an angle 176 with respect to an axis 173. The axis 173 can correspond to an axis along which the upper surface of the semiconductor body 102 extends. In some examples, the angle 176 can be less than 90 degrees. For example, the angle 176 can be in the range of at least 83 degrees to at most 89 degrees, such as 86 degrees.In one example, at least one region of the side wall 172 extends along a c-axis 175 of the semiconductor body 102 (e.g., the c-axis 175 can correspond to a crystallographic c-axis of the material, such as SiC, of ​​the semiconductor body 102).

[0069] In some examples, after forming one or more trenches 170, the third structured mask layer 166 can be removed. The third structured mask layer 166 can be removed by applying an etching process.

[0070] In some examples, an initial curing process (e.g., a low-temperature curing process) can be performed. The initial curing process can prevent and / or mitigate wafer warping of the semiconductor body. The initial curing process can be performed before forming one or more trenches 170 and / or after performing the first, second, third, and / or fourth implantation processes.

[0071] In 1012 (illustrated in Fig. 1F) A third structured photoresist 184 is formed above the semiconductor body 102. In some examples, a third photoresist (not shown) can be formed above the semiconductor body 102. The third photoresist can be built up (e.g., structured) to form the third structured photoresist 184. One or more regions 185A of the top surface of the semiconductor body 102 lie beneath (and / or are covered by) one or more regions of the third structured photoresist 184. In some examples, the one or more regions 185A can have boundary regions (e.g., edge regions) of the top surface of the semiconductor body 102. One or more regions 185B of the top surface of the semiconductor body 102 are not covered by the third structured photoresist 184.In some examples, one or more regions 185B of the upper surface of the semiconductor body 102 may be located beneath (and / or covered by) a screen layer (not shown), such as a screen layer (e.g., a scattering oxide layer) formed using one or more of the techniques described herein with respect to the first screen layer 108, the second screen layer 122, the third screen layer 138, and / or the fourth screen layer 152. Alternatively and / or additionally, one or more regions 185B of the upper surface of the semiconductor body 102 may be exposed. In some examples, one or more regions 185B may have a central region of the upper surface of the semiconductor body 102 between boundary regions (e.g., edge regions) of the upper surface of the semiconductor body 102.

[0072] In 1013 (illustrated in Fig. 1G) A fifth implantation process is performed to form one or more second-type current propagation regions in the semiconductor body 102. The fifth implantation process (e.g., an ion implantation process) may include the implantation of second-type dopants through the top surface of the semiconductor body 102 (e.g., through one or more regions of the top surface of the semiconductor body 102 that are laterally offset from the third structured photoresist 184) and the implantation of second-type dopants through the bottoms of one or more trenches 170. The dopants implanted via the fifth implantation process may be n-type dopants such as nitrogen dopants, phosphorus dopants, and / or other n-type dopants.In one example, the fifth implantation process involves an area-wide implantation extending horizontally over at least one region of the semiconductor body 102. In an example where there is a (not shown) screen layer over the top surface of the semiconductor body 102 and / or in the one or more trenches 170, when the dopants are implanted via the fifth implantation process, the screen layer can scatter ion beams from the fifth implantation process, attenuate and / or prevent the channeling of implanted dopants, and / or attenuate and / or prevent damage to the top surface of the semiconductor body 102.

[0073] In one example, the one or more stream propagation areas can be at least one of a first stream propagation area 182, a second stream propagation area 180, a third stream propagation area 179 (e.g., is in Fig. (1G only a part of which is shown) etc. In some examples, one, some and / or all of the current propagation areas exhibit similar characteristics to each other and / or are identical and / or equivalent to each other.

[0074] In some examples, each current propagation region of one, some, and / or all of the one or more current propagation regions formed in the semiconductor body 102 comprises: (i) a first region (e.g., a first region 182A of the first current propagation region 182, a first region 180A of the second current propagation region 180, etc.) having a vertical position corresponding to a vertical position of a trench of the one or more trenches 170; and (ii) a second region (e.g., a second region 182B of the first current propagation region 182, a second region 180B of the second current propagation region 180, etc.) lying below a trench of the one or more trenches 170.In some examples, the fifth implantation process involves implanting first dopants through the top surface of the semiconductor body 102 to form the first region of each current propagation region of one, some, and / or all of the one or more current propagation regions (e.g., the first region 182A of the first current propagation region 182, the first region 180A of the second current propagation region 180, etc., can be formed by implanting the first dopants through the top surface of the semiconductor body 102). In some examples, the fifth implantation process involves implanting second dopants through the bottoms of the one or more trenches 170 of the semiconductor body 102 to form the second region of each current propagation region of one, some, and / or all of the one or more current propagation regions formed in the semiconductor body 102 (e.g.,The second area 182B of the first stream propagation area 182, the second area 180B of the second stream propagation area 180, etc., can be formed by implanting the second dopants through the soils of one or more trenches 170. The first and second dopants can be implanted simultaneously (for example, via one or more implantation shots of the fifth implantation process). For example, the first and second dopants can be implanted via a comprehensive implantation of the fifth implantation process.

[0075] In one example, dopants are implanted through the top surface of the semiconductor body 102 to form the first region 180A of the second current propagation region 180, and dopants are implanted through a bottom 171 of the second trench 170B (and / or one or more side walls of the semiconductor body 102 defining the second trench 170B) to form the second region 180B of the second current propagation region 180. The first region 180A of the second current propagation region 180 can have a vertical position corresponding to a vertical position of the second trench 170B (e.g., a vertical position of at least some part of the first region 180A of the second current propagation region 180 corresponds to a vertical position of at least some part of the second trench 170B). The second area 180B of the second stream propagation area 180 may lie under the second trench 170B.

[0076] In some examples, the difference between a first vertical distance D1 and a second vertical distance D2 can be at most 200 nanometers, such as at most 100 nanometers, at most 50 nanometers, and / or at most 10 nanometers (and / or the first vertical distance D1 can be approximately equal to the second vertical distance D2). The first vertical distance D1 corresponds to a distance between a vertical position of the top surface of the semiconductor body 102 (through which dopants are implanted in the fifth implantation process to form the first region 180A of the second current propagation region 180) and a vertical position of a top surface of the first region 180A of the second current propagation region 180.The second vertical distance D2 corresponds to a distance between a vertical position of a bottom of the second trench 170B (through which dopants are implanted in the fifth implantation process to form the second region 180B of the second stream propagation area 180) and a vertical position of a top of the second region 180B of the second stream propagation area 180. In some examples, the first vertical distance D1 and the second vertical distance D2 may be based on one or more parameters of the fifth implantation process, such as a minimum implantation energy level of the fifth implantation process (e.g., the minimum implantation energy level may correspond to a lowest implantation energy level used in the fifth implantation process).In one example, the first vertical distance D1 and the second vertical distance D2 can be a function of the minimum implantation energy level, such that an increase in the minimum implantation energy level results in an increase in the first vertical distance D1 and an increase in the second vertical distance D2. Accordingly, the vertical positions of the top of the first region 180A of the second current propagation region 180 and the top of the second region 180B of the second current propagation region 180 can be controlled by selecting the minimum implantation energy level. In some examples, one or more parameters of the fifth implantation process (e.g., the minimum implantation energy level) and / or a depth of the second trench 170B can be selected such that a vertical position of the first region 180A of the second current propagation region 180 corresponds to a vertical position of the second trench 170B (e.g.,so that the top of the first region 180A of the second current propagation region 180 is higher than the bottom 171 of the second trench 170B). Alternatively and / or additionally, one or more parameters of the fifth implantation process (e.g., the minimum implantation energy level) can be selected such that the top of the first region 180A of the second current propagation region 180 borders the body region 130. In some examples, the one or more parameters may include a number of ion implantation shots, an implantation energy level, and / or an ion implantation dose.

[0077] In some examples, the difference between a third vertical distance D3 and a fourth vertical distance D4 is at most 200 nanometers, such as at most 100 nanometers, at most 50 nanometers, and / or at most 10 nanometers (and / or the third vertical distance D3 may be equal to the fourth vertical distance D4). The third vertical distance D3 corresponds to a distance between a vertical position of the upper surface of the semiconductor body 102 (through which dopants are implanted in the fifth implantation process to form the first region 180A of the second current propagation region 180) and a vertical position of a bottom surface of the first region 180A of the second current propagation region 180.The fourth vertical distance D4 corresponds to a distance between a vertical position of a bottom 171 of the second trench 170B (through which dopants are implanted in the fifth implantation process to form the second region 180B of the second stream propagation area 180) and a vertical position of a bottom of the second region 180B of the second stream propagation area 180. In some examples, the third vertical distance D3 and the fourth vertical distance D4 may be based on an implantation energy level of an implantation shot of the fifth implantation process, such as a maximum implantation energy level of the fifth implantation process (e.g., the maximum implantation energy level may correspond to a highest implantation energy level used in the fifth implantation process).In one example, the third vertical distance D3 and the fourth vertical distance D4 can be a function of the maximum implantation energy level, such that an increase in the maximum implantation energy level results in an increase in the third vertical distance D3 and an increase in the fourth vertical distance D4. Accordingly, the vertical positions of the bottom of the first region 180A and the bottom of the second region 180B of the second current propagation area 180 can be controlled by selecting the maximum implantation energy level. In some examples, one or more parameters of the fifth implantation process (e.g., the maximum implantation energy level) and / or the depth of the second trench 170B can be selected such that the vertical position of the bottom of the first region 180A of the second current propagation area 180 is lower than the bottom 171 of the second trench 170B.In this way, the first region 180A of the second current propagation area 180 can extend from a vertical position higher than the bottom 171 of the second trench 170B to a vertical position lower than the bottom 171 of the second trench 170B. Alternatively and / or additionally, one or more parameters of the fifth implantation process (e.g., the maximum implantation energy level) and / or the depth of the second trench 170B can be selected such that a vertical position of the bottom of the first region 180A of the second current propagation area 180 is lower than or equal to a vertical position of the top of the second region 180B of the second current propagation area 180. Alternatively and / or additionally, one or more parameters of the fifth implantation process (e.g.,the maximum implantation energy level) and / or the depth of the second trench 170B are selected such that a doping concentration of the second conductivity type (e.g., a concentration of an n-type dopant) along a line 186 (e.g., a vertical line) extending through the first region 180A and the second region 180B of the second current propagation region 180 satisfies a condition. The condition may be that along the line 186, the doping concentration (e.g., a concentration of n-type dopants) through the first region 180A and the second region 180B of the second current propagation region 180 exhibits a variance that is less than a threshold variance. Alternatively and / or additionally, the condition may be that under doping concentrations (e.g.,Concentrations of an n-type doping) along line 186 in the first area 180A and the second area 180B of the second current propagation area 180 have a maximum doping concentration. max the doping concentrations and a minimum doping concentration min The following must be fulfilled: concentrationmaxconcentrationmin≤thresh where thresh can be 5, 10 or any other value.

[0078] In one example, the fifth implantation process can comprise one or more implantation shots in which ions are injected into the semiconductor body 102 to form the one or more current propagation regions (e.g., ions are injected through the top surface of the semiconductor body 102 and / or through the bottoms of the one or more trenches 170 into the semiconductor body 102). The one or more implantation shots can differ in their implantation energy level and / or implantation dose.

[0079] In some examples, the maximum implantation energy level of the fifth implantation process (e.g., the maximum implantation energy level of one or more implantation shots of the fifth implantation process used to form one or more current propagation areas) can be at most 2000 keV, such as at most 1800 keV and / or at most 1500 keV. The fifth implantation process can be performed such that implanted dopants lying below a trench 170 reach a target depth TD that is lower than the vertical position of a bottom of the trench 170.In some implementations where one or more current propagation regions are formed via an implantation process performed prior to the formation of one or more trenches 170, a required maximum implantation energy level of the implantation process may exceed the maximum implantation energy level of the fifth implantation process (e.g., the required maximum implantation energy level of the implantation process may be more than 2000 keV, such as up to 3000 keV and / or up to 4000 keV) to implant dopants deep enough to reach the target depth TD.Accordingly, using the techniques provided herein to perform the fifth implantation process (and / or at least form a portion of the one or more current propagation regions), after the one or more trenches 170 have been formed (rather than, for example, before the formation of the one or more trenches 170), the one or more current propagation regions can be implanted with a lower maximum implantation energy level (e.g., implanted dopants of the second conductivity type can reach the target depth TD with the lower maximum implantation energy level).Alternatively and / or additionally, by using the techniques provided herein to perform the fifth implantation process (and / or to form at least one area of ​​the one or more stream propagation areas) after the one or more trenches 170 have been formed (rather than, for example, before the formation of the one or more trenches 170), deeper implantations with the same maximum implantation energy level can be achieved than implantations where the one or more stream propagation areas are formed before the formation of the one or more trenches 170.

[0080] Forming the one or more current propagation regions at the lower maximum implantation energy level may allow for a thinner required thickness of a photoresist and / or hard mask used to perform the fifth implantation process to form the one or more current propagation regions. For example, the third structured photoresist 184, used to implant dopants to form the one or more current propagation regions, may be thinner compared to implantations where the one or more current propagation regions are formed before the one or more trenches are formed.In one example, the thickness of the third structured photoresist 184 can range from at least 0.5 micrometers to at most 2 micrometers, whereas implantations where one or more current propagation regions are formed before one or more trenches are formed may require a photoresist thickness between 4 and 6 micrometers. Alternatively and / or additionally, the third structured photoresist 184 can be replaced by a structured hard mask, such as an oxide mask with SiO2, with a thickness ranging from at least 5 micrometers to at most 2 micrometers.

[0081] Alternatively and / or additionally, forming the one or more current propagation regions at the lower maximum implantation energy level can result in: (i) reduced power consumption for forming the one or more current propagation regions; (ii) increased ion flux and / or reduced implantation time; and / or (iii) the possibility of utilizing a greater variety of dopant-implanting tools to perform the fifth implantation process to form the one or more current propagation regions (e.g., because the maximum implantation energy level is lower, there are multiple available dopant-implanting tools capable of performing an implantation shot at the maximum implantation energy level), thereby improving tool redundancy.

[0082] Alternatively and / or additionally, by training the one or more current propagation regions using one or more of the techniques provided herein, the number of ion implantation shots of the one or more ion implantation shots of the fifth implantation process can be reduced compared with the number of ion implantation shots performed to train the one or more current propagation regions in implantations where the ion implantation shots are performed before the one or more trenches 170 are formed.In one example, the number of ion implantation shots of the one or more ion implantation shots of the fifth implantation process may be three, whereas in implantations where ion implantation shots are performed to form the one or more current propagation areas before the one or more trenches 170 are formed, the number of ion implantation shots may be more than three, such as five, six, seven, etc.The reduced number of ion implantation shots performed to form one or more current propagation regions may result in a reduction of the time required to implant dopants to form one or more current propagation regions, a reduction of the amount of power used to form one or more current propagation regions, and / or a reduction in the amount of work performed by an implantation facility used to form one or more current propagation regions.

[0083] In some examples, one or more ion implantation shots of the fifth implantation process can be performed in one or more channeling directions associated with the channeling of implants into the semiconductor body 102. Compared to performing the one or more ion implantation shots in a direction perpendicular to the top surface of the semiconductor body 102, performing the one or more ion implantation shots along the one or more channeling directions may result in lower implantation energy levels being required for implanted dopants to reach desired depths (e.g., the one or more ion implantation shots can be performed at a lower energy because they are performed by utilizing the one or more channeling directions).Accordingly, in some examples, an implantation angle of one or more ion implantation shots can be based on a channeling direction of one or more channeling directions. In one example, the one or more channeling directions include a channeling direction of 0 degrees with respect to the (in . Fig. 1F (shown) c-axis 175 of the semiconductor body 102, wherein the one or more ion implantation shots may include an implantation shot performed with an implantation angle (e.g., an inclination) corresponding to the channeling direction of 0 degrees (e.g., the implantation angle may be -4 degrees with respect to an axis perpendicular to the top surface of the semiconductor body 102). In one example, the one or more channeling directions include a channeling direction of 17 degrees with respect to the c-axis 175 of the semiconductor body 102, wherein the one or more ion implantation shots may include an implantation shot performed with an implantation angle corresponding to the channeling direction of 17 degrees (e.g., the implantation angle may be 13 degrees with respect to the direction perpendicular to the top surface of the semiconductor body 102).

[0084] In some examples, after performing the fifth implantation process to form one or more current propagation regions, the third structured photoresist 184 can be removed. The third structured photoresist 184 can be removed using an etching process.

[0085] In 1014 (illustrated in Fig. 1G) a cover layer 198 is formed over the semiconductor body 102 and / or a second annealing process (e.g., a high-temperature annealing process) is performed. The cover layer 198 may consist of graphite and / or another material. The cover layer 198 may be formed before the second annealing process is performed. The second annealing process may involve heating the semiconductor body 102 to activate dopants within the semiconductor body 102 (e.g., the dopants may include those implanted via the first, second, third, fourth, and / or fifth implantation processes). For example, the second annealing process may cause the dopants to become electrically activated. In some examples, the cover layer 198 may prevent diffusion of implanted dopants during the second annealing process (e.g.,The top layer 198 can prevent dopants from escaping from the semiconductor body 102 during the second annealing process. In some examples, the temperature used to perform the second annealing process is higher than the temperature used to perform the first annealing process. In some examples, the top layer 198 can be removed after the second annealing process (e.g., by an etching process and / or using one or more other techniques).

[0086] In 1015 (illustrated in Fig. 1H) one or more gate structures 101 are formed in the one or more trenches 170. For example, the one or more gate structures 101 can include at least one first gate structure 101A formed in the first trench 170A, a second gate structure 101B formed in the second trench 170B, etc. In some examples, a gate dielectric layer 133 can be formed in each trench of one, some, and / or all of the one or more trenches 170, and / or a gate electrode 137 can be formed in each trench of one, some, and / or all of the one or more trenches 170, the gate dielectric layer 133 separating the gate electrode 137 from the semiconductor body 102. In some examples, the gate dielectric layer 133 can have an oxide material (e.g. SiO2) and / or one or more other materials.In some examples, the gate electrode 137 can comprise one or more doped semiconductor materials, one or more metals, and / or one or more other materials. In some examples, a dielectric layer 127 (e.g., an interlayer dielectric) can be formed over the gate electrode 137, wherein the dielectric layer 127 can electrically insulate the gate electrode 137 from one or more conductive elements, wiring, and / or interconnect components, etc. (which are located, for example, over the semiconductor body 102).

[0087] In some examples, a vertical position of the first region 180A of the second current propagation region 180 corresponds to a vertical position of the second gate structure 101B, which includes the gate dielectric layer 133 and / or the gate electrode 137 (e.g., a vertical position of at least a certain part of the first region 180A of the second current propagation region 180 corresponds to a vertical position of at least a certain part of the second gate structure 101B). Alternatively and / or additionally, the second region 180B of the second current propagation region 180 can be located below the second gate structure 101B.

[0088] In some examples, the first region 180A of the second current propagation region 180 borders a first sidewall 119 of the second gate structure 101B. In some examples, the second source region 160B (of which, for example, at least one region lies above the first region 180A of the second current propagation region 180) and / or the body region 130 (of which, for example, at least one region lies above the first region 180A of the second current propagation region 180) borders the first sidewall 119 of the second gate structure 101B. In some examples, the first sidewall 119 of the second gate structure 101B corresponds to a region of a surface of the gate dielectric layer 133 in the second gate structure 101B.

[0089] In some examples, the second area 146B (e.g., an upper p-area) and / or the second burial area 116B border a bottom surface 123 of the second gate structure 101B. In some examples, the second gate structure 101B, the second area 146B, and / or the second burial area 116B are arranged such that the second area 146B and / or the second burial area 116B do not border (and / or extend to) a corner 125 of the second gate structure 101B (e.g., a corner of the second gate structure 101B located between the first side wall of the second gate structure 101B and the bottom surface 123 of the second gate structure 101B). In some examples, the second area 146B and the second burial area 116B correspond to a shielding area. The shielding area (which includes, for example, the second area 146B and the second burial area 116B) can provide shielding for the second gate structure 101B (e.g.The shielding region can provide shielding for the gate dielectric layer 133 in the second gate structure 101B. In some examples, the degree of shielding provided to the second gate structure 101B (and / or the gate dielectric layer 133) by the shielding region (e.g., the shielding region can shield the second gate structure 101B from electric fields) can depend on a horizontal distance 135 between a horizontal position of the shielding region and a horizontal position of the corner 125. Alternatively and / or additionally, the RonxA of the semiconductor device can depend on the horizontal distance 135. For example, a decrease in the horizontal distance 135 can be associated with an increase in the degree of shielding and / or an increase in RonxA.For example, the second gate structure 101B, the second region 146B, and / or the second burial region 116B can be positioned to achieve a desired level of shielding for the second gate structure 101B and / or a desired RonxA. In one example, the second gate structure 101B, the second region 146B, and / or the second burial region 116B can be positioned such that the horizontal distance 135 is greater than a threshold distance (e.g., a horizontal distance 135 that is less than or equal to the threshold distance may result in a semiconductor device with a RonxA that is too high for the semiconductor device to function correctly).

[0090] In some examples, the second region 146B (e.g. the upper p-region) borders a second side wall 121 of the second gate structure 101B, with the second side wall 121 being opposite the first side wall 119 of the second gate structure 101B.

[0091] In some examples, a first contact, a second contact, and / or a third contact (not shown) can be formed. The first contact can be a source contact and / or can be connected (e.g., electrically connected) to the second source region 160B. The second contact can be connected (e.g., electrically connected) to the shielding region, such as the second region 146B (e.g., the upper p-region). The third contact can be a drain contact and / or can be connected (e.g., electrically connected) to a second surface of the semiconductor body 102, such as a lower surface (e.g., a back side) of the semiconductor body 102 that is opposite the upper surface of the semiconductor body.

[0092] In some examples, the first, second, and / or third contact can be contacts of a transistor, such as a field-effect transistor (FET), a metal-oxide-semiconductor FET (MOSFET), an insulated-gate bipolar transistor (IGBT), and / or another type of transistor in the semiconductor device. In some examples, the body region 130 defines a channel of the transistor, such as a channel between the second source region 160B and the second current-propagation region 180. In one example, the transistor is a MOSFET (e.g., a vertical MOSFET), and the channel (defined by the body region 130) is a MOSFET channel of the MOSFET. In some examples, the conductivity of the channel is controlled by a voltage applied to the gate electrode 137.In some examples, the breakdown voltage of the transistor depends on the thickness and / or doping concentration of an epitaxial layer (e.g., an epitaxial SiC layer) of one or more epitaxial layers of the semiconductor body 102. In some examples, the one or more burial regions 116, the body region 130, the one or more regions 146 (e.g., the one or more upper p-regions), the one or more source regions 160, and / or the one or more current propagation regions are regions of the epitaxial layer (e.g., the epitaxial SiC layer).

[0093] In some examples, the shielding region (and / or the second region 146B and / or the second burial layer 116B) and the second current-propagation region 180 form a pn junction. The pn junction can form a body diode of the semiconductor device, such as a body diode that conducts current from the shielding region (and / or from another p-doped region of the semiconductor device) to the second current-propagation region 180 (and / or to another n-doped region of the semiconductor device). In some examples, current flows through the second current-propagation region 180 to a drain of the transistor, such as a drain contact of the semiconductor device. In some examples, the drain contact is located on a surface of the semiconductor device, such as on a back side of the semiconductor device (e.g.,The back side of the semiconductor device can correspond to a surface of the semiconductor body 102 that is opposite the top surface of the semiconductor body 102 (e.g., if the back side corresponds to a bottom surface of the semiconductor substrate of the semiconductor body 102). The pn junction can correspond to a junction between a p-doped region (e.g., the shielding region) and an n-doped region (e.g., the second current-propagation region 180 and / or another n-doped region of the semiconductor body 102).

[0094] In some examples, one or more current propagation regions of the semiconductor device can provide a connection (e.g., a low-resistance connection) between a channel (e.g., a MOSFET channel defined by body region 130) and an epitaxial layer (e.g., an epitaxial SiC layer) of one or more epitaxial layers of the semiconductor body 102. Alternatively and / or additionally, current can be propagated or distributed across one or more current propagation regions of the semiconductor device (e.g., one or more current propagation regions can distribute the current across the width of the transistor).

[0095] In some examples, the body region 130 can be formed after the one or more trenches 170 have been formed. For example, the body region 130 (and, for example, the one or more stream propagation regions) can be formed by utilizing the third structured photoresist 184 (e.g., both an implantation process to form the body region and the fifth implantation process to form the one or more stream propagation regions can be performed by utilizing the third structured photoresist 184). Fig. Figure 2 illustrates an example 200 of the semiconductor device in which the body region 130 is formed after the one or more trenches 170 have been formed. In some examples, a sixth implantation process is performed to form the body region 130 of the first conductivity type in the semiconductor body 102. The sixth implantation process (e.g., an ion implantation process) may involve implanting third-order dopants of the first conductivity type through the top surface of the semiconductor body 102 to form the body region 130. The sixth implantation process may involve implanting fourth-order dopants through the bottoms of the one or more trenches 170 to form regions 202 that lie below the trenches 170 and above areas of the one or more current-propagation regions that lie below the one or more trenches 170.In one example, the regions 202 can encompass at least one of a third region 202A, a fourth region 202B, etc. The fourth region 202B can lie below the second gate structure 101B and above the second region 180B of the second current propagation region 180. The fourth region 202B can provide shielding for the gate structure 101B, at least partially, due to an electrical potential of the fourth region 202B. The fourth region 202B can be connected to the first contact (e.g., the source contact) via an electrical connection (not shown). For example, the electrical potential of the fourth region 202B can be based on an electrical potential of the first contact.Alternatively and / or additionally, the fourth region 202B can be in contact with and / or overlap with one or more p-doped regions, wherein the electrical potential of the fourth region 202B can be based on an electrical potential of one or more p-doped regions.

[0096] Fig. Figures 3A - 3B illustrate embodiments in which the semiconductor device is a dual-channel semiconductor device (e.g., a dual-channel MOSFET). Fig. Figure 3A illustrates an example 300 for the dual-channel semiconductor device. The dual-channel semiconductor device can have a current-propagation region 308 comprising a first region 308A, a second region 308B, and / or a third region 308C. In some examples, an implantation process (e.g., the fifth implantation process) involves implanting first dopants through the top surface of the semiconductor body 102 to form the first region 308A and the second region 308B of the current-propagation region 308 (e.g., the first region 308A and the second region 308B can be formed by implanting the first dopants through the top surface of the semiconductor body 102). In some examples, the implantation process (e.g., the fifth implantation process) involves implanting second dopants through the bottom of a trench (e.g.,a trench of one or more trenches 170) to form the third region 308C of the current propagation region 308 (e.g., the third region 308C can be formed by implanting the first dopants through the top surface of the semiconductor body 102). The current propagation region 308 can be adjacent to a gate structure 302. A first source region 304A (of the second conductivity type, for example), a first body region 306A (of the first conductivity type, for example), and / or the first region 308A of the current propagation region 308 (of the second conductivity type, for example) can be adjacent to the first side wall 119 of the gate structure 302.A second source region 304B (of the second conductivity type, for example), a second body region 306B (of the first conductivity type, for example) and / or the second region 308B of the current propagation region 308 (of the second conductivity type, for example) can border the second side wall 121 of the gate structure 302 opposite the first side wall 119. A vertical position of the first region 308A of the current propagation region 308 and a vertical position of the second region 308B of the current propagation region 308 can correspond to a vertical position of the gate structure 302 (e.g., a vertical position of at least a certain part of the first region 308A of the current propagation region 308 and a vertical position of at least a certain part of the second region 308B of the current propagation region 308 can correspond to a vertical position of at least a certain part of the gate structure 302).The third region 308C of the current propagation region 308 can be located below the gate structure 302. In some examples, the current propagation region 308, the gate structure 302, the first source region 304A, the second source region 304B, the first body region 306A and / or the second body region 306B can be located between a first shielding region 310A (e.g., a first shielding region that includes a p-burial region and / or an upper p-region) and / or a second shielding region 310B (e.g., a second shielding region that includes a p-burial region and / or an upper p-region). In some examples, the first body area 306A and / or the first area 308A of the current propagation area 308 borders the first shielding area 310A. In some examples, the second body area 306B and / or the second area 308B of the current propagation area 308 borders the second shielding area 310B.

[0097] Fig. Figure 3B illustrates an example 300 of the two-channel semiconductor device in which a first-type conductivity region 320 is formed between the third region 308C of the current-propagation region 308 and the gate structure 302. In some examples, the region 320 provides a shield for the gate structure 302, at least partially as a result of an electrical potential of the region 320 (e.g., the region 320 can provide a shield for the bottom 123 of the gate structure 302). The region 320 can be connected to the first contact (e.g., the source contact) via an electrical connection (not shown). For example, the electrical potential of the region 320 can be based on an electrical potential of the first contact. In some examples, area 320 can be formed via an implantation process (e.g., the sixth implantation process) that is performed to address one or more body areas (e.g.,to form the first body region 306A, the second body region 306B, etc. For example, the implantation process can be carried out after one or more trenches 170 have been formed, wherein the first body region 306A and / or the second body region 306B can be formed by implanting dopants through the upper surface of the semiconductor body 102, and / or the region 320 can be formed by implanting dopants through the bottom of the trench 170. In some examples, the region 320 can be electrically connected to a source region (e.g., at least one of the first source region 304A, the second source region 304B, etc.).

[0098] Fig. Figure 4 illustrates an exemplary method 400 for fabricating a semiconductor device. In Figure 402, one or more implantation processes are performed to form an implanted region (e.g., a shield region) of the first conductivity type (e.g., p-type) in a semiconductor body (e.g., the semiconductor body 102). In one example, the implanted region comprises a burial region of one or more burial regions 116 and / or a region (e.g., an upper p-region) of one or more regions 146. In another example, the one or more implantation processes comprise the (in Fig. 1B depicted and / or described in this respect) the first implantation process and / or the (in Fig. 1D depicted and / or described in this respect) third implantation process. At 404, a trench (e.g., one of the trenches 170) is formed in the semiconductor body. At 406, after the trench has formed, an implantation process (e.g., the fifth implantation process, which is described in 1D) is initiated. Fig. 1G depicted and / or described in this respect) is carried out to form a current propagation region of a second conductivity type (e.g., n-type) in the semiconductor body. The implantation process may include the implantation of first dopants through a top surface of the semiconductor body to form a first region of the current propagation region (e.g., the first region 180A of the second current propagation region 180). The implantation process may include the implantation of second dopants through a bottom of the trench to form a second region of the current propagation region (e.g., the second region 180B of the second current propagation region 180). At 408, a gate structure is formed in the trench (e.g., the second gate structure 101B is formed in the second trench 170B). A vertical position of the first region of the current propagation region corresponds to a vertical position of the gate structure.The second area of ​​the current propagation region lies beneath the gate structure.

[0099] Fig. Figure 5 illustrates an exemplary method 500 for fabricating a semiconductor device. In 502, one or more implantation processes are performed to form an implanted region (e.g., a shield region) of a first conductivity type (e.g., p-type) in a semiconductor body (e.g., the semiconductor body 102). In one example, the implanted region comprises a burial region of one or more burial regions 116 and / or a region (e.g., an upper p-region) of one or more regions 146. In another example, the one or more implantation processes comprise the (in Fig. 1B depicted and / or described in this respect) the first implantation process and / or the (in Fig.1D depicted and / or described herein) third implantation process. In 504, a seventh implantation process is performed. The seventh implantation process may include the implantation of first dopants of a second conductivity type (e.g., n-type) through an upper surface of the semiconductor body to form a first region of a current propagation region (e.g., at least one of the first region 182A of the first current propagation region 182, the first region 180A of the second current propagation region 180, etc.). In one example, the seventh implantation process includes an area-wide implantation extending horizontally over at least one region of the semiconductor body. The seventh implantation process may be performed using one or more of the techniques provided herein in relation to the fifth implantation process. In 506, after performing the seventh implantation process, a trench (e.g.,A trench of one or more trenches 170 is formed in the semiconductor body. In 508, after the trench has been formed, an eighth implantation process is carried out. The eighth implantation process may include the implantation of a second dopant of the second conductivity type through the bottom of the trench to form a second region of the current propagation domain (e.g., at least one of the second region 182B of the first current propagation domain 182, of the second region 180B of the second current propagation domain 180, etc.). The eighth implantation process may be carried out using one or more of the techniques provided herein with respect to the fifth implantation process. In one example, the eighth implantation process includes an area-wide implantation extending horizontally over at least one region of the semiconductor body.In addition to the eighth implantation process, which involves the implantation of dopants through the bottoms of trenches (e.g., of one or more trenches 170) in the semiconductor body 102, the eighth implantation process may also include, for example, the implantation of dopants through the top surface of the semiconductor body 102 (e.g., the eighth implantation process may increase the concentration of second-type conductivity dopants in the first region of the current propagation domain formed by the seventh implantation process). Alternatively and / or additionally, a structured photoresist and / or a structured hard mask may be used in the eighth implantation process to prevent at least some dopants from passing through the top surface of the semiconductor body 102 (e.g.,The structured photoresist and / or the structured hard mask can lie over and / or cover regions of the upper surface of the semiconductor body 102 that are laterally offset from trenches in the semiconductor body 102. At 510, a gate structure is formed in the trench (e.g., the second gate structure 101B is formed in the second trench 170B). A vertical position of the first region of the current propagation domain corresponds to a vertical position of the gate structure. The second region of the current propagation domain lies below the gate structure.

[0100] According to some embodiments, a method for fabricating a semiconductor device is provided. The method comprises performing one or more first implantation processes to form an implanted region of a first conductivity type in a semiconductor body, forming a trench in the semiconductor body, performing, after forming the trench, a second implantation process to form a current propagation region of a second conductivity type in the semiconductor body, wherein the second implantation process comprises implanting first dopants through an upper surface of the semiconductor body to form a first region of the current propagation region, and implanting second dopants through a bottom of the trench to form a second region of the current propagation region, and forming a gate structure in the trench.wherein a vertical position of the first region of the current propagation area corresponds to a vertical position of the gate structure and wherein the second region of the current propagation area lies below the gate structure.

[0101] According to some embodiments, the method includes forming a structured mask over the upper surface of the semiconductor body, wherein the formation of the trench is carried out utilizing the structured mask, and the removal of the structured mask prior to carrying out the second implantation process.

[0102] According to some embodiments, the first region of the current propagation area borders a first side wall of the gate structure, and the implanted area of ​​the first conductivity type borders a second side wall of the gate structure opposite the first side wall of the gate structure.

[0103] According to some embodiments, the method includes performing a third implantation process to form a body region of the first conductivity type in the semiconductor body, wherein at least one region of the body region lies above the first region of the current propagation region and borders the first side wall of the gate structure.

[0104] According to some embodiments, forming the gate structure includes forming a gate dielectric layer in the trench and forming a gate electrode in the trench, wherein the gate dielectric layer separates the gate electrode from the semiconductor body.

[0105] According to some embodiments, the maximum implantation energy level of the second implantation process is at most 2000 kiloelectronvolts (keV).

[0106] According to some embodiments, the difference between a first vertical distance and a second vertical distance is at most 200 nanometers, the first vertical distance corresponds to a distance between a vertical position of a top surface of the first region of the current propagation region and a vertical position of the top surface of the semiconductor body, and the second vertical distance corresponds to a distance between a vertical position of a top surface of the second region of the current propagation region and a vertical position of a bottom surface of the gate structure.

[0107] According to some embodiments, the semiconductor body contains a SiC substrate and / or an epitaxial SiC layer that lies above the SiC substrate.

[0108] According to some embodiments, the implanted area of ​​the first conductivity type and the current propagation area form a pn junction.

[0109] According to some embodiments, the implantation of the first dopants and the implantation of the second dopants are performed simultaneously.

[0110] According to some embodiments, the method comprises selecting one or more parameters associated with a top surface of the first region of the current propagation area adjacent to the body region, wherein the second implantation process is performed using the one or more parameters, and wherein the one or more parameters comprise a quantity of ion implantation shots, an implantation energy level, and / or an ion implantation dose.

[0111] According to some embodiments, the method comprises selecting one or more parameters associated with a vertical position of a bottom of the first region of the current propagation area that is lower than or equal to a vertical position of a top of the second region of the current propagation area, wherein the second implantation process is carried out using the one or more parameters, and wherein the one or more parameters comprise a quantity of ion implantation shots, an implantation energy level, and / or an ion implantation dose.

[0112] According to some embodiments, the method comprises selecting one or more parameters associated with forming the first region of the current propagation area such that it extends from a first position higher than a vertical position of the trench floor to a second vertical position that is the same as or lower than the vertical position of the trench floor, wherein the second implantation process is carried out using the one or more parameters, and wherein the one or more parameters include a quantity of ion implantation shots, an implantation energy level, and / or an ion implantation dose.

[0113] According to some embodiments, the third implantation process to form the body region is carried out after the trench has been formed, wherein the third implantation process includes implanting third dopants through the upper surface of the semiconductor body to form the body region, and implanting fourth dopants through the bottom of the trench to form a first conductivity region, and the body region is located above the first region of the current propagation region, and the first conductivity region is located above the second region of the current propagation region.

[0114] According to some embodiments, the third implantation process, to form the body area, is carried out before the trench is formed.

[0115] According to some embodiments, a method for fabricating a semiconductor device is provided. The method comprises performing one or more first implantation processes to form an implanted region of a first conductivity type in a semiconductor body; performing a second implantation process, which includes implanting first dopants of a second conductivity type through an upper surface of the semiconductor body to form a first region of a current propagation region; forming, after performing the second implantation process, a trench in the semiconductor body; performing, after forming the trench, a third implantation process, which includes implanting second dopants of the second conductivity type through a bottom of the trench to form a second region of the current propagation region; and forming a gate structure in the trench.wherein a vertical position of the first region of the current propagation area corresponds to a vertical position of the gate structure and wherein the second region of the current propagation area lies below the gate structure.

[0116] According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a semiconductor body having a body region of a first conductivity type, a current propagation region of a second conductivity type, and an implanted region of the first conductivity type; a trench-gate structure in the semiconductor body comprising a gate electrode and a gate dielectric layer separating the gate electrode from the semiconductor body; the implanted region and the current propagation region forming a pn junction; a vertical position of a first region of the current propagation region corresponding to a vertical position of the trench-gate structure; the first region of the current propagation region adjoins a first side wall of the trench-gate structure; and a second region of the current propagation region lies below the trench-gate structure.wherein a difference between a first vertical distance and a second vertical distance is at most 200 nanometers, wherein the first vertical distance corresponds to a distance between a vertical position of a top surface of the first region of the current propagation region and a vertical position of a top surface of the semiconductor body, and wherein the second vertical distance corresponds to a distance between a vertical position of a top surface of the second region of the current propagation region and a vertical position of a bottom surface of the trench-gate structure.

[0117] According to some embodiments, the semiconductor device includes a SiC substrate and / or an epitaxial SiC layer that lies above the SiC substrate.

[0118] According to some embodiments, the implanted area borders the second side wall of the trench-gate structure, opposite the first side wall of the trench-gate structure.

[0119] According to some embodiments, the upper surface of the first region of the current propagation area borders the body region.

[0120] It can be understood that combinations of one or more embodiments described herein, including combinations of embodiments described with reference to different figures, are considered herein.

[0121] Rather, the specific characteristics and processes described above are revealed as exemplary forms for implementing the requirements.

[0122] Any aspect or design described herein as an “example” should not necessarily be considered advantageous over other aspects or designs. Rather, the use of the word “example” is intended to present a possible aspect and / or implementation that may be included in the techniques presented herein. Such examples are not necessary or intended to be limiting for such techniques. Different embodiments of such techniques may include such an example, alone or in combination with other features, and / or may vary and / or omit the illustrated example.

[0123] As used in this application, the term "or" is intended to mean an inclusive "or" and not an exclusive "or". That is to say, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is to say, if X uses A, uses XB, or uses both A and B, then in each of the preceding cases, "X uses A or B" is satisfied. Furthermore, the indefinite article "a", as used in this application and the attached claims, is to be generally understood to mean "one or more", unless otherwise stated or it is clear from the context that it refers to a singular form. Unless otherwise stated, "first", "second", or the like are also not intended to imply any temporal aspect, spatial aspect, order, etc. Rather, such terms are used only as identifiers, names, etc.Used for features, elements, objects, etc. For example, a first element and a second element generally correspond to an element A and an element B, or to two different or two identical elements, or to the same element.

[0124] Although the disclosure has been presented and described with respect to one or more implementations, equivalent changes and modifications will also occur to the person skilled in the art based on reading and understanding this description and the accompanying claims. In particular, with regard to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components, unless otherwise specified, are intended to correspond to any component that performs the specified function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the disclosure illustrated herein.Furthermore, while a particular feature of the disclosure may have been disclosed in respect of only one of several implementations, such a feature may be combined with one or more other features of the other implementations, as may be desirable and advantageous for any given or particular application. Moreover, to the extent that the terms "contains," "exhibiting," "has," "with," or variations thereof are used in either the detailed description or the claims, such terms shall be understood to be inclusive, similar to the terms "exhibiting" or "comprising."

Claims

[1] Method for manufacturing a semiconductor device comprising: Performing one or more first implantation processes to form an implanted area (116, 130, 146) of a first conductivity type in a semiconductor body (102); Forming a trench (170) in the semiconductor body (102); Performing, after forming the trench (170), a second implantation process to form a current propagation region of a second conductivity type in the semiconductor body (102), wherein the second implantation process has: Implanting the first dopants through an upper surface of the semiconductor body to form a first region (180A, 182A) of the current propagation domain; and Implanting a second dopant through a bottom of the trench (170) to form a second area (180B, 182B) of the stream propagation area; and Forming a gate structure (101) in the trench (170), wherein a vertical position of the first area (180A, 182A) of the current propagation area corresponds to a vertical position of the gate structure (101) and the second area (180B, 182B) of the current propagation area lies below the gate structure (101). [2] Method according to claim 1, comprising: Forming a structured mask (166) over the upper surface of the semiconductor body (102), wherein the formation of the trench (170) is carried out using the structured mask (166); and Remove the structured mask (166) before performing the second implantation process. [3] Method according to any one of the preceding claims, wherein the first area (180A, 182A) of the current propagation area borders a first side wall (119) of the gate structure (101) and the implanted area (146) of the first conductivity type borders on one of the first side walls (119) of the gate structure (101) opposite the second side wall (121) of the gate structure (101). [4] A method according to any of the preceding claims, comprising: Performing a third implantation process to form a body region (130) of the first conductivity type in the semiconductor body (102), wherein at least one region of the body region (130) is located above the first region (180A, 182A) of the current propagation region and borders the first side wall (119) of the gate structure (101). [5] Method according to any of the preceding claims, wherein forming the gate structure (101) comprises: Formation of a gate dielectric layer (133) in the trench (170); and Forming a gate electrode (137) in the trench (170), wherein the gate dielectric layer (133) separates the gate electrode (137) from the semiconductor body (102). [6] Method according to any one of the preceding claims, wherein a maximum implantation energy level of the second implantation process is at most 2000 kiloelectronvolts. [7] Method according to any one of the preceding claims, wherein a difference between a first vertical distance (D1) and a second vertical distance (D2) is at most 200 nanometers, the first vertical distance (D1) corresponds to a distance between a vertical position of a top surface of the first region (180A, 182A) of the current propagation region and a vertical position of the top surface of the semiconductor body (102) and the second vertical distance (D2) corresponds to a distance between a vertical position of a top of the second region (182A) of the current propagation area and a vertical position of a bottom of the gate structure (101). [8] Method according to any one of the preceding claims, wherein the semiconductor body (102) a silicon carbide substrate, hereinafter referred to as SiC substrate, and / or has an epitaxial SiC layer that lies above the SiC substrate. [9] Method according to any of the preceding claims, wherein the implanted region of the first conductivity type and the current propagation region form a pn junction. [10] Method according to any of the preceding claims, wherein the implantation of the first dopants and the implantation of the second dopants are carried out simultaneously. [11] A method according to any of the preceding claims, comprising: Selecting one or more parameters associated with a top of the first area (180A, 182A) of the current propagation area adjacent to the body area (130), wherein the second implantation process is performed using one or more parameters and one or more parameters may include a number of ion implantation shots, an implantation energy level and / or an ion implantation dose. [12] A method according to any of the preceding claims, comprising: Selecting one or more parameters associated with a vertical position of a bottom of the first region (180A, 182A) of the current propagation domain that is lower than or equal to a vertical position of a top of the second region (180B, 182B) of the current propagation domain, wherein the second implantation process is performed using one or more parameters and one or more parameters may include a number of ion implantation shots, an implantation energy level and / or an ion implantation dose. [13] A method according to any of the preceding claims, comprising: Selecting one or more parameters associated with forming the first area (180A, 182A) of the current propagation area such that it extends from a first vertical position higher than a vertical position of the bottom of the trench (170) to a second vertical position equal to or lower than the vertical position of the bottom of the trench (170), wherein the second implantation process is performed using one or more parameters and one or more parameters may include a number of ion implantation shots, an implantation energy level and / or an ion implantation dose. [14] Method according to claim 4, wherein the third implantation process to form the body area (130) is carried out after the trench (170) has been formed, the third implantation process exhibits: Implanting third dopants through the upper surface of the semiconductor body (102) to form the body region (130); and Implanting fourth dopants through the bottom of the trench to create a first-type conductivity area, and the body area (130) lies above the first area of ​​the current propagation area and the area of ​​the first conductivity type lies above the second area (180B, 182B) of the current propagation area. [15] Method according to claim 4, wherein the third implantation process to form the body area (130) is carried out before the trench (170) is formed. [16] Method for manufacturing a semiconductor device comprising: Performing one or more first implantation processes to form an implanted area (116, 130, 146) of a first conductivity type in a semiconductor body (102); Performing a second implantation process, which includes implanting first dopants of a second conductivity type through an upper surface of the semiconductor body (102) to form a first region (180A, 182A) of a current propagation domain; Forming, after performing the second implantation process, a trench (170) in the semiconductor body (102); Perform, after forming the trench (170), a third implantation process comprising the implantation of a second dopant of the second conductivity type through a bottom of the trench (170) to form a second area (180B, 182B) of the current propagation domain; and Forming a gate structure (101) in the trench (170), wherein a vertical position of the first area (180A, 182A) of the current propagation area corresponds to a vertical position of the gate structure (170) and the second area (180B, 182B) of the current propagation area lies below the gate structure (101). [17] Semiconductor device comprising: comprising a semiconductor body (102): a body area (130) of a first conductivity type; a current propagation area of ​​a second conductivity type; and an implanted area (146, 116) of the first conductivity type; a trench-gate structure (101) in the semiconductor body (102) comprising a gate electrode (137) and a gate dielectric layer (133) separating the gate electrode (137) from the semiconductor body (102), wherein the implanted area (116) and the current propagation area form a pn junction, a vertical position of a first area (180A, 182A) of the stream propagation area corresponds to a vertical position of the trench-gate structure (101), the first area (180A, 182A) of the stream propagation area borders a first side wall (119) of the trench-gate structure (101), and the top of the first area (180A, 182A) of the stream propagation area borders the body area (130), a second area (180B, 182B) of the stream propagation area lies beneath the trench-gate structure (101), a difference between a first vertical distance (D1) and a second distance (D2) is at most 200 nanometers, the first vertical distance (D1) corresponds to a distance between a vertical position of a top surface of the first region (180A, 182A) of the current propagation region and a vertical position of a top surface of the semiconductor body (102) and the second vertical distance (D2) corresponds to a distance between a vertical position of a top of the second area (180B, 182B) of the stream propagation area and a vertical position of a bottom of the trench-gate structure (101). [18] Semiconductor device according to claim 17, comprising: a silicon carbide substrate, hereinafter referred to as SiC substrate, and / or an epitaxial SiC layer that lies above the SiC substrate. [19] Semiconductor device according to claim 17, wherein the implanted area borders on one of the first side walls (119) of the trench-gate structure (101) opposite the second side wall (121) of the trench-gate structure (101).

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