Procedure and system

Abstract

The present invention relates to a computer-implemented method for transmitting data, in particular in a flight control system, comprising the steps of: - Sending a synchronization signal by a first computing unit; - Receiving the synchronization signal by a second and / or a third processing unit at a separate reception time; - Transfer of first data from the third computing unit to the second computing unit, wherein the transfer of the first data takes place at a first transmission time which depends on the respective reception time of the reception of the synchronization signal by the second and / or third computing unit; - Transfer of the first and / or second data from the second computing unit to the first computing unit, whereby the transfer takes place at a second transmission time which depends on the respective reception time of the reception of the synchronization signal by the second and / or third computing unit.

Description

[0001] The present invention relates to a computer-implemented method for transmitting data, in particular in a flight control system.

[0002] Systems or system architectures for the transmission of data between computing units or for reading data into a computing unit from a large number of other computing units are known from the state of the art.

[0003] Such systems are known, for example, in flight control systems or flight control computers or “flight control computers” (FCC).

[0004] In Fig. Figure 3 shows an example of a known system or system architecture.

[0005] In this case, a first computing unit 1, for example in the form of a “central processing unit” (CPU) and / or a processor, is electrically connected to a plurality of second computing units 2, for example each in the form of a “field programmable gate array” (FPGA), each via a high-speed data bus B.

[0006] The high-speed data bus 3 is used for the electrical connection of the second processing units 2 to the first processing unit 1

[0007] It is thus known that individual second computing units, e.g. FPGAs, are connected to a first computing unit, e.g. a CPU, via a high-speed data bus, whereby each second computing unit can be individually controlled and / or read out by the first computing unit.

[0008] A high-speed data bus B is thus an electrical interface of the first processing unit 1, wherein the first processing unit 1 has three electrical interfaces. Fig. 3, the second computing unit 2 shown with a dashed line can optionally be connected to the first computing unit 1 via the high-speed data bus B shown with a dashed line.

[0009] The first processing unit 1, e.g., the CPU, is thus the communication master and has the corresponding number of high-speed data buses B to connect the second processing units 2, e.g., FPGAs, as communication slaves. The limited number of high-speed data buses B that a first processing unit can have results in a limitation of the maximum number of connectable second processing units 2. This consequently limits the number of electrical interfaces or connections, e.g., for sensors, that the system, e.g., in an FCC, can have.

[0010] Furthermore, the overhead for processing the data in the first processing unit 1, e.g., the CPU, is higher when multiple high-speed data buses B are controlled or processed. This reduces the performance of the first processing unit, for example, and increases the runtime for processing the data.

[0011] For example, in order to reduce costs, it is desirable to reduce the number of computers in systems or system architectures, especially in flight control systems, and to increase the number of functions per computer.

[0012] This means that systems or system architectures should have fewer computers, but each of them is more complex when viewed individually. This results in higher demands on the computing power or performance of the CPUs or primary computing units of the computers and an increased number of electrical interfaces that are read and processed by a computer, CPU, or primary computing unit.

[0013] It is desirable for systems, especially in FCC, to exhibit highly deterministic behavior with regard to the execution of software, as well as with regard to the processing of electrical interfaces, e.g., when reading sensors, controlling outputs, etc. To ensure this, deterministic data transmission, from the electrical input through a signal processing chain, with low latency and low temporal fluctuation (jitter), is required.

[0014] To minimize system delays, particularly high latency requirements are required. Especially for longer transmission distances, such as those across multiple FPGAs, a coordinated design is necessary to keep both latency and jitter as low as possible.

[0015] Against this background, the present invention is based on the object of providing a method which is improved compared to the above-mentioned method, in particular in order to connect an increased number of computing units to a first computing unit with a limited number of electrical interfaces.

[0016] This object is achieved by the method having the features of independent claim 1. Advantageous developments of the invention are the subject of the dependent claims.

[0017] Accordingly, the invention provides: A computer-implemented method for transmitting data, in particular in a flight control system, comprising the steps: - Sending a synchronization signal by a first computing unit; - Receiving the synchronization signal by a second and / or a third computing unit at a respective reception time; - transmitting first data from the third computing unit to the second computing unit, wherein the transmission of the first data takes place at a first transmission time which depends on the respective reception time of the reception of the synchronization signal by the second and / or third computing unit; - transmitting the first and / or second data from the second computing unit to the first computing unit, wherein the transmission takes place at a second transmission time which depends on the respective reception time of the reception of the synchronization signal by the second and / or third computing unit.

[0018] The term “time” is preferably to be interpreted broadly within the scope of the invention and includes, for example, a period of time or a time period.

[0019] In other words, data from any computing unit is preferably transferred to a first computing unit via one or more further computing units.

[0020] This allows data from any number of computing units to be transferred to them via a single electrical interface and / or a single data channel, e.g. a pin or connection of the first computing unit.

[0021] It is preferably provided that the first transmission time is a sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit, a first time offset and / or a time duration, in particular a collection of the first data and / or that the second transmission time is the sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit, a second time offset and / or a time duration, in particular a collection of the second data.

[0022] Preferably, the method comprises the step of transmitting the first data from the third computing unit to the second computing unit: - Collecting the first data by the third computing unit.

[0023] Preferably, the method comprises the step of transmitting the first and / or second data from the second computing unit to the first computing unit: - Collecting the second data by the second computing unit.

[0024] Collecting data includes, for example, reading a sensor, etc.

[0025] Preferably, it is provided that the collection of the first data takes place at a first collection time, which is a sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit and the first time offset, and / or that the collection of the second data takes place at a second collection time, which is a sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit and the second time offset.

[0026] It is preferably provided that the transmission of the first and / or the second data from the second computing unit to the first computing unit takes place via exactly one data channel, in particular a high-speed data bus.

[0027] The data channel preferably comprises an electrical interface.

[0028] Between the transmission and reception of the synchronization signal, a signal transmission of the synchronization signal can take place via the data channel and / or via a signal channel.

[0029] It is preferably provided that the steps of the method are carried out several times, in particular periodically.

[0030] It is preferably provided that the first and / or the second transmission time is adapted, in particular, to a latency time of the third and / or second computing unit.

[0031] The invention also relates to a system having a first, second and third computing unit, each of which is designed to carry out a method according to the invention.

[0032] The system preferably comprises a plurality of computing units, all of whose data can be transmitted to a first computing unit via a single data channel or an electrical interface.

[0033] The computing units are preferably communicative, e.g. connected via wires, e.g. via pins.

[0034] It is preferably provided that the first, second and / or third computing unit each comprise or represent a processor, in particular a CPU, an FPGA and / or an ASIC.

[0035] In particular, the second and / or third computing units can each comprise or represent, for example, an interface component, an input / output component, a field-programmable gate array (FPGA), and / or an application-specific integrated circuit (ASIC). The second and / or third computing units can each have an electrical connection, for example, for integrating a sensor.

[0036] It is preferably provided that the first, second and / or third computing unit are connected directly, i.e. in each case without an intermediate component and / or further computing unit, or indirectly, i.e. at least once in pairs via an intermediate component and / or a further computing unit, in particular in each case via a data channel, in particular a high-speed data bus.

[0037] The high-speed data bus can be, for example, a “Peripheral Component Interconnect Express” (PCIe).

[0038] Preferably, the system is part of a flight control system of an aircraft, in particular an airplane.

[0039] The invention also relates to a computer program which comprises instructions which cause the system according to the invention to carry out the method steps of the method according to the invention.

[0040] The invention also relates to a computer-readable medium on which the computer program according to the invention is stored.

[0041] The computing units, the data channel, and / or the signal channel preferably comprise or form a synchronized transmission path for transmitting data, with the possibility of optimizing latency by preparing the data at the latest possible time, in particular by adjusting a time offset. The system is, for example, an architecture that has transmission paths with multiple points.

[0042] Synchronous data transmission is preferred to minimize data transmission latency.

[0043] The invention preferably has the following advantages: - Preferably, the lowest possible latency and jitter are present; - Preferably, adaptation to the amount of data to be transmitted is carried out by adjusting a time offset; - Preferably, there is a possibility to adjust the transmission time(s) at which a transmission takes place, in particular depending on the respective computing unit; - Preferably, compensation can be made for line lengths of lines, data channels and / or signal channels that transmit the synchronization signal or the data and / or an amount of data to be transmitted and, accordingly, a duration of preparation of the data to be transmitted; - Preferably, a lower processing effort is required compared to a “star architecture”, as used, for example, in Fig. 3, in which multiple buses are controlled or processed by the first processing unit. This increases, for example, the performance of the first processing unit and reduces the runtime for data processing; - Preferably, there is no limitation due to the availability and / or the number of data buses of the first computing unit, e.g. the CPU; - Preferably, a flexible expansion of the system, in particular with additional computing units, can be carried out, in particular without affecting a software architecture and / or software drivers.

[0044] It should be noted here that the terms "a" and "an" do not necessarily refer to exactly one of the elements, although this represents a possible embodiment, but can also refer to a plurality of the elements. Likewise, the use of the plural also includes the presence of the element in question in the singular, and conversely, the singular also encompasses several of the elements in question. Furthermore, all features of the invention described herein can be combined with one another as desired or claimed in isolation from one another.

[0045] Further advantages, features, and effects of the present invention will become apparent from the following description of preferred embodiments with reference to the figures, in which identical or similar components are designated by the same reference numerals. Herein: Fig. 1: a flowchart of an embodiment of a method according to the invention. Fig. 2: a schematic block diagram of an embodiment of a system according to the invention. Fig. 3: a schematic block diagram of an embodiment of a system known from the prior art.

[0046] In Fig. 1 shows a time-optimized sequence of an embodiment of the method according to the invention, wherein a synchronization signal S is sent from a first computing unit to a second and third computing unit and is received by the second and third computing units, and wherein data is transmitted from the third to the second and from the second computing unit to the first computing unit.

[0047] The diagram in Fig. 1 has a timeline represented by a horizontal arrow, over which the steps of the method S1 to S4 are plotted in rows.

[0048] The vertical arrows represent the times at which the synchronization signals S are sent by the first computing unit and the times at which the synchronization signals S are received by the second and third computing units.

[0049] The first processing unit is a master and the second and third processing units are slaves.

[0050] The synchronization signal S is sent and received periodically.

[0051] At times t0, t0+1, t0+2, etc., where 1, 2, etc. are counters for the individual periods at which a synchronization signal S is sent, a synchronization signal S is sent and received.

[0052] As an example, the procedure for the first period is as follows: In step S1, first data is collected by the third computing unit at a first collection time, which is determined by adding the reception time t0 of the reception of the synchronization signal S by the third computing unit and a first time offset Offset1 or is a sum of the reception time t0 of the reception of the synchronization signal S by the third computing unit and a first time offset Offset1.

[0053] The first data is collected over a first time period TS1.

[0054] In step S2, second data is collected by the second computing unit at a second collection time, which is determined by adding the reception time t0 of the reception of the synchronization signal S by the second computing unit and a second time offset Offset2 or is a sum of the reception time t0 of the reception of the synchronization signal S by the second computing unit and a second time offset Offset2.

[0055] The second data is collected over a first time period TS2.

[0056] In step S3, the first data is transmitted or transferred from the third computing unit to the second computing unit.

[0057] The transmission of the first data from the third computing unit to the second computing unit takes place over a third time period TS3.

[0058] In step S4, the first and / or second data are transmitted or transferred from the second computing unit to the first computing unit.

[0059] The transmission of the first and / or second data from the second computing unit to the first computing unit takes place over a fourth time period TS4.

[0060] At time T, all data is present in the first computing unit.

[0061] There is a latency time Latency1 between the start of collecting the first data and time T.

[0062] There is a latency Latency2 between the start of collecting the second data and time T.

[0063] The latency times Latency1 and Latency1 depend, for example, on the computing units and the structure of the system or the transmission links, etc.

[0064] By adjusting the first time offset Offset1 and / or the second time offset Offset2, the time T can be shifted and / or adjusted or optimized.

[0065] The first period is followed by a second period, as can be seen from the repeated representation of the time periods TS1, TS2 and TS3 in the right area of Fig. 1.

[0066] In Fig. Figure 2 shows a basic or general structure of an embodiment of a system according to the invention and its transmission links. The system is part of an FCC.

[0067] The system has a first processing unit 1 in the form of a CPU. The first processing unit can also be referred to as the central processing unit.

[0068] The system further comprises a second and a third computing unit 2 and 3, each in the form of an FPGA.

[0069] The system can optionally be extended by additional computing units 4, which are indicated by the dashed boxes in Fig. 2. These extensions enable compliance with additional FCC requirements.

[0070] The first processing unit 1 is connected to the second processing unit 2 and the second processing unit 2 is connected to the third processing unit 3 via a Fig. 2 communicatively connected by a data channel indicated by a double arrow.

[0071] The optional computing units 4 can each be connected to one of the computing units 2 or 3 via a Fig. 2 can be communicatively connected via a data channel indicated by a double arrow. Several optional computing units 4 can be communicatively connected to one of the computing units 2 or 3.

[0072] The first computing unit 1 is connected to each computing unit 2, 3 and optionally 4 via a signal channel SK, which is designed to transmit synchronization signals.

[0073] The synchronization signals can also be transmitted via the data channel(s).

[0074] The first processing unit, as the communication master, provides a synchronization signal to all other processing units in the system. Depending on this synchronization signal, the respective data is prepared, e.g., collected and / or transmitted, at exactly the right time.

Claims

[1] Computer-implemented method for transmitting data, in particular in a flight control system, comprising the steps: - Sending a synchronization signal by a first computing unit; - Receiving the synchronization signal by a second and / or a third computing unit at a respective reception time; - transmitting first data from the third computing unit to the second computing unit, wherein the transmission of the first data takes place at a first transmission time which depends on the respective reception time of the reception of the synchronization signal by the second and / or third computing unit; - transmitting the first and / or second data from the second computing unit to the first computing unit, wherein the transmission takes place at a second transmission time which depends on the respective reception time of the reception of the synchronization signal by the second and / or third computing unit. [2] Computer-implemented method according to claim 1, characterized by that the first transmission time is a sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit, a first time offset and / or a time duration, in particular a collection of the first data and / or that the second transmission time is the sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit, a second time offset and / or a time duration, in particular a collection of the second data. [3] Computer-implemented method according to claim 1 or 2, characterized by that the method comprises the step of transmitting the first data from the third computing unit to the second computing unit: - Collecting the first data by the third computing unit. [4] Computer-implemented method according to one of the preceding claims, characterized by that the method comprises the step of transmitting the first and / or second data from the second computing unit to the first computing unit: - Collecting the second data by the second computing unit. [5] Computer-implemented method according to one of claims 2 to 4, characterized bythat the collection of the first data takes place at a first collection time, which is a sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit and the first time offset, and / or that the collection of the second data takes place at a second collection time, which is a sum of the reception time of the reception of the synchronization signal by the second and / or third computing unit and the second time offset. [6] Computer-implemented method according to one of the preceding claims, characterized by that the transmission of the first and / or the second data from the second computing unit to the first computing unit takes place via exactly one data channel, in particular a high-speed data bus. [7] Computer-implemented method according to one of the preceding claims, characterized by that the steps of the procedure are carried out several times, in particular periodically. [8] Computer-implemented method according to one of the preceding claims, characterized by that the first and / or the second transmission time is adapted, in particular, to a latency time of the third and / or second computing unit. [9] System comprising a first, second and third computing unit, each configured to carry out a method according to any one of the preceding claims. [10] System according to claim 9, characterized by that the first, second and / or third computing unit each comprise or represent a processor, in particular a CPU, an FPGA and / or an ASIC. [11] System according to claim 9 or 10, characterized by that the first, second and / or third computing unit are connected directly or indirectly, in particular via a data channel, in particular a high-speed data bus. [12] System according to one of claims 9 to 11, characterized bythat the system is part of the flight control system of an aircraft, in particular an airplane. [13] A computer program comprising instructions causing the system of any one of claims 9 to 12 to carry out the method steps of the method of any one of claims 1 to 8. [14] A computer-readable medium on which the computer program according to claim 13 is stored.

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