INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE SOURCE OR DRAIN CONTACT SELECTIVE

Abstract

Integrated circuit structures with backside source or drain contact selectivity are described. In one example, an integrated circuit structure includes a first epitaxial source or drain structure at one end of several horizontally stacked nanowires or a fin, with a first conductive source or drain contact vertically below and in contact with a bottom side of the first epitaxial source or drain structure, and with a first hard mask material below and in contact with the first conductive source or drain contact.A second epitaxial source or drain structure is located at one end of two multiple horizontally stacked nanowires or a fin, with a second conductive source or drain contact vertically below and in contact with a bottom side of the second epitaxial source or drain structure and a second hard mask material below and in contact with the second conductive source or drain contact.

Description

TECHNICAL FIELDEmbodiments of the disclosure relate to the field of advanced integrated circuit structure fabrication, and more particularly to integrated circuit structures having a back-side source or drain contact selectivity.BACKGROUNDIn recent decades, the scaling of features in integrated circuits has been a driving force behind a steadily growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited useful area of semiconductor chips. For example, reducing the transistor size allows for the inclusion of a larger number of memory or logic devices on a chip, which lends itself to the fabrication of products with increased capacity. However, the development towards increasingly large capacities also entails problems. The need to optimize the performance of each device is becoming increasingly important.Variability in conventional and currently known manufacturing processes may limit the ability to extend it to within the range of the 10-nanometer node or the sub-10-nanometer node. Thus, manufacturing the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies into current manufacturing processes or instead of current manufacturing processes.In the fabrication of integrated circuit devices, multiple gate transistors, such as tri-gate transistors, have become more prevalent with continuous downscaling of device dimensions. Tri-gate transistors are generally fabricated on either bulk silicon substrates or on silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred at high yield due to their lower cost and compatibility with the existing bulk silicon substrate infrastructure.However, the scaling of multiple gate transistors was not without consequences. With the reduction in the dimensions of these basic devices of microelectronic circuitry and the increase in the clean number of basic devices fabricated in a given area, the limitations on the semiconductor processes used to fabricate these devices have become prevalent.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates cross-sectional views of a front-side power-delivery interconnect stack and a back-side power-delivery interconnect stack, according to an embodiment of the present disclosure. FIGS. 2-3, 4A-4E, and 5-8 illustrate oblique cross-sectional views representing various operations in methods of fabricating an integrated circuit structure having back-side source or drain contact selectivity, according to an embodiment of the present disclosure. FIG. 9 illustrates cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a back-side source or drain implant and contact selectivity, according to an embodiment of the present disclosure. FIG. 10A illustrates a top view of a semiconductor device having a gate contact disposed over a non-active portion of a gate electrode. FIG. 10B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over a non-active portion of a gate electrode. FIG. 11A illustrates a top view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. FIG. 11B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. FIGS. 12A-12J illustrate cross-sectional views of various operations in a method of fabricating a gate all around structure of an integrated circuit, according to an embodiment of the present disclosure. FIG. 13 illustrates a computing device according to an implementation of the disclosure. FIG. 14 illustrates an interposer that includes one or more embodiments of the disclosure. FIG. 15 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure. FIG. 16 illustrates a cross-sectional view of a flip-chip-mounted die according to an embodiment of the present disclosure.DESCRIPTION OF THE EMBODIMENTSIntegrated circuit structures having back-side source or drain contact selectivity are described. In the following description, numerous specific details, such as specific integration and material regimens, are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be understood by those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order not to unnecessarily obscure embodiments of the present disclosure. It will also be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration.". Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, summary, or detailed description below.This description includes references to "one embodiment" or "an embodiment.". The appearances of the phrases "in exactly one embodiment" or "in one embodiment" are not necessarily referring to the same embodiment. Certain features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.Terminology. The following paragraphs provide definitions or context for terms that occur in this disclosure (including the appended claims):"Comprising" This term is to be understood as open ended. As used in the appended claims, this term does not exclude additional structure or operations."Configured to" Various units or components may be described or claimed as "configured to" perform a task or tasks. In such contexts, "configured to" is used to imply a structure by indicating that the units or components include a structure that performs that task or tasks during operation. As such, the unit or component may be said to be configured to perform the task even if the specified unit or component is currently not ready for use (e.g., not powered on or active). Expressly, indicating that a unit or circuit or component is "configured to" perform one or more tasks is not intended to invoke 35 U.S.C. § 112 sixth paragraph on that unit or component."First," "Second," etc. As four are used, these terms are used as labels for sounds they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.)."Coupled" - The following description refers to elements or nodes or features that are "coupled" to each other. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.In addition, certain terminology may also be used in the following description for the purpose of reference only and accordingly is not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "back," "side," "outside of the circuit board," and "inside the circuit board" describe the orientation or position, or both, of portions of the component within a consistent but arbitrary frame of reference made clear by reference to the text and associated drawings describing the component being discussed. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import."Inhibit" - As used herein, prevent is used to describe a reduction or minimization effect. When a component or feature is described as inhibiting an action, motion, or condition, it / she may completely prevent the result or result or future state. Additionally, "inhibit" may also refer to a reduction or reduction in the result, performance, or effect that might otherwise occur. Accordingly, when a component, element, or feature is referred to as inhibiting a result or condition, it does not need to completely prevent or eliminate the result or condition.Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of an integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers all up to (but not including) the deposition of metal interconnection layers. Following the last FEOL operation, the result is typically an insulated transistor wafer (e.g., without any wires).Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of an IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, isolation layers (dielectrics), metal planes, and bonds for chip-package interconnects. In the BEOL portion of the fabrication stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Although an example processing scheme using an FEOL processing scenario may be illustrated, such approaches may be particularly applicable to BEOL processing as well. Likewise, although an example processing scheme using a BEOL processing scenario may be illustrated, such may also be particularly applicable to FEOL processing.One or more embodiments relate to coloring (selectivity) for back-side source or drain contact structures, e.g., using dual epitaxial (epi) back-side contacts. One or more embodiments described herein relate to gate all around integrated circuit structures fabricated using backside hardmask selectivity or coloring. It should be understood that unless otherwise indicated, reference to nanowires herein may indicate nanowires or nanoribbons or nanoplates or sheets. One or more embodiments described herein relate to fin-based integrated circuit structures fabricated using backside hardmask selectivity or staining. In one embodiment, a back contact staining scheme with single pass front side processing to enable cell height scaling is described. In one embodiment, a back side contact coloring scheme for facilitating patterned PMOS and NMOS implants and patterned contact metallization is described.To provide context, as cell heights are scaled, an edge placement error (EPE) for a BM0 connection decreases to a right color back contact (Ex: NEPI vs. PEPI). In addition, the simultaneous scaling of the poly pitch increases the importance of contact resistance reduction by factors such as selection of epitaxial etch, implant species, and contact metallization, which may be different for contacts of different colors. Although patterning schemes for enabling independent selection of PMOS and NMOS epitaxial etches, implants, and contact metal for front side contacts are well known, patterning schemes that enable the same for back side contacts are limited by bond distortions that set a high lower limit for pattern registration errors. A coloring scheme presented herein attenuates these two problems without requiring changes to front end processing.According to one or more embodiments of the present disclosure, a coloring scheme is described in which NMOS and PMOS are opened, etched, implanted, and metallized independently on the backside without any front side processing changes, and then colored after contact metallization to increase the BM0to backside contact EPE tolerance that decreases as the cell height is further scaled to smaller dimensions. To be compatible with the minimum registration and absolute maximum error achievable on the backside with bond distortions, this method involves that the backside pad holder material is isotropically removable from the backside, so that the lithographic patterning need only expose a narrow region of the place holder material for the backside contact to enable the removal. For post-contact coloring to increase the BM0 to back contact EPE, two fillable materials are required that can be selectively etched to each other and to other materials exposed after a BM0 etch.To provide a wider context, low electrical resistance power delivery solutions are needed because semiconductor scaling continues to clamp interconnects into increasingly narrower spaces. Back side power delivery, a scheme in which a power delivery interconnect network is directly connected to the transistors from the back side of the wafer, rather than sharing space with front side routing, is a possible solution for future semiconductor technology generations.Typically, power is supplied from a front side interconnect. At the standard cell level, power may be provided directly above transistors or from upper and lower cell boundaries. Power provided by upper and lower cell boundaries allows for a relatively shorter standard cell height with slightly higher power network resistance. However, a front side power network shares the interconnect stack with signal routing and reduces signal routing lanes. Additionally, for high power designs of the upper and lower cell boundaries, power metal wires must be wide enough to reduce power network resistance and improve performance. This normally leads to an increase in cell height. According to one or more embodiments of the present disclosure, delivering power from a wafer or substrate backside may be implemented to solve area and performance problems. At the cell level, performance of a wider metal 0 at the upper and lower cell boundaries may no longer be required and thus the cell height may be reduced. In addition, the power network resistance may be significantly reduced, resulting in performance improvement. At the block and chip level, front-side signal routing traces are increased due to the eliminated power routing and the power network resistance is significantly reduced due to very wide wires, large vias, and reduced interconnect layers.In previous technologies, a bump-to-transistor power delivery network required significant block resources. Such resource usage on the metal stack has come to be expressed in some process nodes as standard cell architectures with layout versioning or limitations of cell placement at the block level. In one embodiment, removing the power delivery network from the front side metal stack allows free sliding cell placement in the block without power delivery complications and placement-induced delay time variation.As an example comparison, FIG. 1 illustrates cross-sectional views of a front-side power-delivery interconnect stack and a back-side power-delivery interconnect stack, according to an embodiment of the present disclosure.Referring to FIG. 1, a front-side power-supply interconnect stack 100 includes a transistor 102 and signal and power-supply metallization 104. The transistor 102 includes a bulk substrate 106, semiconductor fins 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes conductive vias 114, conductive lines 116, and a metal bump 118.Referring again to FIG. 1, a back-side power-supply interconnect stack 150 includes a transistor 152, a front-side signal metallization 154A, and a power-supply metallization 154B. Transistor 152 includes semiconductor nanowires or nanoribbons 158, terminal 160 and device contact 162, and deep boundary via 163. Front side signal metallization 154A includes conductive vias 164A, conductive lines 166A, and a metal bump 168A. The power delivery metallization 154B includes conductive vias 164B, conductive lines 166B, and a metal bump 168B. It is understood that a backside power approach may also be implemented for structures including semiconductor fins.To provide further context, a basic component of a back side power delivery network is an electrically functional feature that couples the source or drain contacts of a transistor to the back side interconnect network. Therefore, a design and method for fabricating an interface feature compatible with existing library cell design conventions and transistor contact process flows is required.Currently, there are no solutions used in high volume manufacturing because back side power delivery has not yet been introduced in high volume manufacturing. Approaches may ultimately include deep trench contact (TCN), direct source-drain contacts from the back side, or replacement of a gate contact trace with a back side power contact. Depending on the proposed scheme, solutions may suffer from high resistance contacts that negate the inherent value of cooptimizing back side power delivery with front-end transistor processing, leading to defects, performance risks, and degradation.In a first aspect, a back side contact staining scheme with single pass front side processing to enable cell height scaling is described.According to an embodiment of the present disclosure, back side connections to the gates and / or sources / drains may be formed. In certain embodiments, a hard mask "color" is used for selectivity in the fabrication of such a compound.As an example processing scheme, FIGS. 2-3, 4A-4E, and 5-8 illustrate cross-sectional oblique views representing various operations in methods of fabricating an integrated circuit structure having back-side source or drain contact selectivity, according to an embodiment of the present disclosure. It should be appreciated that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires or nanoribbons or nanoplates or sheets.Referring to FIG. 2, a starting structure 200 includes a plurality of horizontally stacked nanowires (or nanoribbons or nanoplates or forksheets, or alternatively a fin) 202, each over a corresponding sub-fin 204 on a substrate 201, such as silicon nanowires over a silicon sub-fin on a silicon substrate. A corresponding gate stack 206, such as a stack including a metal gate electrode and a high-k gate dielectric layer, is over and around each of the plurality of horizontally stacked nanowires 202. Alternatively, the gate stacks 206 may be dummy gate stacks at this stage. A gate cap dielectric layer 207, such as a silicon nitride cap, may be present on each gate stack 206. Dielectric sidewall spacers 208, such as silicon nitride or carbon doped silicon nitride spacers, are located along the sides of each gate stack 206 and may be maintained by various processing operations over each gate stack 206 (along with an optional helmet layer). A shallow trench isolation structure 210, such as a silicon oxide isolation structure, adjoins the sub-fin 204. A cavity 212 is located between gate stacks at locations where source or drain structures are ultimately to be formed. The gate stacks 206 may be used as a mask to etch trenches into exposed portions of the fins (e.g., nanowire formation fins), e.g., in source and drain regions of the fins, forming the illustrated structure with voids 212. In one embodiment, the etching extends at least partially into or even completely through the sub-fins 204.Referring to FIG. 3, an etch below the source or drain locations is extended for later backside contact formation. For example, an etch is extended into source or drain locations and then first conductive source or drain contacts 214 (e.g., deep titanium nitride via structures) are formed at these locations, e.g., by a deposition and etchback process.Following fabrication of the structure of FIG. 3, epitaxial source or drain structures are formed, front side processing is completed, the structure is reversed, and back side exposure is performed.As an example resulting structure, structure 400 of FIG. 4A is shown back up of the exposure. The structure 400 includes a front side carrier 402, a front side BEOL structure 404 and gate stacks 410. Epitaxial source or drain structures 406 and 408, such as silicon germanium or epitaxial silicon source or drain structures (or vice versa), are then received in trenches between the gate stacks 410 at the ends of nanowires (or fins). The first source or drain conductive contacts 412 (which may be place holder structures) are over the epitaxial source or drain structures 406 and 408 and were exposed by the backside exposure. A patterning stack 414 is formed and patterned on the exposed back side.Referring to FIG. 4B, selected ones of the first conductive source or drain contacts 412 are removed, e.g., by a masking and etching process, to form voids 416. Other of the first source or drain conductive contacts 412 are retained. In one embodiment, the first source or drain conductive contacts 412 are removed at n-type locations while the first source or drain conductive contacts 412 are maintained at p-type locations. In another embodiment, the first source or drain conductive contacts 412 are removed at p-type locations while the first source or drain conductive contacts 412 are maintained at n-type locations. The patterning stack 414 may be reduced to a patterning stack 414A, as shown.Referring to FIG. 4C, the cavities 416 may be etched to form cavities 418, which may be wider than the cavities 416.Referring to FIG. 4D, second conductive source or drain contacts 420 (e.g., deep tungsten via structures) are formed in the cavities 418, e.g., by a deposition and etching process.Referring to FIG. 4E, the second source or drain conductive contacts 420 are selectively recessed, e.g., based on metal selectivity, to form recessed second source or drain conductive contacts 420A. A "coloring" dielectric or hard mask material 422 such as silicon nitride is then formed in the recesses, e.g., using a deposition and planarization process.Referring to FIG. 5, the structure 500 is shown in mirror image perspective to FIG. 4E, in which the remaining ones of the first source or drain conductive contacts 412 are removed, e.g., by a selective etching process, to form voids 424.Referring to FIG. 6, the cavities 424 may be etched to form cavities 426 that may be wider than the cavities 424.Referring to FIG. 7, third conductive source or drain contacts 428 (e.g., deep tungsten via structures) are formed in the cavities 426, e.g., by a deposition and etching process.Referring to FIG. 8, a structure 800 is formed by selectively recessing the third source or drain conductive contacts 428 to form recessed third source or drain conductive contacts 428A, e.g., based on metal selectivity. A "coloring" dielectric or hard mask material 430, such as silicon carbide, is then formed in the recesses, e.g., using a deposition and planarization process. In an embodiment, the hard mask material 430 has a different composition than the hard mask material 422 to provide an etch selectivity between the locations of the epitaxial source or drain structure 406 and the locations of the epitaxial source or drain structure 408.It should be appreciated that for further processing, a hard mask location 422 or 430 may be selectively removed to expose contact to the epitaxial source or drain structures 406 or 408, respectively. For example, a bottom ILD may be deposited, patterned, and etched, and vias may be metallized, connecting BM0to selected ones of the epitaxial source or drain structures 406 or 408. It should be appreciated that such a via may not extend the entire length of the epitaxial source or drain structure 406 or 408, and thus portions of the corresponding "colored" hard mask material 422 or 430 may remain on the corresponding recessed second source or drain conductive contacts 420A or recessed second source or drain conductive contacts 428A at locations into and / or out of the page.In a second aspect, a back side contact coloring scheme for facilitating patterned PMOS and NMOS implants and patterned contact metallization is described.To provide context, future power benchmarks for devices may require a reduction in contact resistance by a combination of an increased contact area and a reduced contact metal epitaxy interface resistance. The contact area can be increased by an epitaxial etching, wherein the optimum for NMOS and PMOS can be different. The contact metal epitaxy interface resistance can be reduced by ion implantations that induce amorphization of epitaxy followed by recrystallization and by the choice of contact metals. Patterning schemes for enabling independent selection of PMOS and NMOS epitaxial etches, implants and contact metal for front side contacts are well known, but patterning schemes that enable the same for back side contacts are limited by bond distortions that set a high lower limit for pattern registration errors. According to one or more embodiments of the present disclosure, a coloring scheme for back contacts overcoming this limitation is described.Previous solutions do not allow patterned epitaxial etching, ion implantation, and contact metallization for back side contacts. A power contact flow according to the prior art only allows a single epitaxial etch, surface covering ion implantation and a single contact metal selection. Further reductions in contact resistance may require patterned NMOS and PMOS epitaxial etching, ion implantation, and contact metallization.According to an embodiment of the present disclosure, a coloring scheme is described in which NMOS and PMOS back side contacts may be opened, etched, implanted, and metallized independently of each other, because different filler materials are used for NMOS and PMOS, which may be selectively removed from each other. The amount of filler materials that can be used is limited to materials that (1) can fill without voids and (2) can be recessed at this point in the flow without damage to exposed materials (e.g., gate, spacers, etc.), (3) are compatible with epitaxial deposition, and (4) can be selectively removed from each other and from materials exposed after back-side uncovering.As an example processing scheme, FIG. 9 illustrates cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a back-side source or drain implantation and contact selectivity, according to an embodiment of the present disclosure.Referring to part (a) of FIG. 9, an output structure 900 includes an n-type source or drain structure 902, a p-type source or drain structure 906, a first contact place holder 904, and a differentiated second contact place holder 908.Referring to part (b) of FIG. 9, a structure 900 ais obtained after inverting and back exposing the structure 900 and removing the second contact pad holder 908. An implantation process 912, such as a B / Ge implantation process, is performed into the exposed p-type source or drain structure 906.Referring to part (c) of FIG. 9, a contact interface 914 and a contact metal 916 are formed on the exposed and implanted p-type source or drain structure 906.Referring to part (d) of FIG. 9, the second place holder 904 is removed. An implantation process 918, such as a P / As implantation process, is performed into the exposed n-type source or drain structure 902.Referring to part (e) of FIG. 9, a contact interface 918 and a contact metal 920 are formed on the exposed and implanted n-type source or drain structure 902.It will be appreciated that the above-described two-material approach may be detectable in end products. Cross-sections may show different contact "colors" having different heights (due to different pad material recess operations). The final appearance may deviate from previous approaches in that the dimensions between different contact colors may match a front structure registration error that is significantly smaller than would appear due to a back structure registration error. Cross-sections may also show remaining coloring dielectric materials outside the vias, i.e., the coloring dielectric materials may also remain in non-contacted regions. Cross-sections may include different epitaxial etch profiles, implant species, and contact metals in adjacent NMOS and PMOS backside contacts that are closer than they can be reliably patterned on the backside due to bond distortions. It should be appreciated that although the above figures depict gate-all-around-based transistors, embodiments may be applied to channels of any shape or material (fin, nanowire, nanoribbon, nano comb / formsheet, etc.). It should be appreciated that although the figures show a single layer of transistors, embodiments may be applied to multi-layer transistor architectures. It should be appreciated that although the figures show that all back side contact regions are metallized and covered with a dielectric, back side contact regions that do not require active interconnects may be depopulated with a patterning operation prior to back side contact metallization (i.e., fill non-active regions with dielectric).It should be appreciated that, as used throughout the disclosure, a sub-fin, nanowire, nanoribbon, or fin described herein may be a silicon sub-fin, silicon nanowire, silicon nanoribbon, or silicon fin. As used throughout, a silicon layer or structure may be used to describe a silicon material that consists of a very substantial amount, if not all, of silicon. However, it should be appreciated that practically 100% pure Si may be difficult to form and therefore could include a minute percentage of carbon, germanium or tin. Such impurities may be contained as inevitable impurities or a component during deposition of Si, or may "contaminate" the Si upon diffusion during post-deposition processing. Thus, embodiments described herein relating to a silicon layer or structure may include a silicon layer or structure containing a relatively small amount, e.g., an "impurity level", of non-Si atoms or species, such as Ge, C, or Sn. It will be appreciated that a silicon layer or structure as described herein may be undoped or doped with dopant atoms such as boron, phosphorus or arsenic.It should be appreciated that, as used throughout the disclosure, a sub-fin, nanowire, nanoribbon, or fin described herein may be a silicon germanium sub-fin, silicon germanium nanowire, silicon germanium nanoribbon, or silicon germanium fin. As used throughout, a silicon germanium layer or structure may be used to describe a silicon germanium material that consists of substantial portions of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In particular embodiments, a silicon germanium layer or structure includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60). In other embodiments, the amount of silicon is greater than the amount of germanium. In particular embodiments, a silicon germanium layer or structure includes approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30). It should be appreciated that practically 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and therefore could include a minute percentage of carbon or tin. Such impurities may be contained as inevitable impurities or a component during deposition of SiGe, or may "contaminate" the SiGe upon diffusion during post-deposition processing. Thus, embodiments described herein relating to a silicon germanium layer or structure may include a silicon germanium layer or structure containing a relatively small amount, e.g., an "impurity level", of non-Ge and non-Si atoms or species, such as carbon or tin. It will be appreciated that a silicon germanium layer or structure as described herein may be undoped or doped with dopant atoms such as boron, phosphorus or arsenic.In another aspect, it is understood that back-side source or drain contact selectivity may be implemented with front-side architectures. In one example, the back-side source or drain contact selectivity may be implemented with contact over active gate (COAG) structures and processes. It is also understood that "color" hard mask COAG features below may be applicable to concepts related to the back side contacts described above. One or more embodiments of the present disclosure relate to semiconductor structures or devices having one or more gate contact structures (e.g., as gate contact vias) disposed over active portions of gate electrodes of the semiconductor structures or devices. One or more embodiments of the present disclosure relate to methods of fabricating semiconductor structures or devices having one or more gate contact structures formed over active portions of gate electrodes of the semiconductor structures or devices. Approaches described herein may be used to reduce standard cell area by allowing gate contact formation over gate active regions. According to one or more embodiments, tapered gate and trench contacts are implemented to enable COAG fabrication. Embodiments may be implemented to enable patterning with tight snap-fit fashion.To provide further background to the importance of a COAG processing scheme, in technologies where space and layout constraints are somewhat looser compared to current generation space and layout constraints, contact to a gate structure may be made by making contact to a portion of the gate electrode that is disposed over an isolation region. As an example, FIG. 10A illustrates a top view of a semiconductor device having a gate contact disposed over a non-active portion of a gate electrode.Referring to FIG. 10A, a semiconductor structure or device 1000A includes a diffusion or active region 1004 disposed in a substrate 1002 and within an isolation region 1006. One or more gate lines (also known as poly lines), such as gate lines 1008A, 1008B, and 1008C, are disposed over the diffusion or active region 1004 as well as over a portion of the isolation region 1006. Source or drain contacts (also known as trench contacts), such as contacts 1010A and 1010B, are disposed over source and drain regions of the semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B provide contact to trench contacts 1010A and 1010B, respectively. A separate gate contact 1014, and an overlying gate contact via 1016, provide contact to gate line 1008B. In contrast to the source or drain contacts 1010A or 1010B, the gate contact 1014 is arranged over the isolation region 1006, but not over the diffusion or active region 1004, in a plan view perspective. Furthermore, neither the gate contact 1014 nor the gate contact via 1016 is arranged between the source or drain trench contacts 1010A and 1010B.FIG. 10B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over a non-active portion of a gate electrode. Referring to FIG. 10B, a semiconductor structure or device 1000B, e.g., a non-planar version of the device 1000A of FIG. 10A, includes a non-planar diffusion or active region 1004B (e.g., a fin structure) formed by the substrate 1002 and within the isolation region 1006. The gate line 1008B is disposed over the non-planar diffusion or active region 1004B as well as over a portion of the isolation region 1006. As shown, gate line 1008B includes a gate electrode 1050 and a gate dielectric layer 1052 along with a dielectric cap layer 1054. The gate contact 1014 and the overlying gate contact via 1016 are also seen from this perspective along with an overlying metal interconnect 1060, all of which are disposed in interlayer dielectric stacks or layers 1070. Also, when viewed from the perspective of FIG. 10B, the gate contact 1014 is disposed over the isolation region 1006, but not over the non-planar diffusion or active region 1004B.Referring again to FIGS. 10A and 10B, in the arrangement of the semiconductor structure or device 1000A and 1000B, respectively, the gate contact is placed over the isolation regions. Such an arrangement wastes layout space. However, placing the gate contact over active regions would either require an extremely close coverage accuracy budget or gate dimensions would have to increase to provide sufficient space for arranging the gate contact. Furthermore, contact to a gate over diffusion regions has been historically avoided because of the risk of drilling through other gate material (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address the above problems by providing feasible approaches and the resulting structures to fabricate contact structures that contact portions of a gate electrode formed over a diffusion or active region.As an example, FIG. 11A illustrates a top view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. Referring to FIG. 11A, a semiconductor structure or device 1100A includes a diffusion or active region 1104 disposed in a substrate 1102 and within an isolation region 1106. One or more gate lines, such as gate lines 1108A, 1108B, and 1108C, are disposed over the diffusion or active region 1104 as well as over a portion of the isolation region 1106. Source or drain contacts, such as contacts 1110A and 1110B, are disposed over source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B provide contact to trench contacts 1110A and 1110B, respectively. A gate contact via 1116 without an intervening separate gate contact layer provides contact to gate lines 1108B. In contrast to FIG. 10A, from a plan view perspective, the gate contact 1116 is disposed over the diffusion or active region 1104 and between the source or drain contacts 1110A and 1110B.FIG. 11B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. Referring to FIG. 11B, a semiconductor structure or device 1100B, e.g., a non-planar version of the device 1100A of FIG. 11A, includes a non-planar diffusion or active region 1104B (e.g., a fin structure) formed by the substrate 1102 and within the isolation region 1106. The gate line 1108B is disposed over the non-planar diffusion or active region 1104B as well as over a portion of the isolation region 1106. As shown, gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152 along with a dielectric cap layer 1154. The gate contact via 1116 is also seen from this perspective along with an overlying metal interconnect 1160, both of which are disposed in interlayer dielectric stacks or layers 1170. Also, when viewed from the perspective of FIG. 11B, the gate via 1116 is disposed over the non-planar diffusion or active region 1104B.Accordingly, referring again to FIGS. 11A and 11B, in one embodiment, the trench contact vias 1112A, 1112B and the gate contact via 1116 are formed in a same layer and are substantially coplanar. Otherwise, compared to FIGS. 10A and 10B, the contact to the gate line would include an additional gate contact layer, e.g., which could be perpendicular to the corresponding gate line. However, in the structure(s) described in association with FIGS. 11A and 11B, the fabrication of structures 1100A and 1100B, respectively, enables the placement of a contact directly from a metal interconnect layer on an active gate portion without short circuit to adjacent source-drain regions. In one embodiment, such an arrangement provides a large area reduction in circuit layout by eliminating the need for transistor gates to extend on insulation to form a reliable contact. As used throughout, in one embodiment, reference to an active portion of a gate refers to that portion of a gate line or structure that is disposed (from a plan view perspective) over an active or diffusion region of an underlying substrate. In an embodiment, reference to an inactive portion of a gate refers to that portion of a gate line or structure disposed over an isolation region of an underlying substrate (from a plan view perspective).In an embodiment, the semiconductor structure or device 1100 is a non-planar device, such as, but not limited to, a fin FET or tri-gate device. In such an embodiment, a corresponding semiconducting channel region consists of or is formed in a three-dimensional body. In such an embodiment, the gate electrode stacks of gate lines 1108A and 1108B surround at least a top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is fabricated to be a discrete three-dimensional body, as in a gate all around device. In such an embodiment, the gate electrode stacks of gate lines 1108A and 1108B completely surround the channel region, respectively.In general, one or more embodiments relate to approaches to, and structures formed from, providing a gate contact via directly on an active transistor gate. Such approaches may eliminate the need for extending a gate line on an insulation for contact purposes. Such approaches may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from a gate line or structure. In an embodiment, the removal of the above features is achieved by recessing contact metals in a trench contact (TCN) and introducing an additional dielectric material in the process flow (e.g., trench isolation layer (TILA)). The additional dielectric material is included as a trench contact dielectric cap layer having etch characteristics different from the gate dielectric material cap layer used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., using a gate isolation layer (GILA)).As an example fabrication scheme, a starting structure includes one or more gate stack structures disposed above a substrate. The gate stack structures may include a gate dielectric layer and a gate electrode. Trench contacts, e.g. contacts to diffusion regions of the substrate or to an epitaxial region formed within the substrate, are spaced apart from gate stack structures by dielectric spacers. An isolation cap layer may be disposed on the gate stack structures (e.g., GILA). In an embodiment, contact blocking regions or "contact plugs" that may be made of an interlayer dielectric material are included in regions where contact formation is to be blocked.In one embodiment, the contact pattern is substantially perfectly aligned with an existing gate pattern while eliminating the use of a lithography process with an extremely close coverage accuracy budget. In such an embodiment, this approach enables using an intrinsically highly selective wet etch (or anisotropic dry etch processes), some of which are isotropic gas phase etch without plasma (e.g., versus classic dry or plasma etch) to create contact openings. In an embodiment, a contact structure is formed by utilizing an existing gate structure in combination with a contact plug lithography process. In such an embodiment, the approach enables the need for an otherwise critical lithography operation to create contact patterning as used in other approaches to be eliminated. This also allows perfect or nearly perfect self-alignment with a larger edge placement error margin. In an embodiment, a trench contact grid is not separately patterned, but is instead formed between poly (gate) lines. For example, in such an embodiment, a trench contact grid is formed subsequent to the gate grid patterning but prior to gate grid intersections.Furthermore, the gate stack structures may be manufactured by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process, rather than being adopted from prior processing. In one embodiment, dummy gates are removed by a dry etching or wet etching process. In one embodiment, dummy gates are formed of polycrystalline silicon or amorphous silicon and are removed by a dry etching process including SF 6. In another embodiment, dummy gates are formed of polycrystalline silicon or amorphous silicon and are removed by a wet etching process including aqueous NH 4 OH, or tetramethylammonium hydroxide. In one embodiment, dummy gates are made of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.In one embodiment, one or more approaches described herein substantially provide a dummy or replacement gate process in combination with a dummy and replacement contact process. In such an embodiment, the replacement contact process is performed after the replacement gate process to enable high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing at least a portion of the permanent gate structures is performed at a temperature higher than approximately 600 degrees Celsius, e.g., after a gate dielectric layer is formed. The anneal is performed prior to the formation of the permanent contacts.Next, the trench contacts may be recessed to provide recessed trench contacts having a height below the top surface of adjacent spacers. An isolation cap layer is then formed on the recessed trench contacts (e.g., TILA). According to an embodiment of the present disclosure, the isolation cap layer on the recessed trench contacts is made of a material having a different etch characteristic than the isolation cap layer on the gate stack structures.The trench contacts may be selectively recessed from the materials of the spacers and the gate isolation cap layer by a process. For example, in an embodiment, the trench contacts are recessed by an etching process, such as a wet etching process or a dry etching process. The trench contact isolation cap layer may be formed by a process suitable for providing a conformal and sealing layer above the exposed portions of the trench contacts. For example, in one embodiment, the trench contact isolation cap layer is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, e.g., by chemical mechanical polishing (CMP), to provide the trench contact isolation cap layer material only above the recessed trench contacts.With regard to suitable material combinations for gate or trench contact isolation cap layers, in one embodiment, one of the pair of gate versus trench contact isolation cap material is silicon oxide while the other is silicon nitride. In another embodiment, one of the pair of gate to trench contact isolation cap material is made of silicon oxide while the other is made of carbon doped silicon nitride. In another embodiment, one of the pair of gate versus trench contact isolation cap material is made of silicon oxide while the other is made of silicon carbide. In another embodiment, one of the pair of gate to trench contact isolation cap material is made of silicon nitride while the other is made of silicon nitride doped with carbon. In another embodiment, one of the pair of gate to trench contact isolation cap material is made of silicon nitride while the other is made of silicon carbide. In another embodiment, one of the pair of gate to trench contact isolation cap material is carbon doped silicon nitride while the other is silicon carbide.In another aspect, back-side source or drain contact selectivity is implemented with nanowire or nanoribbon structures. In a particular example, nanowire or nanoribbon exposure processing may be performed by a replacement gate trench. Examples of such exposure processes are described below. Additionally, in yet another aspect, backend (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to the patterning complexity. Embodiments described herein may be implemented to enable integration of the front side and back side interconnects for nanowire transistors. Embodiments described herein may provide an approach to achieving a relatively broader interconnect pitch. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to enable robust functionality of scaled low-power, high-performance nanowire or nanoribbon transistors.One or more embodiments described herein relate to dual epitaxial (EPI) interconnects for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire / nanoribbon transistors that are partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. Deep trenching on one of the source or drain side allows direct contact to a back side interconnect level.As an example process flow for fabricating another gate all-around device, FIGS. 12A-12J illustrate cross-sectional views of various operations in a method for fabricating a gate all-around structure of an integrated circuit, according to an embodiment of the present disclosure.Referring to FIG. 12A, a method of fabricating an integrated circuit structure includes forming a starting stack including alternating sacrificial layers 1204 and nanowires 1206 above a fin 1202, such as a silicon fin. The nanowires 1206 may be referred to as a vertical arrangement of nanowires. A protective cap 1208 may be formed over the alternating sacrificial layers 1204 and nanowires 1206, as shown. Relaxed buffer layer 1252 and defect modification layer 1250 may be formed below alternating sacrificial layers 1204 and nanowires 1206, as also shown.Referring to FIG. 12B, a gate stack 1210 is formed over the vertical array of horizontal nanowires 1206. Portions of the vertical arrangement of the horizontal nanowires 1206 are then exposed by removing portions of the sacrificial layers 1204 to provide recessed sacrificial layers 1204' and voids 1212, as shown in FIG. 12C.It should be appreciated that the structure of FIG. 12C may be fully fabricated without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), a fabrication process in one embodiment involves the use of a process scheme that provides a gate-all-around structure of an integrated circuit with epitaxial bumps, which may be vertically discrete source or drain structures.Referring to FIG. 12D, upper gate spacers 1214 are formed on sidewalls of the gate structure 1210. Cavity spacers 1216 are formed in the cavities 1212 below the upper gate spacers 1214. A deep trench contact etch is then optionally performed to form trenches 1218 and form recessed nanowires 1206'. A patterned relaxed buffer layer 1252' and a patterned defect modification layer 1250' may also be present, as shown.A sacrificial material 1220 is then formed in the trenches 1218, as shown in FIG. 12E. In other processing schemes, an insulated trench bottom or silicon trench bottom may be used.Referring to FIG. 12F, a first epitaxial source or drain structure (e.g., left features 1222) is formed at a first end of the vertical array of horizontal nanowires 1206'. A second epitaxial source or drain structure (e.g., right features 1222) is formed at a second end of the vertical array of horizontal nanowires 1206'. In an embodiment, the epitaxial source or drain structures 1222 are vertically discrete source or drain structures as shown and may be referred to as epitaxial bumps.An interlayer dielectric (ILD) material 1224 is then formed on the sides of the gate electrode 1210 and adjacent to the source or drain structures 1222, as shown in FIG. 12G. Referring to FIG. 12H, a replacement gate process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. The ILD material 1224 is then removed, as shown in FIG. 12I. The sacrificial material 1220 is then removed from one of the source-drain locations (e.g., on the right side) to form the trench 1232, but is not removed from the other of the source-drain locations to form the trench 1230.Referring to FIG. 12J, a first conductive contact structure 1234 is formed coupled to the first epitaxial source or drain structure (e.g., the left side features 1222). A second conductive contact structure 1236 is formed that is coupled to the second epitaxial source or drain structure (e.g., right side features 1222). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In an embodiment, although not shown in FIG. 12J, the method further includes forming an exposed surface of the second conductive contact structure 1236 on a bottom surface of the fin 1202. Conductive contacts may include a contact resistance reducing layer and a primary contact electrode layer, examples of which may include Ti, Ni, Co (for the former and W, Ru, Co for the latter).In an embodiment, the second conductive contact structure 1236 along the fin 1202 is deeper than the first conductive contact structure 1234, as shown. In such an embodiment, the first conductive contact structure 1234 is not along the fin 1202, as shown. In another such embodiment, not shown, the first conductive contact structure 1234 is partially along the fin 1202.In an embodiment, the second conductive contact structure 1236 is along an entirety of the fin 1202. In an embodiment, although not shown, in the case that the bottom surface of the fin 1202 is exposed by a backside substrate removal process, the second conductive contact structure 1236 has an exposed surface at a bottom surface of the fin 1202.In another aspect, to provide access to both conductive contact structures of a pair of asymmetric source and drain contact structures, integrated circuit structures described herein may be fabricated using a backside exposure fabrication approach. In some embodiments, exposing the back side of a transistor or other device structure includes wafer level back side processing. Unlike conventional TSV-type technology, exposing the back side of a transistor as described herein may be performed at the density of the device cells and even within sub-regions of a device. Further, such exposing of the back side of a transistor may be performed to remove substantially all of the donor substrate on which a device layer has been disposed during front side device processing. As such, a micron-depth TSV becomes unnecessary, and the thickness of a semiconductor in the device cells subsequent to a backside exposure of a transistor may be as small as several tens or hundreds of nanometers.Exposure techniques described herein may allow paradigm switching from bottom-up device fabrication to center-out fabrication, where the center (center) is any layer used in front-side fabrication, is exposed from the back-side, and is reused in back-side fabrication. Processing both a front side and an exposed back side of a device structure may address many of the challenges associated with fabricating 3D ICs when primarily set to front side processing.For example, an approach for exposing the back side of a transistor may be used to remove at least a portion of a support layer and an intervening layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a carrier layer in the donor host substrate is polished (e.g., CMP) and / or etched with a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the backing layer may be employed. For example, if the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etching process known as suitable for thinning the Group IV semiconductor may also be employed.In some embodiments, the foregoing is preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intermediate layer. The cracking process can be used to remove a substantial portion of the carrier layer as a bulk mass, thereby reducing the polishing or etching time required to remove the carrier layer. For example, if a support layer has a thickness of 400-900 μm, 100-700 μm may be cleaved by applying any blanket implant known to promote wafer level fracture. In some embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired. Following such a cracking process, the thickness of the support layer remaining in the donor host substrate assembly may then be polished or etched to complete the removal. Alternatively, if the backing layer is not broken, the grinding, polishing and / or etching process may be employed to remove a greater thickness of the backing layer.Next, exposure of an intermediate layer is detected. Detection is used to identify a point where the back surface of the donor substrate has approached almost to the device layer. It is known that any endpoint detection technique suitable for detecting a transition between the materials used for the support layer and the intermediate layer may be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorbance or emission of the backside surface of the donor substrate while polishing or etching is performed. In some other embodiments, the endpoint criteria are associated with a change in optical absorbance or emission of byproducts during polishing or etching of the donor substrate backside surface. For example, the absorbance or emission wavelengths associated with the carrier layer etch byproducts may change as a function of the different compositions of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with a change in mass of species in byproducts of polishing or etching the backside surface of the donor substrate. For example, the byproducts of processing may be sampled by a quadrupole mass analyzer and a change in species mass may be correlated with the different compositions of the support layer and the intermediate layer. In another embodiment, the endpoint criteria are associated with a change in friction between a backside surface of the donor substrate and a polishing surface in contact with the backside surface of the donor substrate.Detection of the intermediate layer may be improved when the removal process is selective to the support layer relative to the intermediate layer, as non-uniformity of the support removal process may be mitigated by an etch rate delta between the support layer and the intermediate layer. Detection can even be skipped if the grinding, polishing and / or etching process removes the intermediate layer at a rate sufficiently below the rate at which the support layer is removed. If no endpoint criterion is employed, a grinding, polishing and / or etching process of a predetermined fixed duration may stop on the interlayer material if the thickness of the intermediate layer is sufficient for the selectivity of the etch. In some examples, the carrier etch rate:etch rate ratio of the intermediate layer is 3:1-10:1 or more.Upon exposure of the intermediate layer, at least a portion of the intermediate layer may be removed. For example, one or more component layers of the intermediate layer may be removed. A thickness of the intermediate layer may be uniformly removed by polishing, for example. Alternatively, a thickness of the intermediate layer may be removed with a masked or blanket etch process. The process may employ the same polishing or etching process as that employed to thin the carrier, or may be a distinct process with distinct process parameters. For example, if the intermediate layer provides an etch stop for the charge carrier removal process, the latter operation may employ another polishing or etching process that promotes removal of the intermediate layer over removal of the device layer. If less than several hundred nanometers of an intermediate layer thickness is to be removed, the removal process may be relatively slow, optimized for uniformity across the wafer, and more accurately controlled than that used to remove the support layer. For example, a CMP process employed may employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or more) between semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded within the intermediate layer, for example, as electrical isolation between adjacent device regions.For embodiments where the device layer is exposed by complete removal of the intervening layer, backside processing may begin on an exposed backside of the device layer or particular device regions therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through a thickness of the device layer disposed between the intermediate layer and a device region previously fabricated in the device layer, such as a source or drain region.In some embodiments where the carrier layer, intermediate layer, or device layer backside is recessed with a wet and / or plasma etch, such an etch may be a patterned etch or a materially selective etch that provides significant non-planarity or topography in the device layer backside surface. As described further below, the patterning may be within a device cell (i.e., "intra-cell patterning") or may be across device cells (i.e., "inter-cell patterning"). In some patterned etch embodiments, at least a partial thickness of the intermediate layer is employed as a hard mask for back-side device layer patterning. Thus, a masked etch process may precede a correspondingly masked device layer etch.The processing scheme described above may result in a donor-host substrate assembly including IC devices having a back side of an intermediate layer, a back side of the device layer, and / or a back side of one or more semiconductor regions within the device layer, and / or a front side metallization that are exposed. Additional backside processing of any of these exposed regions may then be performed during downstream processing.As described throughout the present application, a substrate may be made of a semiconductor material that can withstand a manufacturing process and migrate charge therein. In one embodiment, a substrate described herein is a bulk substrate comprised of a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, a bulk substrate is comprised of an epitaxial layer grown on a distinct crystalline substrate, e.g., an epitaxial silicon layer grown on a boron-doped bulk monocrystalline silicon substrate. A bulk substrate may alternatively be made of a Group III-V material. In one embodiment, a bulk substrate is made of a Group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, Indiumgalliumarsenid Aluminiumgalliumarsenid indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is made of a Group III-V material and the charge carrier dopant impurity atoms are such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.As described throughout the present application, isolation regions, such as shallow trench isolation regions or sub-fin isolation regions, may be made of a material suitable to ultimately electrically isolate or contribute to the isolation of portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed in an underlying bulk substrate, such as isolation of active fin regions. For example, in one embodiment, an isolation region is comprised of one or more layers of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.As described throughout the present application, gate lines or gate structures may consist of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is a metal gate and the gate dielectric layer is a high-k material. For example, in one embodiment, the gate dielectric layer is made of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Further, a portion of the gate dielectric layer may include a layer of native oxide formed by the upper few layers of a semiconductor substrate. In an embodiment, the gate dielectric is comprised of a high-k top portion and a bottom portion comprised of an oxide of a semiconductor material. In an embodiment, the gate dielectric layer is comprised of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.In one embodiment, a gate electrode is comprised of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode is a non-work-out adjusting fill material formed above a work function adjusting metal layer. The gate electrode layer may be made of a p-type work function metal or an n-type work function metal depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may be a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A p-type metal layer will allow formation of a PMOS gate electrode having a work function that is between about 4.9 eV and about 5.2 eV. In an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An n-type metal layer will allow formation of an NMOS gate electrode having a work function that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may be a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may be comprised of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.As described throughout the present application, spacers associated with gate lines or electrode stacks may be made of a material suitable to ultimately electrically isolate or contribute to the isolation of a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are made of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon doped silicon nitride.In one embodiment, the interlayer dielectric (ILD) material, as used throughout the present specification, is made of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO 2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.In one embodiment, as also used throughout the present specification, metal lines or interconnect line material (and via material) are comprised of one or more metal structures or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including Ta and / or TaN and / or Ti and / or TiN), stacks of different metals or alloys, etc. Accordingly, the interconnect lines may be a single layer of material or may be formed from some layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form interconnect lines. In one embodiment, the interconnect lines are made of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. The interconnect lines are sometimes referred to in the art as conductive traces, wires, lines, metal, or simply interconnect.In one embodiment, hard mask materials, as also used throughout the present description, are comprised of dielectric materials different from the interlayer dielectric material. In an embodiment, different hard mask materials may be used in different regions to provide different growth or etch selectivity to each other and to underlying dielectric and metal layers. In some embodiments, a hard mask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hard mask material may include a metal species. For example, a hard mask or overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially, minor amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, depending on the particular implementation, other hard mask layers known in the art may be used. The hard mask layers may be formed by CVD, PVD, or other deposition methods.In an embodiment, as also used throughout the present specification, lithography operations are performed using 193 nm immersion lithography (i193), extreme UV (EUV) lithography, or Elektronenstrahldirektschreib(EBDW: electron beam direct write) lithography, or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographical masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographical masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.In one embodiment, approaches described herein may involve forming a contact pattern that is very well aligned with an existing gate pattern while eliminating the use of a lithography process with an extremely close coverage accuracy budget. In such an embodiment, this approach enables using an intrinsically highly selective wet etch (e.g., relative to dry or plasma etch) to create contact openings. In an embodiment, a contact structure is formed by utilizing an existing gate structure in combination with a contact plug lithography process. In such an embodiment, the approach enables the need for an otherwise critical lithography operation to create contact patterning as used in other approaches to be eliminated. In an embodiment, a trench contact grid is not separately patterned, but is instead formed between poly (gate) lines. For example, in such an embodiment, a trench contact grid is formed subsequent to the gate grid patterning but prior to gate grid intersections.Furthermore, a gate stack structure may be manufactured by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process, rather than being adopted from prior processing. In one embodiment, dummy gates are removed by a dry etching or wet etching process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etching process including the use of SF 6. In another embodiment, dummy gates are comprised of polycrystalline silicon or amorphous silicon and are removed with a wet etching process including the use of aqueous NH 4 OH, or tetramethylammonium hydroxide. In one embodiment, dummy gates are made of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.In one embodiment, one or more approaches described herein substantially provide a dummy or replacement gate process in combination with a dummy and replacement contact process to arrive at the structure. In such an embodiment, the replacement contact process is performed after the replacement gate process to enable high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing at least a portion of the permanent gate structures is performed at a temperature higher than approximately 600 degrees Celsius, e.g., after a gate dielectric layer is formed. The anneal is performed prior to the formation of the permanent contacts.In some embodiments, the arrangement of a semiconductor structure or device places a gate contact over portions of a gate line or a gate stack over isolation regions. However, such an arrangement can be seen as an inefficient use of layout space. In another embodiment, a semiconductor device includes contact structures contacting portions of a gate electrode formed over an active region. Generally, one or more embodiments of the present disclosure include first using a gate-aligned trench contact process prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned with an existing gate pattern. In contrast, other approaches typically involve an additional lithography process with strict registration accuracy of a lithographic contact structure with an existing gate structure in combination with selective contactless etching. For example, another process may include patterning a poly (gate) grid with separately patterning contact features.It should be appreciated that pitch division processing and patterning scenarios may be implemented to enable embodiments described herein or may be included as part of embodiments described herein. Pitch partitioning typically refers to pitch bisecting, pitch quartering, etc. Pitch partitioning schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or mainly unidirectional) in a predefined pitch. Pitch division processing is then implemented as a technique to increase line density.In an embodiment, the term "lattice structure" is used herein for fins, gate lines, metal lines, ILD lines, or hard mask lines to refer to a narrow pitch lattice structure. In such an embodiment, the narrow pitch is not directly achievable by a selected lithography. For example, a patterning based on a selected lithography may be first formed, but the pitch may be halved through the use of spacer mask patterning, as is known in the art. Moreover, the original pitch may be swept by a second pass of a spacer mask pattern. Accordingly, the grid-like structures described herein may space metal lines, ILD lines, or hard mask lines in a substantially uniform pitch and have a substantially uniform width. For example, in some embodiments, the pitch variation would be within ten percent and the width variation would be within ten percent, and in some embodiments, the pitch variation would be within five percent and the width variation would be within five percent. The structure may be manufactured by a pitch bisecting or pitch quartering or other pitch pitch division approach. In one embodiment, the grid does not necessarily have a single pitch.In one embodiment, a cover film is patterned using lithography and etch processing, which may include, for example, spacer-based double patterning (SBDP) or pitch-bisecting or spacer-based quad-patterning (SBQP) or pitch-bisecting. It should be appreciated that other pitch sharing approaches may also be implemented. In any case, in one embodiment, a grid-like layout may be made by a selected lithography approach, such as 193 nm immersion lithography (193i). Pitch division may be implemented to increase the density of lines in the grid-like layout by a factor of n. Grid-like layout formation with 193i lithography plus pitch by a factor of 'n' may be referred to as 193i+P / n pitch. In such an embodiment, 193 nm immersion scaling can be extended for many generations with cost effective grid sizing.It should also be appreciated that not all aspects of the processes described herein need to be implemented to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need never be formed over active portions of the gate stacks prior to fabricating gate contacts. The gate stacks described above may actually be permanent gate stacks as initially formed. Additionally, the processes described herein may be used to form one or more semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal oxide semiconductor (MOS) transistors for logic or memory or are bipolar transistors. Additionally, in one embodiment, the semiconductor devices have a three-dimensional architecture, such as a tri-gate device, a dual-gate independent access device, a fin-FET, a nanowire, or a nanoribbon. One or more embodiments may be particularly useful for fabricating semiconductor devices having a 10-nanometer (10 nm) technology node or sub-10-nanometer (10 nm) technology node.Additional or intervening operations for FEOL layer or structure fabrication may include standard microelectronic fabrication processes, such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other associated action with microelectronic component fabrication. It will also be appreciated that the process operations described for the previous process flow may be implemented in alternative sequences, not every operation needs to be performed, or additional process operations may be performed, or both.Embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, a semiconductor memory may be fabricated. In addition, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronics devices, etc. The integrated circuits may be coupled to a bus and other components in the systems. For example, a processor may be coupled to memory, a chipset, etc., by one or more buses. Each of the processor, memory, and chipset may be manufactured using the approaches disclosed herein.FIG. 13 illustrates a computing device 1300 according to an implementation of the disclosure. The computing device 1300 houses a board 1302. The board 1302 may include a number of components including, but not limited to, a processor 1304 and at least one communication chip 1306. The processor 1304 is physically and electrically coupled to the board 1302. In some implementations, at least one communication chip 1306 is also physically and electrically coupled to the board 1302. In further implementations, the communication chip 1306 is a part of the processor 1304.Depending on its applications, computing device 1300 may include other components that may not be physically and electrically coupled to board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so forth).The communication chip 1306 enables wireless communications for the transmission of data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain them. The communication chip 1306 may implement any of a number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. The computing device 1300 may include a plurality of communication chips 1306. For example, a first communication chip 1306 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1306 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.The processor 1304 of the computing device 1300 includes an integrated circuit die encapsulated within the processor 1304. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures built according to implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers or memory to convert that electronic data, or both, to other electronic data that may be stored in registers or memory.The communication chip 1306 also includes an integrated circuit die encapsulated within the communication chip 1306. According to another implementation of the disclosure, the integrated circuit die of the communication chip is built according to implementations of the disclosure.In further implementations, another component housed within computing device 1300 may include an integrated circuit die built according to implementations of embodiments of the disclosure.In various embodiments, the computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1300 may be any other electronic device that processes data.FIG. 14 illustrates an interposer 1400 that includes one or more embodiments of the disclosure. Interposer 1400 is an intermediate substrate used as a bridge from a first substrate 1402 to a second substrate 1404. The first substrate 1402 may be, for example, an integrated circuit die. The second substrate 1404 may be, for example, a memory module, a computer motherboard, or other integrated circuit die. Generally, the purpose of an interposer 1400 is to spread a connection to a wider pitch or redirect a connection to another connection. For example, an interposer 1400 may couple an integrated circuit die to a ball grid array (BGA) 1406, which may then be coupled to the second substrate 1404. In some embodiments, the first and second substrates 1402 / 1404 are attached to opposite sides of the interposer 1400. In other embodiments, the first and second substrates 1402 / 1404 are attached to the same side of the interposer 1400. And in further embodiments, three or more substrates are interconnected by way of the interposer 1400.The interposer 1400 may be formed of an epoxy, a fiberglass reinforced epoxy, a ceramic, or a polymeric material such as polyimide. In further implementations, interposer 1400 may be formed of alternating rigid or flexible materials, which may include the same materials previously described for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.Interposer 1400 may include metal interconnects 1408 and vias 1410, including, but not limited to, through-silicon vias (TSVs) 1412. The interposer 1400 may further include embedded devices 1414 that include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1400. According to embodiments of the disclosure, devices or processes disclosed herein may be used in the fabrication of the interposer 1400 or in the fabrication of components included in the interposer 1400.FIG. 15 is an isometric view of a mobile computing platform 1500 employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.The mobile computing device 1500 may be a portable device configured for both electronic data display, electronic data processing, and wireless transmission of electronic data. For example, the mobile computing platform 1500 may be any of a tablet, a smart phone, a laptop computer, etc., and includes a display screen 1505, which in the embodiment is a touch screen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system 1510, and a battery 1513. As illustrated, the larger the degree of integration in the system 1510 permitted by a higher transistor packaging density, the larger the portion of the mobile computing platform 1500 occupied by the battery 1513 or nonvolatile storage such as a solid state drive, or the larger the transistor gate number for improved platform functionality. Likewise, the greater the charge carrier mobility of each transistor in the system 1510, the greater the functionality. As such, techniques described herein may enable performance and form factor improvements in the mobile computing platform 1500.The integrated system 1510 is further illustrated in the expanded view 1520. In the exemplary embodiment, packaged device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or graphics processor) fabricated according to one or more processes described herein or including one or more features described herein. The packaged device 1577 is further coupled to the board 1560 along with a power management integrated circuit (PMIC) 1515 and / or RFIC (wireless) integrated circuit (RFIC) 1525, including a broadband RF (wireless) transmitter and / or receiver (e.g., including digital baseband and an analog front end module further includes a power amplifier on a transmission path and a low noise amplifier on a reception path) and / or a controller 1511 thereof. Functionally, the PMIC 1515 performs battery power regulation, DC-DC conversion, etc., and thus has an input coupled to the battery 1513, and an output provides power supply to all other functional modules. As further illustrated, in the embodiment, RFIC 1525 has an output coupled to an antenna to provide any of a number of wireless standards or protocols for implementation, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated on separate ICs coupled to the package substrate of the packaged device 1577, or within a single IC (SoC) coupled to the package substrate of the packaged device 1577.In another aspect, semiconductor packages are used to protect an integrated circuit (IC) chip or die and also provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and to support greater circuit density. Furthermore, the demand for higher performance devices results in a need for an improved semiconductor package that enables a thin packaging profile and low overall curvature compatible with subsequent package processing.In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount a die to a ceramic or organic package substrate. In particular, C4 solder ball interconnects may be implemented to provide flip-chip interconnects between semiconductor devices and substrates. Flip-chip or controlled collapse chip connection (C4 chip connection) is one type of mounting used for semiconductor devices such as integrated circuit (IC) chips, MEMS, or components that use solder bumps instead of wire bonds. The solder bumps are deposited on the C4 pads located on the top side of the substrate package. In order to mount the semiconductor device on the substrate, it is turned upside down to the mounting surface with the active side down. The solder bumps are used to directly connect the semiconductor device to the substrate.FIG. 16 illustrates a cross-sectional view of a flip-chip-mounted die according to an embodiment of the present disclosure.Referring to FIG. 16, a device 1600 includes a die 1602, such as an integrated circuit (IC), fabricated according to one or more processes described herein or including one or more features described herein, according to an embodiment of the present disclosure. The die 1602 includes metallized pads 1604 thereon. A package substrate 1606, such as a ceramic or organic substrate, includes interconnects 1608 thereon. The die 1602 and the package substrate 1606 are electrically connected by solder balls 1610 coupled to the metallized pads 1604 and the interconnects 1608. An underfill material 1612 surrounds the solder balls 1610.Processing a flip chip may be similar to conventional IC fabrication, with a few additional operations. Near the end of the fabrication process, the mounting pads are metallized to make them more receptive to solder. This typically consists of several treatments. A small spot of solder is then deposited on each metalized pad. The chips are then cut out of the wafer as usual. To mount the flip chip in a circuit, the chip is inverted to bring the solder pads down onto connectors on the underlying electronic element or circuit board. The solder is then reflowed to produce an electrical connection, typically using ultrasound or alternatively a reflow soldering process. This also leaves a small space between the circuitry of the chip and the underlying mount. In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.In other embodiments, in accordance with an embodiment of the present disclosure, newer encapsulation and die-to-die interconnect approaches, such as through silicon vias (TSVs) and silicon interposers, are implemented to fabricate a high-power multichip module (MCM) and a system-in-package (SiP) that incorporates an integrated circuit (IC) fabricated in accordance with one or more processes described herein or includes one or more features described herein.Accordingly, embodiments of the present disclosure include integrated circuit structures having a back-side source or drain contact selectivity.Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure even though only a single embodiment is described with reference to a particular feature. Examples of features provided in the disclosure are intended to be illustrative and not limiting unless otherwise indicated. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to one skilled in the art utilizing the present disclosure.The scope of the present disclosure includes any feature or combination of features disclosed herein (explicit or implicit), or any generalization thereof, whether or not it attenuates any or all of the problems addressed herein. Accordingly, during a review of the present application (or an application claiming priority thereof), new claims may be formulated for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any convenient manner and not just in the specific combinations listed in the appended claims.The following examples are directed to further embodiments. The various features of the different embodiments may be combined in various ways, including some features and excluding others to suit a variety of different applications.Embodiment 1: An integrated circuit structure includes first multiple horizontally stacked nanowires laterally spaced from second multiple horizontally stacked nanowires. A gate stack is over the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires. A first source or drain epitaxial structure is at an end of the first plurality of horizontally stacked nanowires, with a first source or drain conductive contact vertically below and in contact with a bottom surface of the first source or drain epitaxial structure, and with a first hard mask material below and in contact with the first source or drain conductive contact. A second source or drain epitaxial structure is at an end of the second plurality of horizontally stacked nanowires, having a second source or drain conductive contact vertically below and in contact with a bottom surface of the second source or drain epitaxial structure, and a second hard mask material below and in contact with the second source or drain conductive contact. The second source or drain conductive contact has a same composition as the first source or drain conductive contact, and the second hard mask material has a composition different from a composition of the first hard mask material.Embodiment 2: The integrated circuit structure of Embodiment 1, wherein the second hard mask material has a lowermost surface on the same plane as a lowermost surface of the first hard mask material.Embodiment 3: The integrated circuit structure of Embodiment 1 or 2, wherein the second hard mask material has a same thickness as the first hard mask material.Embodiment 4: The integrated circuit structure of Embodiment 1, 2, or 3, wherein one of the first hard mask material or the second hard mask material includes silicon and carbon, and the other of the first hard mask material or the second hard mask material includes silicon and nitrogen.Embodiment 5: The integrated circuit structure of Embodiment 1, 2, 3, or 4, wherein the first conductive source or drain contact and the second conductive source or drain contact include tungsten.Embodiment 6: An integrated circuit structure includes a first fin laterally spaced from a second fin. A gate stack is over the first fin and the second fin. A first source or drain epitaxial structure is at an end of the first fin, with a first source or drain conductive contact vertically below and in contact with a bottom surface of the first source or drain epitaxial structure, and with a first hard mask material below and in contact with the first source or drain conductive contact. A second epitaxial source or drain structure is at an end of the second fin, with a second conductive source or drain contact vertically below and in contact with a bottom surface of the second epitaxial source or drain structure, and a second hard mask material below and in contact with the second conductive source or drain contact. The second source or drain conductive contact has a same composition as the first source or drain conductive contact, and the second hard mask material has a composition different from a composition of the first hard mask material.Embodiment 7: The integrated circuit structure of Embodiment 6, wherein the second hard mask material has a lowermost surface on the same plane as a lowermost surface of the first hard mask material.Embodiment 8: The integrated circuit structure of Embodiment 6 or 7, wherein the second hard mask material has a same thickness as the first hard mask material.Embodiment 9: The integrated circuit structure of Embodiment 6, 7, or 8, wherein one of the first hard mask material or the second hard mask material includes silicon and carbon and the other of the first hard mask material or the second hard mask material includes silicon and nitrogen.Embodiment 10: The integrated circuit structure of Embodiment 6, 7, 8, or 9, wherein the first conductive source or drain contact and the second conductive source or drain contact include tungsten.Embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure including first multiple horizontally stacked nanowires or a first fin laterally spaced from second multiple horizontally stacked nanowires or a second fin. A gate stack is over the first plurality of horizontally stacked nanowires or the first fin and the second plurality of horizontally stacked nanowires or the second fin. A first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or the first fin, with a first conductive source or drain contact vertically below and in contact with a bottom surface of the first epitaxial source or drain structure, and with a first hard mask material below and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or the second fin, with a second conductive source or drain contact vertically below and in contact with a bottom surface of the second epitaxial source or drain structure, and a second hard mask material below and in contact with the second conductive source or drain contact. The second source or drain conductive contact has a same composition as the first source or drain conductive contact, and the second hard mask material has a composition different from a composition of the first hard mask material.Embodiment 12: The computing device of Embodiment 11, including the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires.Example 13: The computing device of example 11, including the first fin and the second fin.Embodiment 14: The computing device of Embodiment 11, 12, or 13, further including a memory coupled to the board.Embodiment 15: The computing device of embodiment 11, 12, 13, or 14, further including a communication chip coupled to the board.Embodiment 16: The computing device of embodiment 11, 12, 13, 14, or 15, further including a battery coupled to the board.Embodiment 17: The computing device of embodiment 11, 12, 13, 14, 15, or 16, further including a camera coupled to the board.Embodiment 18: The computing device of embodiment 11, 12, 13, 14, 15, 16, or 17, further including a display coupled to the board.Example 19: The computing device of example 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is an encapsulated integrated circuit die.Embodiment 20: The computing device of embodiment 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

An integrated circuit structure comprising: a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires; a gate stack over the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires; a first epitaxial source or drain structure at an end of the first plurality of horizontally stacked nanowires, having a first conductive source or drain contact vertically below and in contact with a bottom surface of the first epitaxial source or drain structure, and having a first hard mask material below and in contact with the first conductive source or drain contact; and a second source or drain epitaxial structure at an end of the second plurality of horizontally stacked nanowires, comprising a second source or drain conductive contact vertically below and in contact with a bottom surface of the second source or drain epitaxial structure, and a second hard mask material below and in contact with the second source or drain conductive contact, wherein the second source or drain conductive contact has a same composition as the first source or drain conductive contact and the second hard mask material has a composition different from a composition of the first hard mask material.The integrated circuit structure of claim 1, wherein the second hard mask material has a lowermost surface on the same plane as a lowermost surface of the first hard mask material.The integrated circuit structure of claim 1 or 2, wherein the second hard mask material has a same thickness as the first hard mask material.The integrated circuit structure of claim 1, 2 or 3, wherein one of the first hard mask material or the second hard mask material comprises silicon and carbon, and the other of the first hard mask material or the second hard mask material comprises silicon and nitrogen.The integrated circuit structure of claim 1, 2, 3 or 4, wherein the first source or drain conductive contact and the second source or drain conductive contact comprise tungsten.An integrated circuit structure comprising: a first fin laterally spaced from a second fin; a gate stack over the first fin and the second fin; a first source or drain epitaxial structure at an end of the first fin, having a first source or drain conductive contact vertically below and in contact with a bottom surface of the first source or drain epitaxial structure, and having a first hard mask material below and in contact with the first source or drain conductive contact; and a second source or drain epitaxial structure at an end of the second fin, comprising a second source or drain conductive contact vertically below and in contact with a bottom surface of the second source or drain epitaxial structure, and a second hard mask material below and in contact with the second source or drain conductive contact, wherein the second source or drain conductive contact has a same composition as the first source or drain conductive contact and the second hard mask material has a composition different from a composition of the first hard mask material.The integrated circuit structure of claim 6, wherein the second hard mask material has a lowermost surface on the same plane as a lowermost surface of the first hard mask material.The integrated circuit structure of claim 6 or 7, wherein the second hard mask material has a same thickness as the first hard mask material.The integrated circuit structure of claim 6, 7 or 8, wherein one of the first hard mask material or the second hard mask material comprises silicon and carbon and the other of the first hard mask material or the second hard mask material comprises silicon and nitrogen.The integrated circuit structure of claim 6, 7, 8 or 9, wherein the first source or drain conductive contact and the second source or drain conductive contact comprise tungsten.A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure comprising: first multiple horizontally stacked nanowires or a first fin laterally spaced from second multiple horizontally stacked nanowires or a second fin; a gate stack over the first multiple horizontally stacked nanowires or the first fin and the second multiple horizontally stacked nanowires or the second fin; a first source or drain epitaxial structure at an end of the first plurality of horizontally stacked nanowires or the first fin, having a first source or drain conductive contact vertically below and in contact with a bottom surface of the first source or drain epitaxial structure, and having a first hard mask material below and in contact with the first source or drain conductive contact; and a second source or drain epitaxial structure at an end of the second plurality of horizontally stacked nanowires or the second fin, comprising a second source or drain conductive contact vertically below and in contact with a bottom surface of the second source or drain epitaxial structure, and a second hard mask material below and in contact with the second source or drain conductive contact, wherein the second source or drain conductive contact has a same composition as the first source or drain conductive contact and the second hard mask material has a composition different from a composition of the first hard mask material.The computing device of claim 11, comprising the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires.The computing device of claim 11, comprising the first fin and the second fin.The computing device of claim 11, 12 or 13, further comprising: a memory coupled to the board.The computing device of claim 11, 12, 13 or 14, further comprising: a communication chip coupled to the board.The computing device of claim 11, 12, 13, 14, or 15, further comprising: a battery coupled to the board.The computing device of claim 11, 12, 13, 14, 15 or 16, further comprising: a camera coupled to the board.The computing device of claim 11, 12, 13, 14, 15, 16, or 17, further comprising: a display coupled to the board.The computing device of claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is an encapsulated integrated circuit die.The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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