SEMICONDUCTOR DEVICE

Abstract

A semiconductor device that features: a substrate (1); a resistance element (3) formed in a first region of the substrate; and a MISFET (2) formed in a second region of the substrate, wherein the substrate (1) comprises: a carrier substrate (SB); an insulating layer (BX) on the support substrate (SB); and a semiconductor layer (SM) on the insulating layer (BX), wherein the resistance element (3) consists of: the semiconductor layer (SMb) located in the first region; and an epitaxial semiconductor layer (EP) formed on the semiconductor layer (SMb) located in the first region, the epitaxial semiconductor layer (EP) comprises: a first semiconductor part formed on the semiconductor layer (SMb) located in the first region; and a second semiconductor part, which is formed on the semiconductor layer (SMb) located in the first area and is spaced apart from the first semiconductor part, the semiconductor layer (SMb) located in the first area comprises: a first connecting part (RG1a) on which the first semiconductor part is formed; a second connecting part (RG1b) on which the second semiconductor part is formed; and an element part (RG2) located between the first connecting part (RG1a) and the second connecting part (RG1b) on which no epitaxial semiconductor layer is formed, wherein a conductivity type of the first semiconductor part, the second semiconductor part, the first interconnect part (RG1a), the second interconnect part (RG1b) and the element part (RG2) is each a first conductivity type, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first low concentration area (R1) of the first conductivity type located next to the element part (RG2), wherein both the first semiconductor part and the second semiconductor part further have a first medium concentration region (R2) of the first conductivity type located on the first low concentration region (R1), where the impurity concentration of the first low-concentration area (R1) of both the first compound part (RG1a) and the second compound part (RG1b) is lower than the impurity concentration of the element part (RG2), where the impurity concentration of the first medium concentration region (R2) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first low concentration region (R1) of both the first interconnect part (RG1a) and the second interconnect part (RG1b), wherein a metal silicide (MS) layer is formed on a surface of both the first semiconductor part and the second semiconductor part, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first high concentration area (R3) of the first conductivity type, which is located next to the first low concentration area (R1), wherein both the first semiconductor part and the second semiconductor part further have a second high-concentration region (R4) of the first conductivity type located on top of the first high-concentration region (R3), where the impurity concentration of the first high-concentration region (R3) of both the first interconnect (RG1a) and the second interconnect (RG1b) is higher than the impurity concentration of the first medium-concentration region (R2) of both the first semiconductor part and the second semiconductor part, where the impurity concentration of the second high-concentration region (R4) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first medium-concentration region (R2) of both the first semiconductor part and the second semiconductor part, wherein the first low concentration area (R1) is located between the element part (RG2) and the first high concentration area (R3) of both the first connecting part (RG1a) and the second connecting part (RG1b), and wherein the metal silicide layer (MS) is formed on a surface of the second area with high concentration (R4).

Description

BACKGROUND

[0001] The present invention relates to a semiconductor device, for example a technique that is effectively applied to a semiconductor device with a resistive element.

[0002] To fabricate a semiconductor device, one technique involves forming an element isolation region on a semiconductor substrate. Semiconductor elements, such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a resistor, are then placed within an active region of the semiconductor substrate defined by the element isolation region. A multilayer wiring structure is then applied to the semiconductor substrate. Another technique utilizes a solvent substrate as the semiconductor substrate.

[0003] The disclosed techniques are listed below. [Patent Document 1] Japanese Unexamined Patent Application Publication JP 2022 - 80 908 A [Patent document 2] US 2022 / 0 157 863 A1 [Patent document 3] US 2002 / 0 089 407 A1 [Patent Document 4] US 5,793,097 A [Patent Document 5] JP S63 - 310 157 A

[0004] Patent document 1 discloses a technique for forming the resistive element using a semiconductor layer of the SOI substrate.

[0005] Patent document 2 discloses a technique for improving the reliability of a semiconductor device. A resistive element consists of a semiconductor layer of the SOl substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer has two semiconductor sections formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region in which one semiconductor section is formed, a region in which another semiconductor section is formed, and a region in which the epitaxial semiconductor layer is not formed.

[0006] Patent document 3 discloses a temperature-compensated semiconductor resistor comprising two series-connected semiconductor resistor elements exhibiting mutually inverse temperature-dependent resistance responses within a relevant temperature range. The semiconductor resistor elements preferably consist of doped polycrystalline semiconductor material, for example, polycrystalline silicon, with opposite doping, i.e., n-doped or p-doped. Furthermore, an integrated semiconductor circuit, in particular a CMOS circuit, is provided, which includes a semiconductor resistor.

[0007] Patent document 4 discloses a conductive structure made of polycrystalline silicon (e.g., a resistor) whose resistance value is controlled and can be less variable and less temperature-dependent with respect to each resistance value, as well as a method for its fabrication. A structure of at least two layers is used, comprising a first polycrystalline silicon layer with a large crystal grain size and a second polycrystalline silicon layer with a small crystal grain size. The first polycrystalline silicon layer exhibits a positive temperature dependence of resistance, while the second polycrystalline layer exhibits a negative temperature dependence of resistance, or vice versa.Furthermore, the polycrystalline silicon layer with large grain size can be formed by high-dose ion implantation and annealing or by depositing the layers by chemical vapor deposition at different temperatures to form layers with large and small grain sizes.

[0008] Patent document 5 discloses a technique for preventing the resistance value of a polycrystalline silicon resistor from fluctuating due to temperature changes, and conversely, for sensing the temperature by exploiting a change in the temperature characteristic of polycrystalline silicon corresponding to the amount of doping impurities. The temperature characteristic of the resistance value of an impurity-doped polycrystalline silicon film depends largely on the concentration of the impurities. At a high concentration, the resistance value increases with increasing temperature. At a low concentration, the resistance value decreases with increasing temperature. At a medium concentration, the resistance value does not fluctuate at all with temperature changes.Accordingly, simply by selecting the correct amount of doping impurities, it is possible to prevent the resistance of polycrystalline silicon from fluctuating due to temperature changes. Furthermore, these resistance fluctuations can be used for temperature measurement. SUMMARY

[0009] If the resistance value of a resistive element in a semiconductor device is increased, the area required to accommodate the resistive element within the semiconductor device also increases. This, however, leads to an increase in the surface area of ​​the semiconductor device, which is detrimental to miniaturization. It is desirable to provide a technique capable of increasing the resistance value of the resistive element within the semiconductor device without increasing its surface area.

[0010] In this respect, the invention provides semiconductor devices with the features of claims 1, 6, 10 and 11. Further embodiments are described in the dependent claims.

[0011] Further problems and new features will become clear from the description of this specification and the accompanying drawings.

[0012] According to one embodiment, a semiconductor device comprises: a substrate; a resistive element formed in a first region of the substrate; and a MISFET formed in a second region of the substrate. The substrate has: a support substrate; an insulating layer on the support substrate; and a semiconductor layer on the insulating layer. The resistive element consists of: the semiconductor layer located in the first region; and an epitaxial semiconductor layer formed on the semiconductor layer located in the first region. The epitaxial semiconductor layer has: a first semiconductor part formed on the semiconductor layer located in the first region; and a second semiconductor part formed on the semiconductor layer located in the first region and spaced apart from the first semiconductor part.The semiconductor layer located in the first region has: a first interconnection region on which the first semiconductor part is formed; a second interconnection region on which the second semiconductor part is formed; and an element region located between the first interconnection region and the second interconnection region, on which no epitaxial semiconductor layer is formed. Each of the conductivity types of the first semiconductor part, the second semiconductor part, the first interconnection region, the second interconnection region, and the element region is a first conductivity type. Both the first interconnection region and the second interconnection region have a first region with a low concentration of the first conductivity type located adjacent to the element region.Both the first and second semiconductor parts have a first region with medium concentration of the first conductivity type, located on the first region with low concentration. The impurity concentration of the first region with low concentration in both the first and second semiconductor parts is lower than the impurity concentration of the element part. The impurity concentration of the first region with medium concentration in both the first and second semiconductor parts is higher than the impurity concentration of the first region with low concentration in both the first and second semiconductor parts. A metal silicide layer is formed on the surface of both the first and second semiconductor parts.Both the first interconnect and the second interconnect have a first high-concentration region of the first conductivity type, located adjacent to the first low-concentration region. Both the first semiconductor and the second semiconductor have a second high-concentration region of the first conductivity type, located on top of the first high-concentration region. The impurity concentration in the first high-concentration region of both the first interconnect and the second interconnect is higher than the impurity concentration in the first medium-concentration region of both the first semiconductor and the second semiconductor.The impurity concentration in the second region, which has a high concentration of both the first and second semiconductor parts, is higher than the impurity concentration in the first region, which has a medium concentration of both the first and second semiconductor parts. The first region, with a low concentration, is located between the element part and the first region, which has a high concentration of both the first and second interconnect parts. The metal silicide layer is formed on a surface of the second region, which has a high concentration of both components.

[0013] According to one embodiment, the resistance value of the resistive element contained in the semiconductor device can be increased without increasing the area of ​​the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view of a main part of a semiconductor device according to an exemplary embodiment. Fig. Figure 2 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment. Fig. Figure 3 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment. Fig. Figure 4 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment. Fig. Figure 5 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment. Fig. Figure 6 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment. Fig. Figure 7 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment. Fig. Figure 8 is a cross-sectional view of a resistance element according to an exemplary embodiment. Fig. Figure 9 is a cross-sectional view of the resistance element according to an exemplary embodiment. Fig. Figure 10 is a partially enlarged cross-sectional view showing part of Fig. 7 enlarged. Fig. Figure 11 is a cross-sectional view of the main part of the semiconductor device according to an exemplary embodiment during a manufacturing process. Fig. Figure 12 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 11. Fig. Figure 13 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 12. Fig. Figure 14 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 13. Fig. Figure 15 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 14. Fig. Figure 16 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 15. Fig. Figure 17 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 16. Fig. Figure 18 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 17. Fig. Figure 19 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 18. Fig. Figure 20 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 19. Fig. Figure 21 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 20. Fig. Figure 22 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 21. Fig. Figure 23 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 22. Fig. Figure 24 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 23. Fig. Figure 25 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 24. Fig. Figure 26 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 25. Fig. Figure 27 is a partially enlarged cross-sectional view of a resistance element in an investigation example. Fig. Figure 28 is a graph showing a correlation between a layer resistance of the resistive element and a length of an element part of a semiconductor layer that forms the resistive element. Fig. Figure 29 is a graph showing the correlation between the layer resistance of the resistive element and the length of the element part of the semiconductor layer that forms the resistive element. Fig. Figure 30 is a partially enlarged cross-sectional view of a resistance element of a modification example. Fig. Figure 31 is a cross-sectional view of a main part of a semiconductor device of the modification example during a manufacturing process. Fig. Figure 32 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 31. Fig. Figure 33 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 32. Fig. Figure 34 is a top view of a main part of a semiconductor device according to another embodiment. Fig. Figure 35 is a cross-sectional view of the main part of the semiconductor device according to another embodiment. Fig. Figure 36 is a cross-sectional view of the main part of the semiconductor device according to another embodiment during a manufacturing process. Fig. Figure 37 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 36. Fig. Figure 38 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 37. Fig. Figure 39 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 38. Fig. Figure 40 is a top view of the main part of the semiconductor device according to another embodiment. Fig. Figure 41 is a top view of the main part of the semiconductor device according to another embodiment. Fig. Figure 42 is a top view of the main part of the semiconductor device according to another embodiment. Fig. Figure 43 is a graph showing the temperature dependence of the resistance value of the resistive element. Fig. Figure 44 is a top view of the main part of the semiconductor device according to another embodiment. Fig. Figure 45 is a cross-sectional view of the main part of the semiconductor device according to another embodiment. Fig. Figure 46 is a cross-sectional view of the main part of the semiconductor device according to another embodiment during the manufacturing process. Fig. Figure 47 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 46. Fig. Figure 48 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 47. Fig. Figure 49 is a cross-sectional view of the main part of the semiconductor device during the manufacturing process according to Fig. 48. DETAILED DESCRIPTION

[0014] In the embodiments described below, the invention is described in a plurality of sections or embodiments where this is necessary for practical reasons. However, these sections or embodiments are not irrelevant to one another unless otherwise stated, and one refers to all or part of the other as a modification example, detail, or supplementary explanation thereof. Also, where reference is made in the embodiments described below to the number of elements (including number of parts, values, amount, range, and the like), the number of elements is not limited to a specific number unless otherwise stated, or except in cases where the number is obviously limited to a specific number in principle, and the number greater or lesser than the stated number is also applicable.Furthermore, it is self-evident that in the embodiments described below, the components (including element steps) are not always indispensable unless otherwise stated, or except where the components are obviously indispensable in principle. Even when the following embodiments mention that components or the like "consist of A" or "are formed from A," elements other than A are naturally not excluded, except where it is expressly stated that A is the only element therein. Similarly, in the embodiments described below, when the shape of the components, their positional relationships, and the like are mentioned, substantially approximate and similar shapes and the like are included unless otherwise stated, or except where it is conceivable that they are obviously excluded in principle.The same applies to the numerical value and the range, as described above.

[0015] Exemplary embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that components with the same function are designated with the same reference numerals in the drawings for the purpose of describing the exemplary embodiments, and their repeated description is omitted. Furthermore, the description of identical or similar sections is generally not repeated unless specifically required in the following exemplary embodiments.

[0016] Furthermore, in some of the drawings used in the following examples, hatching is omitted even in cross-sectional views to improve clarity. Hatching is also used in top views to facilitate the representation of the drawings. (First embodiment)<Hinsichtlich der Struktur der Halbleitervorrichtung>

[0017] A semiconductor device of the present embodiment is described with reference to the drawings. Fig. Figure 1 is a top view of a main part of a semiconductor device of the present embodiment, and Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. Figure 6 shows cross-sectional views of the main part of the semiconductor device of the present embodiment. The cross-sectional view along line AA in Fig. 1 essentially corresponds to the Fig. 2; the cross-sectional view along line BB in Fig. 1 essentially corresponds to the Fig. 3; the cross-sectional view along line CC in Fig. 1 essentially corresponds to the Fig. 4; and the cross-sectional view along line DD from Fig. 1 essentially corresponds to the Fig. 5. Consequently, the Fig. 2, Fig. 3, Fig. 4 to Fig. 5 cross-sectional views essentially perpendicular to a main surface of an SOI substrate 1. The Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5 correspond to top and cross-sectional views of a resistance element formation area 1B in which a resistance element 3 is formed, and Fig. Figure 6 corresponds to a cross-sectional view of a MISFET formation region 1A in which a MISFET 2 is formed. Furthermore, an X-direction, a Y-direction, and a Z-direction are shown, which are located in the Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5 are shown, directions perpendicular to each other, but the X direction and the Y direction are directions that are essentially parallel to the main surface of the SOI substrate 1, and the Z direction is a direction that is essentially perpendicular to the main surface of the SOl substrate 1.

[0018] The semiconductor device of the present embodiment, which is located in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. Figure 6 shows a semiconductor device that uses an SOI (Silicon On Insulator) substrate 1.

[0019] As in the Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. As shown in Figure 6, the SOL substrate 1 comprises a semiconductor substrate (support substrate) SB as the support substrate, an insulating layer (buried insulating film) BX formed on a major surface of the semiconductor substrate SB, and a semiconductor layer SM formed on a top surface of the insulating layer BX. The semiconductor substrate SB is the support substrate that carries the insulating layer BX and a structure on and above the insulating layer BX, but is also a semiconductor substrate itself.

[0020] The semiconductor substrate SB is preferably a single-crystal silicon substrate and consists, for example, of p-type single-crystal silicon. For example, the semiconductor substrate SB can be made of single-crystal silicon with a resistivity of about 1 Ω to 10 Ωcm. The thickness of the semiconductor substrate SB can be, for example, about 700 µm to 750 µm. The insulating layer BX is preferably a silicon oxide film, and the thickness of the insulating layer BX can be, for example, about 10 nm to 20 nm. If the insulating layer BX is a silicon oxide film, it can also be considered a buried oxide film, i.e., a BOX (Bu-ried oxide) layer. The semiconductor layer SM consists of single-crystal silicon or the like. For example, the semiconductor layer SM can be made of single-crystal silicon with a resistivity of about 1 Ω to 10 Ωcm. The semiconductor layer SM can also be viewed as a SOL layer.The thickness of the semiconductor layer SM is less than the thickness of the semiconductor substrate SB, which is the support substrate, and the thickness of the semiconductor layer SM can be, for example, approximately 15 nm to 25 nm. The SOI substrate 1 is formed by the semiconductor substrate SB, the insulating layer BX, and the semiconductor layer SM.

[0021] As in Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. As shown in Figure 6, elemental isolation regions (elemental isolation structures) ST are formed in the SOL substrate 1. The elemental isolation region ST consists of an insulating film (e.g., a silicon oxide film) embedded in an elemental isolation trench. The elemental isolation trench and the elemental isolation region ST filling it penetrate the semiconductor layer SM and the insulating layer BX, and their lower portions reach half the thickness of the semiconductor substrate SB. That is, the elemental isolation region ST is embedded in the elemental isolation trench formed above the semiconductor layer SM, the insulating layer BX, and the semiconductor substrate SB.

[0022] The SOI substrate 1 of the present embodiment has a MISFET formation region 1A, in which the MISFET is formed, and a resistive element formation region 1B, in which the resistive element is formed. The MISFET formation region 1A and the resistive element formation region 1B correspond to distinct planar regions on the same main surface of the SOI substrate 1. The MISFET formation region 1A and the resistive element formation region 1B are each subdivided by the element isolation region ST and are, for example, as shown in Fig. Figure 1 shows the element isolation region ST surrounded by the element isolation region. Therefore, both the MISFET formation region 1A and the resistor element formation region 1B can be considered an active region surrounded by the element isolation region ST.

[0023] A MISFET (Metal Insulator Semiconductor Field Effect Transistor) 2 is formed on the semiconductor layer SM in the MISFET formation region 1A. The resistive element 3 is formed from the semiconductor layer SM in the resistive element formation region 1B. In the SOl substrate 1, the semiconductor layer SM in the MISFET formation region 1A and the semiconductor layer SM in the resistive element formation region 1B are planarly surrounded and subdivided by the element isolation regions ST.

[0024] Here, the semiconductor layer SM in the MISFET formation region 1A is designated by the symbol SMa and referred to as semiconductor layer SMa, and the semiconductor layer SM in the resistive element formation region 1B is designated by the symbol SMb and referred to as semiconductor layer SMb. Semiconductor layer SMa and semiconductor layer SMb each have the same thickness. Furthermore, the term "equal" as used here means that two or more objects being compared (here, "thicknesses") are essentially the same. This means that while the two or more objects being compared are identical in design, they are not necessarily identical in actual manufactured products due to manufacturing differences.

[0025] The semiconductor layer SM in MISFET formation region 1A, i.e., the semiconductor layer SMa, is surrounded by the insulating layer BX and the element insulating region ST, since its side surface contacts the element insulating region ST and its lower part contacts the insulating layer BX. That is, the lower part of the semiconductor layer SMa is covered by the insulating layer BX and the side surface of the semiconductor layer SMa is covered by the element insulating region ST. Furthermore, the semiconductor layer SM in resistor element formation region 1B, i.e., the semiconductor layer SMb, is surrounded by the insulating layer BX and the element insulating region ST, since its side surface contacts the element insulating region ST and its lower part contacts the insulating layer BX. That is, the lower part of the semiconductor layer SMb is covered by the insulating layer BX and the side surface of the semiconductor layer SMb is covered by the element insulating region ST.In plan view, the semiconductor layer SMa and the semiconductor layer SMb are each surrounded by the element isolation region ST and are therefore spaced apart from each other by the element isolation region ST.

[0026] First, the MISFET 2 formed in the MISFET formation area 1A is described (see Fig. 8).

[0027] The MISFET 2 has a gate electrode GE, which is formed above the semiconductor layer SMa via a gate insulating film GF. The gate electrode GE consists, for example, of polycrystalline silicon. A sidewall spacer SW2 is formed as a sidewall insulating film on one sidewall of the gate electrode GE.

[0028] Epitaxial semiconductor layers (EP) are formed on regions of the semiconductor layer SMa located on both sides of a structure consisting of the gate electrode GE and the sidewall spacer SW2. That is, the EP layer is formed on a region of the SMa layer that is not covered by the gate electrode GE and the sidewall spacer SW2. The EP layer is an epitaxial semiconductor layer formed by epitaxial growth and is made, for example, of silicon (single-crystal silicon).

[0029] Here, one of the semiconductor layers EP, formed on both sides of the structure consisting of the gate electrode GE and the sidewall spacer SW2, is designated as semiconductor part (epitaxial semiconductor part) EP1a, and the other is designated as semiconductor part (epitaxial semiconductor part) EP1b. That is, the semiconductor layer EP formed on the semiconductor layer SMa has semiconductor parts EP1a and EP1b, which are formed separately on the semiconductor layer SMa. Semiconductor part EP1a and semiconductor part EP1b are spaced apart from each other, with the gate electrode GE and the sidewall spacer SW2 positioned between them. Therefore, semiconductor part EP1a and semiconductor part EP1b are made of the same material (here, single-crystal silicon) and have the same thickness. In the top view, the gate electrode GE is positioned between semiconductor part EP1a and semiconductor part EP1b.

[0030] In the MISFET formation region 1A, a source / drain region (semiconductor region for source or drain) of MISFET 2 is formed in each of the semiconductor layers EP and SMa. Specifically, a semiconductor region EX formed on the semiconductor layer SMa and a semiconductor region SD formed above the semiconductor layers EP and SMa form the source / drain region of an LDD (Lightly Doped Drain) structure. The impurity concentration in the semiconductor region SD is higher than the impurity concentration in the semiconductor region EX. Furthermore, in the present embodiment, the semiconductor region EX formed in the semiconductor layer SMa is, for example, a p-type semiconductor region. The semiconductor region SD formed above the semiconductor layers EP and SMa is also a p-type semiconductor region, like the semiconductor region EX. That is, the MISFET 2 of the present embodiment is a p-channel MISFET.

[0031] In MISFET formation area 1A, the p-type semiconductor region EX is formed in a region directly below the sidewall spacer SW2 in the semiconductor layer SMa. In MISFET formation area 1A, the p + A p-type semiconductor region SD is formed above the semiconductor layer EP and a region of the semiconductor layer SMa located below the semiconductor layer EP. A region of the semiconductor layer SMa located directly below the gate electrode GE becomes a channel forming region of MISFET 2. The p-type semiconductor regions EX are formed on both sides (both sides in a gate longitudinal direction) of the channel forming region, so that the p-type semiconductor regions EX are in contact with the channel forming region. Therefore, a PN junction is formed between the channel forming region of MISFET 2 and the semiconductor region EX. Furthermore, the p + -Type semiconductor area SD at the p --type semiconductor region EX, and the p-type semiconductor region EX is located between the p + -type semiconductor region SD and the channel formation region. Since, moreover, as described above, the MISFET 2 of the present embodiment is a p-channel type MISFET, the PN junction is formed between the channel formation region of MISFET 2 and the semiconductor region EX.

[0032] Incidentally, one of the two (a pair) is p + -Type semiconductor areas SD, formed on both sides of the gate electrode GE and the sidewall spacer SW2, one source area that configures MISFET 2, and the other is a drain area that configures MISFET 2. The p + The -type semiconductor region SD, which configures the source region, is formed above the semiconductor part EP1a and the underlying semiconductor layer SMa, and the p +The -type semiconductor area SD, which forms the drain area, is formed above the semiconductor part EP1b and the underlying semiconductor layer SMa.

[0033] A metal silicide layer (metal compound layer) MS is applied to a surface (upper layer part) of both the gate electrode GE and the p + -Type semiconductor region SD is formed. In particular, the metal silicide layer MS is formed on the surface (upper layer part) of the semiconductor layer EP (semiconductor parts EP1a, EP1a), which forms the p + -Type semiconductor area SD is formed.

[0034] Next, the resistive element 3 formed in the resistive element formation area 1B is described (see Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5).

[0035] The semiconductor layer (epitaxial semiconductor) EP is formed on the semiconductor layer SMb. In resistive element formation region 1B, the semiconductor layer EP does not form over the entire semiconductor layer SMb, but only partially over it. The semiconductor layer EP is an epitaxial semiconductor layer formed by epitaxial growth and consists, for example, of silicon (single-crystal silicon).

[0036] The semiconductor layer EP formed on the semiconductor layer SMb has spaced-apart semiconductor parts (epitaxial semiconductor parts) EP2a and EP2b. Therefore, the semiconductor part EP2a and the semiconductor part EP2b are formed by epitaxial growth, consist of the same material (here single-crystal silicon) and have the same thickness.

[0037] The semiconductor layers EP (respective semiconductor parts EP2a and EP2b) formed in the resistive element formation area 1B and the semiconductor layers EP (respective semiconductor parts EP1a and EP1b) formed in the MISFET formation area 1A are formed in the same process (same epitaxial growth process). Therefore, the semiconductor layers EP (respective semiconductor parts EP2a and EP2b) formed in the resistive element formation area 1B and the semiconductor layers EP (respective semiconductor parts EP1a and EP1b) formed in the MISFET formation area 1A consist of the same material (here, single-crystal silicon) and have the same thickness.

[0038] Resistor element 3 consists of the semiconductor layer SMb and the semiconductor layer EP formed on the semiconductor layer SMb (semiconductor parts EP2a and EP2b). If the semiconductor layers SMb and EP are made of silicon, resistor element 3 can be considered a silicon resistor element.

[0039] In one case of the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig. Figure 7 shows that the semiconductor part EP2a is formed at one end of the semiconductor layer SMb in one direction (X-direction) of the semiconductor layer SMb, and the semiconductor part EP2b is formed at the other end of the semiconductor layer SMb in the same direction (X-direction). The semiconductor parts EP2a and EP2b are spaced apart from each other.

[0040] The semiconductor layer SMb integrally comprises a region (connector, end) RG1a, which lies directly beneath the semiconductor region EP2a; a region (connector, end) RG1b, which lies directly beneath the semiconductor region EP2b; and a region (element, middle) RG2, which lies between region RG1a and region RG1b and on which the semiconductor layer EP is not formed. In the semiconductor layer SMb, the semiconductor region EP2a is formed on region RG1a and the semiconductor region EP2b is formed on region RG1b, but the semiconductor layer EP is not formed on region RG2.The area RG1a can be considered as an area of ​​the semiconductor layer SMb on which the semiconductor part EP2a is formed, the area RG1b can be considered as an area of ​​the semiconductor layer SMb on which the semiconductor part EP2b is formed, and then the area RG2 can be considered as an area of ​​the semiconductor layer SMb on which the semiconductor layer EP is not formed.

[0041] A metal silicide layer (metal compound layer) MS is formed on each surface (top surface) of semiconductor part EP2a and semiconductor part EP2b. The corresponding metal silicide layer MS is not formed on the surface of semiconductor layer SMb. In semiconductor layer SMb, the surface (top surface) of region RG2, which is not covered by semiconductor layer EP (respective semiconductor parts EP2a and EP2b), is covered with an insulating film pattern (structured insulating film) ZMP2. Furthermore, on the surface (top surface) of each semiconductor part EP2a and EP2b, the areas where the metal silicide layer MS is not formed are also covered with the insulating film pattern ZMP2.Furthermore, the insulating film patterns ZMP2 are formed on opposite side surfaces of the respective semiconductor parts EP2a and EP2b, such that the insulating film pattern ZMP2 on the surface of the semiconductor layer SMb located in the RG2 region and the insulating film pattern ZMP2 on the surface of each of the semiconductor parts EP2a and EP2b are integrally bonded together. Therefore, the metal silicide layer MS is formed in the area not covered by the insulating film pattern ZMP2 on the surface of each of the semiconductor parts EP2a and EP2b, and the insulating film pattern ZMP2 acts as a silicide-blocking layer to prevent the formation of the metal silicide layer MS.

[0042] On the main surface of the SOL substrate 1, an insulating film (interlayer insulating film) L1 is formed as an interlayer insulating film to cover the gate electrode GE, the sidewall spacer SW2, the semiconductor layers SM and EP, and the metal silicide layer MS. A contact hole (through hole, hole) CT, which penetrates the insulating film L1, is formed in the insulating film L1, and a conductive pin or plug (contact pin) PG is formed (embedded) in the contact hole CT. The pin PG consists of two or more pins and includes a pin PG (hereinafter referred to as PG1b) connected to the gate electrode GE, and a pin PG (hereinafter referred to as PG1a) connected to the p +A -type semiconductor area SD is connected to a pin PG (hereinafter referred to as PG2a) that is connected to the semiconductor area EP2a, and a pin PG (hereinafter referred to as PG2b) that is connected to the semiconductor area EP2b. A lower part of each pin PG contacts the metal silicide layer MS. The contact hole CT in which pin PG2a is embedded is hereinafter referred to as contact hole CT2a, and the contact hole CT in which pin PG2b is embedded is hereinafter referred to as contact hole CT2b.

[0043] The pin PG1a contacts the metal silicide layer MS, which is formed on the surface of the p+ type semiconductor region SD, and is connected to the p via the metal silicide layer MS. +Pin PG1b is electrically connected to the -type semiconductor area SD. Furthermore, pin PG1b contacts the metal silicide layer MS formed on the surface of the gate electrode GE and is electrically connected to the gate electrode GE via this layer. Pin PG2a is located on the semiconductor part EP2a, contacts the metal silicide layer MS formed on the surface (upper layer) of the semiconductor part EP2a, and is electrically connected to the semiconductor part EP2a via this layer. Pin PG2b is also located on the semiconductor part EP2b, contacts the metal silicide layer MS formed on the surface (upper layer) of the semiconductor part EP2b, and is electrically connected to the semiconductor part EP2b via this layer.

[0044] An insulating film L2 is formed on the insulating film L1, in which the pin PG is embedded, and a wiring M1 is formed (embedded) in a trench (wiring trench) formed in the insulating film L2. The wiring M1 is electrically connected to the pin via the pin PG. + -Type semiconductor area SD, the gate electrode GE, the semiconductor part EP2a or the semiconductor part EP2b connected.

[0045] Here, the wiring M1 connected to pin PG2a is referred to as wiring M1a. Furthermore, the wiring M1 connected to pin PG2b is referred to as wiring M1b. Wiring M1a is electrically connected to the metal silicide layer MS on the surface of the semiconductor part EP2a via pin PG2a and is further electrically connected to the semiconductor part EP2a via the metal silicide layer MS. Wiring M1b is also electrically connected to the metal silicide layer MS on the surface of the semiconductor part EP2b via pin PG2b and is further electrically connected to the semiconductor part EP2b via the metal silicide layer MS.

[0046] Wiring is also formed in layers above the wiring M1, but a representation and description of a structure above the insulating film L2 and the wiring M1 is omitted here.

[0047] Next, an impurity concentration distribution in the semiconductor layer SMb and the semiconductor parts EP2a and EP2b, which configure the resistive element 3, is determined with reference to Fig. 2 and Fig. 7, Fig. 8, Fig. 9 to Fig. 10 described. Fig. Figure 7 is a cross-sectional view of the main part of the semiconductor device of the present embodiment and shows the same cross-section as Fig. 2, but Fig. Figure 7 shows a multitude of regions R1, R2, R3, and R4, each differing in impurity concentration (however, the impurity concentrations in regions R3 and R4 are the same), in the semiconductor layer SMb and the respective semiconductor parts EP2a and EP2b, which form the resistive element 3. By comparing Fig. 2 and Fig. Figure 7 shows which areas of the semiconductor layer SMb and the respective semiconductor parts EP2a and EP2b, which form the resistive element 3, exhibit which impurity concentrations. Furthermore, Fig. 8 and Fig. 9 cross-sectional views of the resistance element 3 of the embodiment. Fig. 8 and Fig. Figure 9 shows cross-sectional views essentially parallel to the main surface of the SOL substrate 1, however, the cross-sectional view along the line EE corresponds to Fig. 7 essentially the Fig. 8, the cross-sectional view along line FF in Fig. 7 essentially corresponds to the Fig. 9. Also, Fig. 10 a partially enlarged cross-sectional view showing part of Fig. 7 enlarged, and shows part of the resistance element 3.

[0048] The conductivity type of the semiconductor layer SMb and the respective semiconductor parts EP2a and EP2b, which form the resistive element 3, is the same conductivity type (here p-type). That is, the conductivity type of each of the semiconductor part EP2a, the semiconductor part EP2b, the region (connecting part, end) RG1a, the region (connecting part, end) RG1b, and the region (element part, middle part) RG2 are of the same conductivity type (here p-type). Therefore, the respective conductivity types of regions R1, R2, R3, and R4 are also of the same conductivity type (here p-type). Furthermore, as described above, in the present embodiment the respective areas R1, R2, R3, R4 and RG2, which form the resistance element 3, have the same conductivity type, so that no PN junction is formed between the two adjacent areas under the respective areas R1, R2, R3, R4 and RG2.

[0049] The impurity concentration (p-type impurity concentration) in region R3 is higher than the impurity concentration (p-type impurity concentration) in each of regions R1 and R2. Furthermore, the impurity concentration (p-type impurity concentration) in region R4 is higher than the impurity concentration (p-type impurity concentration) in each of regions R1 and R2. The impurity concentration (p-type impurity concentration) in region R2 is also higher than the impurity concentration (p-type impurity concentration) in region R1. The impurity concentration (p-type impurity concentration) in region R3 and the impurity concentration (p-type impurity concentration) in region R4 are equal. Therefore, regions R3 and R4 each have the highest impurity concentration (p-type impurity concentration) among regions R1, R2, R3, and R4, respectively.Furthermore, area R1 has the lowest defect concentration (p-type defect concentration) among areas R1, R2, R3, and R4. Considering the points mentioned above, area R3 will henceforth be referred to as high-density area R3, area R4 as high-density area R4, area R2 as medium-density area R2, and area R1 as low-density area R1. Moreover, the term "equal" as used here means that two or more objects being compared (here, "defect concentration") are essentially the same. That is, while the two or more objects being compared are identical in design, they may not necessarily be identical in the products actually manufactured due to differences in production.

[0050] In the present embodiment, the defect concentration (p-type defect concentration) in region RG2 of the semiconductor layer SMb is lower than the defect concentration (p-type defect concentration) in each of the high-concentration regions R3 and R4, and higher than the defect concentration (p-type defect concentration) in the low-concentration region R1. Specifically, the defect concentration (p-type defect concentration) in region RG2 of the semiconductor layer SMb and the defect concentration (p-type defect concentration) in region R2 with medium concentration are equal. The defect concentration in region RG2 of the semiconductor layer SMb is essentially uniform. Furthermore, the term "equal" as used here means that two or more objects to be compared (here, "defect concentration") are essentially the same.This means that the two or more objects being compared are identical in design, but not necessarily identical in the products actually manufactured due to differences in production.

[0051] Both the RG1a and RG1b regions of the SMb semiconductor layer consist of the low-concentration region R1 and the high-concentration region R3. Furthermore, the EP2a and EP2b semiconductor regions each consist of the medium-concentration region R2 and the high-concentration region R4.

[0052] In region RG1a of the SMb semiconductor layer, the low-concentration region R1 and the high-concentration region R3 are adjacent to each other in the X-direction. Furthermore, region R1, with its low concentration, is located next to region RG2 in region RG1a of the SMb semiconductor layer, meaning that region R1 is in contact with region RG2. This means that region R1, with its low concentration, lies between region R3, with its high concentration, and region RG2 in region RG1a of the SMb semiconductor layer. Additionally, in semiconductor region EP2a, region R2, with its medium concentration, and region R4, with its high concentration, are adjacent to each other in the X-direction.Region R2, with medium concentration of semiconductor part EP2a, lies on top of region R1, with low concentration, in region RG1a of the semiconductor layer SMb, and region R4, with high concentration of semiconductor part EP2a, lies on top of region R3, with high concentration, in region RG1a of the semiconductor layer SMb. Therefore, region R2, with medium concentration of semiconductor part EP2a, and region R1, with low concentration, in region RG1a of the semiconductor layer SMb, overlap vertically, and region R4, with high concentration of semiconductor part EP2a, and region R3, with high concentration, in region RG1a of the semiconductor layer SMb, overlap vertically.

[0053] In region RG1b of the semiconductor layer SMb, the low-concentration region R1 and the high-concentration region R3 are adjacent to each other in the X-direction. Furthermore, region R1, with its low concentration, is located next to region RG2 in region RG1b of the semiconductor layer SMb, so that region R1 is in contact with region RG2. This means that region R1, with its low concentration, lies between region R3, with its high concentration, and region RG2 in region RG1b of the semiconductor layer SMb. Additionally, in semiconductor region EP2b, region R2, with its medium concentration, and region R4, with its high concentration, are adjacent to each other in the X-direction.Region R2, with medium concentration of semiconductor part EP2b, lies on top of region R1, with low concentration, in region RG1b of the semiconductor layer SMb, and region R4, with high concentration of semiconductor part EP2b, lies on top of region R3, with high concentration, in region RG1b of the semiconductor layer SMb. Therefore, region R2, with medium concentration of semiconductor part EP2b, and region R1, with low concentration, in region RG1b of the semiconductor layer SMb, overlap vertically, and region R4, with high concentration of semiconductor part EP2b, and region R3, with high concentration, in region RG1b of the semiconductor layer SMb, overlap vertically.

[0054] Here, semiconductor part EP2a has an end (side surface) E1 that faces semiconductor part EP2b, and semiconductor part EP2b has an end (side surface) E2 that faces semiconductor part EP2a. The end E1 of semiconductor part EP2a and the end E2 of semiconductor part EP2b are opposite each other and, in this case, Fig. 1, are opposite each other in the X-direction. Region R2, with a medium concentration of semiconductor part EP2a, is located near end E1 of semiconductor part EP2a and reaches end E1 of semiconductor part EP2a. Furthermore, region R2, with a medium concentration of semiconductor part EP2b, is located near end E2 of semiconductor part EP2b and reaches end E2 of semiconductor part EP2b.

[0055] Although details will be described later, the medium concentration region R2 corresponds to a region into which the p-type defects are introduced in an ion implantation process to form the p-type semiconductor region EX, but into which the p-type defects are introduced in an ion implantation process to form the p + -Type semiconductor region SD were not introduced. Furthermore, the high-concentration areas R3 and R4 correspond to areas into which the p-type defects were introduced during the ion implantation process to form the p + -type semiconductor region SD are introduced. Furthermore, the low-concentration region R1 corresponds to a region into which the p-type defects are not introduced during the ion implantation process to form the p-type semiconductor region EX, and in which the type defects are not introduced during the ion implantation process to form the p +-type semiconductor region SD were not introduced. Therefore, the impurity concentration (p-type impurity concentration) in the medium concentration region R2 is the same as the impurity concentration (p-type impurity concentration) in the p-type semiconductor region EX, and the impurity concentration of each of the high concentration regions R3 and R4 is the same as the impurity concentration (p-type impurity concentration) of the p-type semiconductor region EX. + -Type semiconductor range SD. Furthermore, the term "equal" as used here means that two or more objects being compared (here "defect concentration") are essentially the same. This means that the two or more objects being compared are identical in design, but not necessarily identical in the products actually manufactured due to differences in production.

[0056] Next, the functionality of resistance element 3 will be explained.

[0057] The resistive element 3 consists of a semiconductor layer SM (i.e., semiconductor layer SMb) in the resistive element formation area 1B and a semiconductor layer EP (specifically, semiconductor parts EP2a and EP2b) formed on the semiconductor layer SMb. A predetermined potential (voltage) is applied to the metal silicide layer MS on the surface of semiconductor part EP2a from the wiring M1a via pin PG2a. Furthermore, a predetermined potential (voltage) is applied to the silicide layer MS on the surface of semiconductor part EP2b from the wiring M1b via pin PG2b. If there is a potential difference between the potential (voltage) of wiring M1a and the potential (voltage) of wiring M1b, i.e., if there is a difference between the potential (voltage) of pin PG2a and the potential (voltage) of pin PG2b, a current flows in the resistive element 3.For example, if the potential (voltage) of wiring M1a is higher than the potential (voltage) of wiring M1b, a high potential (high voltage) is applied from pin PG2a to the metal silicide layer MS on the surface of semiconductor part EP2a, and a low potential (low voltage) is applied from pin PG2b to the metal silicide layer MS on the surface of semiconductor part EP2b. As a result, current flows in pin PG2b through the metal silicide layer MS on the surfaces of semiconductor part EP2a, then through semiconductor part EP2a, then through semiconductor layer SMb, then through semiconductor part EP2b, and finally through the metal silicide layer MS on the surface of semiconductor part EP2b, in that order, from pin PG2a.Furthermore, if the potential (voltage) of wiring M1b is higher than the potential (voltage) of wiring M1a, a high potential (high voltage) is applied from pin PG2b to the metal silicide layer MS on the surface of semiconductor part EP2b, and a low potential (low voltage) is applied from pin PG2a to the metal silicide layer MS on the surface of semiconductor part EP2a. As a result, current flows in pin PG2a through the metal silicide layer MS on the surface of semiconductor part EP2b, then through semiconductor part EP2b, then through semiconductor layer SMb, then through semiconductor part EP2a, and finally through the metal silicide layer MS on the surface of semiconductor part EP2a, in that order, from pin PG2b.

[0058] The resistance value of resistor 3 is primarily determined by the RG2 region of the semiconductor layer SMb. This is because, due to the thinness of the RG2 region, its cross-sectional area becomes small perpendicular to the direction of current flow. Reducing the thickness of the RG2 region increases the resistance value of resistor 3. Furthermore, the resistance value of resistor 3 is also defined by the impurity concentration in the RG2 region (region R2 with medium concentration) of the semiconductor layer SMb. A low impurity concentration in the RG2 region of the semiconductor layer increases the resistance value of resistor 3, while a high impurity concentration decreases the resistance value of resistor 3.

[0059] Furthermore, in the present embodiment, MISFET 2 is a p-channel MISFET, and the conductivity type of both the SMb and EP semiconductor layers (respective semiconductor parts EP2a and EP2b) that form the resistive element 3 is p-type. By reversing all conductivity types, MISFET 2 can be an n-channel MISFET, and the conductivity type of both the SMb and EP semiconductor layers (respective semiconductor parts EP2a and EP2b) that form the resistive element 3 can be n-type. <Hinsichtlich des Herstellungsprozesses der Halbleitervorrichtung>

[0060] A manufacturing process for the semiconductor device of the present embodiment is described with reference to the drawings. Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. Figures 26 are cross-sectional views of the main part of the semiconductor device of the present embodiment during the manufacturing process. Each of the Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. 26 shows a cross-section accordingly Fig. 6 (a cross-section of the MISFET formation area 1A) and cross-sections corresponding to the Fig. 2 and Fig. 7 (a cross-section of the resistance element formation area 1B).

[0061] First, as in Fig. As shown in Figure 11, the SOI substrate 1 is prepared. As shown in Figure 11. Fig. As can be seen in Figure 11, the SOL substrate 1 comprises the semiconductor substrate SB as a support substrate, the insulating layer BX formed on the main surface of the semiconductor substrate SB and the semiconductor layer SM formed above the upper surface of the insulating layer BX.

[0062] Next, as in Fig. As shown in Figure 12, the element isolation areas ST are formed in the SOL substrate 1.

[0063] To form the element isolation area ST, for example, an element isolation trench ST1 is created in the main surface of the SOI substrate 1 (semiconductor layer SM) using photolithography, dry etching, or similar techniques to penetrate the semiconductor layer SM and the insulating layer BX, reaching the substrate SB with its lower portion. Since the lower portion of the element isolation trench ST1 is located at half the thickness of the substrate SB, the substrate SB is exposed at the lower part of the element isolation trench ST1. The isolation area ST can then be formed by embedding an insulating film in the element isolation trench ST1 using film formation techniques, CMP techniques, or similar methods.

[0064] In SOI substrate 1, the element isolation region ST is formed, dividing the semiconductor layer SM into a multitude of sections (i.e., active regions). The semiconductor layer SM forming the respective active regions is surrounded by the element isolation region ST. The semiconductor layer SM located in the MISFET formation region 1A is the semiconductor layer SMa, and the semiconductor layer SM located in the resistor element formation region 1B is the semiconductor layer SMb. Each of the semiconductor layers SMa and SMb has a bottom portion in contact with the insulating layer BX and a side surface in contact with the element isolation region ST.

[0065] Next, as in Fig. As shown in Figure 13, in the MISFET formation area 1A, the gate electrode GE is formed over the main surface of the SOI substrate 1, that is, over the main surface of the semiconductor layer SM (SMa), via the gate insulating film GF. An insulating film (cap insulating film) CP with the same planar shape as that of the gate electrode GE can be formed on the gate electrode GE. Furthermore, the thickness of the gate electrode GE in the present embodiment is, for example, 100 nm. Furthermore, the term "equal" as used here means that two or more objects to be compared (here "planar shapes") are essentially the same. This means that the two or more objects to be compared are identical in design, but not necessarily identical in the products actually manufactured due to differences in the manufacturing process.

[0066] A specific example for each step in the formation of the gate insulating film GF and the gate electrode GE is described. First, an insulating film for the gate insulating film GF is formed on the main surface of the SOl substrate 1, that is, on the main surface of the semiconductor layer SM. Next, a conductive film (e.g., a polysilicon film) for the gate electrode GE is formed on this insulating film, and then an insulating film (which will later become the insulating film CP) is formed on top of this conductive film. At this stage, a laminated film of the conductive film for the gate electrode GE and the insulating film on top of it is formed in both the MISFET formation area 1A and the resistive element formation area 1B.The laminated film, consisting of the conductive film for the gate electrode GE and the insulating film on it, is then structured using photolithography and etching techniques, allowing the gate electrode GE to be formed from the structured conductive film. The gate electrode GE is formed in the MISFET formation area 1A, and the insulating film for the gate insulating film GF remains between the gate electrode GE and the semiconductor layer SM, becoming the gate insulating film GF. Next, the insulating film CP, structured to have the same planar shape as the gate electrode GE, is formed on the gate electrode GE. In the resistor element formation area 1B, the entire laminated film, consisting of the conductive film for the gate electrode GE and the insulating film on it, is removed.Furthermore, a portion other than that covered by the gate electrode GE in the insulating film for the gate electrode GF can be removed by performing dry etching, which is carried out in a structuring step of the conductive film for the gate electrode GE, or by performing wet etching after performing dry etching. Consequently, in the SOL substrate 1, the gate insulating film GF and the gate electrode GE are formed in the MISFET formation area 1A, but are not formed in the resistive element formation area 1B.

[0067] Furthermore, in the following description, a stack consisting of the gate insulating film GF formed in the MISFET formation area 1A, the gate electrode GE located on it and the insulating film CP located on it is referred to as stack LM1.

[0068] Next, as in Fig. As shown in Figure 14, an insulating film ZM1 of a silicon oxide film or the like is formed on the main surface of the SOI substrate 1, that is, on the main surface of the semiconductor layer SM, to cover the stack LM1 using a CVD (chemical vapor deposition) process or the like. Then, a photoresist pattern RP1 is formed on the insulating film ZM1 using a photolithographic technique. The photoresist pattern RP1 is formed in the resistive element formation area 1B but is not formed in the MISFET formation area 1A.

[0069] Next, the insulating film ZM1 is back-etched using an anisotropic etching technique. This back-etching step, as described in Fig. As shown in Figure 15, the insulating film ZM1 remains as a sidewall spacer (sidewall insulating film) SW1 on the sidewalls of the stack LM1 in the MISFET formation region 1A, the insulating film ZM1 remains as an insulating film pattern (structured insulating film) ZMP1 under the photoresist pattern RP1 in the resistive element formation region 1B, and the other insulating film ZM1 is removed. The photoresist pattern RP1 is then removed by ashing or similar means.

[0070] In this way, the sidewall spacers (sidewall insulating films) SW1 are formed on the sidewalls of the stack LM1 in the MISFET formation area 1A, and the insulating film pattern ZMP1 is formed on the semiconductor layer SM in the resistive element formation area 1B. In the resistive element formation area 1B, the semiconductor layer SM has a portion covered with the insulating film pattern ZMP1 and a portion not covered with the insulating film pattern ZMP1.

[0071] Next, as in Fig. As shown in Figure 16, a semiconductor layer (epitaxial layer) EP is formed by an epitaxial growth process. The semiconductor layer EP is formed on the exposed surface of the semiconductor layer SM. In MISFET formation area 1A, the semiconductor layer EP is formed on a portion of the semiconductor layer SMa that is not covered by the stack LM1 and the sidewall spacers SW1. That is, in MISFET formation area 1A, the semiconductor layer EP is formed on regions of the semiconductor layer SMa located on both sides of a structure consisting of the stack LM1 and the sidewall spacers SW1 formed on its sidewalls. Furthermore, in resistor formation area 1B, the semiconductor layer EP is formed on a portion of the semiconductor layer SMb that is not covered by the insulating film pattern ZMP1. The semiconductor layer EP consists, for example, of silicon (single-crystal silicon).As described above, the semiconductor layer EP has the semiconductor parts EP1a and EP1b, which are formed in the MISFET formation area 1A, and the semiconductor parts EP2a and EP2b, which are formed in the resistive element formation area 1B.

[0072] Next, as in Fig. As shown in Figure 17, the sidewall spacer SW1 and the insulating film pattern ZMP1 are removed by etching. During this etching process, the insulating film CP on the gate electrode GE can also be removed. Furthermore, this etching process can prevent or suppress the etching of the semiconductor layers EP, SM, and the gate electrode GE, provided that the probability of the semiconductor layers EP, SM, and the gate electrode GE being etched is lower than that of the sidewall spacer SW1 and the insulating film pattern ZMP1.

[0073] Next, as in Fig. As shown in Figure 18, a p-type defect, for example boron (B), is ion-implanted into the semiconductor layers EP and SM in the MISFET formation region 1A and in the resistive element formation region 1B. This ion implantation is referred to below as ion implantation IM1 and is shown in Fig. Figure 18 is schematically represented by arrows. During ion implantation IM1, the implantation energy is adjusted so that the p-type defect is introduced into the semiconductor layer EP, but not into the semiconductor layer SM beneath the semiconductor layer EP. If the implantation energy of ion implantation IM1 is high, the p-type defect is also introduced into the semiconductor layer SM, which is located beneath the semiconductor layer EP. However, by keeping the implantation energy of ion implantation IM1 low to a certain degree, ion implantation IM1 can be performed in such a way that the p-type defect is introduced into the semiconductor layer EP, but not into the semiconductor layer SM, which is located beneath the semiconductor layer EP.

[0074] Through ion implantation IM1, the p-type defect is implanted in the semiconductor layer EP (respective semiconductor parts EP1a and EP1b) and an area of ​​the semiconductor layer SMa that is not covered by the semiconductor layer EP (respective semiconductor parts EP1a and EP1b) and the gate electrode GE in the MISFET formation region 1A, thereby forming a p-type semiconductor region EX.

[0075] Furthermore, ion implantation IM1 in resistive element formation region 1B implants the p-type defect into the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) and into an area of ​​the semiconductor layer SMb that is not covered by the semiconductor layer EP (respective semiconductor parts EP2a and EP2b). During ion implantation IM1, virtually no p-type defect is introduced into an area of ​​the semiconductor layer SMb that is covered by the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) in resistive element formation region 1B.

[0076] In Fig. In Figure 18, in the semiconductor layer SMb and the semiconductor parts EP2a and EP2b, in the resistive element formation region 1B, a region into which the p-type defect is introduced by ion implantation IM1 is represented as a region R2 with medium concentration, and a region into which the p-type defect is not introduced by ion implantation IM1 is represented as a region R1 with low concentration. A p-type defect concentration in the region R2 with medium concentration is higher than a p-type defect concentration in the region R1 with low concentration. As shown in Fig. As shown in Figure 18, during stage IM1 of ion implantation, essentially the entirety of each of the semiconductor parts EP2a and EP2b in the resistive element formation region 1B is converted to the region R2 with medium concentration, and essentially the entire region RG2 of the semiconductor layer SMb in the resistive element formation region 1B that is not covered by the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) has the same defect concentration as the region R2 with medium concentration. Furthermore, during stage IM1 of ion implantation, essentially the entire regions RG1a and RG1b of the semiconductor layer SMb in the resistive element formation region 1B that are covered by the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) are converted to the regions R1 with low concentration.

[0077] Next, as in Fig. As shown in Figure 19, sidewall spacers SW2 are formed as sidewall insulating films on the sidewalls of the gate electrode GE. The sidewall spacers SW2 can be formed, for example, by forming a sidewall spacer SW2 to create an insulating film on the main surface of the SOL substrate 1, thus covering the gate electrode GE and the semiconductor layer EP, and subsequently etching back the insulating film using an anisotropic etching technique. The sidewall spacers SW2 are formed on the sidewalls of the gate electrode GE in the MISFET formation area 1A.

[0078] Next, as in Fig. As shown in Figure 20, a photoresist pattern RP2 is formed over the semiconductor layer SMb and the semiconductor layer EP (semiconductor parts EP2a and EP2b) in the resistive element formation area 1B using a photolithographic technique. In the resistive element formation area 1B, the photoresist pattern RP2 is formed to cover an area of ​​the semiconductor layer SMb that is not covered by the semiconductor layer EP (each semiconductor part EP2a and EP2b), and to cover a portion of each of the semiconductor parts EP2a and EP2b.

[0079] In semiconductor part EP2a, an area near end E1 is covered with the photoresist pattern RP2, but a different area is exposed without being covered with the photoresist pattern RP2. Similarly, in semiconductor part EP2b, an area near end E2 is covered with the photoresist pattern RP2, but a different area is exposed without being covered with the photoresist pattern RP2. End E1 of semiconductor part EP2a and end E2 of semiconductor part EP2b are opposite each other in the X direction. In the top view, the area RG2 of the semiconductor layer SMb, which is not covered by the semiconductor layer EP (in the respective semiconductor parts EP2a and EP2b), lies between end E1 of semiconductor part EP2a and end E2 of semiconductor part EP2b.

[0080] Next, as in Fig. As shown in Figure 21, a p-type defect, such as boron (B), is ion-implanted into the semiconductor layers EP and SM in the MISFET formation region 1A and in the resistive element formation region 1B. This ion implantation is referred to below as ion implantation IM2 and is shown in Fig. Figure 21 is schematically represented by arrows. In ion implantation IM2, the implantation energy is adjusted so that the p-type defect is also introduced into the semiconductor layer SM beneath the semiconductor layer EP. Consequently, the implantation energy of ion implantation IM2 is greater than that of ion implantation IM1, and therefore the implantation depth of ion implantation IM2 is greater than that of ion implantation IM1. The dose amount of ion implantation IM2 is also greater than that of ion implantation IM1.

[0081] Through ion implantation IM, the p-type defect is implanted in the semiconductor layer EP (semiconductor parts EP1a and EP1b) and an area of ​​the semiconductor layer SMa in the MISFET formation region 1A that is not covered by the gate electrode GE and the sidewall spacer SW2, thereby creating the p + The p-type semiconductor region SD is formed. The p-type defect concentration of the p + The SD of the -type semiconductor range is higher than the p-type defect concentration of the p - -Type semiconductor range EX. Through the p-type semiconductor range EX and the p + In the -type semiconductor area SD, a source or drain semiconductor area is formed for the MISFET.

[0082] Furthermore, the p-type defect is implanted by ion implantation IM2 in resistive element formation region 1B into a region of the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) that is not covered with the photoresist pattern RP2, and into the semiconductor layer SMb located directly beneath the region. In resistive element formation region 1B, the p-type defect is not implanted by ion implantation IM2 into a region of the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) that is covered with the photoresist pattern RP2, and into the semiconductor layer SMb located directly beneath the region. In the resistive element formation area 1B, the area RG2 of the semiconductor layer SMb, which is not covered by the semiconductor layer EP (respective semiconductor parts EP2a and EP2b), is covered with the photoresist pattern RP2, so that the p-type defect is not implanted by the ion implantation IM2.After ion implantation IM1, the photoresist pattern RP2 is removed, as shown in . Fig. 22 shown.

[0083] Fig. 21 and Fig. Figure 22 shows, in the semiconductor layer SMb and the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) of the resistive element formation region 1B, the regions into which the p-type defect is introduced by ion implantation IM2, as high-concentration regions R3 and R4. The medium-concentration region R2 is a region into which the p-type defect is introduced by ion implantation IM1, but not by ion implantation IM2, and the low-concentration region R1 is a region into which the p-type defect is not introduced by either ion implantation IM1 or IM2.The p-type impurity concentration of each of the high-concentration regions R3 and R4 is higher than the p-type impurity concentration of the medium-concentration region R2, and the p-type impurity concentration of the medium-concentration region R2 is higher than the p-type impurity concentration of the low-concentration region R1. Furthermore, the p-type impurity concentration of each of the high-concentration regions R3 and R4 is essentially the same as the p-type impurity concentration of the low-concentration region R1. + The p-type semiconductor area SD and the p-type defect concentration of the area R2 with medium concentration is essentially equal to the p-type defect concentration of the p-type semiconductor area EX.

[0084] As in Fig. As shown in Figure 22, during the ion implantation stage IM2 in semiconductor part EP2a, in resistive element formation region 1B, the area near end E1 becomes region R2 with medium concentration, and the area opposite end E1 becomes region R4 with high concentration. Furthermore, in semiconductor part EP2b, in resistive element formation region 1B, the area near end E2 becomes region R2 with medium concentration, and the area opposite end E2 becomes region R4 with high concentration. Essentially, the entire region RG2 (the area not covered by the semiconductor layer EP) of the semiconductor layer SMb in resistive element formation region 1B has the same defect concentration as region R2 with medium concentration.Furthermore, in region RG1a (the area covered by semiconductor part EP2a) of the semiconductor layer SMb, in the resistive element formation region 1B, the area adjacent to region RG2 becomes region R1 with low concentration, and the area opposite this becomes region R3 with high concentration. Furthermore, in the aforementioned region RG1b (the area covered by semiconductor part EP2b) of the semiconductor layer SMb, in resistive element formation region 1B, the area adjacent to region RG2 becomes region R1 with low concentration, and the area opposite this becomes region R3 with high concentration.The region R4 with a high concentration of semiconductor part EP2a and the region R3 with a high concentration in region RG1a of the semiconductor layer SMb overlap vertically, and the region R2 with a medium concentration of semiconductor part EP2a and the region R1 with a low concentration in region RG1a of the semiconductor layer SMb overlap vertically. Furthermore, the region R4 with a high concentration of semiconductor part EP2b and the region R3 with a high concentration in region RG1b of the semiconductor layer SMb overlap vertically, and the region R2 with a medium concentration of semiconductor part EP2b and the region R1 with a low concentration in region RG1b of the semiconductor layer SMb overlap vertically.

[0085] Next, if necessary, an activation annealing is carried out, which is a heat treatment to activate the previously introduced defects.

[0086] Next, an insulating film (for example, a silicon oxide film) is formed over the main surface of the SOL substrate 1 to insulate the gate electrode GE, the sidewall spacers SW2, and the p + -Type semiconductor area SD in the MISFET formation area 1A and to cover the semiconductor layers EP and SMb in the resistive element formation area 1B. Then the insulating film is structured using a photolithography technique and an etching technique to form the insulating film pattern ZMP2 from the structured insulating film, as shown in Fig. 23 shown.

[0087] In resistive element formation area 1B, the insulating film pattern ZMP2 is formed over and on the semiconductor layers EP and SMb. Within resistive element formation area 1B, the region RG2 of the semiconductor layer SMb, which is not covered by the semiconductor layer EP, is covered with the insulating film pattern ZMP2. Furthermore, within resistive element formation area 1B, the insulating film pattern ZMP2 extends over a portion of each of the semiconductor parts EP2a and EP2b. Region R2, with a medium concentration of semiconductor part EP2a, is covered with the insulating film pattern ZMP2, but at least a portion of region R4, with a high concentration of semiconductor part EP2a, is exposed without being covered by the insulating film pattern ZMP2.Furthermore, area R2 with medium concentration of the semiconductor part EP2b is covered with the insulating film pattern ZMP2, but at least part of area R4 with high concentration of the semiconductor part EP2b is exposed without being covered with the insulating film pattern ZMP2.

[0088] Next, as in Fig. As shown in Figure 24, the metal silicide layer (metal compound layer) MS is formed using a salicide technique (self-aligned silicide). In the MISFET formation area 1A, the metal silicide layer MS is formed on the surface (upper layer part) of the p + -Type semiconductor region SD is formed, i.e., on the surface (upper layer part) of the semiconductor layer EP and the surface (upper layer part) of the gate electrode GE. Furthermore, in the resistive element formation region 1B, the metal silicide layer MS is formed in a part of the surface of the semiconductor layer EP (semiconductor parts EP2a, EP2a) that is not covered with the insulating film pattern ZMP2.

[0089] In resistive element formation region 1B, the metal silicide layer MS forms in a portion of the surface of the semiconductor layer EP (semiconductor parts EP2a, EP2b) that is not covered by the insulating film pattern ZMP2, but not in the portion covered by the insulating film pattern ZMP2. Therefore, the metal silicide layer MS forms on the surface of region R4 with a high concentration of semiconductor part EP2a, and the metal silicide layer MS forms on the surface of region R4 with a high concentration of semiconductor part EP2b. The metal silicide layer MS does not form on the surface of region R2 with a medium concentration of semiconductor part EP2a, nor on the surface of region R2 with a medium concentration of semiconductor part EP2b.Furthermore, in resistive element formation region 1B, the area RG2 of the semiconductor layer SMb, which is not covered by the semiconductor layer EP, is covered with the insulating film pattern ZMP2. Therefore, in resistive element formation region 1B, the metal silicide layer MS does not form on the surface of the semiconductor layer SMb. The insulating film pattern ZMP2 can act as a silicide blocking layer, preventing the formation of the metal silicide layer MS.

[0090] Thus, the MISFET 2 is formed in the MISFET formation area 1A and the resistive element 3 is formed in the resistive element formation area 1B.

[0091] Next, as in Fig. As shown in Figure 25, the insulating film (interlayer insulating film) L1 is formed as an interlayer insulating film on the main surface of the SOI substrate 1 to cover the gate electrode GE, the semiconductor layers EP and SM, the sidewall spacers SW2, and the metal silicide layer MS. After the formation of the insulating film L1, the flatness of the top surface of the insulating film L1 can, if necessary, be improved by polishing or similar processes using a CMP method.

[0092] Next, the contact hole (through hole, hole) CT is formed in the insulating film L1 using photolithography and etching techniques. The contact hole CT is designed to penetrate the insulating film L1. In the MISFET formation area 1A, the contact hole CT is located above the gate electrode GE and above the p +-Semiconductor region SD is formed. Furthermore, in the resistive element formation region 1B, the contact hole CT is formed above the semiconductor layer EP (semiconductor parts EP2a, EP2a). In one step of forming the contact hole CT, the etching is preferably carried out under the condition that the metal silicide layer MS and the semiconductor layers EP and SM are less likely to be etched than the insulating film L1.

[0093] Next, as in Fig. As shown in Figure 25, the conductive pin PG is made of tungsten (W) or the like as a conductive part for connection in the contact hole CT.

[0094] Next, as in Fig. As shown in Figure 26, the insulating film L2 is formed on the insulating film L1 for wiring, in which the pins PG are embedded.

[0095] Next, as in Fig. As shown in Figure 26, the wiring M1, which is a first-layer wiring, is formed using a single-damascene process. That is, after forming the wiring trench in the insulating film L2, the wiring M1 is formed in the wiring trench.

[0096] The wiring of the second and subsequent layers is then formed using a dual-damascene process or similar method; however, a description of this process is omitted here. Furthermore, wiring M1 and the upper wiring above it are not limited to damascene wiring and can be formed by structuring the conductive film for the wiring, for example, by tungsten wiring, aluminum wiring, or similar methods.

[0097] The semiconductor device of the present embodiment is manufactured as described above. <Hinsichtlich der Hauptfunktionen und Effekte>

[0098] In the present embodiment, the resistive element 3 is formed by the semiconductor layer SM forming the SOI substrate and the epitaxial semiconductor layer (semiconductor layer EP) formed on the semiconductor layer SM.

[0099] In particular, as in the Fig. 2, Fig. 3, Fig. 4 to Fig. As shown in Figure 5, the resistive element 3 is formed by the semiconductor layer SMb, which is the semiconductor layer SM located in the resistive element formation region 1B, and the semiconductor layer EP (epitaxial semiconductor layer) formed on the semiconductor layer SMb. The semiconductor layer EP has two semiconductor parts, EP2a and EP2b, which are formed separately on the semiconductor layer SMb. The semiconductor layer SMb comprises: the region RG1a (first interconnection region) on which the semiconductor part EP2a is formed; the region RG1b (second interconnection region) on which the semiconductor part EP2b is formed; and the region RG2 (element region, middle region), which lies between the region RG1a and the region RG1b and on which the semiconductor layer EP is not formed.

[0100] In the present embodiment, the semiconductor layer SMb, which forms the resistive element 3, has region RG2 (element part, middle part) where the semiconductor layer EP is not formed, and the resistance value of the resistive element 3 can be increased by region RG2. That is, the semiconductor layer EP is not formed on the semiconductor layer SMb located in region RG2, and the thickness of the resistive element 3 in region RG2 is thinner than the thickness of the resistive element 3 in either region RG1a or RG1b. This makes it possible to achieve the resistance value of the resistive element 3 by region RG2. In particular, the thickness T1 (see Fig. 2) The semiconductor layer SMb is thinner than the thickness of the gate electrode GE, preferably 30 nm or less (T1 ≤ 30 nm). By using the semiconductor layer SMb, located in region RG2 and having a thin (low) thickness T1, as the current path for the resistive element 3, the resistance value of the resistive element 3 can be achieved, and consequently, its resistance value can be increased. Furthermore, the thin thickness T1 of the semiconductor layer in region RG2 achieves the resistance value of the resistive element 3, thus reducing the length of the resistive element 3 required to ensure the necessary resistance value (length along the direction in which the current flows). Since the area required for arranging the resistive element 3 in the semiconductor device can be reduced, this is consequently advantageous for miniaturizing (reducing the area of) the semiconductor device.

[0101] The semiconductor layer SM of the SOI substrate 1 is also used to form the MISFET 2 and the resistive element 3, and the channel region of the MISFET 2 is formed in the semiconductor layer SMa directly beneath the gate electrode GE. Therefore, the thickness T1 of region RG2 of the semiconductor layer SMb is approximately equal to the thickness of the semiconductor layer SMa located directly beneath the gate electrode GE of the MISFET. The thickness of the semiconductor layer SMa and the semiconductor layer SMb is preferably 30 nm or less, more preferably 3 nm to 30 nm.

[0102] In contrast to the present embodiment, it is assumed here that the semiconductor layer EP (semiconductor parts EP2a and EP2b) is not formed on the semiconductor layer SMb. In this case, the pins PG2a and PG2b are connected to the semiconductor layer SMb instead of the semiconductor parts EP2a and EP2b. However, since the thickness of the semiconductor layer SMb is thin in this case when the contact holes CT are formed, the problem arises that the contact holes CT2a and CT2b could pierce (penetrate) the semiconductor layer SMb, which is undesirable.

[0103] In contrast, in the present embodiment, the semiconductor part EP2a is formed on region RG1a of the semiconductor layer SMb, the semiconductor part EP2b is formed on region RG1b of the semiconductor layer SMb, and the pin PG2a is positioned above and electrically connected to the semiconductor part EP2a, and the pin PG2b is also positioned above and electrically connected to the semiconductor part EP2b. Therefore, when forming the contact holes CT, it is possible to adequately prevent the contact holes CT2a and CT2b from penetrating the semiconductor layers EP and SMb. This improves the reliability of the semiconductor device. Furthermore, the manufacturing result of the semiconductor device can be improved.

[0104] Furthermore, in the present embodiment, as in the Fig. 2, Fig. 3, Fig. 4 to Fig. Figure 5 shows that the semiconductor parts EP2a and EP2b are formed on the semiconductor layer SMb, and the metal silicide layer MS is formed on the surface (upper layer part) of each of the semiconductor parts EP2a and EP2b. Therefore, in the resistive element formation area 1B, the thickness of the semiconductor area (here the semiconductor layer EP and the semiconductor layer SMb) used to form the metal silicide layer MS can be increased by the thickness corresponding to the presence of the semiconductor parts EP2a and EP2b, so that the metal silicide layer MS can be adequately formed.

[0105] The thickness of the semiconductor layer EP formed on the semiconductor layer SMb (respective semiconductor parts EP2a and EP2b) can be, for example, about 20 nm to 60 nm.

[0106] In the present embodiment, the resistive element 3 is formed from the semiconductor layer SMb and the semiconductor layer EP (semiconductor parts EP2a and EP2b). One of the main features of the present embodiment is that the resistance of the resistive element 3 is further increased by adjusting the impurity concentrations in the semiconductor layer SMb and the semiconductor layer EP (respective semiconductor parts EP2a and EP2b).

[0107] This means that in the present embodiment, each of the regions RG1a and RG1b (first connecting part and second connecting part) of the semiconductor layer SMb is arranged adjacent to region RG2 (element part, middle part) of the semiconductor layer SMb and has the p-type region R1 with low concentration (first low concentration region) with an impurity concentration that is lower than that of region RG2 (element part, middle part) of the semiconductor layer SMb. Furthermore, each of the semiconductor parts EP2a and EP2b has the p-type region R2 with medium concentration (first medium concentration region), which is located on top of the low concentration region R1 and has an impurity concentration that is higher than that of the low concentration region R1. This allows the resistance of the resistive element 3 to be increased. This will be explained in more detail below with reference to Fig. 27 and Fig. 10, mentioned above, described.

[0108] Here, it is assumed that the impurity concentrations in the semiconductor layer SMb and the semiconductor parts EP2a and EP2b, which form the resistive element 3, are uniform, and this case is referred to below as the investigation example. Resistorive element 3 is also referred to as resistive element 103 in the investigation example. Fig. Figure 27 is a partially enlarged cross-sectional view of the resistance element 103 of the example under investigation and shows a cross-sectional view corresponding to the one mentioned above. Fig. 10.

[0109] The resistive element 103 of the investigation example differs from the resistive element 3 of the present embodiment in that the impurity concentrations in the semiconductor layer SMb and the semiconductor parts EP2a and EP2b are uniform in the resistive element 103 of the investigation example.

[0110] When a current flows in the resistive element 103 of the example under investigation, the current flows mainly in the paths YG101, which are shown schematically in Fig. Figure 27 is shown. Furthermore, a case is described here in which the potential of the aforementioned pin PG2a is higher than the potential of pin PG2b. Since, in the case of the resistive element 103 of the example under investigation, the impurity concentration is essentially uniform throughout the entire resistive element 103, the current flowing through region RG2 of the semiconductor layer SMb flows uniformly towards region RG1b of the semiconductor layer SMb and the semiconductor part EP2b on it, reaches the metal silicide layer MS, which is formed on the surface of the semiconductor part EP2b, and continues to flow from the metal silicide layer MS to pin PG2b on it.

[0111] In contrast, when current flows in the resistive element 3 of the present embodiment, the current flows mainly in the paths YG1, which are schematically shown in Fig. Figure 10 is shown. Furthermore, the case is also described here in which the potential of pin PG2b is higher than the potential of pin PG2a.

[0112] In the case of resistive element 3 of the present embodiment, region RG1b of the semiconductor layer SMb has the low-concentration region R1 adjacent to region RG2 (element part, middle part) of the semiconductor layer SMb, and semiconductor part EP2b has the medium-concentration region R2, which is located on top of the low-concentration region R1. The impurity concentration of the low-concentration region R1 in region RG1b of the semiconductor layer SMb is lower than the impurity concentration of region RG2 (element part, middle part) of the semiconductor layer SMb, and the impurity concentration of region R2 with medium concentration in region RG1b of the semiconductor layer SMb is higher than the impurity concentration of region R1 with low concentration.Consequently, the current that has flowed through region RG2 of the semiconductor layer SMb flows mainly towards region R2 with medium concentration of semiconductor part EP2b, while avoiding region R1 with low concentration in region RG1b of the semiconductor layer SMb, and flows through semiconductor part EP2b to reach the metal silicide layer MS formed on the surface of semiconductor part EP2b, and continues to flow from the metal silicide layer MS to the pin PG2b on it.

[0113] In the low-concentration region R1 in the RG1b region adjacent to the RG2 region of the SMb semiconductor layer, current flow is difficult, so the main current paths in the Fig. 10 shows the area R5 converging. This means that a cross-sectional area of ​​the current path (area of ​​a cross-section essentially perpendicular to a current direction) in the area shown in Fig. The area R5 shown in Figure 10 becomes smaller. Consequently, the resistance element 3 of the present embodiment can change the resistance value of the resistance element 3 in the area shown in Figure 10. Fig. The area R5 shown in Figure 10 is reached. Therefore, the resistance value of the resistive element 3 in the present embodiment is greater than that of the resistive element 103 in the example under investigation. Furthermore, area R5 corresponds to a near-region of a location where the upper surface of the semiconductor layer SMb and the end E2 of the semiconductor part EP2b make contact with each other.

[0114] Furthermore, the current does not always flow in the low-concentration region R1 within region RG1b of the SMb semiconductor layer, and may also flow in this region with a lower current density than that of the main path. Even in this case, the current flowing in the low-concentration region R1 within region RG1b of the SMb semiconductor layer is reduced by making the impurity concentration in this region lower than that in region RG2 of the SMb semiconductor layer.

[0115] A similar phenomenon occurs in region RG1a and in semiconductor part EP2a of the semiconductor layer SMb. However, the current direction is reversed, and the current flowing from the metal silicide layer MS formed on the surface of semiconductor part EP2a through semiconductor part EP2a flows mainly from region R2, with medium concentration of semiconductor part EP2a, towards region RG2 (element part) of the semiconductor layer SMb, while bypassing region R1, with low concentration in region RG1a of the semiconductor layer SMb. This increases the resistance of resistive element 3.

[0116] Although the case described here is where the potential of pin PG2a is higher than the potential of pin PG2b, the direction of the current flowing in resistive element 3 is also reversed when the potential of pin PG2b is higher than the potential of pin PG2a. However, the same phenomenon can occur as in the case where the potential of pin PG2a is higher than the potential of pin PG2b.

[0117] In this embodiment, the resistance of the resistive element 3 can be increased by adjusting the impurity concentrations in the semiconductor layer SMb and the semiconductor layer EP (respective semiconductor parts EP2a and EP2b) without changing the dimensions of the resistive element 3. Consequently, the resistance value of the resistive element 3 can be increased without increasing the area required to accommodate the resistive element 3 in the semiconductor device, and therefore without increasing the area of ​​the semiconductor device. This is therefore advantageous for miniaturizing (reducing the area of ​​the semiconductor device).

[0118] Furthermore, in the present embodiment, each of the regions RG1a and RG1b of the semiconductor layer SMb has a high-concentration region R3 (first high-concentration region R3), which is adjacent to the low-concentration region R1 and has a higher impurity concentration than that of the medium-concentration region R2. Furthermore, each of the semiconductor regions EP2a and EP2b has a high-concentration region R4 (second high-concentration region), which is located on top of the high-concentration region R3 and has an impurity concentration higher than that of the medium-concentration region R2. The low-concentration region R1 in region RG1a of the semiconductor layer SMb lies between region RG2 of the semiconductor layer SMb and the high-concentration region R3 in region RG1a of the semiconductor layer SMb.Furthermore, the low-concentration region R1 lies within region RG1b of the semiconductor layer SMb, between region RG2 of the semiconductor layer SMb and region R3 with high concentration within region RG1b of the semiconductor layer SMb. The metal silicide layer MS then forms on the surface of region R4 with high concentration of semiconductor part EP2a and on the surface of region R4 with high concentration of semiconductor part EP2b.

[0119] Fluctuations in the contact resistance between pins PG2a and PG2b and semiconductor parts EP2a and EP2b can be a factor in fluctuations in the resistance value of the resistive element 3. In the present embodiment, the region R4 is provided with a high concentration in each of the semiconductor parts EP2a and EP2b, and the metal silicide layer MS is formed on the surface of the region R4 with a high concentration. This makes it possible to reduce the contact resistance between pins PG2a and PG2b and semiconductor parts EP2a and EP2b and to suppress the fluctuations in the contact resistance between pins PG2a and PG2b and semiconductor parts EP2a and EP2b.This makes it possible to suppress or prevent fluctuations in the resistance value of the resistor and to suppress or prevent deviations from design values ​​in the resistance value of resistor element 3. This allows the performance of the semiconductor device with resistor element 3 to be improved.

[0120] The semiconductor parts EP2a and EP2b, which form the resistive element 3, can be manufactured in the same process as the semiconductor layers EP (respective semiconductor parts EP1a and EP1b), which form the source / drain regions (p +The p-type semiconductor regions (SD) of MISFET 2 can be formed by an epitaxial growth process. Furthermore, regions R3 with medium concentrations of the respective semiconductor parts EP2a and EP2b, which form the resistive element 3, can be formed by the ion implantation process to create the p-type semiconductor region EX for MISFET 2. Additionally, regions R4 with high concentrations of the semiconductor parts EP2a and EP2b, which form the resistive element 3, can be formed, and region R3 with high concentration of the semiconductor layer SMb can be formed by the ion implantation process to create the p-type semiconductor region EX for MISFET 2. + -Type semiconductor area SD for the MISFET 2 can be formed. Consequently, the number of manufacturing processes for the semiconductor device can be reduced, and the manufacturing costs of the semiconductor device can be lowered.

[0121] Fig. Figure 28 is a graph showing a correlation between the layer resistance of resistive element 3 and the length D1 of region RG2 of the semiconductor layer SMb. A vertical axis of the graph in Fig. 28 corresponds to the layer resistance of the resistance element 3. Furthermore, a horizontal axis corresponds to Fig. 28 of length D1 of region RG2 of the semiconductor layer SMb, which forms the resistive element 3. However, the layer resistance of the vertical axis of the graph is Fig. 28 standardized by the layer resistance when D1 = 5 µm. The length D1 is essentially parallel to the main surface of the SOL substrate 1 and along the current direction and corresponds to the length (dimension) in the X-direction in Fig. 1. Furthermore, the length D1 also corresponds to a distance between the semiconductor part EP2a and the semiconductor part EP2b.

[0122] As can be seen from the graphic of Fig. As can be seen in Figure 28, the layer resistance of the resistive element 3 increases when the length D1 of region RG2 of the semiconductor layer SMb forming the resistive element 3 is shortened. This can be explained as follows: with respect to the occupation ratio of the resistance to the total resistance of the resistive element 3, the increase in resistance, due to the difficulty for current to flow in the regions R1 with low concentrations of regions RG1a and RG1b of the semiconductor layer SMb described above, becomes large when the aforementioned length D1 is shortened. Therefore, the present embodiment has a large effect when the length D1 is short. The aforementioned length D1 is preferably 5 µm or less (i.e., D1 ≤ 5 µm), more preferably 3 µm or less (i.e., D1 ≤ 3 µm), and even more preferably 2 µm or less (i.e., D1 ≤ 2 µm).

[0123] Fig. Figure 29 is a graph showing a correlation between the heat generation quantity of the resistance element 3 and the aforementioned length D1. The vertical axis of the graph in Fig. 29 corresponds to the heat generation quantity of resistance element 3. Furthermore, the horizontal axis of the graph corresponds to Fig. 29 of length D1 of region RG2 of the semiconductor layer SMb, which forms the resistive element 3. However, the heat generation quantity of the vertical axis of the graph in Fig. 29 standardized by the amount of heat generated when D1 = 5 µm.

[0124] In Fig. 29 shows that the slope of the graph increases when the aforementioned length D1 is 7 µm or more. Consequently, the aforementioned length D1 is preferably 7 µm or less (i.e., D1 ≤ 7 µm).

[0125] Next, a modification example of the resistance element 3 of the present embodiment will be described with reference to Fig. 30 described. Fig. Figure 30 is a cross-sectional view showing a modification example of the resistance element 3 of the present embodiment, and shows a cross-sectional view accordingly. Fig. 10, listed above.

[0126] In one case of Fig. In Figure 30 (modification example), a gap SK is formed between the semiconductor part EP2b and the underlying semiconductor layer SMb near the end E2 of the semiconductor part EP2b. Furthermore, a gap SK is formed near the end E1 of the semiconductor part EP2a between the semiconductor part EP2a and the underlying semiconductor layer SMb; however, this structure corresponds to a structure in which the reference numeral EP2b is replaced by the reference numeral EP2a, the reference numeral E2 is replaced by the reference numeral E1, and the reference numeral RG1b is replaced by the reference numeral RG1a.

[0127] The gap SK is a section in which the semiconductor layer EP (specifically semiconductor parts EP2a and EP2b) is located above the semiconductor layer SMb, and the lower surface of the semiconductor layer EP (specifically semiconductor parts EP2a and EP2b) and the upper surface of the semiconductor layer SMb are separated from each other. The rest of the gap SK is filled with the insulating film pattern ZMP2.

[0128] In the case of Fig. 10. As mentioned above, when current flows in the resistive element 3, it mainly flows in the Fig. 10 schematically shown paths YG2. That is, the current that has flowed through the region RG2 of the semiconductor layer SMb flows towards the region R2 with medium concentration of the semiconductor part EP2b, while avoiding the region R1 with low concentration in the region RG1b of the semiconductor layer SMb, and flows through the semiconductor part EP2b to reach the metal silicide layer MS formed on the surface of the semiconductor part EP2b.

[0129] In the case of Fig. In the modified example (30), the current cannot cross the SK gap. Consequently, in this case, Fig. 30 (Modification example) the current mainly in the paths YG2, which are schematically shown in Fig. Figure 30 shows the current flowing through region RG2 of the semiconductor layer SMb. This means that the current bypasses the gap SK, enters the low-concentration region R1 in region RG1b of the semiconductor layer SMb, then flows towards the medium-concentration region of semiconductor part EP2b above the low-concentration region R1, and flows through semiconductor part EP2b to reach the metal silicide layer MS formed on the surface of semiconductor part EP2b. In the case of Fig. 30 (modification example) can, since the current path runs through a part of the low-concentration area R1 by providing the gap SK, further increase the resistance value of the resistive element 3 than in the case where the gap SK is missing. Consequently, in the case of Fig. 30 (modification example) the resistance value of resistor element 3 can be further increased without changing the dimensions of resistor element 3. Thus, if the modification example of Fig. When applied, the resistance value of the resistive element 3 can be further increased without increasing the area required to arrange the resistive element 3 in the semiconductor device, i.e., without increasing the area of ​​the semiconductor device, making it more advantageous for miniaturization (reduction of the area) of the semiconductor device.

[0130] A method for obtaining a structure of Fig. 30 is referred to in the Fig. 31, Fig. 32 to Fig. 33 described. Fig. 31, Fig. 32 to Fig. Figure 33 are cross-sectional views of a main part of a semiconductor device of a modification example of the present embodiment during its manufacturing process. Fig. 31 corresponds to the same process as that of Fig. 15 mentioned above, Fig. 32 corresponds to the same process as that of Fig. 16 mentioned above, and Fig. 33 corresponds to the same process as that of Fig. 17 mentioned above.

[0131] In the case of the modification example, as in Fig. As shown in Figure 31, the insulating film pattern ZMP1 formed by etching the aforementioned insulating film ZM1 has a rear portion SH on an outer circumferential side surface. The rear portion SH is a part where a lower portion of the side surface of the insulating film pattern ZMP1 protrudes outwards. This can be achieved by adjusting the etching conditions for the aforementioned insulating film ZM1. For example, the amount of over-etching during the etching of the insulating film ZM1 is reduced.

[0132] If the semiconductor layer EP is formed by an epitaxial growth process in a state where the insulating film pattern ZMP1 has the rear part SH, the semiconductor layer EP (semiconductor parts EP2a and EP2b) is formed to cover the rear part SH of the insulating film pattern ZMP1, as shown in Fig. 32 shown. If the side wall spacers SW1 and the insulating film pattern ZMP1 are then removed by etching, as shown in Fig. As shown in Figure 33, the gap SK is formed between the semiconductor part EP2b and the underlying semiconductor layer SMb near the end E2 of the semiconductor part EP2b, and the gap SK is formed between the semiconductor part EP2a and the underlying semiconductor layer SMb near the end E1 of the semiconductor part EP2a. The area where the rear part SH was present becomes the gap SK. When the insulating film pattern ZMP2 mentioned above is subsequently formed, the gap SK is filled with the insulating film pattern ZMP2. (Second example)

[0133] Fig. 34 is a top view of a main part of a semiconductor device according to a second embodiment, and Fig. Figure 35 is a cross-sectional view of the main part of the semiconductor device of the second embodiment. A top view is shown ( Fig. 34) and a cross-sectional view ( Fig. 35) of the resistance element formation area 1B. A cross-sectional view at a point on line GG in Fig. 34 essentially corresponds to the Fig. 35. In Fig. 35, the insulating films L1 and L2 mentioned above, the insulating film pattern ZMP2 and the wiring M1 are omitted for the sake of simplicity.

[0134] A difference between the semiconductor device of the second embodiment and the semiconductor device of the first embodiment will be explained below with reference to the Fig. 34 and Fig. 35 described.

[0135] In a second embodiment, in the resistive element formation region 1B, the semiconductor layer EP formed on the semiconductor layer SMb has not only the semiconductor parts EP2a and EP2b, but also one or more semiconductor parts EP2c. In one case of Fig. 34 and Fig. 35 two EP2c semiconductor parts are provided, but the number of EP2c semiconductor parts can be one, three or more.

[0136] The semiconductor part EP2c is formed on the semiconductor layer SMb, spaced apart from the semiconductor parts EP2a and EP2b, and positioned between them. If multiple semiconductor parts EP2c are present, they are spaced apart. The conductivity types of the semiconductor layer SMb and the semiconductor parts EP2a, EP2b, and EP2c are the same and are p-type.

[0137] By including the semiconductor part EP2c in the resistive element formation region 1B, the semiconductor layer SMb not only has the aforementioned regions RG1a, RG1b, and RG2, but also a region (connecting region) RG3, on which the semiconductor part EP2c is formed. Since region RG3 of the semiconductor layer SMb is the region directly beneath the semiconductor part EP2c, the number of regions RG3 and the number of semiconductor parts EP2c are equal. Because the semiconductor part EP2c is located between the semiconductor parts EP2a and EP2b in the semiconductor layer SMb, region RG3 is located between regions RG1a and RG1b, but away from regions RG1a and RG1b. That is, region RG3 exists in the center of region RG2 (the element part) of the semiconductor layer SMb.

[0138] The impurity concentration (p-type impurity concentration) in region RG3 of the SMb semiconductor layer is lower than the impurity concentration (p-type impurity concentration) in region RG2 of the SMb semiconductor layer. Likewise, the impurity concentration (p-type impurity concentration) in semiconductor region EP2c is higher than the impurity concentration (p-type impurity concentration) in region RG3 of the SMb semiconductor layer. Specifically, the impurity concentration (p-type impurity concentration) in region RG3 of the SMb semiconductor layer is the same as the impurity concentration (p-type impurity concentration) in the aforementioned low-concentration region R1, and the impurity concentration (p-type impurity concentration) in semiconductor region EP2c is the same as the impurity concentration (p-type impurity concentration) in region RG2 of the SMb semiconductor layer.Furthermore, the term "equal" as used here means that two or more objects being compared (here, "concentration of defects") are essentially the same. This means that the two or more objects being compared are identical in design, but not necessarily identical in the products actually manufactured due to differences in production.

[0139] On each of the semiconductor parts EP2a and EP2b, the pin PG is arranged and is electrically connected to the pin PG, but the pin PG is not arranged on the semiconductor part EP2c and is not connected to the semiconductor part EP2c.

[0140] Other configurations of the semiconductor device according to the second embodiment are essentially the same as those of the semiconductor device according to the first embodiment, so their repeated description is omitted here.

[0141] Next, a difference will be drawn between the manufacturing process of the semiconductor device of the second embodiment and the manufacturing process of the first embodiment mentioned above ( Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. 26) with reference to the Fig. 36, Fig. 37, Fig. 38 to Fig. 39 described. Fig. 36, Fig. 37, Fig. 38 to Fig. Figure 39 shows cross-sectional views of the main part of the semiconductor device of the second embodiment during the manufacturing process and show a cross-section accordingly. Fig. 35 mentioned above.

[0142] Fig. Figure 36 is a cross-sectional view in the same process as the one in Fig. 17 mentioned above. If, in the present second embodiment, the semiconductor layer EP is formed by epitaxial growth, the semiconductor parts EP2a, EP2b and EP2c are formed on the semiconductor layer SMb in the resistive element formation region 1B, as shown in Fig. 36 shown.

[0143] Fig. Figure 37 is a cross-sectional view in the same process as the one in Fig. 18 mentioned above. In the present second embodiment, when the ion implantation IM1 mentioned above is performed to form the p-type semiconductor region EX, the p-type defect is implanted into the semiconductor layers EP (respective semiconductor parts EP2a, EP2b, EP2c) and the region RG2 of the semiconductor layer SMb that is not covered by the semiconductor layer EP (respective semiconductor parts EP2a, EP2b and EP2c). During ion implantation IM1, the p-type defect is hardly introduced into the respective regions RG1a, RG1b and RG3 of the semiconductor layer SMb that are covered by the semiconductor layer EP (respective semiconductor parts EP2a, EP2b and EP2c) in the resistive element formation region 1B. At the stage where ion implantation IM1 is performed, essentially the entirety of each of the semiconductor parts EP2a, EP2b and EP2c in the resistive element formation area 1B is converted to the area R2 with medium concentration.Then, essentially the entire RG2 area of ​​the SMb semiconductor layer in the resistive element formation area 1B, which is not covered by the EP semiconductor layer (respective semiconductor parts EP2a, EP2b and EP2c), receives the same impurity concentration as the medium concentration area R2, and essentially the entire RG1a, RG1b and RG3 areas of the SMb semiconductor layer in the resistive element formation area 1B, which is covered by the EP semiconductor layer (respective semiconductor parts EP2a, EP2b and EP2c), becomes the low concentration area R1.

[0144] Fig. Figure 38 is a cross-sectional view in the same process as the one in Fig. 21 mentioned above. In the second embodiment, the semiconductor part EP2c is also covered with the photoresist pattern RP2. If the ion implantation IM2 described above is used to form the p +Since the p-type semiconductor region SD is used, the p-type defect is not implanted into the semiconductor part EP2c and the RG3 region of the underlying semiconductor layer SMb in the resistive element formation region 1B, because the semiconductor part EP2c is covered with the photoresist pattern RP2. With regard to the remaining process, the present embodiment is the same as Fig. 24 of the first embodiment.

[0145] Fig. Figure 39 is a cross-sectional view in the same process as the one in Fig. 24 mentioned above. In the second embodiment, the semiconductor part EP2c is covered with the insulating film pattern ZMP2. Consequently, if the metal silicide layer MS is formed by a salicide technique, the metal silicide layer MS is not formed on the surface of the semiconductor part EP2c. With regard to the rest of the process, the second embodiment is also the same as Fig. 24 of the first embodiment.

[0146] In the case of resistive element 3 of the second embodiment, the impurity concentration (p-type impurity concentration) of region RG3, which is located under the semiconductor part EP2c, is lower than the impurity concentration (p-type impurity concentration) of region RG2 (the region not covered by the semiconductor layer EP) of the semiconductor layer SMb. Therefore, the impurity concentration (p-type impurity concentration) of the semiconductor part EP2c is higher than the impurity concentration (p-type impurity concentration) of region RG3 of the semiconductor layer SMb.In particular, the defect concentration (p-type defect concentration) of region RG3 of the semiconductor layer SMb is the same as the defect concentration (p-type defect concentration) of the low-concentration regions R1 of regions RG1a and RG1b of the semiconductor layer SMb, and the defect concentration (p-type defect concentration) of semiconductor part EP2c is the same as the defect concentration (p-type defect concentration) of the medium-concentration regions R2 of semiconductor parts EP2a and EP2b. Furthermore, the term "equal" as used here means that two or more objects being compared (here, "defect concentration") are essentially the same. This means that the two or more objects being compared are identical in design, but not necessarily identical in the products actually manufactured due to differences in the manufacturing process.

[0147] Therefore, the current flowing in semiconductor region EP2c and region RG3 within and around resistive element 3 is as follows. That is, the current flowing through region RG2 of semiconductor layer SMb flows primarily towards semiconductor region EP2c, bypassing region RG3 of semiconductor layer SMb. Then, the current flowing through semiconductor region EP2c flows towards region RG2 of semiconductor layer SMb, bypassing region RG3 of semiconductor layer SMb, and flows into region RG2 of semiconductor layer SMb. This further increases the resistance of resistive element 3.

[0148] For this reason, the resistance of the resistive element 3 can be increased when the semiconductor part EP2c and the region RG3 are provided (second embodiment) compared to when the semiconductor part EP2c and the region RG3 are not provided (first embodiment). Consequently, in the second embodiment, the resistance value of the resistive element 3 can be further increased without changing its dimensions. Thus, the resistance value of the resistive element 3 can be further increased without increasing the area required for arranging the resistive element 3 in the semiconductor device, and therefore without increasing the area of ​​the semiconductor device. This is more advantageous for miniaturizing (reducing the area of) the semiconductor device.

[0149] Since the pin PG is not connected to the semiconductor part EP2c, the substance corresponding to the area R4 with high concentration is not formed in the semiconductor part EP2c.

[0150] Furthermore, in the first embodiment mentioned above, the length D1 corresponds to the distance between the semiconductor part EP2a and the semiconductor part EP2b, and the length D1 is preferably 5 µm or less.

[0151] In the present second embodiment, a distance D2 between the semiconductor parts EP2a, EP2b and EP2c is preferably 5 µm or less. That is, in the present second embodiment, the region RG2 of the semiconductor layer SMb is subdivided into a plurality of regions by the semiconductor parts EP2c and the region RG3 below it, and each length (length along the current direction, here length in the X-direction) of the plurality of regions is preferably 5 µm or less. (Third embodiment)

[0152] Fig. Figure 40 is a top view of a main part of a semiconductor device according to a third embodiment and shows a top view of the resistive element formation area.

[0153] In a third embodiment, a plurality of resistive elements 3 are formed, and the plurality of resistive elements 3 are connected by the wiring M1 (in Fig. 40 wiring connections shown (M1a, M1b, M1c, M1d, M1e and M1f) are connected in series. Fig. Figure 40 shows a case in which the five resistor elements 3 are connected in series; however, the number of resistor elements 3 connected in series can be changed. Fig. In section 5, the five resistor elements 3 are designated as resistor element 3a, resistor element 3b, resistor element 3c, resistor element 3d and resistor element 3e, in order from top to bottom. Fig. 40.

[0154] The respective resistive elements 3a, 3b, 3c, 3d, 3e have the same structure. Furthermore, each of the resistive elements 3a, 3b, 3c, 3d, 3e has the same structure as resistive element 3 of the first embodiment. The resistive elements 3a, 3b, 3c, 3d, 3e each extend in the X direction and are arranged in the Y direction. The semiconductor part EP2a of resistive element 3a and the semiconductor part EP2a of resistive element 3b are electrically connected to each other via pin PG and wiring M1c, and the semiconductor part EP2b of resistive element 3b and the semiconductor part EP2b of resistive element 3c are electrically connected to each other via pin PG and wiring M1d.Furthermore, the semiconductor part EP2a of resistive element 3c and the semiconductor part EP2a of resistive element 3d are electrically connected to each other via pin PG and wiring M1e, and the semiconductor part EP2b of resistive element 3d and the semiconductor part EP2b of resistive element 3e are electrically connected to each other via pin PG and wiring M1f. Furthermore, the semiconductor part EP2b of resistive element 3a is electrically connected to wiring M1b via pin PG, and the semiconductor part EP2a of resistive element 3e is electrically connected to wiring M1a via pin PG. Consequently, resistive element 3a, resistive element 3b, resistive element 3c, resistive element 3d, and resistive element 3e are connected in series between wiring M1b and wiring M1a, and the resistive element 3 with the high resistance value can be formed by their entirety.For example, if a low voltage is applied from wiring M1a via pin PG to the semiconductor part EP2a of the resistive element 3e, and if a higher voltage than the low voltage is applied to the semiconductor part EP2b of the resistive element 3a from wiring M1b via pin PG, the current flows in wiring M1a through the resistive elements 3a, 3b, 3c, 3d, 3e in succession from wiring M1b. (Fourth example)

[0155] Each of the Fig. 41 and Fig. Figure 42 is a top view of a main part of a semiconductor device according to a fourth embodiment and shows a top view of a resistive element formation area.

[0156] The Fig. 41 and Fig. Figure 42 shows a resistive element 3f and a resistive element 3g, respectively. The resistive element 3f has the same structure as the resistive element 3 of the first embodiment. Consequently, the semiconductor layer SMb that forms the resistive element 3f consists of a single-crystal semiconductor (e.g., single-crystal silicon).

[0157] The resistive element 3g of the fourth embodiment has a similar structure to the resistive element 3 of the first embodiment and consists of the semiconductor layer SMb and the semiconductor parts EP2a and EP2b mentioned above. However, unlike the resistive element 3f, the region RG2 (the region not covered by the semiconductor layer EP) of the semiconductor layer SMb that forms the resistive element 3g consists of a polycrystalline semiconductor (e.g., polycrystalline silicon). Fig. 41 is the semiconductor layer SMb consisting of a polycrystal semiconductor, shaded with dots for easier understanding.

[0158] A polycrystal semiconductor region of resistive element 3g (i.e., region RG2 of the semiconductor layer SMb) can be formed by damaging the single-crystal semiconductor layer SMb through ion implantation, thereby transforming the single-crystal region into the polycrystal region. During ion implantation for polycrystallization, resistive element 3f can be covered with the photoresist pattern. This prevents the semiconductor layer SMb, which forms resistive element 3f, from becoming polycrystallized.

[0159] In one case of Fig. 41. Resistor element 3f and resistor element 3g are connected in series. Specifically, the semiconductor part EP2a of resistor element 3f and the semiconductor part EP2a of resistor element 3g are electrically connected to each other via pin PG and wiring M1g. Furthermore, the semiconductor part EP2b of resistor element 3f is electrically connected to wiring M1b via pin PG, and the semiconductor part EP2b of resistor element 3g is electrically connected to wiring M1a via pin PG. Consequently, resistor element 3f and resistor element 3g are connected in series between wiring M1a and wiring M1b.For example, if the low voltage is applied to the semiconductor part EP2b of the resistive element 3g from the wiring M1a via the pin PG, and if the voltage higher than the low voltage is applied to the semiconductor part EP2b of the resistive element 3f from the wiring M1a via the pin PG, the current flows in the wiring M1a from the wiring M1b through the resistive elements 3f and 3g in succession.

[0160] In one case of Fig. 42. The resistive element 3f and the resistive element 3g are connected in parallel. In particular, the semiconductor part EP2a of the resistive element 3f and the semiconductor part EP2a of the resistive element 3g are electrically connected to each other via pin PG and the wiring M1a, and the semiconductor part EP2b of the resistive element 3f and the semiconductor part EP2a of the resistive element 3g are electrically connected to each other via pin PG and the wiring M1b. Consequently, the resistive element 3f and the resistive element 3g are connected in parallel between the wiring M1a and the wiring M1b.For example, if the low voltage is applied to the semiconductor part EP2b of each of the resistive elements 3f and 3g from the wiring M1b via the pins PG, and if the voltage higher than the low voltage is applied to the semiconductor part EP2b of each of the resistive elements 3f and 3g from the wiring M1a via the pins PG, the current in the wiring M1b flows both via a path that runs from the wiring M1a to the resistive element 3g and via a path that runs from the wiring M1a to the resistive element 3f.

[0161] Fig. Figure 43 is a graph showing the temperature dependence of the resistance value of the resistive element. A horizontal axis of the graph represents... Fig. 43 corresponds to the temperature of the resistance element and a vertical axis of the graph of Fig. 43 corresponds to the resistance value of the resistor element. The resistance value on the vertical axis of the graph of Fig. 43 is normalized by the resistance value at 27°C. The graph further shows... Fig. 43. A solid line indicates a case with the resistance element 3f alone, a dashed line indicates a case with the resistance element 3g alone, and a line with a dot indicates a case where the resistance element 3f and the resistance element 3g are connected in parallel (in one case of Fig. 42), and a line with two dots shows a case where the resistive element 3f and the resistive element 3g are connected in series (in a case of Fig. 41).

[0162] Since the semiconductor layer SMb, which forms the resistive element 3f, consists of a single-crystal semiconductor (e.g., single-crystal silicon), the resistance value of resistive element 3f has a positive temperature dependence. Since the region RG2 of the semiconductor layer SMb, which forms the resistive element 3g, consists of a polycrystalline semiconductor (e.g., polycrystalline silicon), the resistance value of resistive element 3g has a negative temperature dependence. The positive temperature dependence corresponds to a case in which the resistance value increases with increasing temperature, and the negative temperature dependence corresponds to a case in which the resistance value decreases with increasing temperature.

[0163] Resistor element 3f and resistor element 3g exhibit opposite temperature dependencies of their resistance values. This is because the temperature dependence of the resistance of a single-crystal semiconductor (e.g., single-crystal silicon) and the temperature dependence of the resistance of a polycrystalline semiconductor (e.g., polycrystalline silicon) are reversed.

[0164] When resistive element 3f and resistive element 3g are connected in series, the temperature dependence of the resistance of resistive element 3f and the temperature dependence of the resistance of resistive element 3g cancel each other out. For this reason, as can be seen from the graph of Fig. As can be seen from Figure 43, the resistance temperature coefficient of the resistive element consisting of the resistive elements 3f and 3g connected in series is smaller than the resistance temperature coefficient of resistive element 3f alone and the resistance temperature coefficient of resistive element 3g alone. Furthermore, as can be seen from the graph of Fig. As can be seen in Figure 43, the resistance temperature coefficient of the resistive element forming the parallel-connected resistive elements 3f and 3g is made smaller than the resistance temperature coefficient of resistive element 3f alone and the resistance temperature coefficient of resistive element 3g alone. Here, the resistance temperature coefficient corresponds to a coefficient that indicates the rate at which the resistance changes per 1°C of temperature, and a slope of the graph in Fig. 43 corresponds approximately to the resistance temperature coefficient. The positive temperature dependence mentioned above means that the resistance temperature coefficient is a positive value, and the negative temperature dependence mentioned above means that the resistance temperature coefficient is a negative value.

[0165] In the fourth embodiment, by connecting the resistive element 3f and the resistive element 3g in series or parallel, the resistance temperature coefficient of the entire resistive element can be reduced (its absolute value). This makes it possible to suppress or prevent fluctuations in the resistance value of the resistive element due to factors such as changes in the ambient temperature of the semiconductor device or temperature changes of the semiconductor device due to heat generation. This makes it possible to achieve high performance of the semiconductor device (improved temperature drift). Furthermore, as shown in the diagram of Fig. As can be seen in Figure 43, the resistance temperature coefficient of the entire resistive element (the absolute value) is further reduced when resistive elements 3f and 3g are connected in series, rather than when resistive elements 3f and 3g are connected in parallel.

[0166] Furthermore, a polycrystalline semiconductor (e.g., polycrystalline silicon) melts more easily than a single-crystal semiconductor (e.g., single-crystal silicon) when a large current flows. This means that the polycrystalline semiconductor has a lower melting current than the single-crystal semiconductor. The melting current represents the lower limit of the current at which melting can occur. Therefore, the 3g resistor with a polycrystalline region tends to have a lower melting current than the 3f resistor without a polycrystalline region.

[0167] Consequently, in the fourth embodiment, the width W1 (dimension in the Y direction) of the region RG2 of the semiconductor layer SMb, which forms the resistive element 3g, is preferably 0.2 µm or more (W1 ≥ 0.2 µm), more preferably 0.2 µm or more and 1.0 µm or less (1.0 µm ≥ W1 ≥ 0.2 µm), and further preferably 0.5 µm or more and 1.0 µm or less (1.0 µm ≥ W1 ≥ 0.5 µm). Thus, the melting current of the resistive element 3g with the polycrystal region can be increased to a certain extent, thereby reducing the risk of the resistive element 3g melting with the polycrystal region when a high current flows. This further improves the reliability of the semiconductor device.

[0168] However, since the resistive element 3f does not have a polycrystal region, a melting phenomenon is less likely to occur. Consequently, in the fourth embodiment, the width W2 (dimension in the Y direction) of the region RG2 of the semiconductor layer SMb forming the resistive element 3f can be smaller than the width W1 of the region RG2 of the semiconductor layer SMb forming the resistive element 3g, and is also permissible at 0.2 µm or less. (Fifth example)

[0169] Fig. 44 and Fig. Figures 45 are a top view (44) and a cross-sectional view (45) of a semiconductor device according to a fifth embodiment and show the top view and the cross-sectional view of the resistive element formation area 1B in which the resistive element 3 is formed. The cross-sectional view along line HH in Fig. 44 essentially corresponds to Fig. 45. In Fig. For the sake of simplicity, the insulating films L1 and L2 mentioned above, the insulating film pattern ZMP2, and the wiring M1 are omitted from the figures. Furthermore, the following is shown in the Fig. 44 and Fig. The resistance element 3 shown in Figure 45 is hereby referred to as resistance element 3h.

[0170] The in the Fig. 44 and Fig. The resistance element 3h shown in Figure 45 is similar to the resistance element 3 of the first embodiment, but differs from the resistance element 3 of the first embodiment in the following points.

[0171] In one case of Fig. 44 and Fig. 45, the semiconductor layer EP formed on the semiconductor layer SMb in the resistive element formation region 1B has not only the semiconductor parts EP2a and EP2b, but also the semiconductor part EP2d. That is, the semiconductor part EP2a, the semiconductor part EP2b, and the semiconductor part EP2d are formed on the semiconductor layer SMb, and the semiconductor part EP2a, the semiconductor part EP2b, and the semiconductor part EP2d are spaced apart from each other. The semiconductor part EP2d is spaced apart from the semiconductor parts EP2a and EP2b and is located between the semiconductor part EP2a and the semiconductor part EP2b.

[0172] By including the semiconductor part EP2d in the resistive element formation region 1B, the semiconductor layer SMb not only has regions RG1a, RG1b, and RG2, but also a region (connecting region) RG4, on which the semiconductor part EP2d is formed. Region RG4 of the semiconductor layer SMb is located directly beneath the semiconductor part EP2d. Since the semiconductor part EP2d is positioned between the semiconductor parts EP2a and EP2b within the semiconductor layer SMb, region RG4 is spaced apart from regions RG1a and RG1b and is located between them. That is, region RG4 exists in the center of region RG2 (the element formation region) of the semiconductor layer SMb. Consequently, region RG2 of the semiconductor layer SMb is divided into two regions, RG2a and RG2b, by the semiconductor part EP2c and the underlying region RG4.A portion of the RG2 region of the SMb semiconductor layer, located between the RG1a and RG4 regions, corresponds to the RG2a region, and a portion of the RG2 region of the SMb semiconductor layer, located between the RG1b and RG4 regions, corresponds to the RG2b region.

[0173] The RG2a area (which is located in the Fig. 44 and Fig. The area 45 (corresponding to the area shaded with dots), located between area RG1a and area RG4 in area RG2 of the semiconductor layer SMb, consists of a polycrystalline semiconductor (e.g., polycrystalline silicon). Furthermore, area RG2b, located between area RG1b and area RG4 in area RG2 of the semiconductor layer SMb, consists of a single-crystal semiconductor (e.g., single-crystal silicon). That is, area RG2 (an area not covered by the semiconductor layer EP) of the semiconductor layer SMb, which forms the resistive element 3h, has area RG2a made of polycrystalline material and area RG2b made of single-crystal material, and area RG2a made of polycrystalline material and area RG2b made of single-crystal material are connected in series between area RG1a and area RG1b. Furthermore, the area RG4 located below the semiconductor part EP2d lies between the area RG2a made of polycrystal and the area RG2b made of single crystal.The RG4 region can consist of a single-crystal semiconductor or a poly-crystal semiconductor; however, in this case, the RG4 region consists of a single-crystal semiconductor (e.g., single-crystal silicon).

[0174] In the fifth embodiment, the resistance of the polycrystalline region RG2a has a negative temperature dependence, while the resistance of the single-crystal region RG2b has a positive temperature dependence. Consequently, the polycrystalline region RG2a and the single-crystal region RG2b have opposite temperature dependencies of their resistance. As a result, the temperature dependence of the resistance of the polycrystalline region RG2a and the temperature dependence of the resistance of the single-crystal region RG2b cancel each other out. This makes it possible to reduce the absolute value of the temperature coefficient of resistance of the resistive element 3h in the fifth embodiment to a lower value than the absolute value of the temperature coefficient of resistance of the resistive element 3 in the first embodiment.For this reason, in the case of the fifth embodiment, it is also possible to suppress or prevent fluctuations in the resistance value of the resistive element due to a factor such as a change in the ambient temperature of the semiconductor device or a temperature change of the semiconductor device due to heat generation. This makes it possible to achieve the high performance of the semiconductor device (improvement of temperature drift).

[0175] Next, a difference will be drawn between the manufacturing process of the semiconductor device of the fifth embodiment and the manufacturing process of the first embodiment ( Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. 26) hereinafter referred to as the Fig. 46, Fig. 47, Fig. 48 to Fig. 49 described. Fig. 46, Fig. 47, Fig. 48 to Fig. Figure 49 shows cross-sectional views of the main part of the semiconductor device of the fifth embodiment during the manufacturing process and show the cross-section accordingly. Fig. 45.

[0176] Fig. Figure 46 is a cross-sectional view in the same process as the one in Fig. 17. In the fifth embodiment, where the semiconductor layer EP is formed by epitaxial growth, the semiconductor parts EP2a, EP2b and EP2d are formed on the semiconductor layer SMb in the resistive element formation region 1B, as shown in Fig. 46 shown.

[0177] Fig. Figure 47 is a cross-sectional view in the same process as the one in Fig. 18. In the fifth embodiment, when ion implantation IM1 is performed to form the p-type semiconductor region EX, the p-type defect is implanted into the semiconductor layers EP (respective semiconductor parts EP2a, EP2b, EP2d) and the respective regions RG2a and RG2b of the semiconductor layer SMb that are not covered by the semiconductor layer EP (respective semiconductor parts EP2a, EP2b, EP2d) in the resistive element formation region 1B. With this ion implantation IM1, the p-type defect is hardly introduced into the respective regions RG1a, RG1b, RG4 of the semiconductor layer SMb that are not covered by the semiconductor layer EP (respective semiconductor parts EP2a, EP2b, EP2d) in the resistive element formation region 1B.

[0178] Fig. Figure 48 is a cross-sectional view in the same process as the one in Fig. 21. In the fifth embodiment, region RG2b of the semiconductor layer SMb is covered with the photoresist pattern RP2, while region RG2a of the semiconductor layer SMb may be exposed without being covered with the photoresist pattern RP2. If ion implantation IM2 is used to form the p + When the p-type defect is implanted in the resistive element formation area 1B of the semiconductor layer SD, the p-type defect is not implanted in the RG2b region of the semiconductor layer SMb because this region is covered with the photoresist pattern RP2. However, the p-type defect can be implanted in the RG2a region of the semiconductor layer SMb because this region is not covered with the photoresist pattern RP2 and is exposed.

[0179] One step from Fig. 49 is not performed in the above-mentioned embodiments and is carried out after step 49. Fig. 48. In the fifth embodiment, after the execution of step (ion implantation IM2) of Fig. 48. The photoresist pattern RP2 is removed by ashing or the like, and then a photoresist pattern RP3 is formed on the semiconductor layer SMb and the semiconductor layer EP in the resistive element formation area 1B using a photolithographic technique. In the resistive element formation area 1B, the region RG2b of the semiconductor layer SMb is covered with the photoresist pattern RP3, but the region RG2a of the semiconductor layer SMb is not covered with the photoresist pattern RP3 and remains exposed. The MISFET formation area 1A is also covered with the photoresist pattern RP3.

[0180] After the formation of the photoresist pattern RP3, an ion implantation IM3 is performed to polycrystallize the RG2a region of the semiconductor layer SMb. During ion implantation IM3, for example, germanium (Ge) or boron difluoride (BF2) is implanted. Since the RG2a region of the semiconductor layer SMb is damaged by the ion implantation IM3, the RG2a region of the single-crystal silicon semiconductor layer becomes amorphous. Subsequently, the RG2a region of the semiconductor layer SMb transitions from an amorphous state to a polycrystal state by undergoing an annealing (heat treatment) after the removal of the photoresist pattern RP3. Consequently, the RG2a region of the semiconductor layer SMb then consists of the polycrystal semiconductor (for example, polycrystal silicon).

[0181] Since the RG2b region of the SMb semiconductor layer is covered with the RP3 photoresist pattern, it is not damaged by the IM3 ion implantation and remains in a single-crystal state. Furthermore, since the SMa and EP semiconductor layers in the MISFET formation region 1A are also covered with the RP3 photoresist pattern, they are not damaged by the IM3 ion implantation and remain in a single-crystal state.

[0182] In the fifth embodiment, the step of forming the insulating film pattern ZMP2 and the metal silicide layer MS is also carried out, but its description is omitted here. Furthermore, in the fifth embodiment, the semiconductor part EP2d is covered with the insulating film pattern ZMP2, so that the metal silicide layer MS is not formed on the surface of the semiconductor part EP2d when the metal silicide layer MS is formed using a silicide technique.

[0183] As also described in the fourth embodiment, the polycrystal semiconductor (for example, polycrystal silicon) melts more easily than the single-crystal semiconductor (for example, single-crystal silicon) when a large current flows through it.

[0184] Consequently, in the fifth embodiment, the width W3 (dimension in the Y direction) of the region RG2a (polycrystal region) of the semiconductor layer SMb, which forms the resistive element 3h, is 0.2 µm or more (W3 ≥ 0.2 µm), preferably 0.2 µm or more and 1.0 µm or less (1.0 µm ≥ W3 ≥ 0.2 µm), and more preferably 0.5 µm or more and 1.0 µm or less (1.0 µm ≥ W3 ≧ 0.2 µm). Thus, the melting current of the polycrystal region (region RG2a) of the resistive element 3h can be increased to a certain extent, thereby reducing the risk of the polycrystal region (region RG2a) melting when a large current flows through it. This allows the reliability of the semiconductor device to be further improved.

[0185] Since the region RG2b of the semiconductor layer SMb, which forms the resistive element 3h, is the single-crystal region and not the polycrystal region, the melting phenomenon is less likely to occur. Therefore, in the fifth embodiment, the width W4 (dimension in the Y direction) of the region RG2b of the semiconductor layer SMb, which forms the resistive element 3h, can be smaller than the width W3 of the region RG2a (polycrystal region) of the semiconductor layer SMb, which forms the resistive element 3h, and is also permissible at 0.2 µm or less. However, if, in the resistive element 3h, the width W4 of the region RG2b of the semiconductor layer SMb is the same as the width W3 of the region RG2a (polycrystal region) of the semiconductor layer SMb, the present embodiment can offer the advantage of simple formation of the resistive element 3h.

Claims

[1] A semiconductor device comprising: a substrate (1); a resistance element (3) formed in a first region of the substrate; and a MISFET (2) formed in a second region of the substrate, wherein the substrate (1) comprises: a carrier substrate (SB); an insulating layer (BX) on the support substrate (SB); and a semiconductor layer (SM) on the insulating layer (BX), wherein the resistance element (3) consists of: the semiconductor layer (SMb) located in the first region; and an epitaxial semiconductor layer (EP) formed on the semiconductor layer (SMb) located in the first region, the epitaxial semiconductor layer (EP) comprises: a first semiconductor part formed on the semiconductor layer (SMb) located in the first region; and a second semiconductor part, which is formed on the semiconductor layer (SMb) located in the first region and is spaced apart from the first semiconductor part, the semiconductor layer (SMb) located in the first area comprises: a first connecting part (RG1a) on which the first semiconductor part is formed; a second connecting part (RG1b) on which the second semiconductor part is formed; and an element part (RG2) located between the first connecting part (RG1a) and the second connecting part (RG1b) on which no epitaxial semiconductor layer is formed, wherein a conductivity type of the first semiconductor part, the second semiconductor part, the first interconnect part (RG1a), the second interconnect part (RG1b) and the element part (RG2) is each a first conductivity type, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first low concentration area (R1) of the first conductivity type located next to the element part (RG2), wherein both the first semiconductor part and the second semiconductor part further have a first medium concentration region (R2) of the first conductivity type located on the first low concentration region (R1), where the impurity concentration of the first low-concentration area (R1) of both the first compound part (RG1a) and the second compound part (RG1b) is lower than the impurity concentration of the element part (RG2), where the impurity concentration of the first medium concentration region (R2) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first low concentration region (R1) of both the first interconnect part (RG1a) and the second interconnect part (RG1b), wherein a metal silicide (MS) layer is formed on a surface of both the first semiconductor part and the second semiconductor part, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first high concentration area (R3) of the first conductivity type, which is located next to the first low concentration area (R1), wherein both the first semiconductor part and the second semiconductor part further have a second high-concentration region (R4) of the first conductivity type located on top of the first high-concentration region (R3), where the impurity concentration of the first high-concentration region (R3) of both the first interconnect (RG1a) and the second interconnect (RG1b) is higher than the impurity concentration of the first medium-concentration region (R2) of both the first semiconductor part and the second semiconductor part, where the impurity concentration of the second high-concentration region (R4) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first medium-concentration region (R2) of both the first semiconductor part and the second semiconductor part, wherein the first low concentration area (R1) is arranged between the element part (RG2) and the first high concentration area (R3) of both the first connecting part (RG1a) and the second connecting part (RG1b), and wherein the metal silicide layer (MS) is formed on a surface of the second area with high concentration (R4). [2] The semiconductor device according to claim 1, wherein the first area with medium concentration (R2) and the element part (RG2) each have the same impurity concentration. [3] The semiconductor device according to claim 1, wherein the first high concentration area (R3) and the second high concentration area (R4) each have the same impurity concentration. [4] The semiconductor device according to claim 1, further comprising an element isolation region (ST) formed in the substrate (1), penetrating the semiconductor layer (SM) and the insulating layer (BX) and having a lower part reaching the support substrate (SB), wherein the semiconductor layer (SMb) located in the first region is surrounded by the element isolation region (ST), in a top view. [5] The semiconductor device according to claim 4, wherein the semiconductor layer (SMa) located in the second region is surrounded by the elemental insulation region (ST), in the top view, and wherein the semiconductor layer (SMb) located in the first region and the semiconductor layer (SMa) located in the second region are separated from each other by the element insulation region (ST). [6] A semiconductor device which has: a substrate (1); a resistance element (3) formed in a first region of the substrate; and a MISFET (2) formed in a second region of the substrate, wherein the substrate (1) comprises: a carrier substrate (SB); an insulating layer (BX) on the support substrate (SB); and a semiconductor layer (SM) on the insulating layer (BX), wherein the resistance element (3) consists of: the semiconductor layer (SMb) located in the first region; and an epitaxial semiconductor layer (EP) formed on the semiconductor layer (SMb) located in the first region, the epitaxial semiconductor layer (EP) comprises: a first semiconductor part formed on the semiconductor layer (SMb) located in the first region; and a second semiconductor part that is formed on the semiconductor layer (SMb) located in the first area and is spaced apart from the first semiconductor part; the semiconductor layer (SMb) located in the first area comprises: a first connecting part (RG1a) on which the first semiconductor part is formed; a second connecting part (RG1b) on which the second semiconductor part is formed; and an element part (RG2) located between the first connecting part (RG1a) and the second connecting part (RG1b) on which no epitaxial semiconductor layer is formed, wherein a conductivity type of the first semiconductor part, the second semiconductor part, the first interconnect part (RG1a), the second interconnect part (RG1b) and the element part (RG2) is each a first conductivity type, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first low concentration area (R1) of the first conductivity type located next to the element part (RG2), wherein both the first semiconductor part and the second semiconductor part further have a first medium concentration region (R2) of the first conductivity type located on the first low concentration region (R1), where the impurity concentration of the first low-concentration area (R1) of both the first compound part (RG1a) and the second compound part (RG1b) is lower than the impurity concentration of the element part (RG2), where the impurity concentration of the first medium concentration region (R2) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first low concentration region (R1) of both the first interconnect part (RG1a) and the second interconnect part (RG1b), wherein the epitaxial semiconductor layer (EP) is also formed on the semiconductor layer (SMa) located in the second region, the epitaxial semiconductor layer (EP) comprises: a third semiconductor part formed on the semiconductor layer (SMa) located in the second region; and a fourth semiconductor part, which is formed on the semiconductor layer (SMa) located in the second region and is spaced apart from the third semiconductor part, wherein the MISFET (2) has a gate electrode (GE) formed via a gate insulating film (GF) on the semiconductor layer (SMa) located in the second region, wherein one source region of the MISFET (2) is formed in the semiconductor layer (SM) and the third semiconductor part is located in the second region, wherein a drain region of the MISFET (2) is formed in the semiconductor layer (SM) and the fourth semiconductor part is located in the second region, wherein the source region consists of a first source region with a low concentration of the first conductivity type formed in the semiconductor layer (SM) and a first source region with a high concentration of the first conductivity type formed in the semiconductor layer (SM) and the third semiconductor part, and having an impurity concentration that is higher than that of the first source region with a low concentration, wherein the drain region consists of a first low-concentration drain region of the first conductivity type formed in the semiconductor layer (SM), and a first high-concentration drain region of the first conductivity type formed in the semiconductor layer (SM) and the fourth semiconductor part, which has an impurity concentration higher than that of the first low-concentration drain region, and where the impurity concentration of the element part (RG2), the first medium concentration area (R2), the first low concentration source area and the first low concentration drain area is the same. [7] The semiconductor device according to claim 6, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first high concentration area (R3) of the first conductivity type, which is located next to the first low concentration area (R1), wherein both the first semiconductor part and the second semiconductor part further have a second high-concentration region (R4) of the first conductivity type located on top of the first high-concentration region (R3), where the impurity concentration of the first high-concentration region (R3) of both the first interconnect (RG1a) and the second interconnect (RG1b) is higher than the impurity concentration of the first medium-concentration region (R2) of both the first semiconductor part and the second semiconductor part, where the impurity concentration of the second high-concentration region (R4) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first medium-concentration region (R2) of both the first semiconductor part and the second semiconductor part, wherein the first low concentration area (R1) is arranged between the element part (RG2) and the first high concentration area (R3) of both the first connecting part (RG1a) and the second connecting part (RG1b), and where the first high concentration area (R3), the second high concentration area (R4), the first high concentration source area and the first high concentration drain area each have the same impurity concentration. [8] The semiconductor device according to claim 7, wherein a metal silicide layer (MS) is formed on a surface of the second area with high concentration (R4). [9] The semiconductor device according to claim 6, wherein the thickness of the element part (T1) is thinner than the thickness of the gate electrode (GE). [10] A semiconductor device comprising: a substrate (1); a resistance element (3) formed in a first region of the substrate; and a MISFET (2) formed in a second region of the substrate, wherein the substrate (1) comprises: a carrier substrate (SB); an insulating layer (BX) on the support substrate (SB); and a semiconductor layer (SM) on the insulating layer (BX), wherein the resistance element (3) consists of: the semiconductor layer (SMb) located in the first region; and an epitaxial semiconductor layer (EP) formed on the semiconductor layer (SMb) located in the first region, the epitaxial semiconductor layer (EP) comprises: a first semiconductor part formed on the semiconductor layer (SMb) located in the first region; and a second semiconductor part that is formed on the semiconductor layer (SMb) located in the first area and is spaced apart from the first semiconductor part; the semiconductor layer (SMb) located in the first area comprises: a first connecting part (RG1a) on which the first semiconductor part is formed; a second connecting part (RG1b) on which the second semiconductor part is formed; and an element part (RG2) located between the first connecting part (RG1a) and the second connecting part (RG1b) on which no epitaxial semiconductor layer is formed, wherein a conductivity type of the first semiconductor part, the second semiconductor part, the first interconnect part (RG1a), the second interconnect part (RG1b) and the element part (RG2) is each a first conductivity type, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first low concentration area (R1) of the first conductivity type located next to the element part (RG2), wherein both the first semiconductor part and the second semiconductor part further have a first medium concentration region (R2) of the first conductivity type located on the first low concentration region (R1), where the impurity concentration of the first low-concentration area (R1) of both the first compound part (RG1a) and the second compound part (RG1b) is lower than the impurity concentration of the element part (RG2), where the impurity concentration of the first medium concentration region (R2) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first low concentration region (R1) of both the first interconnect part (RG1a) and the second interconnect part (RG1b), wherein the epitaxial semiconductor layer (EP) further has a third semiconductor part which is formed on the semiconductor layer (SMb) located in the first region, is spaced apart from the first semiconductor part and the second semiconductor part and is arranged between the first semiconductor part and the second semiconductor part, wherein the semiconductor layer (SMb) located in the first area further has a third connecting part (RG3) on which the third semiconductor part is formed, wherein the third connecting part (RG3) is present in the middle of the element part (RG2), where the impurity concentration in the third compound part (RG3) is lower than the impurity concentration in the element part (RG2), and where the impurity concentration in the third semiconductor part is higher than the impurity concentration in the third interconnect part (RG3). [11] A semiconductor device comprising: a substrate (1); a resistance element (3) formed in a first region of the substrate; and a MISFET (2) formed in a second region of the substrate, wherein the substrate (1) comprises: a carrier substrate (SB); an insulating layer (BX) on the support substrate (SB); and a semiconductor layer (SM) on the insulating layer (BX), wherein the resistance element (3) consists of: the semiconductor layer (SMb) located in the first region; and an epitaxial semiconductor layer (EP) formed on the semiconductor layer (SMb) located in the first region, the epitaxial semiconductor layer (EP) comprises: a first semiconductor part formed on the semiconductor layer (SMb) located in the first region; and a second semiconductor part that is formed on the semiconductor layer (SMb) located in the first area and is spaced apart from the first semiconductor part; the semiconductor layer (SMb) located in the first area comprises: a first connecting part (RG1a) on which the first semiconductor part is formed; a second connecting part (RG1b) on which the second semiconductor part is formed; and an element part (RG2) located between the first connecting part (RG1a) and the second connecting part (RG1b) on which no epitaxial semiconductor layer is formed, wherein a conductivity type of the first semiconductor part, the second semiconductor part, the first interconnect part (RG1a), the second interconnect part (RG1b) and the element part (RG2) is each a first conductivity type, wherein both the first connecting part (RG1a) and the second connecting part (RG1b) further have a first low concentration area (R1) of the first conductivity type located next to the element part (RG2), wherein both the first semiconductor part and the second semiconductor part further have a first medium concentration region (R2) of the first conductivity type located on the first low concentration region (R1), where the impurity concentration of the first low-concentration area (R1) of both the first compound part (RG1a) and the second compound part (RG1b) is lower than the impurity concentration of the element part (RG2), wherein the impurity concentration of the first medium concentration region (R2) of both the first semiconductor part and the second semiconductor part is higher than the impurity concentration of the first low concentration region (R1) of both the first interconnect part (RG1a) and the second interconnect part (RG1b), and wherein a gap (SK) is formed between the first semiconductor part and the underlying semiconductor layer (SM) near one end (E1) of the first semiconductor part on one side opposite the second semiconductor part. [12] The semiconductor device according to claim 1, further comprising an intermediate insulating film (L1) formed on the substrate (1) to cover the semiconductor layer (SM) and the epitaxial semiconductor layer (EP), wherein a large number of conductive pins (PG) are embedded in the interlayer insulating film (L1), and wherein the plurality of conductive pins (PG) comprises a first pin (PG2a) formed on the first semiconductor part and electrically connected to the first semiconductor part, and a second pin (PG2b) formed on the second semiconductor part and electrically connected to the second semiconductor part.

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