Light-emitting diode indicator device

Abstract

Display device (100), comprising: a substrate (110) which has: a first subpixel (SP_1) and a second subpixel (SP_2), each having an associated emitting region (EA); and a non-emitting region (NEA) which surrounds the emitting regions (EA); a respective first electrode (310) in each of the first subpixel (SP_1) and the second subpixel (SP_2); a bank (320), wherein the bank (320) has a respective bank hole (BH) in each of the emitting areas (EA) and a bank trench (BT) in the non-emitting area (NEA); a first spacer (330) on the bench (320); a second spacer (340) inside the bank trench (BT); an emitting layer (350) on the first electrodes (310) and the bank trench (BT), which has several stacks (351, 353) and at least one charge-generating layer (352) between the several stacks (351, 353); and a second electrode (360) on the emitting layer (350), and wherein the second spacer (340) has at least one first spacer pattern (340a) and a second spacer pattern (340b) with a spacer pattern hole (PH) in between.

Description

Technical field

[0001] The present disclosure relates to a display device, such as a light-emitting diode display device, and in particular a display device (such as a light-emitting diode display device) which has a structure for reducing or preventing leakage current between adjacent subpixels. Discussion of the state of the art

[0002] For a current display device that shows information and allows interaction by a user who views the information, it is necessary to have diverse sizes, diverse shapes and diverse functions.

[0003] The display device may include a liquid crystal display (LCD) device, an electrophoresis display (EPD) device and / or a light-emitting diode (LED) display device.

[0004] The LED display device is an emission-type display and can be manufactured to be lightweight and thin-profile because, unlike an LCD device, it does not require an additional light source. Furthermore, the LED display device offers advantages in terms of power consumption due to low-voltage drive and boasts superior color reproduction, response time, viewing angle, and contrast ratio. As a result, the LED display device has been researched as a next-generation display.

[0005] Although an organic light-emitting diode (OLED) display device can be exemplified by the LED display device, the material of an emitting layer is not limited to this.

[0006] The LED display device shows information by illuminating multiple pixels that have an emissive layer. LED displays can be classified as either active-matrix or passive-matrix, depending on the pixel control method used.

[0007] The active matrix type LED display device displays an image by controlling a current flowing through a light-emitting diode, using a thin-film transistor (TFT).

[0008] The LED indicator device has an anode, an emitting layer, and a cathode. When a voltage is applied to the anode and the cathode, a hole from the anode and an electron from the cathode move towards the emitting layer. The hole and the electron combine in the emitting layer to generate an exciton, and light is emitted when the exciton transitions from an excited state to a ground state.

[0009] To provide high-quality image information, the resolution of LED display devices is progressively increasing. As the resolution increases, the spacing between adjacent subpixels decreases. As a result, the image information becomes distorted due to leakage current along a lateral direction between the adjacent subpixels.

[0010] Although various methods have been proposed to prevent lateral leakage current in order to obtain a high-resolution LED display device, they are insufficient and further development is required.

[0011] DE 10 2018 129 156 A1 describes a display device with a bank hole in the upper part of a bank layer, wherein a cover layer is continuously formed in the lower surface and the side surfaces of the bank hole. OVERVIEW

[0012] Accordingly, embodiments of the present disclosure are directed to a light-emitting diode display device which essentially avoids one or more of the problems arising from the limitations and disadvantages of the prior art.

[0013] One objective of the present disclosure is to provide a light-emitting display device in which leakage currents between adjacent subpixels are reduced or prevented.

[0014] Additional features and advantages of the disclosure will be detailed in the following description and will be partly apparent to those skilled in the art from the description or can be learned by carrying out the disclosure. These and other advantages of the disclosure can be realized and achieved by means of the structure which is particularly emphasized in the written description, the claims thereto, and the accompanying drawings, or which can be derived from them.

[0015] To achieve these and other advantages, and in accordance with the objective of the present disclosure as embodied and generally described herein, a display device according to claim 1 and a display device according to claim 18 are provided according to a first aspect of the present invention. Further embodiments are described in the dependent claims.

[0016] It should be understood that both the preceding general description and the following detailed description are explanatory and exemplary and are intended to provide a further explanation of the disclosure as claimed, without limiting its scope. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are included to provide a deeper understanding of the revelation and are incorporated into this description as a part of it, illustrate various forms of revelation and, together with the description, serve to explain the principles of revelation. The drawings include: is Fig. 1 a top view showing a light-emitting diode display device according to an embodiment of the present disclosure; is Fig. 2 a top view showing a subpixel and a bank trench having a second spacer of a light-emitting diode display device, according to an embodiment of the present disclosure; is Fig. 3 a cross-sectional view showing a light-emitting diode display device according to an embodiment of the present disclosure; are Fig. 4A to 4D cross-sectional views showing a manufacturing process of a light-emitting diode display device according to an embodiment of the present disclosure; and is Fig. 5 a view showing an emitting layer of a light-emitting diode indicator device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Advantages and features of the present disclosure and implementation methods thereof are described by the following exemplary embodiments with reference to the accompanying drawings. However, the present disclosure can be implemented in various forms and is not to be understood as being limited to the exemplary embodiments listed herein. Instead, these exemplary embodiments are provided so that this disclosure is sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of the present disclosure. Furthermore, the protected scope of the present disclosure is defined by the claims and their equivalents.

[0019] The shapes, sizes, ratios, angles, numbers, and the like shown in the drawings to describe various exemplary embodiments of the present disclosure are given merely as examples. Therefore, the present disclosure is not limited to the illustrations in the drawings. The same reference numerals refer to the same elements throughout, unless otherwise indicated.

[0020] In the following description, where a detailed description of the relevant known function or configuration might unnecessarily obscure a feature or aspect of the present disclosure, a detailed description of such a known function or configuration may be omitted or a brief description may be provided.

[0021] Where terms like "exhibit", "have", "include", and the like are used, one or more other elements may be added unless the term, such as "only", is used. An element described in the singular is intended to include a plural of elements and vice versa, unless the context clearly indicates otherwise.

[0022] When interpreting an element, the element should be understood to include an error or tolerance range, even if no explicit description of such an error or tolerance range is provided.

[0023] Where positional relationships are described, for example, where the positional relationship between two parts is described using "on," "above," "below," "above," "below," "next to," "near," or the like, one or more other parts may be located between the two parts unless a more restrictive term, such as "immediately" (or "in an immediate way"), "directly" (or "in a direct way"), or "closely" (or "closely"), is used. For example, where one element or layer is located "on" another element or layer, a third layer or element may be located between them.

[0024] Although the terms “first,” “second,” A, B, (a), (b), and the like may be used herein to refer to different elements, these elements should not be interpreted as being limited by these terms, since they are not used to define any particular order or precedence. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and similarly, a second element could be called a first element, without departing from the scope of the present revelation.

[0025] Features of different embodiments of the present disclosure can be partially or completely connected or combined with one another. They can be technically linked and operated in various ways as those skilled in the art can reasonably understand. The embodiments can be implemented independently of one another or in conjunction with one another in a wide variety of combinations.

[0026] A light-emitting diode display device according to various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0027] Fig. Figure 1 is a top view showing a light-emitting diode display device according to an embodiment of the present disclosure.

[0028] In Fig. 1. A light-emitting diode (LED) display device 100 according to an embodiment of the present disclosure can have various elements for generating signals or for driving several subpixels SP_1, SP_2, and SP_3 in a display area AA. For example, the LED display device 100 can have at least one drive circuit for controlling a display panel. A drive circuit for controlling or driving the subpixels SP_1, SP_2, and SP_3 can have a gate drive unit 112, data signal lines, a multiplexer MUX, an electrostatic discharge circuit ESD, a high-level voltage line VDD, a low-level voltage line VSS, and an inverter circuit. The LED display device 100 can further have elements that are different from the elements for driving the subpixels SP_1, SP_2, and SP_3.For example, the LED display device can have 100 elements that provide a touch detection function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure detection function, and / or haptic feedback. The elements can be located in a non-display area (NA) or on an external circuit connected via a interface.

[0029] A substrate 110 can have a display area AA and a non-display area NA. In the display area AA of the substrate 110, several pixels P are arranged and an image is displayed. In the non-display area NA of the substrate 110, no image is displayed. For example, the non-display area NA can be called a boundary area, and there is no restriction in this regard. The non-display area NA can be adjacent to the display area AA and can be located outside of the display area AA. Alternatively, the non-display area NA can be arranged so that it surrounds all or part of the display area AA. The non-display area NA can be a region in which the several subpixels SP_1, SP_2, and SP_3 are not arranged, and there is no restriction in this regard.

[0030] Each pixel P in the display area AA can have multiple associated subpixels SP_1, SP_2, and SP_3. Each subpixel SP_1, SP_2, and SP_3 is an individual unit that emits light. The multiple subpixels SP_1, SP_2, and SP_3 can include a red subpixel SP_R, a green subpixel SP_G, a blue subpixel SP_B, and / or a white subpixel, and there is no restriction in this regard.

[0031] Each subpixel SP_1, SP_2, and SP_3 has a light-emitting diode and a subpixel circuit. For example, each subpixel SP_1, SP_2, and SP_3 can have a light-emitting diode for displaying an image and a subpixel circuit for driving or controlling the light-emitting diode.

[0032] Each subpixel SP can contain multiple transistors, one or more capacitors, and multiple traces. For example, each subpixel SP can have a 2T1K configuration, which includes two transistors and one capacitor. Alternatively, each subpixel SP can have a 3T1K, 4T1K, 5T1K, 6T1K, 7T1K, 3T2K, 4T2K, 5T2K, 6T2K, 7T2K, or 8T2K configuration.

[0033] The non-display area NA is a region in which several lines and several driver circuits for controlling the multiple subpixels SP_1, SP_2, and SP_3 of the display area AA are located. For example, several integrated circuits (ICs) and a driver circuit, such as the gate driver unit 112 and a data driver unit, can be located in the non-display area NA.

[0034] Although the non-display area NA changes the display area AA from a rectangular shape to Fig. The shape and arrangement of the display area AA and the non-display area NA, which are adjacent to each other, are not limited to the area enclosed by the LED display device 100. The display area AA and the non-display area NA can have a shape corresponding to a design of part of electronic equipment that includes the LED display device 100. The display area AA and the non-display area NA can have a circular shape corresponding to a wristwatch for a wearable device, and can have a free shape for a dashboard. For example, the display area AA can have a pentagonal shape, a hexagonal shape, an octagonal shape, a circular shape, and an elliptical shape, and there is no restriction in this respect.

[0035] The non-display area NA can have a bending area BA. The bending area BA can be located between the display area AA and a pad part 114 of the non-display area NA. The bending area BA can be a region in which a connecting line part is located.

[0036] The bending region BA can be a region in which a section of the substrate 110 is bent such that the pad part 114 and an external module bonded to the pad part 114 are positioned above a rear face of the substrate 110. For example, because the bending region BA is bent towards the rear face of the substrate 110, the external module bonded to the pad part 114 of the substrate 110 moves towards the rear face of the substrate 110 and is not visible in a top view of the substrate 110. Fig. 1 the display device 100 in top view before bending the bending area BA can be shown such that the pad part 114 in Fig. Since the bending area BA is visible, the pad portion 114 can be positioned on a rear side of the display device 100 such that it is no longer visible from the front of the display device 100. Furthermore, because the bending area BA is bent, the size of the non-display area NA is reduced in a user's top view, resulting in a narrow border. Although the bending area BA is located within the non-display area NA of the LED display device 100, there is no restriction in this regard. For example, the bending area BA can be located within the display area AA, and the display area AA can be bent in various directions such that the bending area BA of the display area AA has a similar effect to the bending area BA of the non-display area NA.

[0037] The pad part 114 is located on one side of the non-display area NA. The pad part 114 is a metallic pattern where the external module, such as a flexible printed circuit board (FPCB) or a chip-on-foil (COF), is bonded. Although the pad part 114 is located adjacent to one side of the substrate 110, its shape and arrangement are not restricted thereto.

[0038] The gate driver unit 112, which provides a gate signal to a thin-film transistor (TFT), can be located on another side of the non-display area NA. The gate driver unit 112 can have multiple gate driver circuits, and these multiple gate driver circuits can be formed directly on the substrate 110. For example, the gate driver unit 112 formed directly on the substrate 110 can be of a gate-in-panel (GIP) type.

[0039] The gate control unit 112 can be located between the display area AA and a dam DAM of the non-display area NA.

[0040] The high-level voltage line VDD, the low-level voltage line VSS, the multiplexer MUX, the electrostatic discharge circuit ESD and / or the multiple connecting line parts may be located between the display area AA and the pad part 114 of the non-display area NA, or may be located closer to the display area AA than the pad part 114 of the non-display area NA is to the display area AA.

[0041] The high-level voltage line VDD, the low-level voltage line VSS, the multiplexer MUX and the electrostatic discharge circuit ESD may be located between the display area AA and the bending area BA / may be located closer to the display area AA than the bending area BA is to the display area AA.

[0042] The multiple connecting line sections can be arranged in the non-display area NA. For example, the multiple connecting line sections can be arranged in the bending area BA of the non-display area NA, where the substrate 110 is bent. The multiple connecting line sections can form a structure for transmitting signals (voltages) from the external module, which is bonded to the pad section 114, to the display area AA or to a circuit unit, such as a gate driver unit 112. For example, multiple signals, such as signals for controlling the gate driver unit 112, a data signal, a high-level voltage, and a low-level voltage, can be transmitted through the multiple connecting line sections.

[0043] The dam DAM is positioned within the non-display area NA such that it surrounds all or part of the display area AA. The dam DAM may be adjacent to the display area AA or it may be located outside of the display area AA.

[0044] The dam DAM can be arranged around a circumferential area of ​​the display area AA to control the flow of an organic material for a second encapsulation layer on the light-emitting diode. The dam DAM can consist of a single dam structure or multiple individual dam structures.

[0045] The DAM dam can be located in the middle of or between the display area AA and the high-level voltage line VDD, the low-level voltage line VSS, the multiplexer MUX and the electrostatic discharge circuit ESD.

[0046] A crack detection line PCD can be located in the non-indication area NA of substrate 110.

[0047] The crack detection line PCD can be arranged between an end section or edge of the substrate 110 and the dam DAM. Alternatively, the crack detection line PCD can be arranged below the dam DAM in such a way that it partially overlaps the dam DAM.

[0048] Fig. Figure 2 is a top view of a light-emitting diode display device according to an embodiment of the present disclosure, which shows a subpixel and a bank trench which has a second spacer.

[0049] In Fig. 2. The substrate 110 can have an emitting region EA and a non-emitting region NEA surrounding the emitting region EA. The emitting region EA can be arranged as multiple emitting regions EA spaced apart from each other. The non-emitting region NEA can be arranged to surround the emitting region EA, i.e., to surround each of the multiple emitting regions EA.

[0050] The emitting area EA is a region in which light is emitted towards an external object (the display device). As in Fig. As shown in Figure 3, the issuing area EA can be a region in which a Bank 320 is not located.

[0051] The non-emitting area (NEA) is a region in which light is not emitted towards an external object (the display device). As in Fig. As shown in Figure 3, the non-emitting area (NEA) can be a region in which a Bank 320 is located.

[0052] Each of the multiple pixels P of the display area AA can have a first subpixel SP_1, a second subpixel SP_2 and a third subpixel SP_3.

[0053] Each of the first subpixel SP_1, the second subpixel SP_2 and the third subpixel SP_3 can have the emitting area EA, i.e., a corresponding instance of an emitting area EA can be found among the multiple emitting areas EA.

[0054] Each pixel P can have subpixels, with each subpixel emitting light corresponding to a different assigned color. For example, each pixel P can have a first subpixel SP_1, a second subpixel SP_2, and a third subpixel SP_3, each corresponding to a different assigned color.

[0055] Alternatively, each pixel P can have multiple subpixels, which in turn have subgroups of subpixels, each subgroup emitting light corresponding to a different assigned color. For example, each pixel P can have a first subpixel SP_1, two second subpixels SP_2, and a third subpixel SP_3, where the first subpixel SP_1 emits light of a first color, the second subpixels SP_2 emit light of a second color that differs from the first color, and the third subpixel SP_3 emits light of a third color that differs from both the first and second colors.

[0056] The first subpixel SP_1, the second subpixel SP_2 and the third subpixel SP_3 can have a rectangular shape, a pentagonal shape, a hexagonal shape, an octagonal shape, a circular shape or an elliptical shape, and there is no restriction in this regard.

[0057] The first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 can each emit light that corresponds to a different assigned color. For example, the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 can each emit light that corresponds to at least one of the colors red, green, and blue, respectively.

[0058] The third subpixel SP_3 can have a size larger than the first subpixel SP_1 and the second subpixel SP_2. As in Fig. As shown in Figure 2, the third subpixel SP_3 can be larger than the first subpixel SP_1 and larger than the second subpixel SP_2.

[0059] In the light-emitting diode display device, when the resolution is increased, the spacing between the first subpixel SP_1, the second subpixel SP_2 and the third subpixel SP_3 is reduced.

[0060] The LED display device 100 can have an emitting layer comprising multiple stacks (emitting units) and a charge generation layer between the multiple stacks. The charge generation layer can maintain a charge equilibrium between the multiple stacks.

[0061] The charge-generating layer can have multiple layers, including a first charge-generating layer and a second charge-generating layer. Each of the first and second charge-generating layers can have a negative-type charge-generating layer and a positive-type charge-generating layer. The first charge-generating layer can consist of an alkali metal, such as lithium (Li), sodium (Na), potassium (K), and cesium (Cs), or an organic layer doped with magnesium (Mg), strontium (Sr), barium (Ba), and radium (Ra).

[0062] A metal in the charge generation layer can cause a lateral leakage current (LLC). For example, when a subpixel is driven, neighboring subpixels may emit faint light due to a leakage current along a lateral direction between them, potentially distorting the image information.

[0063] The first subpixel SP_1, the second subpixel SP_2 and the third subpixel SP_3 can have different drive voltages to emit light.

[0064] For example, the drive voltage for emitting blue light can be higher than the drive voltage for emitting red or green light.

[0065] When the third subpixel SP_3 is activated, the neighboring subpixels can be caused to emit a faint light. An electron from the third subpixel SP_3 is transferred to the neighboring subpixels through the charge generation layer, which is continuously arranged between the adjacent subpixels. As a result, the third subpixel SP_3 can be in a similar state to the neighboring subpixels, which are in an off state, and can emit a faint light. Consequently, color purity and color reproducibility are reduced. In particular, the faint light can occur at relatively low grayscale levels.

[0066] The lateral leakage current can be reduced or minimized by means of a bank trench BT, which has a second spacer 340, which is arranged between the adjacent subpixels in the non-emitting area NEA.

[0067] Although in Fig. 2. In one embodiment, the second spacers 340 are arranged to surround each of the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3. In another embodiment, the second spacers 340 can be arranged to surround some of the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3. In some examples, the second spacers 340 can be arranged to surround the third subpixel SP_3, which is configured to emit only blue light. Because these subpixels have the highest drive voltage, there is a greater risk of leakage current from these subpixels to neighboring subpixels.

[0068] The emitting layer 350 is arranged on a first electrode 310 and the bank trench BT, which has the second spacer 340. Because the emitting layer 350 is interrupted between the adjacent subpixels in some exemplary embodiments by means of the bank trench BT, which has the second spacer 340, the transfer of electrons in the emitting layer 350 of the subpixel to the adjacent subpixel is minimized.

[0069] Because the lateral leakage current between neighboring subpixels is reduced or minimized, detection degradation between neighboring subpixels at a relatively low grayscale level is reduced and color reproducibility is improved.

[0070] Although in Fig. 2. In one embodiment, where the second spacer 340 and the bank groove BT are arranged amidst the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3, in another embodiment the second spacer 340 and the bank groove BT can be omitted between adjacent subpixels. In other words, assigned instances of the second spacer 340 and the bank groove BT can be arranged between an adjacent pair of subpixels, between several adjacent pairs of subpixels, or between all adjacent pairs of subpixels.

[0071] A first spacer 330 can be arranged such that it has a predetermined spacing from the multiple subpixels SP_1, SP_2, and SP_3. For example, the first spacer 330 can have a spacing from the multiple subpixels SP_1, SP_2, and SP_3 and can be surrounded by the multiple subpixels SP_1, SP_2, and SP_3. Although in Fig. 2. If a first spacer 330 is surrounded by four subpixels SP_1, SP_2, and SP_3, there is no restriction in this respect. The first spacer 330 can provide a space between the subpixels SP_1, SP_2, and SP_3 and can be separated from the subpixels SP_1, SP_2, and SP_3 by appropriate spaces. As used herein, the first spacer 330 can be referred to as an on-the-bench spacer, and the second spacer 340 can be referred to as an inside-the-bench spacer. It will be acknowledged that "first" and "second" are used merely as designations to refer to the spacers and are not to be considered restrictive.

[0072] The subpixels emitting light of the same color can be arranged symmetrically with respect to the first spacer 330. For example, the second subpixels SP_2 can be arranged facing each other or opposite each other with respect to the first spacer 330. The first spacer 330 can be located in a central region between the subpixels emitting light of the same color.

[0073] The first spacer 330 can diminish, reduce or occupy a space between the substrate 110, which has an emissive layer 350 and an upper substrate (an encapsulation layer 400), in order to minimize breakage of the LED display device 100 due to external influence.

[0074] Furthermore, the first spacer 330 can protect the emitting layer 350. For example, the emitting layer 350 can be formed using a precious metal mask (FMM), and the precious metal mask can be deformed due to its weight. Because the precious metal mask contacts the first spacer 330, deterioration or deformation of the bed 320 due to contact between the precious metal mask and the bed 320 is prevented.

[0075] Fig. Figure 3 is a cross-sectional view showing a light-emitting diode display device according to an embodiment of the present disclosure, and Fig. Figures 4A to 4D are cross-sectional views showing a manufacturing process of a light-emitting diode display device according to an embodiment of the present disclosure. Fig. 3 is along a line II' of Fig. 2 recorded.

[0076] In Fig. 3 The substrate 110 carries different elements of the LED display device 100. The substrate 110 can be made of glass or plastic material which has flexibility.

[0077] For example, substrate 110 can contain one of polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone and polycarbonate, and there is no restriction in this regard.

[0078] If the substrate 110 contains polyimide (PI), the substrate 110 can have two PI layers or two PI layers and an inorganic layer between the two PI layers.

[0079] A buffer layer 120 is arranged on a whole of the substrate 110.

[0080] Buffer layer 120 can contain an inorganic insulating material, such as silicon nitride (SiNx) and silicon dioxide (SiOx). Buffer layer 120 can also contain an organic insulating material, and there is no restriction in this regard.

[0081] The buffer layer 120 can have a single layer or multiple layers, each comprising one or more layers of silicon nitride (SiNx) and silicon oxide (SiOx). If the buffer layer 120 has multiple layers, a layer of silicon oxide (SiOx) and a layer of silicon nitride (SiNx) can be arranged alternately.

[0082] The buffer layer 120 can be omitted according to a type and material of the substrate 110 as well as a structure and type of thin-film transistor.

[0083] A thin-film transistor 200 can be arranged on the buffer layer 120. The thin-film transistor 200 can have a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode.

[0084] Although a drive thin-film transistor is known as the thin-film transistor 200 in the Fig. As shown in Figures 3 and 4A to 4D, the LED display device 100 may also include a different thin-film transistor, such as a switching thin-film transistor. Although in Fig. While the thin-film transistor 200 has a top-gate structure in sections 3 and 4A to 4D, the thin-film transistor can also have a different structure, such as a bottom-gate structure.

[0085] A semiconductor pattern 210 of the thin-film transistor 200 is arranged on the buffer layer 120.

[0086] Semiconductor pattern 210 can incorporate a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material can be low-temperature polycrystalline silicon, and there is no restriction in this regard. If semiconductor pattern 210 incorporates a polycrystalline semiconductor material, power consumption is reduced and reliability is improved.

[0087] Semiconductor pattern 210 can incorporate an oxide semiconductor material. For example, the oxide semiconductor material can be one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO), and there is no restriction in this regard. If semiconductor pattern 210 incorporates an oxide semiconductor material, an effect that suppresses leakage current is enhanced, and subpixel brightness variation during low-frequency driving is minimized.

[0088] If the semiconductor pattern 210 has a polycrystalline semiconductor material or an oxide semiconductor material, a section of the semiconductor pattern 210 may have a conductive region.

[0089] The semiconductor pattern 210 can consist of amorphous silicon (a-Si) or an organic semiconductor material, such as pentacene, and there is no restriction in this regard.

[0090] A first insulating layer 130 is arranged on the semiconductor pattern 210.

[0091] The first insulating layer 130 can be arranged between the semiconductor pattern 210 and a gate electrode 230 to isolate the semiconductor pattern 210 and the gate electrode 230.

[0092] The first insulating layer 130 can comprise an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx). The first insulating layer 130 can also comprise an organic insulating material, and there is no restriction in this regard.

[0093] The first insulating layer 130 can have contact holes to electrically connect a source electrode 250 and a drain electrode 270 to the semiconductor pattern 210.

[0094] A gate electrode 230 of the thin-film transistor 200 is arranged on the first insulating layer 130 such that it overlaps the semiconductor pattern 210.

[0095] The gate electrode 230 can be made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and can have a single layer or multiple layers thereof. However, there is no restriction in this regard.

[0096] A second insulating layer 140 is arranged on the gate electrode 230.

[0097] The second insulating layer 140 is arranged between the gate electrode 230 and the source electrode 250 as well as between the gate electrode 230 and the drain electrode 270 in such a way that it insulates the gate electrode 230 as well as the source electrode 250 and the drain electrode 270.

[0098] The second insulating layer 140 can comprise an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx). The second insulating layer 140 can also comprise an organic insulating material, and there is no restriction in this regard.

[0099] The second insulating layer 140 can have contact holes to electrically connect the source electrode 250 and the drain electrode 270 to the semiconductor pattern 210.

[0100] A source electrode 250 and a drain electrode 270 are arranged on the second insulating layer 140.

[0101] The source electrode 250 and the drain electrode 270 can be connected to the semiconductor pattern 210 through the contact holes in the first insulating layer 130 and the second insulating layer 140.

[0102] The source electrode 250 and the drain electrode 270 can comprise one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and can have a single layer or multiple layers thereof. However, there is no restriction in this regard.

[0103] For example, the source electrode 250 and the drain electrode 270 can have a triple layer of titanium (Ti) / aluminium (Al) / titanium (Ti), and there is no restriction in this regard.

[0104] A passivation layer 150 is arranged on the source electrode 250 and the drain electrode 270.

[0105] The passivation layer 150 can protect the thin-film transistor 200. The passivation layer 150 can comprise an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx). The passivation layer 150 can also comprise an organic insulating material, and there is no restriction in this regard.

[0106] The passivation layer 150 can have a contact hole to electrically connect the thin-film transistor 200 and a connecting electrode 170.

[0107] The passivation layer 150 can be omitted according to a structure and type of thin-film transistor 200.

[0108] A planarization layer 160 can be arranged on the passivation layer 150 or the thin-film transistor 200.

[0109] The planarization layer 160 can protect the thin-film transistor 200 and can mitigate or level out a step difference due to different patterns.

[0110] The planarization layer 160 can contain an organic insulating material, such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin, and there is no restriction in this regard.

[0111] The planarization layer 160 can have a single layer or multiple layers based on an arrangement of electrodes.

[0112] In the LED display device 100, because the number of signal lines increases with increasing resolution, the signal lines cannot be formed as a single layer with a predetermined spacing. As a result, the signal lines can be formed in multiple layers to maintain sufficient spacing. Furthermore, if the planarization layer 160 has multiple layers of a dielectric material, it can be used as a capacitor between metal layers.

[0113] The planarization layer 160 can have a first planarization layer 161 and a second planarization layer 162.

[0114] For example, a contact hole can be formed in the first planarization layer 161, and the connecting electrode 170 can be arranged in the contact hole of the first planarization layer 161. The second planarization layer 162, which has a contact hole, can be arranged on top of the first planarization layer 161 and the connecting electrode 170. A first electrode (such as an anode) 310 can be arranged in the contact hole of the second planarization layer 162. As a result, the thin-film transistor 200 and the first electrode 310 can be electrically connected to each other via the connecting electrode 170.

[0115] One end section of the connecting electrode 170 can be connected to the thin-film transistor and the other end section of the connecting electrode 170 can be connected to the first electrode 310.

[0116] The connecting electrode 170 can comprise one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and can have a single layer or multiple layers thereof. However, there is no restriction in this regard.

[0117] The connecting electrode 170 can be omitted based on a design and type of LED display device 100.

[0118] The first electrode 310 can be arranged on the planarization layer 160. The first electrode 310 can be arranged in the emitting region EA and a section of the non-emitting region NEA.

[0119] If the LED display device 100 is of a top-emission type, the first electrode 310 can function as a reflective electrode comprising an opaque conductive material. The first electrode 310 can comprise silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr), or an alloy thereof. For example, the first electrode 310 can have a triple layer of silver (Ag) / lead (Pb) / copper (Cu), and there is no restriction in this regard. Alternatively, the first electrode 310 can also comprise a transparent conductive material having a relatively high work function, such as indium tin oxide (ITO).

[0120] If the LED display device 100 is of a bottom-emission type, the first electrode 310 can function as a transparent electrode made of a transparent conductive material. The first electrode 310 can be made of either indium tin oxide (ITO) or indium zinc oxide (IZO).

[0121] A bank 320 can be arranged on the first electrode 310 and the planarization layer 160. The bank 320 can be arranged on at least part of the first electrode 310, for example at the edges of the first electrode 310, but not in the center of the first electrode 310. The bank 320 can be arranged on a section of the first electrode 310 in the non-emitting region NEA and cannot be arranged on a section of the first electrode 310 in the emitting region EA.

[0122] The Bank 320 can subdivide the multiple SP subpixels to minimize light blurring effects or problems and prevent color mixing at different viewing angles.

[0123] Bank 320 can define the issuing area EA and the non-issuing area NEA and can be located in the non-issuing area NEA.

[0124] Bank 320 can have a bank hole BH, which exposes the first electrode 310, and can have a bank trench BT in the non-emitting area NEA between the adjacent subpixels.

[0125] Bank 320 may contain at least one inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx), one organic insulating material, such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin, and a photoresist containing black pigment, and there is no restriction in this regard.

[0126] Bank 320 can be transparent, black, or any other color. Bank 320 can be arranged to cover an end section of the first electrode 310.

[0127] The bank trench BT can be formed by removing a section of bank 320. If bank 320 is completely removed in a region for bank trench BT, the bank trench BT can expose the planarization layer 160. Although in Fig. 3. While the bank 320 in the region for the bank trench BT is completely removed, in another embodiment the bank 320 may be partially removed. The bank 320 in the region for the bank trench BT may have a thickness of one-half to one-third of the thickness of the bank 320 in an adjacent region of the non-emitting area NEA.

[0128] The bank trench BT can overlap a first contact electrode 540_R, a first contact connection electrode 520, a second contact electrode and a second contact connection electrode 540_C.

[0129] A manufacturing process for the bank trench BT is described with reference to Fig. 4A to 4D will be illustrated.

[0130] At least one first spacer 330 can be arranged on the bench 320. The first spacer 330 can be made of the same material as the bench 320. The first spacer 330 can be formed simultaneously with the bench 320 or can be formed by a different process than the bench 320.

[0131] The thickness of the first spacer 330 can be greater than the thickness of the bench 320. For example, the thickness of the first spacer 330 can be within a range of approximately 1 µm to approximately 2 µm.

[0132] A second spacer 340 can be arranged on the bench 320 and the planarization layer 160. At least part of the second spacer 340 can be arranged on at least part of the bench 320. Edges of the second spacer 340 can be arranged on corresponding edges of the bench 320, while the center of the second spacer 340 cannot be arranged on the bench 320.

[0133] Because in some exemplary embodiments an emitting layer 350 and / or a second electrode 360 ​​are interrupted by the second spacer 340, it is prevented that an electron in the emitting layer 350 moves towards the adjacent subpixel. As a result, a lateral leakage current can be minimized due to the second spacer 340, even if the spacing between the adjacent subpixels is reduced.

[0134] The second spacer 340 can be arranged in the bank trench BT or can cover a section of a side wall of the bank trench BT.

[0135] The second spacer 340 can have a reverse-tapered shape. For example, the second spacer 340 can have a lower surface and an upper surface, and the size / width of the upper surface of the second spacer 340 can be larger than the size / width of the lower surface of the second spacer 340.

[0136] The second spacer 340 can be made of the same material as the bench 320 or the first spacer 330. A manufacturing process for the second spacer 340 is described with reference to Fig. 4A to 4D will be illustrated.

[0137] The thickness of the second spacer (340) can be greater than the thickness of the bench (320).

[0138] A second height or a second vertical distance H2 from the substrate 110 to the top of the second spacer 340 can be smaller than a first height or a first vertical distance H1 from the substrate 110 to the top of the first spacer 330. Because the second spacer 340 is arranged in the bank trench BT, which is formed by partially removing the bank 320, the height or vertical distance of the top of the second spacer 340 from the substrate 110 can be smaller than the height or vertical distance of the top of the first spacer 330 on the bank 320 from the substrate 110. Height and vertical distance here refer to a direction / orientation perpendicular to a display surface of the display device, i.e., perpendicular to the substrate 110. Alternatively or additionally, as in Fig. Figure 3 shows that a fourth height H4 of the second spacer 340 is smaller than a third height H3 of the first spacer 330.

[0139] If the second height or second vertical distance H2 of the top of the second spacer 340 from the substrate 110 is equal to or similar to the first height or first vertical distance H1 of the top of the first spacer 330 from the substrate 110, the second spacer 340 may come into contact with a precious metal mask (FMM) for forming the emitting layer 350 and thereby be distorted or damaged. In the embodiment of the present disclosure, because the second spacer 340 is arranged in the bank trench BT, the first spacer 330, instead of the second spacer 340, contacts the precious metal mask, and distortion or damage to the second spacer 340 is prevented.

[0140] The second spacer 340 can have at least three spacer patterns. For example, the second spacer can have a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c.

[0141] The first spacer pattern 240a, the second spacer pattern 340b, and the third spacer pattern 340c can be arranged so that they are separated from each other, i.e., separated laterally in a cross-sectional view. A spacer pattern hole PH can be arranged between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. In other words, a first spacer pattern hole PH can be arranged between the first spacer pattern 340a and the second spacer pattern 340b, and a second spacer pattern hole PH can be arranged between the spacer pattern 340b and the third spacer pattern 340c.In some examples, the second spacer 340 can have a first spacer pattern, a second spacer pattern, and a third spacer pattern, wherein a first spacer pattern hole PH is located between the first and second spacer patterns, and a second spacer pattern hole PH is located between the second and third spacer patterns. The second spacer can have at least one first spacer pattern and one second spacer pattern with a spacer pattern hole between them. Increasing numbers of spacer patterns and spacer pattern holes can advantageously further reduce the leakage current between subpixels. The second spacer, which has spacer patterns, can prevent the emitting layer 350 (and the second electrode 360) from forming or being deposited on side slopes of the second spacer.This is because the spacer patterns form overhangs, meaning that these slopes are shaded from above before deposition occurs. This allows for the formation of breaks / cuts / gaps in the emitting layer 350, thereby reducing leakage current between subpixels.

[0142] At least one of the spacer patterns can be arranged so that it is separated from bank 320. For example, the spacer pattern 340b of the second spacer 340 can be arranged so that it is separated from bank 320. The second spacer pattern 340b can be wider than the first spacer pattern 340a and wider than the third spacer pattern 340c.

[0143] At least one of the spacer patterns can be arranged to cover a section of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 can be arranged to cover a section or, each, associated sections of the bank 320.

[0144] Although in Fig. 3 the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 cover a section of the bench 320, the second spacer 340 in another embodiment may have several second spacer patterns 340b which are separated from the bench 320 in the bench trench BT.

[0145] Although in Fig. 3 the second spacer 340 has three spacer patterns, the number of spacer patterns can be changed according to a design, and there is no restriction in this respect.

[0146] An emitting layer 350 can be arranged on the first electrode 310, the bank 320, the first spacer 330, the second spacer 340 and the planarization layer 160.

[0147] Because the emitting layer 350 is interrupted in the non-emitting region NEA in some exemplary embodiments by means of the second spacer 340 and the spacer pattern hole PH, electron movement in the emitting layer 350 towards the adjacent subpixel is prevented. As a result, lateral leakage current can be minimized, even when the spacing between the adjacent subpixels is reduced. The emitting layer 350 may not form a continuous layer, but may instead have a number of cuts, gaps, or interruptions that separate the respective sections of the emitting layer 350 from one another. This can be the case due to the second spacer 340 in the bank trench BT.In particular, the emitting layer 350 may have: a break between a section of it which is arranged on the bank layer 320 and a section of it which is arranged on the first spacer pattern 340a, a break between a section of it which is arranged on the first spacer pattern 340a and a section of it which is arranged on the second spacer pattern 340b (i.e. due to the first spacer pattern hole PH), a break between a section of it which is arranged on the second spacer pattern 340b and a section of it which is arranged on the third spacer pattern 340c (i.e. due to the second spacer pattern hole PH), and / or a break between a section of it which is arranged on the third spacer pattern 340c and a section of it which is arranged on the bank 320.As used herein, a cut in a layer can refer to a cut through that layer, i.e., a complete cut through that layer, or to a surface cut in that layer, i.e., a cut that passes partially through that layer (i.e., a reduction with respect to thickness). In some examples, the emitting layer 350 may be reduced with respect to thickness in the region of the second spacer 340. For example, the second spacer 340 may have one or more chamfered sides where the emitting layer 350 is thinner, patchy, or non-continuous. The transmission of leakage current through the emitting area into this region may therefore be reduced.In other words, in the region of the second spacer 340, the deposition of the emitting layer 350 may be reduced to such an extent that the transmission of leakage current into this region is reduced during use. In the region of the second spacer 340, the emitting layer 350 may not be continuous or may not be uniform.

[0148] A section of the emitting layer 350 can be located on the planarization layer 160, and a section of the emitting layer 350 can be located in the bank trench BT. A section of the emitting layer 350 can be located between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340, i.e., in the spacer pattern holes PH.

[0149] The emitting layer 350 can have multiple stacks (emitting units). For example, the emitting layer 350 can have a first stack 351 and a second stack 353 (made of Fig. 5) and a charge generation layer 352 (from Fig. 5) exhibit. The structure of the emitting layer 350 is described with reference to Fig. 5 will be illustrated.

[0150] A second electrode (such as a cathode) 360 can be arranged on the emitting layer 350.

[0151] The second electrode 360 ​​can be interrupted in the non-emitting region NEA by means of the second spacer 340. The second electrode 360 ​​cannot form a continuous layer, but can instead have a number of cuts, gaps, or interruptions that separate respective sections of the second electrode 360 ​​from one another and correspond to the cuts / gaps / interruptions of the emitting layer 350.

[0152] A section of the second electrode 360 ​​can be arranged in the bank trench BT, and a section of the second electrode 360 ​​can be arranged between the first spacer pattern 340a, the second spacer pattern 340b and the third spacer pattern 340c of the second spacer 340, i.e. in the spacer pattern holes PH.

[0153] For example, each of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c has a reverse-tapered shape, in which a lateral surface of each spacer pattern 340a, 340b, and 340c and a top surface of the planarization layer 162 form an acute angle. As a result, the emitting layer 350 and the second electrode 360 ​​can be interrupted between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c, and a residual layer RL, which has the emitting layer 350 and the second electrode 360, can be arranged on the planarization layer 162 between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c.In other words, the term "residual layer" RL can be used to refer to the emitting layer 350 and the second electrode 360, which are arranged in the spacer pattern holes PH of the second spacer 340. The portion of the emitting layer 350 that is present in the residual layer RL can be separate from the portions of the emitting layer 350 that are arranged on the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. The portion of the second electrode 360 ​​that is present in the residual layer RL can be separate from the portions of the second electrode 360 ​​that are arranged on the first spacer pattern 340a, the second spacer pattern 340a, and the third spacer pattern 340c.The sections of the emitting layer 350, which are arranged on one or more of the spacer patterns 340a, 340b, 340c, can be separated from the sections of the emitting layer 350 which are arranged on the adjacent bank 320. The sections of the second electrode 360, which are arranged on one or more of the spacer patterns 340a, 340b, 340c, can be separated from the sections of the second electrode 360 ​​which are arranged on the adjacent bank 320.

[0154] The second electrode 360 ​​can supply an electron to the emitting layer 350 and can have a conductive material which has a relatively low work function.

[0155] If the LED display device 100 is of a top-emission type, the second electrode 360 ​​can function as a transparent electrode comprising a transparent conductive material. The second electrode 360 ​​can comprise either indium tin oxide (ITO) or indium zinc oxide (IZO).

[0156] Alternatively, the second electrode 360 ​​can also comprise a semi-transparent conductive material. For example, the second electrode 360 ​​can comprise at least one of the following alloys, such as lithium fluoride / aluminium (LiF / Al), cesium fluoride / aluminium (CsF / Al), magnesium:silver (Mg:Ag), calcium / silver (Ca / Ag), lithium fluoride / magnesium:silver (LiF / Mg:Ag), lithium fluoride / calcium / silver (LiF / Ca / Ag), and lithium fluoride / calcium:silver (LiF / Ca:Ag).

[0157] If the LED display device 100 is of a bottom-emission type, the second electrode 360 ​​can function as a reflective electrode comprising an opaque conductive material. For example, the second electrode 360 ​​can comprise silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr), or an alloy thereof.

[0158] Although not shown, a topcoat (CPL) can be arranged on the second electrode 360°.

[0159] The cover layer can protect the second electrode 360 ​​and improve the light extraction effect of the emitting layer 350. The cover layer can be a single layer or a multiple layer, and there is no restriction in this regard.

[0160] The top layer can be omitted based on a design and type of LED display device 100.

[0161] An encapsulation layer 400 can be arranged on the second electrode 360 ​​or the cover layer. The encapsulation layer 400 can protect the first electrode 310, the emitting layer 350, and the second electrode 360 ​​from moisture, oxygen, or particles from the outside of the display device. For example, the encapsulation layer 400 can prevent the ingress of oxygen and moisture from the outside to prevent oxidation of the materials of the first electrode 310, the second electrode 360, and the emitting layer 350.

[0162] The encapsulation layer 400 can have a transparent material so that light emitted from the emitting layer 350 can pass through the encapsulation layer 400.

[0163] The encapsulation layer 400 can comprise a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 to prevent the ingress of moisture or oxygen. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 can have a successively laminated structure.

[0164] The first encapsulation layer 410 and the third encapsulation layer 430 can comprise an inorganic material, such as silicon nitride (SiNx), silicon dioxide (SiOx), and aluminum oxide (AlyOz), and there is no restriction in this regard. The first encapsulation layer 410 and the third encapsulation layer 430 can be formed by a vacuum layer deposition process, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), and there is no restriction in this regard.

[0165] Each of the first encapsulation layer 410 and the third encapsulation layer 430 can have multiple layers, each having at least two layers. For example, the first encapsulation layer 410 can have a triple layer of silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx), and there is no restriction in this regard. Alternatively, the first encapsulation layer 410 can have a quadruple layer of silicon dioxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx) / silicon oxide (SiOx) have, and there is no restriction in this regard.

[0166] The second encapsulation layer 420 can cover one or more particles generated during a manufacturing process. The second encapsulation layer 420 can flatten an area of ​​the first encapsulation layer 410. For example, the second encapsulation layer 420 can be referred to as a particle cover layer.

[0167] The second encapsulation layer 420 can comprise an organic material from a polymer, such as silicon oxycarbide (SiOCz), epoxy, polyimide, polyethylene and acrylate, and there is no restriction in this regard.

[0168] The second encapsulation layer 420 can consist of a thermo-curable material, which is able to be cured by means of heat, or a photo-curable material, which is able to be cured by means of light.

[0169] A touch detection layer 500 can be arranged on the encapsulation layer 400.

[0170] The touch detection layer 500 can have a first touch electrode 540_R, a first touch connection electrode 520, a second touch electrode and a second touch connection electrode 540_C.

[0171] A section of the first contact electrode 540_R, the first contact connecting electrode 520, the second contact electrode and the second contact connecting electrode 540_C can be arranged to overlap the second spacer 340 and / or the bank trench BT.

[0172] The first contact electrode 540_R, the first contact connection electrode 520, the second contact electrode, and the second contact connection electrode 540_C can have a mesh pattern in which metal conductors, each with a relatively narrow width, intersect. The mesh pattern can be diamond-shaped. Alternatively, the mesh pattern can also be rectangular, pentagonal, hexagonal, circular, or elliptical, and there is no restriction in this regard.

[0173] The first contact electrode 540_R, the first contact connection electrode 520, the second contact electrode, and the second contact connection electrode 540_C may have an opaque conductive material with a relatively low resistance. For example, the first contact electrode 540_R, the first contact connection electrode 520, the second contact electrode, and the second contact connection electrode 540_C may have one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and may have a single layer or multiple layers thereof. However, there is no restriction in this regard.

[0174] For example, the first contact electrode 540_R, the first contact connecting electrode 520, the second contact electrode and the second contact connecting electrode 540_C can have a triple layer of titanium (Ti) / aluminium (Al) / titanium (Ti), and there is no restriction in this regard.

[0175] The first contact electrode 540_R, the first contact connection electrode 520, the second contact electrode and the second contact connection electrode 540_C can be made of the same material as the source electrode 250 and the drain electrode 270.

[0176] A touch buffer layer 510 can be arranged on the encapsulation layer 400. The touch buffer layer 510 can prevent the ingress of a solution (developing solution or etching solution) used in a manufacturing process for the touch sensing layer 500, or it can prevent the ingress of moisture from the outside of the display device into the emitting layer 350. Additionally, the touch buffer layer 510 can prevent multiple touch sensing metals on the touch buffer layer 510 from being interrupted by an external influence, and it can suppress an interference signal that is generated when the touch sensing layer 500 is activated.

[0177] The contact buffer layer 510 can comprise at least one inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx), and one organic insulating material, such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin, and there is no restriction in this respect.

[0178] The first contact connection electrode 520 can be arranged on the contact buffer layer 510.

[0179] For example, the first contact connection electrode 520 can be arranged between the adjacent first contact electrodes 540_R along a first direction (X-direction). The first contact connection electrode 520 can electrically connect the multiple first contact electrodes 540_R, which are spaced apart from each other and adjacent along the first direction (X-direction), and there is no restriction in this respect.

[0180] The first contact connection electrode 520 can be arranged to overlap the second contact connection electrode 540_C, which connects the adjacent second contact electrodes along a second direction (Y-direction). Because the first contact connection electrode 520 and the second contact connection electrode 540_C are arranged as different layers, the first contact connection electrode 520 and the second contact connection electrode 540_C can be electrically insulated.

[0181] A contact insulating layer 530 can be arranged on the contact buffer layer 510 and the first contact connecting electrode 520.

[0182] The contact insulating layer 530 can have a contact hole for electrically connecting the first contact electrode 540_R and the first contact connecting electrode 520.

[0183] The contact insulating layer 530 can electrically insulate the first contact connection electrode 520 and the second contact connection electrode 540_C.

[0184] The contact insulating layer 530 can have a single layer or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx), and there is no restriction in this respect.

[0185] The first contact electrode 540_R, the second contact electrode and the second contact connecting electrode 540_C can be arranged on the contact insulating layer 530.

[0186] The first contact electrode 540_R and the second contact electrode can be arranged at a distance from each other. Multiple first contact electrodes 540_R can be spaced apart along the first direction (X-direction). Adjacent first contact electrodes 540_R along the first direction (X-direction) can be connected to the first contact connection electrode 520 between the first contact electrodes 540_R. For example, adjacent first contact electrodes 540_R can be connected to the first contact connection electrode 520 through the contact hole in the contact insulating layer 530.

[0187] The adjacent second contact electrodes along the second direction (Y-direction) can be connected to each other by the second contact connection electrode 540_C. The second contact electrode and the second contact connection electrode 540_C can be formed in the same layer. For example, the second contact connection electrode 540_C can be located in the same layer as the second contact electrode and between the second contact electrodes. The second contact connection electrodes 540_C can be formed such that they extend from the second contact electrode.

[0188] The first contact electrode 540_R, the second contact electrode and the second contact connection electrode 540_C can be formed by the same process.

[0189] A touch planarization layer 550 can be arranged on the first touch electrode 540_R, the second touch electrode and the second touch connection electrode 540_C.

[0190] A touch control circuit can receive a touch signal from the first touch electrode 540_R and transmit a touch control signal to the second touch electrode. The touch control circuit can detect a user's touch using the mutual capacitance between the first touch electrode 540_R and the second touch electrode. For example, when a touch occurs at the LED display device 100, the capacitance between the first touch electrode 540_R and the second touch electrode can change. The touch control circuit can detect this change in capacitance to calculate a touch coordinate.

[0191] The manufacturing process of the bank trench BT and the second spacer 340 will be illustrated below.

[0192] In Fig. 4A is the first electrode 310 in the emitting region EA formed on the substrate 110, which has the thin-film transistor 200.

[0193] In Fig. 4B are the bank 320 and the first spacer 330 formed in the non-emitting area NEA of the substrate 110, which has the first electrode 310.

[0194] Bank 320 can have bank hole BH, which exposes the first electrode 310 in the emitting area EA. Bank hole BH can be formed by removing a section of bank 320.

[0195] At least one first spacer 330 can be arranged on the bank 320.

[0196] Although in Fig. 4B where bank 320 and first spacer 330 are formed by the same process using a raster mask, bank 320 and first spacer 330 can be formed by different processes in another embodiment.

[0197] In Fig. 4C is the bank trench BT formed between the adjacent subpixels. The bank trench BT can be formed by etching a section of bank 320. The planarization layer 160 can be exposed through the bank trench BT.

[0198] Although in Fig. 4C If an entire section of the bank 320 is removed in a region where the bank trench BT is located, a section of the bank 320 can be removed in another embodiment. For example, a section of the bank 320 can remain on the planarization layer 160 in the region where the bank trench BT is located by removing a section of the bank 320 instead of an entire section of the bank 320, i.e., by removing only a portion of the thickness of the bank 320.

[0199] In Fig. 4D, the second spacer 340 can be formed in the bank trench BT.

[0200] The second spacer 340 can have the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c can be arranged so that they are spaced apart from each other. The spacer pattern hole PH can be arranged between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c.

[0201] At least one of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340 can cover a section of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 can be arranged to each cover associated sections of the bank 320. The second spacer pattern 340b of the second spacer 340 can be arranged to be at a distance from the bank 320.

[0202] Although in Fig. 4A to 4D the bench hole BH, the bench trench BT, the first spacer 330 and the second spacer 340 are formed by different processes, in another embodiment the bench hole BH and the bench trench BT can be formed simultaneously and then the first spacer 330 and the second spacer 340 can be formed simultaneously.

[0203] Fig. Figure 5 is a view showing an emitting layer of a light-emitting diode indicator device according to an embodiment of the present disclosure.

[0204] Although the emitting layer in Fig. 5 comprising two stacks (emitting units) and one charge generation layer, in another embodiment the emitting layer may comprise three or more stacks and two or more charge generation layers.

[0205] In Fig. 5. The emitting layer 350 can have multiple stacks (emitting units). For example, the emitting layer 350 can have a first stack 351, a second stack 353, and a charge-generating layer 352 between the first stack 351 and the second stack 353.

[0206] The first electrode (such as the anode) 310, the first stack 351, the charge generation layer 352, the second stack 353 and the second electrode (such as the cathode) 360 can be arranged sequentially on the substrate 110, which has the first subpixel SP_1, the second subpixel SP_12 and the third subpixel SP_3.

[0207] The first stack 351 can include a hole injection layer 351-A, a first hole transport layer 351-B, a first emitting material layer 351-C and a first electron transport layer 351-D.

[0208] The second stack 353 can include a second hole transport layer 353-A, a second emitting material layer 353-B, a second electron transport layer 353-C and an electron injection layer 353-D.

[0209] The charge generation layer 352 can have a negative (N)-type charge generation layer n-CGL (352-n), which supports the injection of an electron towards the first stack 351, and a positive (P)-type charge generation layer p-CGL (352-p), which supports the injection of a hole towards the second stack 353.

[0210] Although not shown, an electron barrier layer can be arranged between the first hole injection layer 351-A and the first emitting material layer 351-C, and a hole barrier layer can be arranged between the first emitting material layer 351-C and the charge generation layer 352. Furthermore, an electron barrier layer can be arranged between the charge generation layer 352 and the second emitting material layer 353-B, and a hole barrier layer can be arranged between the second emitting material layer 353-B and the electron injection layer 353-D.

[0211] A section of the emitting layer 350 can be interrupted between adjacent subpixels by means of the bank trench BT, which has the second spacer 340 below the emitting layer 350. In other words, the emitting layer 350 can have one or more cuts, gaps, or interruptions between adjacent subpixels SP_1, SP_2, and SP_3. As a result, electron movement within the emitting layer 350 towards the adjacent subpixel is prevented. In particular, detection degradation between adjacent subpixels at relatively low grayscale levels is reduced, and color reproducibility is improved.

[0212] The first emitting material layer 351-C and the second emitting material layer 353-B can be arranged to correspond to each subpixel and be spaced apart from each other. Or the first emitting material layer 351-C and the second emitting material layer 353-B can be arranged to overlap the bank hole BH and an end section of bank 320.

[0213] The 351-A hole injection layer can facilitate the injection of a hole. The 351-A hole injection layer can contain at least one of HATCN (1,4,5,8,9,11-hexaazatriphenylenehexanitrile), CuPc (copper phthalocyanine), PEDOT (poly(3,4)-ethylenedioxythiophene), PANI (polyaniline), and NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), and there is no restriction in this regard.

[0214] The first hole transport layer 351-B and the second hole transport layer 353-A can support hole transport. The first hole transport layer 351-B and the second hole transport layer 353-A can contain at least one of NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-di(phenyl)benzidine), s-TAD, and MTDATA (4,4',4"-tris(N-3-methylphenyl-N-phenylamino)triphenylamine), and there is no restriction in this regard.

[0215] The first electron transport layer 351-D and the second electron transport layer 353-C can support the transport of one electron. The first electron transport layer 351-D and the second electron transport layer 353-C can contain at least one of Alq3 (tris(8-hydroxyquinoline)aluminium), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), TAZ, spiro-PBD, BAlq, and SAlq, and there is no restriction in this regard.

[0216] The electron injection layer 353-D supports the injection of an electron. The electron injection layer 353-D can contain at least one of Alq3 (tris(8-hydroxyquinoline)aluminium), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), TAZ, spiro-PBD, BAlq, and SAlq, and there is no restriction in this respect.

[0217] The first emitting material layer 351-C and the second emitting material layer 353-B can be arranged in the bank hole BH such that they are spaced apart between adjacent subpixels. For example, the first emitting material layer 351-C and the second emitting material layer 353-B can be arranged in each subpixel using a precious metal mask (FMM).

[0218] The first emitting material layer 351-C and the second emitting material layer 353-B can overlap and can emit light corresponding to the same color. The first emitting material layer 351-C and the second emitting material layer 353-B can emit light of the same wavelength, and there is no restriction in this regard.

[0219] The first emitting material layer 351-C and the second emitting material layer 353-B can have emitting materials which emit red light, green light and blue light, and the emitting materials can be formed using a phosphorescent material or a fluorescent material.

[0220] For example, a first red-emitting material layer 351R and a second red-emitting material layer 353R in the first subpixel SP_1 can be formed from a phosphorescent material having a host material of CBP (carbazole-biphenyl) or mCP (1,3-bis(carbazol-9-yl)) and a dopant material of one of PIQIr(acac) (bis(1-phenyl-isoquinoline)acetylacetonate iridium), PQlr(acac) (bis(1-phenyl-quinoline)acetylacetonate iridium), PQIr (tris(1-phenyl-quinoline) iridium) and PtOEP (octaethylporphyrin platinum), or they can be formed from a fluorescent material having PBD:Eu(DBM)3(phen) or perylene. However There is no such restriction.

[0221] For example, a first green-emitting material layer 351G and a second green-emitting material layer 353G in the second subpixel SP_2 can be formed from a phosphorescent material having a host material of CBP or mCP and a dopant material of an Ir complex containing Ir(ppy)3(fac tris(2-phenylpyridine)iridium), or they can be formed from a fluorescent material containing Alq3 (tris(8-hydroxyquinoline)aluminum). However, there is no restriction in this regard.

[0222] For example, a first blue-emitting material layer 351B and a second blue-emitting material layer 353B in the third subpixel SP_3 can be formed from a phosphorescent material having a host material of CBP or mCP and a dopant of (4,6-F2ppy)2Irpic, or they can be formed from a fluorescent material having one of Spiro-DPVBi, Spiro-6P, distyrylbenzene (DSB), distyrylaryl (DSA), PFO polymer, and PPV polymer. However, there is no restriction in this regard.

[0223] The first emitting material layer 351-C and the second emitting material layer 353-B may each have an additional emitting material layer. For example, the additional emitting material layer may be located above or below the first emitting material layer 351-C and the second emitting material layer 353-B. The additional emitting material layer may emit light of the same color as, or a different color than, the first emitting material layer 351-C and the second emitting material layer 353-B.

[0224] The N-type charge-generating layer n-CGL (352-n) can be formed from an alkali metal, an alkali metal compound, an electron-injecting organic material, or an alloy thereof. For example, the N-type charge-generating layer n-CGL (352-n) can be a mixed layer of N-type materials, such as an anthracene derivative doped with lithium (Li) or cesium (Cs), and there is no restriction in this regard.

[0225] The p-type charge-generating layer p-CGL (352-p) can be formed from an organic material used for a hole injection layer. For example, the p-type charge-generating layer p-CGL (352-p) can have a single layer of p-type materials, such as HATCN or F4-TCNQ, and there is no restriction in this regard.

[0226] Each layer of the first stack 351, the second stack 353 and the charge generation layer 352 can have multiple layers or can be omitted.

[0227] Consequently, in the LED display device according to an embodiment of the present disclosure, because the bank trench, which has at least one second spacer, is arranged between the adjacent subpixels, the lateral leakage current, which increases when the spacing between the adjacent subpixels decreases, is reduced or prevented.

[0228] Because the emitting layer is interrupted by means of the trench, which in some exemplary embodiments has at least one second spacer between the adjacent subpixels, electrons are prevented from moving in the emitting layer towards the adjacent subpixel.

[0229] Because the lateral leakage current between neighboring subpixels is reduced or prevented, the detection degradation between neighboring subpixels is reduced at a relatively low gray level, i.e., for a relatively low brightness, and color reproducibility is improved.

[0230] Exemplary embodiments of the present disclosure can also be described as follows:

[0231] According to an exemplary embodiment of the present disclosure, a display device may comprise: a substrate having: a first subpixel and a second subpixel, each having an associated emitting region; and a non-emitting region surrounding the emitting regions; a first electrode in each of the first subpixel and the second subpixel; a bank, the bank having an associated bank hole in the emitting region and a bank trench in the non-emitting region; a first spacer on the bank; a second spacer in the bank trench; an emitting layer on the first electrodes and the bank trench, comprising multiple stacks and at least one charge-generating layer between the multiple stacks; and a second electrode on the emitting layer.

[0232] In some exemplary embodiments, the second spacer can have a reverse-tapered shape.

[0233] In some exemplary embodiments, the height of a top surface of the second spacer from the substrate may differ from the height of a top surface of the first spacer from the substrate.

[0234] In some exemplary embodiments, the height of the top of the second spacer from the substrate may be less than the height of the top of the first spacer from the substrate.

[0235] In some exemplary embodiments, the thickness of the second spacer can be greater than the thickness of the bench.

[0236] In some exemplary embodiments, the second spacer may have at least one first spacer pattern and a second spacer pattern with a spacer pattern hole in between.

[0237] In some exemplary embodiments, the second spacer may have at least a first spacer pattern, a second spacer pattern and a third spacer pattern with a first spacer pattern hole between the first spacer pattern and the second spacer pattern and a second spacer pattern hole between the second spacer pattern and the third spacer pattern.

[0238] In some exemplary embodiments, at least one of the first spacer pattern, the second spacer pattern and the third spacer pattern covers a section of the bank.

[0239] In some exemplary embodiments, the display device may further comprise: a thin-film transistor on the substrate; and a planarization layer on the thin-film transistor.

[0240] In some exemplary embodiments, the bank trench can expose the planarization layer.

[0241] In some exemplary embodiments, the second spacer can be arranged on the planarization layer.

[0242] In some exemplary embodiments, the emitting layer can be arranged on the planarization layer.

[0243] In some exemplary embodiments, the emitting layer may have a cut in the non-emitting area, which is formed by means of the second spacer.

[0244] In some exemplary embodiments, the at least one charge-generating layer can comprise a first charge-generating layer and a second charge-generating layer.

[0245] In some exemplary embodiments, each of the multiple stacks can have an emitting material layer.

[0246] In some exemplary embodiments, the display device may further comprise: an encapsulation layer on the second electrode; and a touch detection layer on the encapsulation layer.

[0247] In some exemplary embodiments, the touch detection layer may have a first touch electrode and a second touch electrode which overlap the second spacer.

[0248] In some exemplary embodiments, the height of the second spacer can be less than the height of the first spacer.

[0249] According to another exemplary embodiment of the present disclosure, a display device may comprise: a substrate comprising: a display area having multiple subpixels and a non-emitting area between the multiple subpixels; and a non-display area adjacent to the display area; a respective first electrode in each of the multiple subpixels; a bank dividing the multiple subpixels; an emitting layer on the first electrodes; a second electrode on the emitting layer; and a cut in the emitting layer of / between two adjacent subpixels of the multiple subpixels.

[0250] In some exemplary embodiments, the bank can have several bank holes, each corresponding to the several subpixels, and a bank trench, which corresponds to the non-emitting area.

[0251] In some exemplary embodiments, the display device may further include a first spacer on the bench.

[0252] In some exemplary embodiments, the cut can be formed by means of a second spacer in the bank trench.

[0253] In some exemplary embodiments, the second spacer can be made of the same material as the bench.

[0254] In some exemplary embodiments, the height of the second spacer can be less than the height of the first spacer.

[0255] According to yet another exemplary embodiment of the present disclosure, a method for manufacturing a display device may comprise: forming several first electrodes spaced apart from one another on a substrate; forming a bank on the substrate on which the several first electrodes are formed; forming a bank hole in the bank such that a section of each of the several first electrodes is exposed, and forming a bank trench between adjacent first electrodes of the several first electrodes in the bank; forming a second spacer in the bank trench; forming an emission layer on the second spacer and the bank trench, wherein the emission layer has several stacks and at least one charge-generating layer between the several stacks; and forming a second electrode on the emission layer.

[0256] In some exemplary embodiments, the method may further include the formation of a first spacer on the bench simultaneously with the formation of the second spacer.

[0257] Although the section described herein is mainly with reference to an exemplary embodiment in which the section has a second spacer in the bank trench, the section may have a different shape according to actual needs.

[0258] It will be apparent to those skilled in the art that numerous modifications and variations can be made to the present disclosure without altering its scope. Therefore, it is intended that the present disclosure encompasses such modifications and variations as fall within the scope of the attached claims.

Claims

[1] Display device (100), comprising: a substrate (110) which has: a first subpixel (SP_1) and a second subpixel (SP_2), each having an associated emitting region (EA); and a non-emitting region (NEA) which surrounds the emitting regions (EA); a respective first electrode (310) in each of the first subpixel (SP_1) and the second subpixel (SP_2); a bank (320), wherein the bank (320) has a respective bank hole (BH) in each of the emitting areas (EA) and a bank trench (BT) in the non-emitting area (NEA); a first spacer (330) on the bench (320); a second spacer (340) inside the bank trench (BT); an emitting layer (350) on the first electrodes (310) and the bank trench (BT), which has several stacks (351, 353) and at least one charge-generating layer (352) between the several stacks (351, 353); and a second electrode (360) on the emitting layer (350), and wherein the second spacer (340) has at least one first spacer pattern (340a) and a second spacer pattern (340b) with a spacer pattern hole (PH) in between. [2] Display device (100) according to claim 1, wherein the second spacer (340) has a reverse tapered shape. [3] Display device (100) according to claim 1 or claim 2, wherein the height of a top surface of the second spacer (340) from the substrate (110) differs from the height of a top surface of the first spacer (330) from the substrate (110). [4] Display device (100) according to any one of claims 1 to 3, wherein the height of a top surface of the second spacer (340) from the substrate (110) is less than the height of a top surface of the first spacer (330) from the substrate (110). [5] Display device (100) according to any one of the preceding claims, wherein the thickness of the second spacer (340) is greater than the thickness of the bank (320). [6] Display device (100) according to any one of claims 1 to 5, wherein the second spacer (340) further comprises: at least a third spacer pattern (340c) with a second spacer pattern hole (PH) between the second spacer pattern (340b) and the third spacer pattern (340c). [7] Display device (100) according to claim 6, wherein at least one of the first spacer pattern (340a), the second spacer pattern (340b) and the third spacer pattern (340b) covers a section of the bank (320). [8] Display device (100) according to any one of the preceding claims, further comprising: a thin-film transistor (200) on the substrate (110); and a planarization layer (160) on the thin-film transistor (200). [9] Display device (100) according to claim 8, wherein the bank trench (BT) exposes the planarization layer (160). [10] Display device (100) according to claim 8 or 9, wherein the second spacer (340) is arranged on the planarization layer (160). [11] Display device (100) according to any one of claims 8 to 10, wherein the emitting layer (350) is arranged on the planarization layer (160). [12] Display device (100) according to any one of the preceding claims, wherein the emitting layer (350) has a cut in the non-emitting area (NEA) formed by means of the second spacer (340). [13] Display device (100) according to any one of the preceding claims, wherein the at least one charge generation layer (352) comprises a first charge generation layer (352-n) and a second charge generation layer (352-p). [14] Display device (100) according to any one of the preceding claims, wherein each of the multiple stacks (351, 353) has an emitting material layer (351-C, 353-B). [15] Display device (100) according to any one of the preceding claims, further comprising: an encapsulation layer (400) on the second electrode (360); and a touch detection layer (500) on the encapsulation layer (400). [16] Display device (100) according to claim 15, wherein the touch detection layer (500) has a first touch electrode (540_R) and a second touch electrode which overlap the second spacer (340). [17] Display device (100) according to any one of the preceding claims, wherein the height of the second spacer (340) is less than the height of the first spacer (330). [18] Display device (100), comprising: a substrate (110) comprising: a display area (AA) which has several subpixels (SP_1, SP_2, SP_3) and a non-emitting area (NEA) between the several subpixels (SP_1, SP_2, SP_3); and a non-display area (NA) which is adjacent to the display area (AA); a respective first electrode (310) in each of the multiple subpixels (SP_1, SP_2, SP_3); a bank (320) which divides the several subpixels (SP_1, SP_2, SP_3); an emitting layer (350) on the first electrodes (310); a second electrode (360) on the emitting layer (350); and a section in the emitting layer (350) between two adjacent subpixels of the multiple subpixels (SP_1, SP_2, SP_3), where the bank (320) has a bank trench (BT) which corresponds to the non-emitting area (NEA), wherein the cut is formed by means of a second spacer (340) in the bank trench (BT), and wherein the second spacer (340) has at least one first spacer pattern (340a) and a second spacer pattern (340b) with a spacer pattern hole (PH) in between. [19] Display device (100) according to claim 18, wherein the bank (320) has: several bank holes (BH) which correspond in an assigned manner to the several subpixels (SP_1, SP_2, SP_3). [20] Display device (100) according to claim 18 or 19, which further comprises a first spacer (330) on the bench (320). [21] Display device (100) according to claim 18, wherein the second spacer (340) is made of the same material as the bench (320). [22] Display device (100) according to claim 21, wherein the height of the second spacer (340) is less than the height of the first spacer (330).

Images