PACKAGING ARCHITECTURE WITH COMPENSATION LAYERS FOR "KNOWN GOOD DIE"-TO-"KNOWN GOOD DIE" HYBRID BONDENS ON WAFER SCALE

Abstract

Microelectronic arrangements, associated components and methods are disclosed herein.In some embodiments, a microelectronic arrangement may comprise a first layer with a first die having a first contact; a second die with a second contact; and a terminal layer on the first and second dies having a first terminal and a second terminal, wherein the first terminal is coupled to the first contact and offset from it in a first direction, and the second terminal is coupled to the second contact and offset from it in a second direction different from the first; and a second layer comprising a third die with third and fourth contacts, wherein the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first terminal, and the second contact is coupled to the fourth contact by the second terminal.

Description

TECHNICAL FIELDThe present disclosure relates to techniques, methods, and apparatuses related to packaging architecture for known good die (KGD) to wafer-scale KGD hybrid bonding.BACKGROUNDElectronic circuits, when typically fabricated on a wafer of semiconductor material such as silicon, are referred to as integrated circuits (ICs). The wafer with such ICs is usually cut into numerous individual dies. The dies may be packaged into an IC package that includes one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package can be integrated onto an electronic system, e.g. a consumer electronics system, or server, e.g. mainframe computer.BRIEF DESCRIPTION OF THE DRAWINGSEmbodiments will be readily apparent from the following detailed description taken in conjunction with the accompanying drawings. To simplify this description, like reference numerals designate similar structural elements. Exemplary embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. FIG. 1 is a circuit diagram of top views of two layers of dies for bonding together and a stacked view according to some embodiments of the present disclosure. FIG. 2 is a circuit diagram of top views of two layers of dies and a compensation layer for bonding together, and a stacked view according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. FIG. 4A is a circuit diagram of stacked views of two dies and two compensation layers for bonding together, in accordance with some embodiments of the present disclosure. FIG. 4B is a circuit diagram of other stacked views of two dies and two compensation layers for bonding together, in accordance with some embodiments of the present disclosure. FIG. 5 is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. FIGS. 6A and 6B are schematic cross-sectional views of further example microelectronic assemblies in accordance with some embodiments of the present disclosure. FIGS. 7A and 7B are schematic cross-sectional views of further example microelectronic assemblies in accordance with some embodiments of the present disclosure. FIGS. 8A-8E are schematic cross-sectional views of various stages of manufacture of an example microelectronic assembly, in accordance with some embodiments of the present disclosure. FIG. 9 is a schematic flow diagram depicting example operations associated with fabricating a microelectronic assembly, in accordance with various embodiments of the present disclosure. FIG. 10 is a top view of a wafer and dies that may be included in a microelectronic assembly, according to any of the embodiments disclosed herein. FIG. 11 is a cross-sectional side view of an IC device that may be included in a microelectronic assembly, in accordance with any of the embodiments disclosed herein. FIG. 12 is a cross-sectional view of an IC device package that may include one or more microelectronic assemblies, according to any of the embodiments disclosed herein. FIG. 13 is a cross-sectional side view of an IC device assembly that may include a microelectronic assembly, in accordance with any of the embodiments disclosed herein. FIG. 14 is a block diagram of an example electrical device that may include a microelectronic assembly, in accordance with any of the embodiments disclosed herein.DETAILED DESCRIPTIONOverviewTo illustrate the IC packages described herein, it is important to understand the phenomena that may occur in the placement and packaging of ICs. The following basic information can be regarded as a basis on which the present disclosure can be properly explained. Such information is offered for purposes of explanation only and, accordingly, is not to be construed as limiting the broad scope of the present disclosure and its possible applications.Advances in semiconductor processing and logic design have enabled an increase in the amount of logic circuitry that may be included in processors and other IC devices. As a result, many processors now have multiple cores monolithically integrated on a single die. Generally, these types of monolithic ICs are also referred to as planar because they have the shape of a flat surface and are typically manufactured on a single silicon wafer from a monocrystalline silicon ingot (boule). The typical manufacturing process for such monolithic ICs is referred to as a planar process that allows photolithography, etching, heat diffusion, oxidation, and other such processes to take place on the surface of the wafer such that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer.Present day technologies allow hundreds and thousands of such active circuit elements to be formed on a single die, thus enabling numerous logic circuits thereon. In such monolithic dies, the fabrication process must be optimized for all the circuits equally, resulting in trade-offs between different circuits. Due to the limitation that the circuits are to be placed on a planar surface, some circuits are more distant than others, resulting in reduced performance such as longer delays. Manufacturing yield can also be severely compromised, as the entire die may need to be discarded, even if only one circuit is not functioning.One solution to overcome such negative effects of monolithic dies is to split the circuits into smaller dies (e.g., chiplets, tiles) that are electrically coupled by connecting bridges. The smaller dies are part of an array of connected dies that together form a complete IC with respect to application and / or functionality, e.g., a memory chip, microprocessor, microcontroller, standard IC (e.g., repetitive processing routine chip, simple tasks, application specific IC, etc.), and system-on-chip (SOC). In other words, the individual dies are interconnected to provide the functionalities of a monolithic IC. By using separate dies, each individual die can be optimally designed and manufactured for a particular functionality. A processor core comprising logic circuits could be performance-oriented, for example, and thus may require a very speed optimized layout. This presents other manufacturing requirements compared to a USB controller that is built to meet certain USB standards rather than for processing speed. Thus, by separating different portions of the overall design into different dies, each optimized for design and fabrication, the overall yield and cost of the combined die solution may be improved.Connectivity between these dies is achievable in many different ways. For example, in 2.5D packaging solutions, a silicon interposer and through-silicon vias (TSVs) connect the dies to silicon connection speed with minimum footprint. In another example, a silicon bridge embedded under the edges of two connected dies facilitates electrical coupling between them. In a three-dimensional (3D) architecture, the dies are stacked one above the other, which results in a smaller overall footprint. Typically, electrical connectivity and mechanical coupling is achieved in such a 3D architecture using TSVs and high pitch solder-based bumps (e.g., C2 connections). The silicon bridge and the 3D stack architecture may also be combined, allowing the top packaged chips to communicate with other chips horizontally using the silicon bridge and vertically using through-mold vias (TMVs) that are typically larger than TSVs. Another packaging architecture uses hybrid bonding processes to fabricate high density interconnects between die stacks in a true 3D configuration. Hybrid bonding technology allows for much smaller bond distances of less than 100 nanometers, thereby achieving bond densities of greater than 10 M.IOs / millimeter2 2.Wafer-level processing cannot be performed because a single wafer may include more than one non-functional die; attaching such non-functional dies to a good die wastes resources and reduces overall manufacturing yield. The wafer-to-wafer hybrid bonding process may provide good bonding yields, but generally does not allow for testing multiple KGDs on a base die or a single die. The die-to-wafer hybrid bonding process is susceptible to defects due to foreign materials introduced onto the bonding surface during dicing, chemical mechanical polishing, grinding, thinning, etc. Collectively bonding singulated dies on a wafer may allow for fast hybrid bonding, but is sensitive to defects caused by die singulation, thinning, and die thickness variations. The cleaning of the dies after dicing may mitigate some of the defects of die-to-wafer bonding, but although theoretically suitable, it is difficult in practice to achieve full cleaning without damaging the bonding surfaces.One solution for hybrid wafer-to-wafer hybrid bonding is to reconstitute KGDs on a substrate using die bonder to form a known good wafer ("KGW") and then bond one KGW to another KGW. However, the die bonder has limited die placement capabilities, which typically results in misalignment errors (misalignment errors) and bond defects between KGDs of the KGWs. Further, wafer-to-wafer hybrid bonding requires that the two bonding surfaces have bond contacts that are mirror images (e.g., have conductive bonds on each surface that mate to form a bond, where the two bonding surfaces need not be uniform, but should be imaged such that the conductive bonds on each surface are aligned with each other for bonding). Any change in bond pad alignment may result in poor contact or no contact at all of the interconnects, which may cause failure of an IC package or electronic assembly. Bond pad alignment is a great challenge because it affects the ability to bond KGDs to KGDs in the package assembly. Incomplete interconnects result in device yield losses, which increases costs, particularly in heterogeneous packages, as multiple dies are discarded even if only a single die fails. As such, bond pad alignment is a major problem for package designs, particularly for wafer-to-wafer processes using reconstituted KGDs. Various of the embodiments disclosed herein may help achieve improved bond pad alignment with smaller bond spacings relative to conventional approaches. Disclosed herein are devices and a method in which, after the KGWs are created, compensation layers are added to a top surface of the KGWs, for example using adaptive patterning techniques that measure and calculate individual KGD placement errors to pattern the compensation layers, and then form hybrid bond layers on a top surface of the compensation layers. A compensation layer may correct the individual KGD placement errors such that after formation of the hybrid bond layers, the hybrid bond layers for both KGWs may be symmetric for optimal bond overlay and may further provide a continuous electrical path through the compensation layers.Accordingly, microelectronic assemblies, associated components, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer comprising a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact in a second direction different from the first direction; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds, the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the metal-to-metal bonds, and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the metal-to-metal bonds.Each of the structures, assemblies, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which is solely responsible for the entirety of the desirable attributes disclosed herein.Details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art.The term "circuit" and "circuitry" means one or more passive and / or active electrical and / or electronic components arranged to cooperate with one another to provide a desired function. The terms also refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical electrical and / or electronic hardware component.The term "integrated circuit" refers to a circuit integrated into a monolithic semiconductor or an analog material.In some embodiments, the IC dies disclosed herein may comprise substantially monocrystalline semiconductors such as silicon or germanium as a base material (e.g., substrate, body) on which integrated circuits are fabricated using conventional semiconductor processing techniques. The semiconductor base material may include, for example, N-type or P-type materials. The dies may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a semiconductor-on-insulator (SOI) structure. In some other embodiments, the base material may include one or more materials that alternate from the IC dies, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, Indiumgalliumarsenid gallium antimonide, or other combinations of Group III-N, Group III-V, Group II-VI, or Group IV materials. In yet other embodiments, the base material may comprise, for example, compound semiconductors having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g., P, As, Sb). In still other embodiments, the base material may comprise an intrinsic IV or III-V semiconductor material or an alloy that is / is not intentionally doped with any electrically active impurity; in alternative embodiments, nominal impurity dopant levels may be present. In still other embodiments, the dies may comprise a non-crystalline material, such as polymers; thus, the base material may comprise, e.g., silicon oxide filled epoxy. In other embodiments, the base material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the base material may comprise one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, Indiumgalliumarsenid silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each possibly with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, The material may be doped with tantalum, tungsten and magnesium, etc. Although some examples of the material for the dies are described herein, any material(s) or structure that can serve as a base (e.g., base material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of the present disclosure.Unless otherwise described, the IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured for execution) certain functionality. In such an example, the term "memory die" may be used to describe a die comprising one or more ICs implementing memory circuitry (e.g., ICs implementing one or more of memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In another such example, the term "compute die" may be used to describe a die comprising one or more ICs implementing logic / compute circuitry (e.g., ICs implementing one or more I / O functions, arithmetic operations, data pipelining, etc.).In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die.". It should be noted that the terms "chip", "die", and "IC die" are used interchangeably herein.The term "insulating" means "electrically insulating", the term "conductive" means "electrically conductive", unless otherwise stated. With respect to optical signals and / or components, components, and elements operating on or using optical / n signal(s), the term "conductive" may also mean "optically conductive.".The terms "oxide", "carbide", "nitride", etc. refer to compounds each containing oxygen, carbon, nitrogen, etc.Further, the term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to solid bodies (and / or liquid materials that solidify after processing described herein) that are substantially electrically non-conductive. They may include, by way of example and not limitation, organic polymers and plastics, epoxy mold compound (EMC), as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride and aluminum oxide, or a combination thereof. They may comprise dielectric materials, high polarizability materials and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and shapes or shape-like materials used in packaging applications, including, for example, materials used in organic interposers, package carriers, and other such components.In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those monolithically integrated within an IC mounted on an IC or those connected to an IC. The ICs described herein may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein may be deployed in a single IC die or as part of a chipset for performing one or more related functions in a computer.In various embodiments of the present disclosure, the transistors described herein may be field effect transistors (FETs), e.g., MOSFETs. Generally, an FET is a three terminal device that includes source, drain, and gate terminals and uses an electric field to control the current flowing through the device. An FET typically includes a channel material, a source region and a drain region provided in and / or over the channel material, and a gate stack including a gate electrode material, alternatively referred to as a "work function" material, provided over a portion of the channel material (the "channel portion") between the source and drain regions, and optionally also a gate dielectric material between the gate electrode material and the channel material.In the general sense, a "connection" refers to any element that provides a physical connection between two other elements. An electrical connection establishes electrical connectivity between two electrical components, for example, thus facilitating communication of electrical signals between them; an optical connection establishes optical connectivity between two optical components, thus facilitating communication of optical signals between them. As used herein, both electrical connections and optical connections are included in the term "connection.". The type of connection described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with respect to an electronic device, e.g., an IC operating using electrical signals, the term "connection" describes any element formed from an electrically conductive material to provide electrical connectivity to one or more elements associated with the IC or / and between various such elements. In such cases, the term "connection" may refer to both conductive traces (sometimes also referred to as "lines", "wires", "metal lines", or "trenches") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, electrically conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Similarly, "interconnect", when used with respect to a device that also operates on optical signals, such as a photonic IC (PIC), may describe any element formed of an optically conductive material to provide optical connectivity to one or more elements associated with the PCI. In such cases, the term "connection" may refer to optical waveguides including optical fiber, optical distributors, optical combiners, optical couplers, and optical vias.The term "waveguide" refers to any structure that serves to direct the propagation of light from one location to one, usually through a substrate material such as silicon or glass. In various examples, waveguides may be formed from silicon, doped silicon, silicon nitride, glasses such as silicon dioxide (e.g., silicon dioxide or SiO 2), borosilicate (e.g., 70-80 wt % SiO 2, 7-13 wt % B 2 O 3, 4-8 wt % Na 2 O, or K 2 O, and 2-8 wt % Al 2 O 3) and so forth. Waveguides may be formed using various techniques including, but not limited to, the formation of waveguides in situ. In some embodiments, waveguides may be formed, for example, in situin glass using low temperature glass-to-glass bonding or by direct laser writing. Waveguides formed in situ may have lower loss characteristics.The term "conductive trace" may be used to describe an electrically conductive element that is insulated by an insulating material. Within IC dies, such an insulating material includes an interlayer low-k dielectric provided within the IC die. Within package substrates and printed circuit boards (PCBs), this insulating material comprises organic materials such as Ajinomoto Buildup Film (ABF), polyimides, or epoxy resin. Such conductor tracks are generally arranged in a plurality of planes, or a plurality of layers, of a metallization stack.The term "conductive via" may be used to describe an electrically conductive element connecting two or more conductive traces of different levels of a metallization stack. To this end, a via may be provided substantially perpendicular to the plane of an IC die / chip or support structure over which an IC structure is provided and may connect two conductive traces in adjacent planes or two conductive traces in non-adjacent planes.The term "package substrate" may be used to describe any substrate material that facilitates the packaging together of any collection of semiconductor dies and / or other electrical components, such as passive electrical components. After use herein, a package substrate may be formed of any material including, but not limited to, insulating materials such as resin impregnated glass fibers (e.g., PCB or printed wiring boards (PWB), glass, ceramic, silicon, silicon carbide, etc. Additionally, after use herein, a package substrate may refer to a substrate including build-up layers (e.g., ABF layers).The term "metallization stack" may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC die / chip and / or a package substrate.As used herein, the term "pitch" (pitch) of links refers to a center-to-center distance between adjacent links.It is understood that one or more levels of underfill (e.g., organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in an IC package 100 described herein and may not be labeled to not overcharge the drawings. In various embodiments, the levels of the underfill may comprise the same or different insulating materials. In some embodiments, the levels of the underfill may comprise thermosetting epoxies with silica particles or an EMC; in some embodiments, the levels of the underfill may comprise any suitable material that can perform underfill functions, such as supporting the dies and reducing thermal stress on interconnects. In some embodiments, the choice of underfill material may be based on design considerations, such as shape factor, size, load, operating conditions, etc.; in other embodiments, the choice of underfill material may be based on material properties and processing conditions, such as cure temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the choice of underfill material may be based on both design and processing considerations.In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymers, dry film photoimageable polymers, acrylates, solvents) may be provided in an IC package described herein, which may not be marked or shown so as not to overcharge the drawings. The solder resist may be a liquid or dry film material comprising photostructurable polymers. In some embodiments, the solder resist may be non-photoimageable.The terms "substantially," "near," "about," "near," and "about" generally refer to within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of a particular value as described herein or as is known in the art.Terms indicating an orientation of various elements, e.g., "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between the elements, generally refer to within + / - 5% of a target value based on the context of a particular value as described herein or known in the art.The term "connected" means a direct connection (which may be one or more of a mechanical, electrical and / or thermal connection) between the things that are connected without any intermediary devices, while the term "coupled" means either a direct connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices.The description uses the phrases "in one embodiment" or "in embodiments" which may each refer to one or more of the same or different embodiments.Further, the terms "comprise", "comprise", "have" and the like as used herein with respect to embodiments of the present disclosure are synonymous.The description may use perspective-based descriptions, such as "over," "under," "above," "below," and "page," such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.The terms "over," "under," "between," and "on" as used herein refer to a relative position of one layer of material or component with respect to other layers or components. For example, a layer disposed above or below another layer may be directly in contact with the other layer or may have one or more intervening layers. In addition, a layer disposed between two layers may be directly in contact with one or both of the two layers, or may have one or more intermediate layers. In contrast, a first layer described as "on" a second layer refers to a layer that is in direct contact with that second layer. Similarly, unless otherwise expressly stated, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.As used herein, the term "place" (dispose) refers to position, location, placement, and / or placement rather than any particular method of formation.The term "between" when used with respect to measurement ranges includes the ends of the measurement ranges.For purposes of the present disclosure, the term "A and / or B" denotes (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). As used herein, the notation "A / B / C" MEANS (A), (B), and / or (C).Although certain elements may be referred to herein in the singular, such elements may include multiple sub-elements. For example, "an electrically conductive material" may include one or more electrically conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.Unless otherwise indicated, the use of ordinal adjective "first / r / s', "second / r / s", and "third / r / s" in describing a common subject matter only indicates that different instances of similar objects are being described, and it is not intended to imply that the objects so described must be in a given order, either temporarily, spatially, in ranking, or in any other manner.In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.The accompanying drawings are not necessarily drawn to scale.In the drawings, like reference numerals refer to the same or analogous elements / materials shown, such that unless otherwise indicated, explanations of an element / material having a particular reference numeral provided in connection with any of the drawings are also applicable to other drawings in which elements / materials may be represented having the same reference numerals. Further, the singular and plural forms of the terms may be used with reference numerals to refer to single and multiple ones of the same or similar type, type, or class of element, respectively.Further, in the drawings, some schematic representations of example structures of various devices and arrangements described herein may be shown with precise right angles and straight lines, but it is understood that such schematic representations may not reflect real process limitations, which may result in the features not looking as "ideal" when one of the structures described herein is examined using, for example, images of suitable characterization tools such as scanning electron microscopy (SEM) images, transmission electron microscope (TEM) images, or contactless profiler. In such images of real structures, possible processing and / or surface defects could also be visible, e.g., surface roughness, curvature or profile deviation, depression or scratches, imperfect straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in the thicknesses of different material layers, occasional screw, edge or combination dislocations within the crystalline region(s), and / or occasional dislocation defects of individual atoms or atomic clusters. There may be other defects not listed here, which however often occur within the device manufacturing and / or packaging region.It should be noted that in the figures, various components (e.g., connections) are shown as aligned (e.g., at the respective interfaces) merely for simplicity of illustration; indeed, some or all of them may be misaligned. Moreover, other components, such as bond pads, landing pads, metallization, etc., may be present in the arrangement, not shown in the figures, to avoid clarity. Further, the figures are intended to show relative arrangements (arrangements) of the components within their arrangements (assemblies), and generally such arrangements may include other components not depicted (e.g., various interface layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation). In some further embodiments, the arrangement as shown in the figures may comprise, for example, multiple dies together with other electrical components. Additionally, although some components of the assemblies are depicted in the figures as planar rectangles or as formed from rectangular solids, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as dictated by the fabrication processes used to fabricate various components, and sometimes unavoidable.In the drawings, a particular number and arrangement of structures and components is shown for purposes of illustration, and any desired number or arrangement of such structures and components may be present in various embodiments.Further, unless otherwise indicated, the structures shown in the figures may take any suitable shape or shape according to material characteristics, manufacturing processes, and operating conditions.For convenience, when a collection of drawings labeled with different letters is present (e.g., FIGS. 8A-8E ), such a collection may be referred to herein without the letters, e.g., as "FIG. 8 "). Similarly, if a collection of reference numerals are present that are labeled with different numerals and / or letters (e.g., 114-1, 114-2, or 108A-1, 108A-2, 108B-1, 108B-2), such a collection may be referred to herein without the numerals and / or letters (e.g., as "114" or "108A" or "108").Various operations, in turn, may be described as multiple discrete acts or operations, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be considered to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the presented order. Described operations may be performed in a different order from the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.Exemplary EmbodimentsFIG. 1 is a circuit diagram of top views of two layers of dies for bonding together and a stacked view according to some embodiments of the present disclosure. The first layer 130- 1 may be reconstituted KGDs (e.g., dies 114- 1) on one carrier 101- 1 (e.g., a first wafer) and the second layer 130- 2 may be reconstituted KGDs (e.g., dies 114- 2) on another carrier 101- 2 (e.g., a second wafer). A wafer with reconstituted KGDs may be referred to herein as KGW. The dies 114- 1 may include conductive contacts 124 on a surface, and the conductive contacts 124 may include conductive contacts 124- 1, 124- 2 with different distances. The dies 114- 2 may include conductive contacts 122 on a surface, and the conductive contacts 122 may include conductive contacts 122- 1, 122- 2 at different distances and in different arrays. The reconstituted dies 114- 1, 114- 2 may be placed using any suitable technique, such as a die bonder. The die bonder may have limited placement accuracy to align the conductive contacts 124 of the dies 114- 1 with the conductive contacts 122 of the dies 114- 2 when the first layer 130- 1 is stacked on the second layer 130- 2 for bonding. The conductive contacts 122, 124 may be misaligned along a width (e.g., y-direction), a length (e.g., x-direction), and / or a rotation angle (e.g., theta ( )). As shown in the stacked diagram (e.g., the bottom diagram), the conductive contacts 124 of the die 114- 1 and the conductive contacts 122 of the die 114- 2 may be misaligned such that a connection cannot be formed (e.g., resulting in open (open) or infinite resistance) or a connection may be formed with an adjacent contact (e.g., resulting in short circuits).Accordingly, embodiments disclosed herein include architectures that enable the use of compensation layers to align and electrically couple the conductive contacts 124 of the die 114- 1 to the conductive contacts 122 of the die 1114- 2.FIG. 2 is a circuit diagram of top views of two layers of dies and a compensation layer for bonding together, and a stacked view according to some embodiments of the present disclosure. FIG. 2 shows the first layer 130- 1 with reconstituted KGDs (e.g., dies 114- 1) on one carrier 101- 1 of FIG. 1 and the second layer 130- 2 may be reconstituted KGDs (e.g., dies 114- 2) on another carrier 101- 2, also from FIG. 1, and further shows a compensation layer 180, also referred to herein as a "pad layer" and having conductive pads 108B. In some embodiments, the compensation layer 180 may further include conductive features 108A, such as vias (e.g., as shown in array 403- 1 in FIG. 4A ) or conductive traces (e.g., as shown in array 403- 2 in FIG. 4B ) coupled to the conductive pads 108B to couple the layers together. In some embodiments, the compensation layer 180 may include only conductive pads 108B coupled to conductive contacts 122, 124 (e.g., as shown in array 403- 3 in FIG. 4B and as shown in FIG. 7B ). The compensation layer 180 may be stacked between the first layer 130- 1 and the second layer 130- 3. The conductive pads 108B of the compensation layer 180 may redirect the connections such that the conductive contacts 124 of the die 114- 1 may be coupled to the conductive contacts 122 of the die 114- 2. In some embodiments, the first layer 130- 1 or the second layer 130- 2 is an unselit wafer.FIG. 1A is a schematic cross-sectional view of an example microelectronic assembly 100, in accordance with some embodiments of the present disclosure. Microelectronic assembly 100, in the embodiment shown, includes a stack of layers 130 (e.g., 130- 1, 130- 2) coupled by at least one compensation layer (e.g., 180- 1, 180- 2) and hybrid bond (HB) interconnects 106. The layer 130- 1 may include dies 114- 1 (e.g., reconstituted KGDs with functional ICs) surrounded by an insulating material 133. Generally, a KGD is typically a semiconductor die with ICs that passed various test operations such as wafer sample, burn-in, function test, screening, etc., and operate within design parameters. The KGDs are manufactured in wafer form, singulated, tested (before or after singulation), and screened before being used in microelectronic assembly 100. The dies 114- 1 may include a substrate 109, a metallization stack 103 (e.g., a back end of line (BEOL) stack), and through silicon vias (TSVs) 115 coupling conductive contacts 124 to the metallization stack 103. Layer 130- 1 may also include a via 110 extending through layer 130- 1.The layer 130- 2 may include dies 114- 2 (e.g., reconstituted KGDs with functional ICs) surrounded by an insulating material 133. The dies 114- 2 may include a substrate 109 and a metallization stack 103 coupled to conductive contacts 122. The die 114- 1 may be coupled to the die 114- 2 in a back-to-front configuration in which the front side (e.g., metallization stack 103) of the die 114- 2 is coupled to a back side of the die 114- 1. The conductive contacts 122, 124 may have multiple spacings and / or dimensions (e.g., as shown in FIG. 7 ). Layer 130- 2 may further include a via 110 (e.g., as shown in FIG. 6 ) extending through layer 130- 2. An insulating material 133 encapsulating the die 114 (e.g., on and around the die 114 in the layers 130- 1, 130- 2) may include an inorganic material such as silicon oxide or an organic material such as resin, epoxy, or a combination such as a molding material (organic polymer with embedded inorganic particles, e.g., silicon oxide, aluminum oxide, etc.).The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k and ultra-low-k dielectric (e.g., carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, organic polymer dielectrics, an EMC, photo-structurable dielectrics, and / or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive paths in a die 114 may include conductive traces and / or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces on the die 114). The conductive paths in the dies 114 may be bounded by liner materials, such as adhesion liners and / or barrier liners, as appropriate. In one embodiment, die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, a fan-out or fan-in-package die, or a die stack (e.g., wafer-stacked, die-stacked, or multilayer die-stacked). In various embodiments, the die 114 may include one or more of a central processing unit (CPU), a memory device (e.g., a high bandwidth memory device), a logic circuit, input / output circuitry, a transceiver such as a field programmable gate array transceiver, gate array logic such as field programmable gate array logic, power delivery circuitry, a III-V or III-N device such as a III-N or III-N amplifier (e.g., GaN amplifier), Peripheral component interconnect express (PCIe) circuitry, dual data rate (DDR) transmission circuitry, or other electronic components known in the art may comprise or be part of same. In some embodiments, die 114- 1 and die 114- 2 may have different functionalities. As used herein, the term "functionality" refers to a die to one or more functions (e.g., capability, task, operation, action, instruction execution, etc.) that the die in question may perform. The die 114- 1 may be, for example, a CPU or a graphics processing unit (GPU), and the die 114- 2 may be a memory. In other embodiments, die 114- 1 and die 114- 2 may have the same or similar functionalities. For example, the die 114- 1 and the die 114- 2 may each include a memory.In particular, the dies 114- 1 in the layer 130- 1 may be coupled to the dies 114- 2 in the layer 130- 2 through the hybrid bond layers 106- 1, 106- 2 and the compensation layers 180- 1, 180- 2. The conductive contacts 124 of the die 114- 1 may be misaligned with (e.g., offset from) the conductive contacts 122 of the dies 114- 2 by different distances, e.g., offset distances 191, 192, 193, 194, 195, 196, 197, 198. In some embodiments, one or more of the offset distances 191, 192, 193, 194, 195, 196, 197, 198 may have a same or a uniform distance. In some embodiments, the offset distances 191, 192, 193, 194, 195, 196, 197, 198 may be different (e.g., have a different width (i.e., y-axis distance), have a different length (i.e., x-axis distance), and / or have a different rotation (i.e., pivot angle along the xy-axis)).A compensation layer 180 may include a conductive path 108 (e.g., conductive pad 108B) through a dielectric material 112. In some embodiments, a conductive path 108 may include a conductive pad 108B and may further include a conductive feature 108A (e.g., a conductive via or conductive trace depicted as conductive feature 108A). As used herein, the terms "conductive feature", "conductive via", and "conductive trace" may be used interchangeably and refer to element 108A in the accompanying drawings. A compensation layer 180 may be formed after testing the layers 130- 1, 130- 2 of the reconstituted KGWs (e.g., dies 114- 1 and / or 114- 2) and quantifying the misalignment (e.g., offset distances 191- 198) of the conductive contacts 124 of the dies 114- 1 to the conductive contacts 122 of the dies 114- 2. After quantifying the misalignment of each set of conductive contacts 124, 122, the compensation layer 180 may be formed to compensate for the misalignment (e.g., offset distances 191- 198) of each set of conductive contacts 124, 122. For small misalignment, a single compensation layer 180 (e.g., as shown in FIG. 7 ) may be sufficient. For large misalignments, two or more compensation layers 180 (e.g., as shown in FIGS. 3, 5, and 6 ) may be required. In particular, as shown in FIG. 3, microelectronic assembly 100 may include a first compensation layer 180- 1 on dies 114- 1 of layer 130- 1 having a conductive via 108A- 1 and a conductive pad 108B- 1 coupled to a conductive contact 124, and a second compensation layer 180- 2 on dies 114- 2 of layer 130- 2 having a conductive via 108A- 2 and a conductive pad 108B- 2 coupled to a conductive contact 122, wherein conductive vias 108A- 1, 108A- 2 and conductive pads 108B- 1, 108B- 2 are positioned to offset misalignment of a set of conductive contacts 124, 122. An offset distance (e.g., 191-198) and position may vary for each set of conductive contacts 124, 122, and may be determined after inspection (e.g., using optical inspection equipment) of the reconstituted KGWs. The compensation layers 180 may be fabricated using any suitable technique for adaptive patterning, including, but not limited to, mask-based lithography, maskless lithography, laser direct write technology, which may utilize inputs based on the adaptive patterning. For example, a compensation layer 180 may be formed using a simple damascene process (e.g., for a pad 108B-only layer as shown in FIG. 7B ) or may be formed using a dual damascene process (e.g., for a pad 108B and a via 108A layer as shown in FIG. 3 ). A dielectric material 112 of the compensation layer 180 may include inorganic materials such as silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbon nitride, or a low-k and ultra-low-k dielectric (e.g., carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, or organic polymer dielectrics (such as polyimide) or EMCs). The material of the conductive path 108 may comprise a metal, such as copper, and may be created using a damascene or dual damascene process, for example. In an example where a polymer dielectric or EMC is used, the patterning and metal electroplating steps may be followed by encapsulation of the metal interconnect pads, vias, and traces with the polymer dielectric or EMC and may then be planarized to expose the interconnects. Although FIG. 3 shows conductive paths 108 of a compensation layer 180 having conductive vias 108A and conductive pads 108B, the conductive paths 108 may include any suitable conductive features, such as conductive traces 108A and conductive pads 108B, or may include only conductive pads 108B. In some embodiments, the dies 114- 1, 114- 2 may include vias coupled to the conductive contacts 124, 122 such that the compensation layers 180- 1, 180- 2 may include only conductive pads 108B.The HB interconnect 106 generally includes an HB layer 106- 1 of metal contacts 107- 1, also referred to herein as "metal pads" or "HB pads", surrounded by a dielectric material 105- 1 coupled to another HB layer 106- 2 of metal contacts 107- 2 surrounded by the dielectric material 105- 2, where the metal contacts 107 are bonded together and the dielectric materials 105 are bonded together by fusion bonds (e.g., oxide-oxide bonds). An HB process generally uses inorganic dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, and / or other forms of inorganic dielectric materials or organic dielectric materials. As used herein, the term "fusion bond" means bonds between a variety of inorganic materials typically used as dielectric materials in semiconductor processing, and may include bonds between oxides, nitrides, carbides, oxy-nitrides, oxy-carbo-nitrides, polyimide, etc. The top surfaces of the HB pads 107 may be substantially coplanar with the top surface of the dielectric material 105. In some cases, the top surface of the HB pads 107 may be one to several nanometers below the top surface of the dielectric material 105. To initiate bonding, the pair of HB layers 106- 1 and 106- 2 are brought into contact with each other. Substantially at room temperature, the dielectric layers 105- 1, 105- 2 begin to bond to each other due to van der Waals forces. The temperature can then be increased. This results in the formation of stronger covalent bonds between the bond layer dielectrics, referred to herein as fusion bonds. This also results in the metal pads 107- 1, 107- 2 being slightly recessed as mentioned, touching, as the coefficient of thermal expansion of the metal (e.g., copper) is higher than that of the surrounding dielectric. This contact and the additional temperature then result in inter-diffusion between the HB pads 107- 1, 107- 2 on the opposing dies. In some embodiments, the inter-diffusion may even result in no recognizable interface between the HB pads 107- 1, 107- 2. That is, the HB pads 107- 1, 107- 2 may substantially fuse to form a single conductive structure.The HB layer 106- 1 may be coupled to the compensation layer 180- 1 and the HB layer 106- 2 may be coupled to the compensation layer 180- 2. The compensation layers 180- 1, 180- 2 may cause the HB pads 107- 1, 107- 2 of the HB layers 106- 1 and / or 106- 2 to align and bond by compensating for any misalignment created by the die bonder.HB processes are particularly advantageous in multi-die modules because they enable extremely high density interconnects. In some embodiments, a pitch of the HB junctions may be between 50 nanometers and 10 micrometers. For example, a pitch of the HB junctions may be between 50 nanometers and 3 micrometers. Thus, extremely high input / output (I / O) densities may be provided to increase bandwidth capabilities.During the fabrication of microelectronic assembly 100, KGDs (e.g., dies 114- 1, 114- 2) are reconstituted on respective carrier wafers to form KGWs (e.g., layers 130- 1, 130- 2), where the KGDs are misaligned for bonding when overlaid. For example, using a die bonder or other similar equipment, the dies 114-1 may be placed on a first carrier wafer and the dies 114-2 may be placed on a second carrier wafer at locations corresponding to their respective HB interconnects. Due to equipment placement constraints (e.g., about 3 sigma of 500 nanometers in current generation die bonder), the respective interconnects of die 114- 1 and die 114- 2 are likely misaligned. The HB pads 107 size and spacing between adjacent pads is typically equal to about half of a distance between the interconnects. For example, for connections spaced about 1 micron apart, the HB pad size is about 500 nanometers and the spacing between adjacent HB pads 107 is about 500 nanometers. Using die placement accuracy of 200 to 500 nanometers, the probability of interruptions and shorts occurring in the interconnects is very high, such that all microelectronic assemblies 100 will fail. By checking and quantifying the misalignment of the interconnects, one or more compensation layers 180 may be formed using adaptive patterning to re-align the interconnects for KGW-to-KGW hybrid bonding such that the reconstituted KGWs resemble unshared wafers on which the interconnects are aligned. Further, the configuration described herein enables wafer-to-wafer HB bonding compatible with wafer-level tools. The HB layers 106 may be formed on the surfaces of the compensation layers 180, or, if only a single compensation layer is used, on the surface of the KGWs, and the assembly may be subjected to HB processing to form HB interconnects. The surfaces of the KGWs may be polished by chemical mechanical polishing (CMP) prior to bonding, which provides a high yield in wafer-to-wafer HB processes and aligns the HB bond pads in the HB bond layers to form HB interconnects. The degree of registration error between the KGWs may aid in determining whether the compensation layer 180 includes a single damascene layer, a dual damascene layer, or multiple damascene / dual damascene layers. The process for forming microelectronic assemblies 100 with compensation layers 180 will be described further below with reference to FIG. 8. The configuration of microelectronic assembly 100 described herein shows die 114- 1 of layer 130- 1 coupled to die 114- 2 of layer 130- 2 in a front-to-back hybrid bond configuration, wherein an active side (e.g., metallization stack 103) of die 114- 2 is coupled to an active side (e.g., metallization stack 103) of die 114- 1.The microelectronic assembly 100 of FIG. 3 may also include a package substrate 102 and a circuit board 131. In particular, a package substrate 102 may be coupled to the layer 130- 1 via interconnects 150, and the circuit board 131 may be coupled to the package substrate 102 via interconnects 190. The interconnects 150, 190 disclosed herein may have any suitable shape, including, for example, solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or terminal areas in a terminal area grid array arrangement. In some embodiments, a set of interconnects 150, 190 may comprise solder (e.g., solder bumps or balls that are subjected to thermal reflow (reflow) to form the interconnects 150, 190). In some embodiments, an underfill material (not shown) may extend around the associated interconnects 150, 190. The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths for routing power, ground, and signals through the dielectric material. The circuit board 131 may be, for example, a motherboard, and other components may be mounted thereon. The circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board as known in the art. In some embodiments, the interconnects 190 may not couple to a circuit board 131, but instead may be coupled to another IC package, interposer, or any other suitable component.In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymers, dry film photoimageable polymers, acrylates, solvents) may be provided in an IC package described herein, which may not be marked or shown so as not to overcharge the drawings. The solder resist may be a liquid or dry film material comprising photostructurable polymers. In some embodiments, the solder resist may be non-photoimageable.Although FIG. 3 shows microelectronic device 100 having a particular number and arrangement of dies 114, compensation layers 180, and HB layers 106, this number and arrangement is for illustrative purposes only. Many of the elements of microelectronic assembly 100 of FIG. 3 are included in others of the accompanying drawings; the discussion of these elements will not be repeated in the discussion of these drawings, and any of these elements may take any of the forms disclosed herein. Further, a number of elements is shown in FIG. 3 as included in microelectronic assembly 100, but a number of these elements may not be present in microelectronic assembly 100. For example, in various embodiments, the package substrate 102 and the circuit board 131 may not be included.FIG. 4A is a circuit diagram of stacked views of two dies and two compensation layers for bonding together, in accordance with some embodiments of the present disclosure. The arrangement 401 includes a die 114- 1 with conductive contacts 124 overlying a die 114- 2 with conductive contacts 122. The dies 114- 1, 114- 2 may be KGDs that are reconstituted on wafer carriers to form respective KGWs. As shown in FIG. 4A, the dies 114- 1, 114- 2 are misaligned such that the sets of conductive contacts 124, 122 are misaligned along a width (e.g., y-direction), a length (e.g., x-direction), and / or a rotation angle (e.g., theta ( )). The sets of conductive contacts 124, 122 may be misaligned by different widths, lengths, and / or angles of rotation. As shown in the arrangement 401, the conductive contacts 124 of the die 114- 1 and the conductive contacts 122 of the die 114- 2 are actually misaligned such that a connection cannot be formed or a connection to an adjacent contact cannot be properly formed. Arrangement 402 illustrates arrangement 401, which further includes a first compensation layer (e.g., compensation layer 180- 1 of FIG. 3 ) having first conductive vias 108A- 1 and first conductive pads 108B- 1 at least partially offsetting misaligned conductive contacts 124, 122. The first conductive vias 108A- 1 and the first conductive pads 108B- 1 may have different dimensions and different offset values depending on the determined misalignments between each set of conductive contacts 124, 122. Arrangement 403- 1 shows arrangement 402, further comprising a second compensation layer (e.g., compensation layer 180- 2 of FIG. 3 ) having second conductive vias 108A- 2 and second conductive pads 108B- 2 that at least partially offset misaligned conductive contacts 124, 122. The second conductive vias 108A- 2 and the second conductive pads 108B- 2 may have different dimensions and different offset values depending on the determined misalignments between each set of conductive contacts 124, 122, as well as based on the partial offset provided by the first conductive vias 108A- 1 and the first conductive pads 108B- 1 of the first compensation layer. In some embodiments, the first conductive vias 108A- 1 and the first conductive pads 108B- 1 have similar dimensions and offset distances as the second conductive vias 108A- 2 and the second conductive pads 108B- 2. In some embodiments, the first conductive vias 108A- 1 and the first conductive pads 108B- 1 have different dimensions and different offset distances compared to the second conductive vias 108A- 2 and the second conductive pads 108B- 2, such that the first compensation layer more aggressively offsets misalignments than the second compensation layer, or vice versa.FIG. 4B is a circuit diagram of other stacked views of two dies and two compensation layers for bonding together, in accordance with some embodiments of the present disclosure. FIG. 4B shows an arrangement 403- 2 and 403- 3 similar to arrangement 403- 1 of FIG. 4A, except for the differences further described. The arrangement 403- 2 includes a first compensation layer (e.g., the compensation layer 180- 1 of FIG. 3 ) and a second compensation layer (e.g., the compensation layer 180- 2 of FIG. 3 ). The first compensation layer includes first conductive traces 108A- 1 and first conductive pads 108B- 1 that at least partially offset the misaligned conductive contacts 124, 122. The second compensation layer includes second conductive traces 108A- 2 and second conductive pads 108B- 2 that offset the misaligned conductive contacts 124, 122. The first conductive traces 108A- 1 and the first conductive pads 108B- 1 may have different dimensions and different offset values depending on the determined misalignments between each set of conductive contacts 124, 122. The second conductive traces 108A- 2 and the second conductive pads 108B- 2 may have different dimensions and different offset values depending on the determined misalignments between each set of conductive contacts 124, 122, as well as based on the partial offset provided by the first conductive traces 108A- 1 and the first conductive pads 108B- 1 of the first compensation layer. In some embodiments, the first conductive traces 108A- 1 and the first conductive pads 108B- 1 have similar dimensions and offset distances as the second conductive traces 108A- 2 and the second conductive pads 108B- 2. In some embodiments, the first conductive vias 108A- 1 and the first conductive pads 108B- 1 have different dimensions and different offset distances compared to the second conductive vias 108A- 2 and the second conductive pads 108B- 2, such that the first compensation layer more aggressively offsets misalignments than the second compensation layer, or vice versa.The arrangement 403- 3 includes a first compensation layer (e.g., the compensation layer 180- 1 of FIG. 3 ) having first conductive pads 108B- 1 and a second compensation layer (e.g., the compensation layer 180- 2 of FIG. 3 ) having second conductive pads 108B- 2 that offset the misaligned conductive contacts 124, 122. As shown in arrangement 403- 3, the first compensation layer includes only first conductive pads 108B- 1 and the second compensation layer includes only second conductive pads 108B- 2 (e.g., as shown for compensation layer 180 in FIG. 7B ). The first conductive pads 108B- 1 and the second conductive pads 108B- 2 may have different dimensions and different offset values depending on the determined misalignments between the individual sets of conductive contacts 124, 122.FIG. 5 is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is the same as that of Fig. 3 except for the differences described further. The configuration of microelectronic assembly 100 described herein shows die 114- 1 of layer 130- 1 coupled to die 114- 2 of layer 130- 2 in a front-to-front hybrid bond configuration, wherein an active side (e.g., metallization stack 103) of die 114- 2 is coupled to an active side (e.g., metallization stack 103) of die 114- 1.FIG. 6A is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is the same as that of Fig. 3 except for the differences described further. The configuration of microelectronic assembly 100, in the embodiment shown, may include a stack of layers 130 (e.g., 130- 1, 130- 2) coupled by two compensation layers (e.g., 180- 1A, 180- 1B) and hybrid bond (HB) interconnects 106. The two compensation layers 180- 1A, 180- 1B are between the layer 130- 1 and the HB layer 106- 1, and there is no compensation layer 180 between the layer 130- 2 and the HB layer 106- 2. The die 114- 1 of the layer 130- 1 is coupled to the die 114- 2 of the layer 130- 2 in a back-to-back configuration, with a back side of the die 114- 2 coupled to a back side of the die 114- 1. The layer 130- 2 may further include a via 110 extending through the insulating material 133 of the layer 130- 2 and coupled to the die 114- 1 in the layer 130- 1 through conductive paths 108 through the compensation layers 180- 1A, 180- 1B.FIG. 6B is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is the same as that of Fig. 6A, except for the differences described further. The configuration of microelectronic assembly 100, in the embodiment shown, may include a third layer 130- 3 of dies 114- 3 in the stack of layers (e.g., 130- 1, 130- 2), each adjacent layer in the stack of layers being coupled by compensation layers (e.g., 180- 1A, 180- 1B, 180- 2, 180- 3) and hybrid bond (HB) connections 106 of hybrid bond layers (e.g., 106- 1, 106- 2, and 106- 3, 106- 4). The dies 114-3 may comprise KGDs that are reconstituted to form a KGW. Although FIG. 6B shows a particular number and arrangement of compensation layers 180, a microelectronic assembly may include any suitable number and arrangement of compensation layers 180.FIG. 7A is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is the same as that of Fig. 3 except for the differences described further. The configuration of microelectronic assembly 100, in the embodiment shown, may include a stack of layers 130 (e.g., 130- 1, 130- 2) coupled by a compensation layer 180 and hybrid bond (HB) interconnects 106. The compensation layer 180 is between the layer 130- 1 and the HB layer 106- 1, and there is no compensation layer 180 between the layer 130- 2 and the HB layer 106- 2. The layer 130- 2 may include a wafer 113 that has not been singulated (e.g., not reconstituted with KGDs). The wafer 113 may include metallization layers having conductive contacts 122 with different spacings. For example, as shown, wafer 113 may include first conductive contacts 122- 1 having a first pitch, second conductive contacts 122- 2 having a second pitch different from the first pitch, and third conductive contacts 122- 3 having a third pitch different from the first and second pitches. Individual conductive contacts 124, 122 may be coupled to individual HB pads 107- 1 and / or 107- 2, or, as shown for the third conductive contacts 122- 3, a single conductive contact 122 may be coupled to two or more HB pads 107- 2. The microelectronic assembly 100 of FIG. 7 may include a single compensation layer 180 between the conductive contacts 122- 1, 122- 2 and the conductive contacts 124, respectively, due to the lesser offset 791, 792. In some embodiments, wafer 113 may comprise a plurality of reconstituted KGDs.FIG. 7B is a schematic cross-sectional view of another example microelectronic assembly in accordance with some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is the same as that of Fig. 7A except for the differences described below. The configuration of microelectronic assembly 100, in the embodiment shown, may include a stack of layers 130 (e.g., 130- 1, 130- 2) coupled by a compensation layer 180 and hybrid bond (HB) interconnects 106. The compensation layer 180 may include conductive pads 108B and may not include conductive vias (e.g., conductive vias 108A as shown in FIG. 7A ). The compensation layer 180, which includes only the conductive pads 108B, may be formed using any suitable process, e.g., a simple damascene process.In various embodiments, any of the features discussed with reference to any of FIGS. 2-7 may be combined with any other features to form a package having one or more ICs as described herein, e.g., to form a modified microelectronic assembly 100. Some such combinations are described above, but in various embodiments further combinations and modifications are possible.Example MethodsFIGS. 8A-8E are schematic cross-sectional views of various stages of manufacture of an example microelectronic assembly 100, in accordance with some embodiments of the present disclosure. FIG. 8A shows the arrangements 801- 1, 801- 2. The assembly 801- 1 may include a carrier 800- 1 on which the dies 114- 1 (e.g., the dies 114- 1A, 114- 1B, 114- 1C) are reconstituted. The dies 114- 1 are KGDs and may include a substrate 109, a metallization stack 103, and through silicon vias (TSVs) 115 coupling conductive contacts 124 to the metallization stack 103. The arrangement 801- 2 may include a carrier 800- 2 on which the dies 114- 2 (e.g., the dies 114- 2A, 114- 2B) are reconstituted. The dies 114- 2 may be KGDs and may include a substrate 109 and a metallization stack 103 coupled to conductive contacts 122. The carriers 800- 1, 800- 2 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer) or glass. In some embodiments, the array 801- 1 or the array 801- 2 may be an unselit wafer. The dies 114- 1, 114- 2 may be placed using any suitable technique, such as a die bonder.FIG. 8B illustrates arrangements 802- 1, 802- 2 after the formation of the layers 130- 1 and / or 130- 2 by depositing an insulating material 133 on and around the dies 114- 1, 114- 2. The insulating material 133 may comprise any suitable material as described above with reference to FIG. 3, and may be deposited using any suitable technique, e.g., using any suitable technique of a plasma enhanced chemical vapor deposition (PECVD) process or a spin coating process. In some embodiments, a liner material (not shown), e.g., silicon nitride or silicon carbon nitride, may be coated on and around the dies 114- 1, 114- 2 prior to depositing the insulating material 133. The liner material may be deposited using any suitable technique, e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), or PECVD. In some embodiments, an insulating material 133 may be deposited to completely cover the dies 114- 1, 114- 2, and the overhang of insulating material 133 may be removed to expose conductive contacts 124, 122 on a top surface of the dies 114- 1 and / or 114- 2. The insulating material 133 may be removed using any suitable technique including mechanical grinding and / or CMP. The layer 130- 1 may further include a via 110 extending through the insulating material 133. The layer 130- 2 may further include a via 110 (not shown) extending through the insulating material 133. Via 110 may be formed using any suitable technique including additive or subtractive processes. In some embodiments, the via 110 may be formed prior to depositing the insulating material 133. In some embodiments, the via 110 may be formed after depositing the insulating material 133.FIG. 8C shows the arrays 803- 1, 803- 2 after the formation of compensation layers 180- 1, 180- 2 on the top surfaces of the arrays 802- 1, 802- 2 of FIG. 8B. The compensation layers 180 may include a dielectric material 112 having conductive paths 108 (e.g., conductive vias 108A and conductive pads 108B) offset in a direction to compensate for misalignment of the dies 114- 1, 114- 2. The arrays 802- 1, 802- 2 in FIG. 8B may be optically inspected to quantify any misalignment vectors of the dies 114- 1, 114- 2 on the carriers 800- 1, 800- 2 (e.g., the true position) and thus the misalignment vectors of the individual sets of conductive contacts 124, 122. The determined misalignment quantifications may be used to pattern the compensation layers 180- 1, 180- 2 and correct the misalignment (e.g., compensate for the offsets). For example, the compensation layer 180- 1 may include a first conductive path 108 having an offset 891 that moves one connection of die 114- 1A in a first direction (e.g., in a positive y direction or to the right), a second conductive path 108 having an offset 892 that moves one connection of die 114- 1B in the first direction, a third conductive path 108 having an offset 893 that moves another connection of die 114- 1B in a second direction (e.g., in a negative y direction or to the left), and a fourth conductive path 108 having an offset 894 that moves the connection of die 114- 1C in the second direction.The conductive paths 108 of the compensation layer 180 may be mapped to offset interconnect misalignment between the dies 114- 1, 114- 2, and as such may be designed to have different sizes, different distances, and / or different directions to each other. For example, the compensation layer 180- 1 may include the first conductive path 108 having an offset 891 that moves one connection of die 114- 1A in a first direction by a first dimension, a second conductive path 108 having an offset 892 that moves one connection of die 114- 1B in the first direction by a second dimension that is different than the first dimension, a third conductive path 108 having an offset 893 that moves another connection of die 114- 1B in a second direction that is different than the first direction by a third dimension that is different than the first and second dimensions, and a fourth conductive path 108 having an offset 894 that moves the connection of die 114- 1C in the second direction by a fourth dimension that is different than the first, the second and third dimensions being different, moved.In another example, the compensation layer 180- 1 may include a first conductive path 108 that moves a connection of a first die 114- 1 in a first direction by a first dimension, a second conductive path 108 that moves a connection of a second die 114- 1 in a second direction by a second dimension, a third conductive path 108 that moves another connection of the second die 114- 1 in a third direction by a third dimension, and a fourth conductive path 108 that moves the connection of a third die 114- 1 in a fourth direction by a fourth dimension, wherein the first, second, third, and fourth directions are different from each other and the first, second, third, and fourth dimensions are different from each other.In another example, the compensation layer 180- 1 may include a conductive path 108 that moves a connection of the dies 114- 1 in a first direction by a first dimension and in a second direction by a second dimension, wherein the first and second directions are different and the first and second dimensions have the same value or different values. In some embodiments, the compensation layer 180- 1 may include a first conductive path 108 that moves a connection of the die 114- 1 in a direction that is a rotational direction. The conductive paths 108 in the compensation layer 180- 2 of the array 803- 2 may have similar offsets in similar directions as the array 803- 1, or may have different offsets (e.g., smaller offsets or larger offsets) in similar directions as the array 803- 1 based on the mispositioning of the single die or dies. The compensation layers 180- 1, 180- 2 may be formed using any suitable technique, including the techniques described above with reference to FIG. 3. For example, the compensation layer 180 may be formed using a BEOL process. In some embodiments, the compensation layers 180 may be formed using an adaptive patterning process, such as direct write lithography. In some embodiments, alignment marks on the dies 114, the insulating material 133, and / or the compensation layers 180 may be patterned and fabricated to assist in aligning the dies 114.FIG. 8D shows the arrays 804- 1, 804- 2 after forming an HB layer 106 (e.g., HB layers 106- 1, 106- 2) on the top surfaces of the arrays 803- 1, 803- 2 of FIG. 8C. The HB layer 106- 1 may include bond pads 107- 1 in a dielectric material 105- 1 and the HB layer 106- 2 may include bond pads 107- 2 in a dielectric material 105- 2. The bond pads 107- 1 of the HB layer 106- 1 may correspond to the bond pads 107- 2 of the HB layer 106- 2 as described above with reference to FIG. 3 to form HB interconnects. In some embodiments, a pitch of the HB junctions is between 50 nanometers and 10 micrometers.FIG. 8E shows microelectronic assembly 100 after inverting assembly 804- 2 of FIG. 8D, removing carriers 800- 1, 800- 2 from assemblies 804- 1, 804- 2 of FIG. 8D, and forming HB interconnects. The arrangement of FIG. 8E may be subjected to a suitable bonding process to form HB interconnects as described above with reference to FIG. 3. The HB connections may be formed where the conductive bond pads align. The HB connections may have multiple spacings as well as non-uniform spacings. Microelectronic device 100 may be fabricated along with other devices, and when fabricated with other devices, the devices may be singulated. The arrangement of FIG. 8E may itself be a microelectronic assembly 100, as shown. Further fabrication operations may be performed on the microelectronic assembly 100 of FIG. 8E to form another microelectronic assembly 100; for example, the microelectronic assembly 100 of FIG. 8E may be coupled to a package substrate 102 via interconnects 150, and the package substrate 102 may be coupled to a circuit board 131 via interconnects 190, similar to the microelectronic assembly 100 of FIG. 3.FIG. 9 is a flow diagram of an example method of manufacturing an example microelectronic assembly 100 of FIGS. 3 and 5- 7, in accordance with various embodiments. At 902, first dies 114- 1 (e.g., KGDs) may be reconstituted on a first wafer carrier to form a layer 130- 1 (e.g., a first KGW) and second dies 114- 2 (e.g., KGDs) may be reconstituted on a second wafer carrier to form a layer 130- 2 (e.g., a second KGW). The first dies 114- 1 and the second dies 114- 2 may be placed using any suitable technique, such as a die bonder. A liner material may be deposited on and over the first dies 114- 1 and the second dies 114- 2, and an insulating material 133 may be deposited on the liner material. The insulating material 133 may be planarized to expose conductive contacts 124 on a surface of the first dies 114- 1 and conductive contacts 122 on a surface of the second dies 114- 2. In some embodiments, a second wafer may include an unselit wafer of the second dies 114- 2.At 904, the first dies 114- 1 may be checked, e.g., by optical imaging, to determine the actual placement of the first dies 114- 1 and the second dies 114- 2, and any mispositioning (e.g., misalignment) may be quantified. The quantified mispositioning may provide an offset value (e.g., length, width, and / or a rotational offset value) for each of the first dies 114- 1 and the second dies 114- 2 (e.g., for each of the respective sets of conductive contacts 122, 124). The determined offset values may be used in subsequent operations to enable adaptive structuring and compensate for the offsets.At 906, a first compensation layer 180 having conductive paths 108 may be formed on the first dies 114- 1 (e.g., on the surface of the first layer 130- 1) to correct for the mispositioning of the first dies 114- 1 and / or the second dies 114- 2. The quantified offset values may be used to account for inaccuracies in the placement of the dies 114. In some embodiments, a compensation layer 180 may be formed using an adaptive patterning process, e.g., by direct write lithography or maskless lithography, etc. In some embodiments, a single compensation layer 180 may be formed on the layer 130- 1. In some embodiments, two or more compensation layers 180 may be formed on layer 130- 1. In some embodiments, a compensation layer 180 may include conductive pads 108B. In some embodiments, a compensation layer 180 may include conductive pads 108B and conductive vias 108A or conductive traces 108A. In some embodiments, a second compensation layer 180 may be formed on layer 130- 2. In some embodiments, two or more compensation layers 180 may be formed on layer 130- 2.At 908, the HB layers 106- 1, 106- 2 may be formed on a top surface of the layers 130- 1 and / or 130- 2 (e.g., on the compensation layers 180- 1 and 180- 2, if included). The HB layers 106- 1, 106- 2 may each include a dielectric material 105- 1, 105- 2 and HB pads 107- 1, 107- 2. The HB pads 107- 1 of the HB layer 106- 1 may be aligned with the HB pads 107- 2 of the HB layer 106- 2, and HB interconnects may be formed. The conductive contacts 124 of the first dies 114- 1 may be coupled to the respective conductive contacts 122 of the second dies 114- 2 through the conductive paths 108 in the compensation layer 180 and the HB connections.Example Components and ComponentsThe microelectronic assemblies 100 disclosed herein may be included in any suitable electronic component. FIGS. 10-14 illustrate various examples of devices that may be included in or include any of microelectronic assemblies 100 disclosed herein.FIG. 10 is a top view of a wafer 1500 and dies 1502 that may be included in any of the microelectronic assemblies 100 disclosed herein (e.g., as any suitable ones of the dies 114). The wafer 1500 may be composed of a semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product comprising any suitable IC. After the manufacture of the semiconductor product is completed, the wafer 1500 may be subjected to a dicing process in which the dies 1502 are separated from each other to provide discrete "chips" of the semiconductor product. The die 1502 may be any of the dies 114 disclosed herein. The die 1502 may include one or more transistors (e.g., some of the transistors 1640 of FIG. 11 as discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 1500 or die 1502 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., processing device 1802 of FIG. 14 ) or other logic configured to store information in memory.To store memory devices or execute instructions stored in the memory array may be formed. In some embodiments, a die 1502 (e.g., a die 114) may be a central processing unit, a radio frequency chip, a power converter, or a network processor. Various microelectronic assemblies 100 disclosed herein may be fabricated using a die-to-wafer assembly technique in which some dies 114 are attached to a wafer 1500, including others of the dies 114, and the wafer 1500 is subsequently singulated.FIG. 11 is a side cross-sectional view of an IC device 1600 that may be included in any of the microelectronic assemblies 100 disclosed herein (e.g., in any of the dies 114). One or more of the IC devices 1600 may be included in one or more dies 1502 (FIG. 10 ). The IC device 1600 may be formed on a die substrate 1602 (e.g., the wafer 1500 of FIG. 10 ) and may be included in a die (e.g., the die 1502 of FIG. 10 ). The die substrate 1602 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type material systems (or a combination of both). The die substrate 1602 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1602 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1602. Although some examples of materials from which the die substrate 1602 may be formed are described herein, any material that may serve as a base for an IC device 1600 may be used. The die substrate 1602 may be part of a singulated die (e.g., the die 1502 of FIG. 10 ) or a wafer (e.g., the wafer 1500 of FIG. 10 ).The IC device 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling current flow in the transistors 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for routing electrical signals to / from the S / D regions 1620. Transistors 1640 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 11, and may have a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, as well as wrap-around (wrap-around) or surround (all-round) gate transistors, such as nanoband and nanowire transistors.Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include a layer or a stack of layers. The one or more layers may comprise silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an anneal process may be performed on the gate dielectric to improve its quality when a high-k material is used.The gate electrode may be formed on the gate dielectric and may include at least one of a P-type work function metal and an N-type work function metal depending on whether the transistor 1640 is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode may be a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these materials, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning) are not limited thereto.In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may be made of a U-shaped structure including a lower portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions substantially perpendicular to the upper surface of the die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may comprise a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etch process steps. In some embodiments, a plurality of spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.S / D regions 1620 may be formed within die substrate 1602 adjacent gate 1622 of each transistor 1640. The S / D regions 1620 may be formed using, for example, an implantation / diffusion process or an etch / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1602 to form the S / D regions 1620. An anneal process that activates the dopants and causes them to diffuse further into the die substrate 1602 may follow the ion implantation process. In the later process, the die substrate 1602 may be first etched to form recesses at the locations of the S / D regions 1620. An epitaxial deposition process may then be performed to fill the recesses with material used to form the S / D regions 1620. In some implementations, the S / D regions 1620 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or a / r Group III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 1620.Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from the devices (e.g., transistors 1640) of device layer 1604 through one or more interconnect layers disposed on device layer 1604 (as shown as interconnect layers 1606- 1610 in FIG. 11). For example, electrically conductive features of device layer 1604 (e.g., gate 1622 and S / D contacts 1624) may be electrically coupled to interconnect structures 1628 of interconnect layers 1606- 1610. The one or more interconnect layers 1606- 1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of the IC device 1600.The interconnect structures 1628 may be disposed within the interconnect layers 1606- 1610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in FIG. 11. Although a particular number of interconnect layers 1606- 1610 are depicted in FIG. 11, embodiments of the present disclosure include IC devices with more or fewer interconnect layers than depicted.In some embodiments, the interconnect structures 1628 may include lines 1628 aand / or vias 1628 bbeing filled with an electrically conductive material, such as a metal. The lines 1628 amay be arranged to route electrical signals in a direction of a plane substantially parallel to a surface of the die substrate 1602 on which the device layer 1604 is formed. For example, lines 1628a may route electrical signals in a direction into and out of the page from the perspective of Figure 11. The vias 1628 bmay be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the die substrate 1602 on which the device layer 1604 is formed. In some embodiments, vias 1628 bmay electrically couple lines 1628 aof different interconnect layers 1606- 1610 together.The interconnect layers 1606- 1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in FIG. 11. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606- 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606- 1610 may be the same.A first interconnect layer 1606 (referred to as metal 1 or "M1") may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628 aand / or vias 1628 bas shown. The lines 1628 aof the first interconnect layer 1606 may be coupled to contacts (e.g., the S / D contacts 1624) of the device layer 1604.A second interconnect layer 1608 (referred to as metal 2 or "M 2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628 bto couple the lines 1628 aof the second interconnect layer 1608 to the lines 1628 aof the first interconnect layer 1606. Although the lines 1628 aand the vias 1628 bare structurally bounded with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, the lines 1628 aand the vias 1628 bmay be structurally and / or materially contiguous (e.g., filled simultaneously during a dual damascene process), in some embodiments.A third interconnect layer 1610 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be sequentially formed on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are "higher up" in metallization stack 1619 in IC device 1600 (i.e., further away from device layer 1604) may be thicker.The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606- 1610. In FIG. 11, the conductive contacts 1636 are shown in the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structures 1628 and configured to route the electrical signals of the transistor or transistors 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and / or electrically couple a chip comprising the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures to route the electrical signals from the interconnect layers 1606- 1610; the conductive contacts 1636 may include, for example, other analog features (e.g., posts) that route the electrical signals to external components.In some embodiments where the IC device 1600 is a double-sided die, the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1604. This metallization stack may include multiple interconnect layers as discussed above with respect to interconnect layers 1606- 1610 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.In other embodiments where the IC device 1600 is a double-sided die, the IC device 1600 may include one or more TSVs through the die substrate 1602; these TSVs may make contact with the device layer or layers 1604 and may provide conductive paths between the device layer or layers 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.FIG. 12 is a side cross-sectional view of an example IC package 2200, which may include microelectronic assemblies, according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).As shown in FIG. 12, the package carrier 2252 may be formed from an insulator (e.g., a ceramic, a build-up film, an epoxy film having filler particles therein, etc.), and may have conductive paths extending through the insulator between the first surface 2272 and the second surface 2274, or between different locations on the first surface 2272, and / or between different locations on the second surface 2274. These conductive paths may take the form of any of the interconnect structures including, e.g., lines and / or vias, as discussed above with reference to FIG. 1.The package carrier 2252 may include conductive contacts 2263 coupled to a conductive path 2262 through the package carrier 2252, allowing circuitry within dies 2256 and / or interposer 2257 to electrically couple to various ones of conductive contacts 2264 (or to other devices included in the package carrier 2252, not shown).The IC package 2200 may include the interposer 2257 coupled to the package carrier 2252 via conductive contacts 2261 of the interposer 2257, first level interconnects (FLI) 2265, and conductive contacts 2263 of the package carrier 2252. FLI 2265 illustrated in FIG. 12 are solder bumps, but any suitable FLI 2265 may be used, such as solder bumps, solder pillars, or bond wires.The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, FLI 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257). FLI 2258 illustrated in FIG. 12 are solder bumps, but any suitable FLI 2258 may be used, such as solder bumps, solder pillars, or bond wires. As used herein, a "conductive contact" may refer to a portion of electrically conductive material (e.g., metal) that serves as an interface between different components; conductive contacts may be recessed into, flush with, or extend away from a surface of a component, and may take any suitable shape (e.g., a conductive pad or socket).In some embodiments, an underfill material 2266 may be disposed between the package carrier 2252 and the interposer 2257 around the FLI 2265, and a mold 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package carrier 2252. In some embodiments, underfill material 2266 may be the same as mold 2268. Exemplary materials that may be used for the underfill material 2266 and the mold 2268 are epoxies, as appropriate. Second level interconnects (SLI) 2270 may be coupled to conductive contacts 2264. SLI 2270 illustrated in FIG. 12 are solder balls (e.g., for a ball grid array (BGA) arrangement), but any suitable SLI 2270 may also be used (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement). SLI 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), interposer, or other IC package, as is known in the art and as discussed below with reference to FIG. 6.In embodiments where the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, in addition to one or more of the dies 2256 comprising components of dies 114 as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, at least some of the dies 2256 may not comprise components of dies 114 as described.Although the IC package 2200 illustrated in FIG. 12 is a flip-chip package, other package architectures may be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, disposed over the first surface 2272 or the second surface 2274 of the package carrier 2252, or on both surfaces of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.FIG. 13 is a side cross-sectional view of an IC device assembly 1700, which may include any of the microelectronic assemblies 100 disclosed herein. In some embodiments, the IC device assembly 1700 may be a microelectronic assembly 100. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 of the circuit board 1702 and an opposing second surface 1742 of the circuit board 1702; generally, components may be disposed on one or both surfaces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any suitable ones of the embodiments of the microelectronic assemblies 100 disclosed herein.In some embodiments, circuit board 1702 may be a PCB comprising multiple metal layers separated from each other by layers of dielectric material and connected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit structure to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, circuit board 1702 may be a non-PCB substrate. In some embodiments, circuit board 1702 may be, for example, a circuit board.The IC device assembly 1700 illustrated in FIG. 13 includes a package-on-interposer structure 1736 coupled to the first surface 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in FIG. 13 ), plug and socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with respect to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 13, multiple IC packages may be coupled to the interposer 1704; indeed, additional interposers may be coupled to the interposer 1704. The interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be, for example, or include a die (die 1502 of FIG. 10 ), an IC device (e.g., the IC device 1600 of FIG. 11 ), or any other suitable component. In general, the interposer 1704 may propagate a connection to another distance or redirect a connection to a different connection (reroute). For example, the interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of conductive contacts of a ball grid array (BGA) of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 13, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the interposer 1704. In some embodiments, three or more components may be connected using the interposer 1704.In some embodiments, the interposer 1704 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and connected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymeric material such as polyimide. In some embodiments, interposer 1704 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714 including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.The IC device assembly 1700 may include an IC package 1724 coupled to the first surface 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with respect to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with respect to the IC package 1720.The IC device assembly 1700 illustrated in FIG. 13 includes a package-on-package structure 1734 coupled to the second surface 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732, which are coupled to each other by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be formed according to any of the package-on-package structures known in the art.FIG. 14 is a block diagram of an example electrical device 1800 that may include one or more of the microelectronic assemblies 100 disclosed herein. For example, any suitable ones of the components of the electrical device 1800 may include one or more of the IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein, and may be disposed in any of the microelectronic assemblies 100 disclosed herein. A number of components are shown in FIG. 14 as included in the electrical device 1800, however, one or more of these components may be omitted or duplicated, depending on what is suitable for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-a-chip (SoC) die.Additionally, in various embodiments, the electrical device 1800 may include no or no more of the components illustrated in FIG. 14, but the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include a display 1806, but may include display interface circuitry (e.g., a connector and driver circuitry) to which a display 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or audio output device 1808 may be coupled.The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data to other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors executing cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., Direct Random Access Memory (DRAM), nonvolatile memory (e.g., Read-Only Memory (ROM)), flash memory, solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. This memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communication for the transmission of data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not comprise any wires, although in some embodiments they may not.The communication chip 1812 may implement any number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), the long term evolution (LTE) project along with any supplements, updates, and / or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as, 3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an acronym standing for Worldwide Interoperability for Microwave Access, which is a meritorious for products that pass compliance and compatibility tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMLS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with enhanced data for GSM evolution (EDGE), GSM EDGE radio access network (GERAN), universal terrestrial radio access network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. Communication chip 1812 may operate according to other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 for facilitating wireless communication and / or for receiving other wireless communication (such as AM or FM radio transmissions).In some embodiments, communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As mentioned above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to shorter range wireless communications such as Wi-Fi or Bluetooth and a second communication chip 1812 may be dedicated to longer range wireless communications such as global positioning system (GPS), edge, gprs, cdma, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications and a second communication chip 1812 may be dedicated to wired communications.The electrical device 1800 may include battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1800 to a power source separate from the electrical device 1800 (e.g., AC line power).The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry as discussed above). The display device 1806 may include, for example, any visual indicators such as a heads-up display (HUD), a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry as discussed above). Audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earphones.The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry as discussed above). The audio input device 1824 may include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a MIDI (musical instrument digital interface) output).The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800 as is known in the art.The electrical device 1800 may include another output device 1810 (or corresponding interface circuitry as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.The electrical device 1800 may include another input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor or radio frequency identification (RFID) reader.The electrical device 1800 may have any desired form factor, such as a computing device or a handheld or mobile computing device (e.g., a mobile phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.Selected ExamplesThe paragraphs below provide various examples of the embodiments disclosed herein.Example 1 is a microelectronic assembly comprising a first layer comprising a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact in a second direction different from the first direction; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds, the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the metal-to-metal bonds, and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the metal-to-metal bonds.Example 2 may include the subject matter of Example 1, and may further specify that a distance of adjacent metal-to-metal bonds is between 50 nanometers and 10 micrometers.Example 3 may include the subject matter of Example 1, and may further specify that a distance of adjacent metal-to-metal bonds is between 50 nanometers and 3 micrometers.Example 4 may include the subject matter of any of Examples 1-3, and may further include a first via between and coupled to the first conductive contact and the first pad, and a second via between and coupled to the second conductive contact and the second pad.Example 5 may include the subject matter of any of Examples 1-3, and may further include a first conductive trace between and coupled to the first conductive contact and the first pad and a second conductive trace between and coupled to the second conductive contact and the second pad.Example 6A may include the subject matter of any of Examples 1-5, and may further specify that the pad layer is a first pad layer, and the microelectronic assembly may further include a second pad layer between the first pad layer and the interconnect layer, wherein the second pad layer includes a third pad and a fourth pad, wherein the third pad is coupled to the first pad and is offset from the first pad in the first direction, and wherein the fourth pad is coupled to the second pad and is offset from the second pad in the second direction.Example 6B may include the subject matter of any of Examples 1-5, and may further specify that the pad layer is a first pad layer, and the microelectronic assembly may further include a second pad layer between the interconnect layer and the third die, wherein the second pad layer includes a third pad and a fourth pad, wherein the third pad is coupled to the third conductive contact and the third conductive contact is offset from the third pad in the first direction, and wherein the fourth pad is coupled to the fourth conductive contact and the fourth conductive contact is offset from the fourth pad in the second direction.Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the first layer further includes an insulating material surrounding the first die and the second die, and the pad layer is on the insulating material.Example 8 may include the subject matter of Example 7, and may further specify that the first layer further includes a via through the insulating material and the pad layer further includes a third pad coupled to the via.Example 9 is a microelectronic assembly comprising a first layer comprising a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact by a first dimension in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact by a second dimension different from the first dimension in the first direction; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds; the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the bonds; and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the bonds.Example 10 may include the subject matter of Example 9, and may further specify that a distance of adjacent metal-to-metal bonds is between 50 nanometers and 10 micrometers.Example 11 may include the subject matter of Examples 9 or 10, and may further specify that the pad layer is a first pad layer, and the microelectronic assembly may further include a second pad layer between the first pad layer and the interconnect layer, wherein the second pad layer includes a third pad and a fourth pad, wherein the third pad is coupled to the first pad and offset from the first pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the second pad and offset from the second pad in the first direction by the second dimension.Example 12 may include the subject matter of Examples 9 or 10, and may further specify that the pad layer is a first pad layer, and the microelectronic assembly may further include a second pad layer between the interconnect layer and the third die, wherein the second pad layer includes a third pad and a fourth pad, wherein the third pad is coupled to the third conductive contact and the third conductive contact is offset from the third pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the fourth conductive contact and the fourth conductive contact is offset from the fourth pad in the first direction by the second dimension.Example 13 may include the subject matter of any examples 9-12, and may further specify that the first direction is a first rotational direction.Example 14 may include the subject matter of any of Examples 9-12, and may further specify that the first pad is further offset from the first conductive contact in a second direction different from the first direction.Example 15 may include the subject matter of Example 14, and may further specify that the first pad is offset from the first conductive contact in the second direction by a third dimension different from the first dimension and the second dimension.Example 16A may include the subject matter of any of Examples 9-15, and may further include a first via between and coupled to the first conductive contact and the first pad and a second via between and coupled to the second conductive contact and the second pad.Example 16B may include the subject matter of any of Examples 9-15, and may further include a first conductive trace between and coupled to the first conductive contact and the first pad and a second conductive trace between and coupled to the second conductive contact and the second pad.Example 13 may include the subject matter of any of Examples 9-15, and may further include an insulating material surrounding the first die, the second die, and the third die.Example 17 is a microelectronic assembly comprising a first layer comprising a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact by a first dimension in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact by a second dimension in a second direction, wherein the second direction is different from the first direction and the second dimension is different from the first dimension; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds; the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the metal-to-metal bonds; and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the metal-to-metal bonds.Example 18 may include the subject matter of Example 17, and may further specify that a distance of adjacent metal-to-metal bonds is between 50 nanometers and 10 micrometers.Example 19A may include the subject matter of Examples 17 or 18, and may further include a first via between and coupled to the first conductive contact and the first pad, and a second via between and coupled to the second conductive contact and the second pad.Example 19B may include the subject matter of Examples 17 or 18, and may further include a first conductive trace between and coupled to the first conductive contact and the first pad and a second conductive trace between and coupled to the second conductive contact and the second pad.Example 20 may include the subject matter of any of Examples 17-19, and may further specify that the pad layer is a first pad layer, and the microelectronic assembly may further include a second pad layer between the first pad layer and the interconnect layer, wherein the second pad layer includes a third pad and a fourth pad, wherein the third pad is coupled to the first pad and offset from the first pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the second pad and offset from the second pad in the first direction by the second dimension.Example 21 may include the subject matter of any of Examples 17-19, and may further specify that the pad layer is a first pad layer, and the microelectronic assembly may further include a second pad layer between the interconnect layer and the third die, wherein the second pad layer includes a third pad and a fourth pad, wherein the third pad is coupled to the third conductive contact and the third conductive contact is offset from the third pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the fourth conductive contact and the fourth conductive contact is offset from the fourth pad in the first direction by the second dimension.Example 22 may include the subject matter of any of Examples 17-21, and may further specify that the first die, the second die, and the third die have active surfaces and the active surfaces of the first die and the second die are opposite the active surface of the third die.Example 23 may include the subject matter of any of Examples 17-21, and may further specify that the first die, the second die, and the third die have active surfaces and the active surfaces of the first die and the second die face the active surface of the third die.Example 24 may include the subject matter of any of Examples 17-21, and may further specify that the first die, the second die, and the third die have back surfaces that are opposite to active surfaces, and the back surfaces of the first die and the second die face the back surface of the third die.Example 25 is a microelectronic assembly comprising a first layer comprising a first die having a first conductive contact; a second die having a second conductive contact; and a first pad layer on the first die and the second die, wherein the first pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact by a first dimension in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact by a second dimension in a second direction, wherein the second direction is different from the first direction and the second dimension is different from the first dimension; a second layer comprising a third die having a first surface with a third conductive contact and a fourth conductive contact, and an opposing second surface with a fifth conductive contact; and a second pad layer on the second surface of the third die, the second pad layer comprising a third pad, the third pad coupled to the fifth conductive contact and offset from the fifth conductive contact in a third direction by a third dimension; and a third layer comprising a fourth die with a sixth conductive contact, and may further specify that the first layer is coupled to the second layer by a first interconnect layer having first metal-to-metal bonds and first fusion bonds; the first conductive contact being coupled to the third conductive contact through the first pad and one or more of the first metal-to-metal bonds; the second conductive contact being coupled to the fourth conductive contact through the second pad and one or more of the first metal-to-metal bonds; the second layer being coupled to the third layer through a second interconnect layer having second metal-to-metal bonds and second fusion bonds; and the fifth conductive contact being coupled to the sixth conductive contact through the third pad and one or more of the second metal-to-metal bonds.Example 26 may include the subject matter of Example 25, and may further specify that a distance of adjacent first metal-to-metal bonds and second metal-to-metal bonds is between 50 nanometers and 10 micrometers.Example 27 may include the subject matter of Examples 25 or 26, and may further include a first via between and coupled to the first conductive contact and the first pad, and a second via between and coupled to the second conductive contact and the second pad.Example 28 may include the subject matter of Examples 25 or 26, and may further include a first conductive trace between and coupled to the first conductive contact and the first pad and a second conductive trace between and coupled to the second conductive contact and the second pad.Example 29 may include the subject matter of Examples 25 or 26, and may further include a third via between and coupled to the fifth conductive contact and the third pad.Example 30 may include the subject matter of Examples 25 or 26, and may further include a third conductive trace between and coupled to the fifth conductive contact and the third pad.

Claims

A microelectronic assembly, comprising: a first layer comprising: a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact in a second direction different from the first direction; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein: the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds, the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the metal-to-metal bonds, and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the metal-to-metal bonds.The microelectronic assembly of claim 1, wherein a distance of adjacent metal-to-metal bonds is between 50 nanometers and 10 micrometers.The microelectronic assembly of claim 1 or 2, wherein a distance between adjacent metal-to-metal bonds is between 50 nanometers and 3 micrometers.The microelectronic assembly of any of claims 1-3, further comprising: a first via between and coupled to the first conductive contact and the first pad; and a second via between and coupled to the second conductive contact and the second pad.The microelectronic assembly of any of claims 1-4, further comprising: a first conductive trace between and coupled to the first conductive contact and the first pad; and a second conductive trace between and coupled to the second conductive contact and the second pad.The microelectronic assembly of any of claims 1-5, wherein the pad layer is a first pad layer, and the microelectronic assembly further comprising: a second pad layer between the first pad layer and the interconnect layer, wherein the second pad layer comprises a third pad and a fourth pad, wherein the third pad is coupled to the first pad and is offset from the first pad in the first direction, and wherein the fourth pad is coupled to the second pad and is offset from the second pad in the second direction.The microelectronic assembly of any of claims 1-6, wherein the pad layer is a first pad layer, and the microelectronic assembly further comprising: a second pad layer between the interconnect layer and the third die, wherein the second pad layer comprises a third pad and a fourth pad, wherein the third pad is coupled to the third conductive contact and the third conductive contact is offset from the third pad in the first direction, and wherein the fourth pad is coupled to the fourth conductive contact and the fourth conductive contact is offset from the fourth pad in the second direction.The microelectronic assembly of any of claims 1-7, wherein the first layer further comprises an insulating material surrounding the first die and the second die, and the pad layer is on the insulating material.The microelectronic assembly of claim 8, wherein the first layer further comprises a via through the insulating material and the pad layer further comprises a third pad coupled to the via.A microelectronic assembly, comprising: a first layer comprising: a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact by a first dimension in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact by a second dimension different from the first dimension in the first direction; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein: the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds; the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the bonds; and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the bonds.The microelectronic assembly of claim 10, wherein a distance of adjacent metal-to-metal bonds is between 50 nanometers and 10 micrometers.The microelectronic assembly of claim 10 or 11, wherein the pad layer is a first pad layer, and the microelectronic assembly further comprising: a second pad layer between the first pad layer and the interconnect layer, wherein the second pad layer comprises a third pad and a fourth pad, wherein the third pad is coupled to the first pad and is offset from the first pad by the first dimension in the first direction, and wherein the fourth pad is coupled to the second pad and is offset from the second pad by the second dimension in the first direction.The microelectronic assembly of claim 10, 11 or 12, wherein the pad layer is a first pad layer, and the microelectronic assembly further comprising: a second pad layer between the interconnect layer and the third die, wherein the second pad layer comprises a third pad and a fourth pad, wherein the third pad is coupled to the third conductive contact and the third conductive contact is offset from the third pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the fourth conductive contact and the fourth conductive contact is offset from the fourth pad in the first direction by the second dimension.The microelectronic assembly of any of claims 10-13, wherein the first direction is a first rotational direction.The microelectronic assembly of any of claims 10-14, wherein the first pad is further offset from the first conductive contact in a second direction different from the first direction.The microelectronic assembly of claim 15, wherein the first pad is offset from the first conductive contact in the second direction by a third dimension different from the first dimension and the second dimension.The microelectronic assembly of any of claims 10-16, further comprising: an insulating material surrounding the first die, the second die, and the third die.A microelectronic assembly, comprising: a first layer comprising: a first die having a first conductive contact; a second die having a second conductive contact; and a pad layer on the first die and the second die, wherein the pad layer comprises a first pad and a second pad, wherein the first pad is coupled to the first conductive contact and is offset from the first conductive contact by a first dimension in a first direction, and wherein the second pad is coupled to the second conductive contact and is offset from the second conductive contact by a second dimension in a second direction, wherein the second direction is different from the first direction and the second dimension is different from the first dimension; and a second layer comprising a third die having a third conductive contact and a fourth conductive contact, wherein: the first layer is coupled to the second layer through a bonding layer having metal-to-metal bonds and fusion bonds; the first conductive contact is coupled to the third conductive contact through the first pad and one or more of the metal-to-metal bonds; and the second conductive contact is coupled to the fourth conductive contact through the second pad and one or more of the metal-to-metal bonds.The microelectronic assembly of claim 18, wherein a distance of adjacent metal-to-metal bonds is between 50 nanometers and 10 micrometers.The microelectronic assembly of claim 18 or 19, further comprising: a first via between and coupled to the first conductive contact and the first pad; and a second via between and coupled to the second conductive contact and the second pad.The microelectronic assembly of claim 18, 19 or 20, further comprising: a first conductive trace between and coupled to the first conductive contact and the first pad; and a second conductive trace between and coupled to the second conductive contact and the second pad.The microelectronic assembly of any of claims 18-21, wherein the pad layer is a first pad layer, and the microelectronic assembly further comprising: a second pad layer between the first pad layer and the interconnect layer, wherein the second pad layer comprises a third pad and a fourth pad, wherein the third pad is coupled to the first pad and is offset from the first pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the second pad and is offset from the second pad in the second direction by the second dimension.The microelectronic assembly of any of claims 18-22, wherein the pad layer is a first pad layer, and the microelectronic assembly further comprising: a second pad layer between the interconnect layer and the third die, wherein the second pad layer comprises a third pad and a fourth pad, wherein the third pad is coupled to the third conductive contact and the third conductive contact is offset from the third pad in the first direction by the first dimension, and wherein the fourth pad is coupled to the fourth conductive contact and the fourth conductive contact is offset from the fourth pad in the first direction by the second dimension.The microelectronic assembly of any of claims 18-23, wherein the first die, the second die, and the third die have active surfaces and the active surfaces of the first die and the second die are opposite the active surface of the third die.The microelectronic assembly of any of claims 18-24, wherein the first die, the second die, and the third die have active surfaces and the active surfaces of the first die and the second die face the active surface of the third die.The microelectronic assembly of any of claims 18-25, wherein the first die, the second die, and the third die have back surfaces that are opposite active surfaces, and the back surfaces of the first die and the second die face the back surface of the third die.

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