IGBT method for operating an RC-IGBT circuit, comprising an IGBT

Abstract

The IGBT (1) comprises, on a single chip, an active region (1-2) configured to conduct a forward load current between a first load terminal (11) on a front side (110) of a semiconductor body (10) of the IGBT (1) and a second load terminal (12) on a rear side (120) of the semiconductor body (10). The active region (1-2) is divided into at least: a first IGBT region (1-21), of which at least 90% is configured to conduct the forward load current based on a first control signal (13-21); and a second IGBT region (1-22), of which at least 90% is configured to conduct the forward load current based on a second control signal (13-22). A first MOS channel conductance-to-area ratio is determined by a total channel width in the first IGBT region (1-21) divided by a total lateral area of ​​the first IGBT region (1-21).A second MOS channel conductance-to-area ratio is determined by dividing the total channel width in the second IGBT region (1-22) by the total lateral area of ​​the second IGBT region (1-22). The second MOS channel conductance-to-area ratio is less than 80% of the first MOS channel conductance-to-area ratio.

Description

TECHNICAL DESCRIPTIONThis description relates to embodiments of an IGBT, to embodiments of operating an IGBT, and to embodiments of a circuit comprising an IGBT.BACKGROUNDMany functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications including, but not limited to, switches in power supplies and power converters.A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region that is terminated by an edge of the chip.In the case of a controllable power semiconductor device, e.g. a transistor, the load current path may be controlled by means of an insulated electrode commonly referred to as gate electrode. For example, upon receiving a corresponding control signal, e.g. from a driver unit via a control terminal of the device, the control electrode may put the power semiconductor device in one of a forward conducting state and a forward blocking state.Further, some devices provide reverse load current capability. There, the active region of the semiconductor body is further configured to conduct a reverse load current along a reverse load current between the two load terminals of the device. For example, the RC (reverse current) IGBT is one representative of such devices. In an RC-IGBT, a single chip accommodates an IGBT structure and a diode structure. Compared to a diode and an IGBT on separate chips connected in antiparallel to each other, the RC-IGBT has some advantages, e.g. in terms of turn-on losses, reverse recovery losses and / or thermal behavior, but may also be more complex in control.Further, to more accurately affect the switching behavior of a transistor, two control signals or more than two control signals may be provided to control the transistor. For example, a dual-gate IGBT (or a dual-gate RC IGBT) is controlled based on two control signals.SUMMARYThe subject matter of the independent claims is presented. Features of embodiments are defined in the dependent claims.According to a first embodiment, an IGBT comprises, in a single chip, an active region configured to conduct a forward load current between a first load terminal at a front side of a semiconductor body of the IGBT and a second load terminal at a back side of the semiconductor body. The active region is divided into at least: a first IGBT region at least 90% of which is configured to conduct the forward load current based on a first control signal; a second IGBT region at least 90% of which is configured to conduct the forward load current based on a second control signal. A first MOS channel conductivity to area ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of the first IGBT region. A second MOS channel conductivity to area ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS channel conductivity to area ratio is less than 80% of the first MOS channel conductivity to area ratio.According to a second embodiment, an IGBT comprises, in a single chip, an active region configured to conduct a forward load current between a first load terminal at a front side of a semiconductor body of the IGBT and a second load terminal at a back side of the semiconductor body. The active region is divided into at least: a first IGBT region including first MOS channels having a first threshold voltage, at least 90% of the first IGBT region configured to conduct the forward load current based on a first control signal; and a second IGBT region including second MOS channels having a second threshold voltage that is at least 115% of the first threshold voltage, at least 90% of the second IGBT region configured to conduct the forward load current based on a second control signal.According to a further embodiment, a method for operating an IGBT according to the first embodiment or according to the second embodiment is presented. The method includes: controlling the first IGBT region based on the first control signal; and controlling the second IGBT region based on the second control signal.According to yet another embodiment, a circuit is presented. The circuit includes an IGBT according to the first embodiment or according to the second embodiment; and a MOSFET connected in parallel with the IGBT.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrating principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings: FIG. 1 schematically and exemplarily illustrates a portion of a horizontal projection of an IGBT according to one or more embodiments; FIG. 2 schematically and exemplarily illustrates a portion of a horizontal projection of an active region of an IGBT according to one or more embodiments; FIG. 3 schematically and exemplarily illustrates a portion of a vertical cross-section of an IGBT according to one or more embodiments; FIG. 4 schematically and exemplarily illustrates a portion of a vertical cross-section of a second IGBT region of an IGBT according to one or more embodiments; FIG. 5 schematically and exemplarily illustrates a portion of a vertical cross-section of a first IGBT region of an IGBT according to one or more embodiments; FIG. 6 schematically and exemplarily illustrates two variants of a portion of a perspective projection of a second IGBT region of an IGBT according to one or more embodiments; FIG. 7 schematically illustrates some examples of a method of operating an IGBT according to one or more embodiments; and FIG. 8 schematically and exemplarily illustrates transfer characteristics of a first IGBT region and a second IGBT region of an IGBT according to one or more embodiments; FIG. 9 schematically and exemplarily illustrates output characteristics of a first IGBT region and a second IGBT region of an IGBT during a turn-off operation according to one or more embodiments; and FIG. 10 schematically and exemplarily illustrates a circuit according to one or more embodiments.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology, such as "top," "bottom," "below," "front," "back," "back," "leading," "trailing," "above," etc., may be used with reference to the orientation of the figures being described. Since portions of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of illustration and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment may be used in or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present invention encompasses such modifications and variations. The examples are described using a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or fabrication steps have been designated by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, and the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / die / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extending direction Z is also referred to herein as "vertical direction Z".In this specification, n-doped is referred to as "first conductivity type", while p-doped is referred to as "second conductivity type". Alternatively, opposite doping relationships may be used such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.In the context of the present description, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe that there is a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, zones, sections or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a section or part of a semiconductor device, wherein "low-ohmic" can mean that the properties of the respective contact are substantially not influenced by the ohmic resistance. Further, in the context of the present description, the term "in contact" is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g., a transition between two elements in contact with each other may not include a further intermediate element or the like.Additionally, in the context of the present specification, unless otherwise indicated, the term "electrical isolation" is used in the context of its generally valid understanding and is thus intended to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically insulated from each other may still be coupled to each other, for example mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example in the case of a transition). To give an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, e.g. by means of an insulation, e.g. a dielectric.Specific embodiments described in this specification relate to, but are not limited to, an IGBT, e.g., a power semiconductor device, that can be used in a power converter or power supply. Thus, in one embodiment, such an IGBT may be configured to carry a load current to be supplied to a load or provided from a power source, respectively. For example, the IGBT may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, e.g. a monolithically integrated IGBT cell and / or derivatives thereof. Such diode / transistor cells may be integrated in a power semiconductor module. A plurality of such cells may form a cell array disposed in an active region of the power semiconductor device.The term "blocking state" of the IGBT may refer to conditions when the RC-IGBT is in a state configured to block a load current flow while an external voltage is applied. In particular, the IGBT may be configured to block a forward load current through the RC IGBT while applying a forward voltage bias. In comparison, the IGBT may be configured to conduct the forward load current in a "conducting state" of the IGBT while applying a forward voltage bias. A transition between the blocking state and the conductive state may be controlled by a control electrode or, in particular, a potential of the control electrode. The electrical characteristics can of course only be applicable within a predetermined operating range of the external voltage and the current density in the IGBT. The term "forward biased blocking state" may therefore refer to conditions where the IGBT is in the blocking state while a forward voltage bias is applied.The term "IGBT" as used in this specification is intended to describe an IGBT on a single chip with high voltage blocking and / or high current carrying capabilities. In other words, such an IGBT is intended for high current, typically in the amper range, e.g. up to several tens or hundreds of amperes, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g. up to at least 400 V or even more, e.g. up to at least 3 kV or even up to 10 kV or more, depending on the respective application.For example, the term "IGBT" as used in this specification is not directed to logic semiconductor devices used, e.g., to store data, compute data, and / or other types of semiconductor-based data processing.For example, the IGBT described below may be a single semiconductor chip having, e.g., a strip cell configuration (or a cell / needle cell configuration) and may be configured to be used as a power component in a low, medium and / or high voltage application.FIG. 1 schematically and exemplarily illustrates a portion of a horizontal projection of an IGBT 1 according to one or more embodiments. Additional reference is made below to the exemplary vertical cross-section illustrated in FIG. 3 and the more detailed illustration of an exemplary active region 1- 2 of FIG. 2.The IGBT 1 includes a semiconductor body 10 coupled to a first load terminal on a front side (also referred to as a first side) 110 and to a second load terminal 12 on a back side (also referred to as a second side) 120 opposite to the front side 110 with respect to the vertical direction Z. The semiconductor body 10 is part of a single chip comprising an active area 1- 2 configured to conduct a forward load current between the first load terminal 11 and the second load terminal 12. In an embodiment, the IGBT 1 may be configured as an RC-IGBT; in this case, the active region 1- 2 is configured to conduct both the forward load current and a reverse load current between the first load terminal 11 and the second load terminal 12.The vertical thickness d of the semiconductor body 10 may be defined as the distance between the front side 110 and the back side 120 along the vertical direction Z, e.g. measured at a horizontal center of the active area 1- 2.The IGBT 1 may have a vertical configuration according to which both the forward load current (and optionally, in the case of the RC-IGBT configuration, the reverse load current) flows substantially parallel to the vertical direction Z.For example, the first load terminal 11 may be a source (or emitter) terminal and the second load terminal 12 may be a drain (collector) terminal.The active region 1- 2 is surrounded by an edge termination region 1- 3 which is terminated by a chip edge 1- 4. Herein, the terms "active area" (sometimes also referred to as "cell array"), "edge termination area" and "chip edge" have the technical meanings typically associated therewith by the skilled person in the context of IGBTs and are therefore not explained in more detail.According to the embodiments disclosed herein, the active region 1- 2 of the IGBT 1 is divided into at least a first IGBT region 1- 21 and a second IGBT region 1- 22.For example, at least 90% of the first IGBT region 1- 21 is configured to conduct the forward load current based on a first control signal 13- 21. This proportion may even be greater than 90%, e.g. at least 95%, at least 98% or even 100%.For example, at least 90% of the second IGBT region 1- 22 is configured to conduct the forward load current based on a second control signal 13- 22. This proportion may even be greater than 90%, e.g. at least 95%, at least 98% or even 100%.As schematically illustrated in FIG. 2, the IGBT 1 may include a first control terminal 13-A and a second control terminal 13-B. In an embodiment, the first control terminal 13-A is electrically isolated from the second control terminal 13-B. The first control signal 13- 21 may be provided via the first control terminal 13- A, and the second control signal 13- 22 may be provided via the second control terminal 13- B. In contrast to the schematic illustration in FIG. 2, according to which the control terminals 13-A and 13-B are arranged in the IGBT regions 1- 21 and 1- 22, respectively, but e.g. the control terminals 13-A and 13-B may be arranged externally therefrom, e.g. in the edge termination region 1- 3 or at another location or at another part of the active region 1- 2. Ways of implementing an electrical connection between the control electrodes associated with the first control terminal 13-A and an electrical connection between the control electrodes associated with the second control terminal 13-B are known to those skilled in the art and therefore will not be explained herein.For example, the second control signal 13- 22 is independent of the first control signal 13- 21. For example, the second control signal 13- 22 may be at least temporarily different from the first control signal 13- 21. For example, the second control signal 13- 22 is generated separately from the first control signal 13- 21. Thereby, the control of the forward load current in the first IGBT region 1- 21 can be independent of the control of the forward load current in the second IGBT region 1- 22. That is, it is understood that in some embodiments, the second IGBT region 1- 22 may be controlled based on both the first control signal 13- 21 and the second control signal 13- 22.According to embodiments described herein, the first IGBT region 1- 21 may have a configuration different from a configuration of the second IGBT region 1- 22.For example:a first MOS channel conductivity to area ratio is determined by a total channel width in the first IGBT region 1- 21 and a total lateral area of the first IGBT region 1- 21; anda second MOS channel conductivity to area ratio is determined by a total channel width in the second IGBT region 1- 22 and a total lateral area of the second IGBT region 1- 22; andthe second MOS channel conductivity to area ratio is less than 80% of the first MOS channel conductivity to area ratio.The above conditions may apply when both the first control signal 13- 21 and the second control signal 13- 22 have a respective voltage value corresponding to the (nominal) ON state, i.e. the forward conduction state, of the IGBT 1. For example, the above conditions hold when both the first control signal 13- 21 and the second control signal 13- 22 have a value of, for example, +15 V or +8 V or the like.That is, the second MOS channel conductivity to area ratio may be different from the first MOS channel conductivity to area ratio. For example, the second MOS channel conductivity to area ratio is less than 80% of the first MOS channel conductivity to area ratio or even less than 60% of the first MOS channel conductivity to area ratio.In addition or alternatively to the example explained in the preceding two paragraphs, the following may apply:the first IGBT region 1-21 includes first MOS channels having a first threshold voltage; andthe second IGBT region 1-22 includes second MOS channels having a second threshold voltage that is at least 115% of the first threshold voltage.Accordingly, the second threshold voltage present in the second IGBT region 1- 22 may be greater than the first threshold voltage present in the first IGBT region 1- 21. For example, the second threshold voltage is at least 120% of the first threshold voltage or even more than 130% of the first threshold voltageBased on the different configurations of the two IGBT regions 1- 21 and 1- 22 and based on the two control signals 13- 21 and 13- 22, advantageous switching behavior can be achieved, along with improved device robustness. For example, the second IGBT region 1- 22 is configured to temporarily conduct at most three times the nominal forward load current of the IGBT while the second control signal 13- 22 corresponds to a nominal ON state of the IGBT 1 and while the first control signal 13- 21 transitions to or corresponds to an OFF state of the IGBT 1. That is, while the first IGBT region 1- 21 is turned off to block the flow of the forward load current in the first IGBT region 1- 21, the entire device forward load current may be temporarily conducted only through the second IGBT region 1- 22, which may be turned off after the first IGBT region 1- 21 is turned off, even in the case of an overload current that is three times the nominal forward load current of the IGBT. For example, this may reduce the total amount of charge carriers stored in the IGBT 1 before the current is finally turned off. As a result, the turn-off losses are reduced.For example, another possible difference in the configurations of the two IGBT regions 1- 21 and 1- 22 may be achieved based on a body region 102 (see FIG. 3 ). For example, the body region 102 extends in both the first IGBT region 1- 21 and the second IGBT region 1- 22, wherein an average dopant dose of the body region of the second IGBT region is at least 120% of the dopant dose of the body region of the first IGBT region. The difference may be even more significant; e.g. the average dopant dose of the body region of the second IGBT region is at least 140% of the dopant dose of the body region of the first IGBT region. For example, the above-described first and second MOS channels may be induced within the body region 102 based on the first control signal 13- 21 and the second control signal 13- 22. Such a difference in body dose may also result in a corresponding difference in threshold voltages in the IGBT regions 1- 21 and 1- 22, as exemplarily described above.Increasing the dopant concentration of the body region 102 in the second IGBT region 1- 22 compared to the first IGBT region 1- 21 may decrease the resistance for the holes (charge carriers) in the body region 102 of the second IGBT region 1- 22, which may result in increased latch-up robustness and an improved ability to temporarily conduct an overload current in the second IGBT region 1- 22. A portion of the second IGBT region 1- 22 may include the same body dopant as in the first IGBT region 1- 21. However, the source region 101 is placed within the higher doped p-body portion. Also in the first IGBT region 1- 21, the dopant concentration of the body region 102 may be locally increased to achieve such an increased latch-up robustness. For the structured p-body dose in the first IGBT region 1- 21, one may have different threshold voltages if n-source regions 101 are located in both parts. There may be a larger area of 1-21 with lower p-body dose and another large area with higher p-body dose. In the case of overcurrent shut-off with re-turning on of the G1 voltage [later in Abs. 121] there is a certain voltage window in which only the part with lower p-body dose turns on.It is understood that the first IGBT region 1- 21 and the second IGBT region 1- 22 form a main portion of the active region 1- 2. For example, the sum of the first IGBT region 1- 21 and the second IGBT region 1- 22 is at least 80%, at least 90%, or even more than 95% of the active region 1- 2. Further, each of the first IGBT region 1- 21 and the second IGBT region 1- 22 may be at least 30% of the active region 1- 2.The first IGBT region 1- 21 may be larger than the second IGBT region 1- 22. For example, the first IGBT region 1- 21 is at least twice as large as the second IGBT region 1- 22.According to an example, the first IGBT region 1- 21 is configured to be controlled based only on a first control signal 13- 21, and the second IGBT region 1- 22 is configured to be controlled based on the second control signal 13- 22. Optionally, the second IGBT region 1- 22 may be configured to be controlled based on the first and second control signals 13- 21, 13- 22. The forward saturation current of the second IGBT region 1- 22 may be limited by the chip design in this example. For example, a saturation current of the forward load current of the IGBT 1 with only the second IGBT region 1- 22 in a forward conducting state may be at most three times or even at most twice a rated value for the forward load current of the IGBT 1 with both IGBT regions 1- 21 and 1- 22 in a forward conducting state. In other words, a saturation current of the forward load current of the IGBT 1, wherein only the second control signal 13- 22 is in a forward conducting state, may be at most three times or even at most twice a rated value for the forward load current of the IGBT 1. Alternatively or additionally, the forward saturation current of the second IGBT region 1- 22 (wherein only the second control signal 13- 22 is in a conductive state) may be limited to a smaller value than the first IGBT region 1- 21 (wherein the first control signal 13- 21 is in a conductive state) by the chip design. For example, the proportion of the forward saturation current of the second IGBT region 1- 22 (wherein only the second control signal 13- 22 is in a conducting state) may be at least 10% smaller, or even at least 20% smaller, than the proportion of the second IGBT region 1- 22 in the entire active IGBT area of the IGBT 1.As will be explained further below, based on the first and second control signals 13- 21 and 13- 22, the first IGBT region 1- 21 and the second IGBT region 1- 22 may be switched asynchronously. For example, the second IGBT region 1- 22 may be turned on with a certain time delay before or after the first IGBT region 1- 21 is turned on. In addition, the second IGBT region 1- 22 may be turned off with a certain time delay after the first IGBT region 1- 21 is turned on. This case could be problematic up to now, since the second IGBT region 1- 22 may be comparatively small, a current density may increase above a critical level, since all or almost all of the load current needs to be temporarily conducted through the second IGBT region 1- 22 when the first IGBT region 1- 21 is turned off before turning off the second IGBT region 1- 22.To this end, it is proposed here to design the second IGBT region 1- 22 to have a high robustness, e.g. by limiting the second MOS channel conductivity to area ratio, as explained above by way of example. There are many ways to limit the second MOS channel conductivity to area ratio, some of which are described below, such as corresponding configurations of at least one of a source region, a body region, and a trench mesa pattern in the second IGBT region 1- 22.Each of the first IGBT region 1- 21 and the second IGBT region 1- 22 may have a total lateral extension of at least 60% of the vertical thickness d of the semiconductor body 10. One or both of these total lateral extents may even be greater, such as at least 100%, 150% or even more than 200% of the vertical thickness d of the semiconductor body 10.The first IGBT region 1- 21 is spatially separated from the second IGBT region 1- 22; e.g., there is no spatial overlap between the first IGBT region 1- 21 and the second IGBT region 1- 22. The first IGBT region 1- 21 may be a (single) first contiguous region and the second IGBT region 1- 22 may be a (single) second contiguous region. In other embodiments, the first IGBT region 1- 21 is divided into two or more spatially distributed first sub-regions and the second IGBT region 1- 22 is divided into two or more spatially distributed second sub-regions. Even in the latter case, there is no lateral overlap between the first portions forming the first IGBT region 1- 21 and the second portions forming the second IGBT region 1- 22.In addition to the first IGBT region 1- 21 and the second IGBT region 1- 22, the active region 1- 2 may optionally include a diode-only region 1- 23, e.g., when the IGBT 1 is configured as an RC-IGBT, which is explained in more detail below.If provided, the diode-only region 1- 23 may be smaller than each of the first IGBT region 1- 21 and the second IGBT region 1- 22. The diode-only region 1- 23 may have a lateral total extension of at least 40% of the vertical thickness d of the semiconductor body 10. For example, at least 90% of the optional diode-only region 1- 23 is configured to conduct only the reverse load current (but not the forward load current, for example). In an embodiment, the diode-only region 1- 23 is not exposed to the first control signal 13- 21 or the second control signal 13- 22. For example, the diode-only region 1- 23 does not include a control trench. Furthermore, it can be provided that the diode-only region 1- 23 does not comprise a semiconductor source region 101 which is electrically connected to the first load terminal 11.It is understood that the arrangement of the first IGBT region 1- 21, the second IGBT region 1- 22, and the optional diode-only region 1- 23 as illustrated in FIG. 2 is exemplary only. For example, the regions 1- 21, 1- 22, and 1- 23 need not necessarily be contiguous regions, but could also be formed by spatially distributed sub-regions, as explained above. Instead of being centrally arranged, the first IGBT region 1- 21 could alternatively or additionally be arranged in circumferential portions of the active region 1- 2. For example, the regions 1- 21, 1- 22 and (optionally) 1- 23 may have a respective rectangular lateral perimeter and may be arranged according to a stripe pattern in the active region 1- 2. The latter variant could facilitate the provision of the control signals to the areas 1-21 and 1-22.Thus, the skilled person can dimension and arrange the three regions 1- 21, 1- 22, and 1- 23 within the active region 1- 2 according to the designated characteristics of the IGBT 1 and other circumstances.Further, the phrase "at least 90%" used in the context of describing these ranges is intended to express that the main purpose of the ranges is to conduct either only the forward load current (in the case of the first IGBT range 1- 21) or only the reverse load current (in the case of the optional diode-only range 1- 23), or, for example, both the forward load current and the reverse load current (in the case of a particular configuration of the second IGBT range 1- 22).In one embodiment, the properties of the regions may vary in respective smaller subsections of 10% or less of the regions, e.g., in a transition region where one of the regions 1-21, 1-22, and 1-23 is adjacent to another of these regions. Such transitions are described in more detail below.Reference is now made in more detail to FIG. 3, which illustrates a portion of a vertical cross-section of an exemplary embodiment of the active region 1- 2 that includes the first IGBT region 1- 21, the second IGBT region 1- 22, and the diode-only region 1- 23. It is again emphasized that the diode-only region 1-23 is optional. In other embodiments, no diode-only region 1-23 is provided.As illustrated, the active region 1- 2 has a vertical configuration, wherein the first load terminal 11 is disposed at the semiconductor body front side 110 and the second load terminal 12 is disposed at the semiconductor body rear side 120. The first load terminal 11 and the second load terminal 12 may be shared by each of the first IGBT region 1- 21, the second IGBT region 1- 22, and the diode-only region 1- 23.A drift region 100 of the first conductivity type may form the main central portion of the semiconductor body 10 with respect to the vertical direction Z. This drift region 100 may be shared by each of the first IGBT region 1- 21, the second IGBT region 1- 22, and (if present) the diode-only region 1- 23.The active region 1- 2 may be configured at both the front side 110 and the back side 120 according to the distribution of the first IGBT region 1- 21, the second IGBT region 1- 22, and (if present) the diode-only region 1- 23.For example, with respect to the back side 120, in electrical connection with the second load terminal 12, a back side emitter 108 is arranged coupled to the drift region 100, wherein the back side emitter 108 is configured according to the separation of the active region 1- 2 into at least the first IGBT region 1- 21, the second IGBT region 1- 22 and (if present) the diode-only region 1- 23.The illustrated exemplary IGBT 1 has an RC-IGBT configuration. In such a case, the following may apply:the first IGBT region 1-21 has an IGBT-only configuration for conducting only the forward load current; andthe second IGBT region 1- 22 has an RC IGBT configuration for conducting both the forward load current and a reverse load current; and optionally whereinthe diode-only region 1-23 has a diode-only configuration for conducting only the reverse load current.Accordingly, the ability to conduct a reverse load current is established by the second IGBT region 1- 22 and the optional diode-only region 1- 23. In one embodiment, the backside emitter 108 may reflect this configuration and may include:a first second conductivity type portion 108-21 in an active region 1-2 portion where the first IGBT region 1-21 (IGBT only region 1-21) is present;a second portion 108-22 comprising both first sub-portions 108-221 of the first conductivity type and second sub-portions 108-222 of the second conductivity type in a portion of the active region 1-2 where the second IGBT region 1-22 (RC-IGBT region 1-22) is present;and optionally, when the diode-only region 1- 23 is implemented, a third portion 108- 23 of the first conductivity type in a portion of the active region 1- 2 where the diode-only region 1- 23 is present.For example, the first portion 108- 21 of the back side emitter 108 is only of the second conductivity type. That is, in one embodiment, the first portion 108- 21 does not include portions of the first conductivity type.Further, the first portion 108- 21 of the back side emitter 108 may have an average dopant dose of at least 5×10 12 cm -2 with respect to its horizontal surface. This average dopant dose may even be larger, e.g. at least 1*10 13 cm -2 or 1*10 14 cm -2. That is, in an embodiment, the first portion 108- 21 of the back side emitter 108 may include a variation of the dopant concentration and / or dopant dose along at least one of the first lateral direction X and the second lateral direction Y.Referring now to the second portion 108- 22 of the back side emitter 108, in an embodiment where the second IGBT region 1- 22 has an RC IGBT configuration, each of the first sub-portions 108- 221 of the second portion 108- 22 of the back side emitter 108 has an average dopant dose of at least 1*10 14 cm -2 with respect to its horizontal surface. This average dopant dose may be even larger, e.g. at least 5*10 14 cm -2 or 1*10 15 cm -2.In another embodiment, where the second IGBT region 1- 22 has a regular IGBT configuration (i.e., no RC IGBT), the second portion 108- 22 of the back side emitter 108 may be configured the same as the first portion 108- 21 in thickness and dopant concentration. However, for lower turn-off losses, it may be advantageous to provide the second portion 108- 22 of the back side emitter 108 with a lower average dopant dose than the average dopant dose of the first portion 108- 21 of the back side emitter 108. For such a structure, it may be advantageous to extend the second portion 108- 22 to the low range. IGBT region 1-21 such that the overlap between 108-22 and 1-21 is in the range between 0.3 and 3 times d, e.g. between 0.5 and 1 times d.Further, each of the first sub-portions 108- 221 may be offset from the diode-only region 1- 23 by a second distance d 2 of at least 20% of the thickness d of the semiconductor body 10. For example, it may be ensured based on the second distance d 2 that the influence of both the first control signal 13- 21 and the second control signal 13- 22 on the diode-only region 1- 23 is small.If the diode-only region 1- 23 is provided, the third portion 108- 23 of the back side emitter region 108 may be a region of only the first conductivity type. In another embodiment, the third portion 108- 23 may include sub-portions (not illustrated) of the second conductivity type that are also electrically connected to the second load terminal, e.g., "p-shorts" similar to the "n-shorts" / first sub-portions 108- 221 of the first conductivity type in the second portion 108- 22 of the back side emitter 108.In an embodiment, the IGBT 1 further comprises a field stop region 107 of the first conductivity type coupled to both the drift region 100 and the back side emitter 108. The dopant concentration of the field stop region 107 may be greater than the dopant concentration of the drift region 100. For example, the dopant concentration of the field stop region 107 is at least ten times the dopant concentration of the drift region 100.As illustrated, the thicknesses of the first portion 108- 21, the second portion 108- 22, and, if implemented, the third portion 108- 23 of the back side emitter 108 may vary. For example, the third portion 108- 23 of the back emitter 108 in the optional diode-only region 1- 23 may be thinner than the remaining portions 108- 21 and 108- 22 of the back emitter 108. There, the field stop region 107 may be thicker compared to its remaining portion laterally overlapping the portions 108- 21 and 108- 22 of the back side emitter 108. The configuration of the back side emitter 108 and the field stop layer 107 in the optional diode-only region 1- 23 may extend into the second IGBT region 1- 22 along a path corresponding to the distance d 2, as illustrated.As stated above, the configuration of the active region 1- 2 may also reflect, at the front side 110, the separation of the active region 1- 2 into the at least first IGBT region 1- 21, the second IGBT region 1- 22, and, if implemented, the diode-only region 1- 23.For example, the RC-IGBT 1 further comprises, between the first load terminal 11 and the drift region 100, a trench mesa pattern, wherein the trench mesa pattern is configured according to the separation of the active region 1- 2 into at least the first IGBT region 1- 21, the second IGBT region 1- 22, and, if implemented, the diode-only region 1- 23. This is described in more detail below:An exemplary configuration of the trench mesa pattern at the front side 110 is illustrated in FIG. 3. The illustrated trench mesa pattern includes first control trenches 14- 21 configured to receive the first control signal 13- 21 and second control trenches 14- 22 configured to receive the second control signal 13- 22. In terms of structure, the first control trenches 14- 21 and the second control trenches 14- 22 may be configured the same.These control trenches 14- 21 and 14- 22 are exemplarily illustrated in FIGS. 4 and 5. For example, each second control trench 14- 22 includes a second control trench electrode 141- 22 configured to receive the second control signal 13- 22 (gate 2). The second control trench electrode 141- 22 is insulated from the semiconductor body 10 based on the second control trench insulator 142- 22. As the second control trench 14- 22, each first control trench 14- 21 may include a first control trench electrode 141- 21 configured to receive the first control signal 13- 21 (gate 1). The first control trench electrode 141- 21 is insulated from the semiconductor body 10 based on the first control trench insulator 142- 21.For example, each first control trench electrode 141- 21 is electrically connected to the first control terminal 13-A. Similarly, each second control trench electrode 141- 22 may be electrically connected to the second control terminal 13-B.For example, the first IGBT region 1- 21 comprises a plurality of the first control trenches 14- 21, but optionally none of the second control trenches 14- 22. That is, in an embodiment, the first IGBT region 1- 21 is controlled exclusively based on the first control trenches 14- 21, since neither of the second control trenches 14- 22 is present in the first IGBT region 1- 21.Further, the second IGBT region 1- 22 may include a plurality of the second control trenches 14- 22, but optionally none of the first control trenches 14- 21. That is, in an embodiment, the second IGBT region 1- 22 is controlled exclusively based on the second control trenches 14- 22, since neither of the first control trenches 14- 21 is present in the RC-IGBT region 1- 22. In another embodiment, a subset of the first control trenches 14- 21 is arranged in the second IGBT region 1- 22; then, the second IGBT region 1- 22 may be controlled based on both the first control signal 13- 21 and the second control signal 13- 22. According to an embodiment, the source regions 101 are placed only next to 14- 22. In another embodiment, source regions 101 are present adjacent to both the second control trenches 14- 22 and the first control trenches 14- 21.In an embodiment, the trench mesa pattern further comprises source trenches 16 electrically connected to the first load terminal 11 and arranged at least in the first IGBT region 1- 21. For example, referring to FIG. 5, each source trench 16 may include a source trench electrode 161 electrically connected to the first load terminal 11. The source trench electrode 161 is insulated from the semiconductor body 10 based on the source trench insulator 162.In an embodiment, a subset of the source trenches 16 may also be arranged in the second IGBT region 1- 22 and, if implemented, in the diode-only region 1- 23.In another embodiment, as illustrated in FIG. 3, the second IGBT region 1- 22 does not include a source trench 16.For example, the diode-only region 1- 23 comprises only source trenches 16, but no control trenches.For example, in contrast to the illustration in FIG. 3, in the second IGBT region 1- 22, the first and second control trenches 14- 21 / 14- 22 may be alternately arranged along the first lateral direction X, and one or more source trenches 16 are arranged between each pair of control trenches 14- 21 / 14- 22.In the first IGBT region 1- 21, for example, one, two or more source trenches 16 may be arranged between each two adjacent first control trenches 14- 21.Referring also to FIGS. 4 and 5, in an embodiment, the trench mesa pattern further includes mesas 17 of the first type arranged in both the first IGBT region 1- 21 and the second IGBT region 1- 22. Each first type mesa 17 includes a source region 101 of the first conductivity type and a portion of the body region 102 of the second conductivity type. For clarity of illustration, only some of the source regions 101 present in the second IGBT region 1- 22 are provided with a respective reference sign. Each bold small square represents a source region 101. Further, each illustrated trench in the RC IGBT region 1- 22 represents one of the pluralities of first control trenches 14- 21, second control trenches 14- 22, and source trenches 16, each of the second control trenches 14- 22 being disposed adjacent to one of the first type mesas 17 in the second IGBT region 1- 22.In each first type mesa 17, both the source region 101 and the body region 102 are electrically connected to the first load terminal 11. For example, a first contact plug 111 may be used for this purpose. At least the body region 102 isolates the source region 101 from the drift region 100.In the first IGBT region 1- 21, each first type mesa 17 is disposed adjacent to at least one of the first control trenches 14- 21. There, each first control trench 14- 21 is configured to induce a conductive channel (i.e. one of the first MOS channels) in the adjacent first type mesa 17 for conducting the forward load current in response to receiving a corresponding configuration of the first control signal 13- 21. Such induction of a conductive channel is well known to those skilled in the art and, accordingly, will not be discussed in greater detail herein.In the second IGBT region 1- 22, each first type mesa 17 is arranged adjacent to at least one of the second control trenches 14- 22 or, if present in the second IGBT region 1- 22, the first control trenches 14- 21. There, each first / second control trench 14- 21 / 14- 22 is configured to induce a conductive channel (i.e., one of the second MOS channels) in the adjacent first type mesa 17 for conducting the forward load current in response to receiving a corresponding configuration of the first / second control signal 13- 22 / 13- 211. As indicated above, such induction of a conductive channel is well known to those skilled in the art and, accordingly, will not be discussed in greater detail herein.If first control trenches 14- 21 are provided in the second IGBT region 1- 22, the number of second control trenches 14- 22 present in the second IGBT region 1- 22 may be at least 40% of the number of first control trenches 14- 21 present in the second IGBT region 1- 22. For example, in the second IGBT region 1- 22, the first control trenches 14- 21 and the second control trenches 14- 22 are arranged alternately with respect to a first lateral direction X. For example, between each pair of control trenches 14- 21 / 14- 22, a number of (zero, one, or more than one) source trenches 16 is arranged.For example, at least in the first IGBT region 1- 21 and optionally in the second IGBT region 1- 22, the trench mesa pattern may further comprise second type mesas 18 that are not equipped with a source region 101 and that may or may not be electrically connected to the first load terminal 11. Furthermore, additional trench types may be provided, such as floating trenches (the trench electrodes of which are not electrically connected to a defined potential) or further control trenches. In another embodiment, each mesa in the first IGBT region 1- 21 is a first type mesa 17.For example, in the optionally provided diode-only region 1- 23, only source trenches 16 but no control trenches are provided. These source trenches 16 can laterally delimit diode mesas 19 in the diode-only region 1- 23, wherein the body region 102 is electrically connected to the first load terminal 11 there. The diode mesas 19 are laterally bounded by the source trenches 16.The trench mesa pattern illustrated in FIG. 3 is an example. In another embodiment, different trench mesa patterns may be provided therefrom.Here, it is understood that the configurations of the front side 110 and the back side 120, i.e., the trench mesa pattern at the front side 110 and the back side emitter 108 at the back side 120, may be aligned with each other according to the separation of the active region 1- 2 into the second IGBT region 1- 22, the first IGBT region 1- 21, and the optional diode-only region 1- 23.That is, in one embodimentthe above-explained trench mesa configuration in the first IGBT region 1- 21 laterally overlaps the above-explained configuration of the first section 108- 21 of the rear-side emitter 108 in the first IGBT region 1- 21;the trench mesa configuration explained above in the second IGBT region 1- 22 laterally overlaps the configuration explained above of the second section 108- 22 of the rear-side emitter 108 in the second IGBT region 1- 22; andthe above-explained trench mesa configuration in the diode-only region 1- 23 overlaps laterally with the above-explained configuration of the third section 108- 23 of the rear-side emitter 108 in the diode-only region 1- 23.In an embodiment, the IGBT 1 further comprises a barrier region 105 of the first conductivity type that couples the trench mesa pattern in the first IGBT region 1- 21 to the drift region 100. For example, the dopant concentration of the barrier region 105 is greater than the dopant concentration of the drift region 100.For example, as illustrated in FIG. 3, the barrier region 105 is provided only in the first IGBT region 1- 21, but is not provided in either the second IGBT region 1- 22 or the optional diode-only region 1- 23.Based on the exemplary design described above, the first IGBT region 1- 21 may form a low saturation IGBT controlled based on the first control signal 13- 21 (gate 1), and the second IGBT region 1- 22 may form a reverse conductivity (RC) and diode control (DC) RCDC IGBT region controlled based on the second control signal 13- 22 (gate 2) and optionally also based on the first control signal 13- 21 (gate 1).FIG. 4 illustrates a more detailed example of a portion of the second IGBT region 1- 22. Accordingly, a first type mesa 17 is disposed between two of the second control trenches 14- 22. A respective source region 101 is provided adjacent to each of the second control trenches 14- 22, such that each of the two second control trenches 14- 22 may induce a respective second MOS channel in the first type mesa 17. However, in another embodiment, only one source region 101 (e.g., arranged to only one control trench) is provided in the first type mesa 17 in the second IGBT region 1- 22, e.g., to ensure that the second MOS channel conductivity to area ratio in the second IGBT region 1- 22 is less than 80% of the first MOS channel conductivity to area ratio in the first IGBT region 1- 21.FIG. 5 illustrates a more detailed example of a portion of the first IGBT region 1- 21. There, the first type mesa 17 is laterally flanked, for example, by only one of the first control trenches 14- 21. The other trench laterally delimiting the first type mesa 17 may be, for example, one of the source trenches 16. Thus, in each first type mesa 17, the source region 101 is laterally adjacent to only the first control trench 14- 21. Accordingly, instead of two first MOS channels in the first type mesa, there is only one first MOS channel per first type mesa 17 in the first IGBT region 1-21. There too, two second type mesas 18 or one of the second type mesas 18 and one of the first type mesas 17 may be arranged adjacent to each source trench 16. In another embodiment, two source regions are provided in the first type mesa 17 in the first IGBT region 1- 21 (or a source region 101 each extending along the entire width of the first type mesa 17), e.g., to ensure that the second MOS channel conductivity to area ratio in the second IGBT region 1- 22 is less than 80% of the first MOS channel conductivity to area ratio in the first IGBT region 1- 21.As illustrated in FIG. 6, the first type mesas 17 may be electrically contacted based on a contact plug 111 (cf. variant (2)) extending below the first surface 110 and adjoining an isolation region 191. Alternatively, a planar contact 112 can be used, ending approximately at the surface 120 (cf. variant (1)).Regardless of the manner of electrically contacting the first type mesas 17, the first type mesas 17 in the second IGBT region 1- 22 may be configured to split the active channel into a plurality of second MOS channels that are comparatively small in width. Such a configuration, which may be achieved, for example, as illustrated in FIG. 6, based on a corresponding lateral structure of the source regions 101 in each first type mesa 17, is a further possibility to restrict the second MOS channel conductivity to area ratio in the second IGBT region 1- 22 to a certain value. Further, similar to the possible increased dopant concentration of the body region 102 in the first type mesas 17 of the second IGBT region 1- 22, the division of the active channel into the plurality of small widths and second MOS channels spatially separated along the second lateral direction Y may also result in an increased latch-up robustness of the second IGBT region 1- 22.The illustration in FIG. 6 is only exemplary. The source region 101 could be laterally structured in various ways, for example. For example, the source regions 101 are provided only on one side of the first type mesa 17 (e.g. on the left side of the contact plug or on the right side of the contact plug), or the source regions 101 could be arranged on the left and right sides alternately along the second lateral direction Y.According to a further embodiment, in the second IGBT region 1- 22, the body region 102 in one or more of the first type mesas 17 comprises a variation of the dopant concentration along the second lateral extension of the respective first type mesa 17. For example, the source regions 101 in the respective first type mesa 17 laterally overlap with those portions of the body region 102 having a comparatively high dopant concentration. For example, based on such a configuration of the body region 102, the load current dependence of the anode efficiency during the reverse load current conduction may be adjusted.The above-described differences between the first IGBT region 1- 21 and the second IGBT region 1- 22 may be achieved, for example, if it is provided that the percentage area occupied by the source region 101 in the first IGBT region 1- 21 is greater than the percentage area occupied by the source region 101 in the second IGBT region 1- 22.Due to its difference in configuration, the second region 1- 22 may have a transmission characteristic and an output characteristic different from the transmission and output characteristics of the first IGBT region 1- 21. This aspect is exemplified in FIGS. 8 to 10.In FIG. 8, the horizontal axis indicates the voltage V GE of the first and second control signals (which are identical in the illustrated example), and in FIGS. 9 and 10, the respective horizontal axis indicates the voltage V CE across the first load terminal 11 and the second load terminal 12. In each of FIGS. 8 to 10, the vertical axis indicates the forward load current I C.In FIG. 8, the IGBT 1 is forward biased, i.e., the voltage V CE across the first load terminal 11 and the second load terminal 12 is positive to allow the forward load current I C to flow. In FIGS. 9 and 10, each of the first control signal 13- 21 (gate 1) and the second control signal 13- 22 (gate 2) has a configuration corresponding to an ON state of the RC-IGBT 1.According to the illustrated examples, as can be derived from FIG. 8, the second MOS channels in the second IGBT region 1- 22 have the second threshold voltage, which is at least 115% of the first threshold voltage of the first MOS channels in the first IGBT region 1- 21. That is, at equal voltage levels of the first and second control signals 13- 21 and 13- 22, the fraction of the forward load current in the second IGBT region 1- 22 is smaller than the fraction of the forward load current in the first IGBT region 1- 21. Further, the second IGBT region 1- 22 may be arranged such that for a value of only the second control signal 13- 22 corresponding to an ON state (while the first control signal 13- 21 corresponds to an OFF state), the forward load current is at most 300% or only at most 200% of the nominal load current (I max_nom) or even smaller than the nominal load current (I max_nom) of the complete IGBT 1. In contrast, under corresponding conditions, the forward load current in the first IGBT region 1- 21 would be much larger, e.g. at a level corresponding to an overload situation (I th_overload).a unit cell) of the trench mesa pattern in the first IGBT region 1- 21 is identical to a pitch of the trench mesa pattern in the second IGBT region 1- 22; and / ora mesa width in the trench mesa pattern in the first IGBT region 1- 21 is identical to a mesa width in the trench mesa pattern in the second IGBT region 1- 22; and / ora trench width in the trench mesa pattern in the first IGBT region 1- 21 is identical to a trench width in the trench mesa pattern in the second IGBT region 1- 22.For example, the geometric dimensions relating to the mesas 17 and 18 and the trenches 14- 21, 14- 22, and 17 in the first IGBT region 1- 21 may be identical to the corresponding geometric dimensions in the second IGBT region 1- 22.Here, a method for operating an IGBT 1 according to one of the preceding embodiments is also presented. The method includes controlling the IGBT 1 based on the first control signal 13- 21 (gate 1) and the second control signal 13- 22 (gate 2).Some examples (1) to (3) of such a method are illustrated in Fig. 7, to which reference is now made. In each example, the first control signal 13- 21 is illustrated with a continuous path denoted by V G1 (i.e., voltage of the first control signal 13- 21 (gate 1)), and the second control signal 13- 22 is illustrated with a dashed path denoted by V G2 (i.e., voltage of the second control signal 13- 22 (gate 2)).As usual, the first control signal 13-21 may be generated by providing a voltage between the first control terminal 13-A and the first load terminal 11, wherein the first control terminal 13-A is electrically connected to the first control trench electrodes 141-21. Similarly, the second control signal 13- 22 may be generated by providing a voltage between the first load terminal 11 and the second control terminal 13- B and the first load terminal 11, wherein the second control terminal 13- B is electrically connected to the second control trench electrodes 141- 22.The voltage is indicated on the vertical axis, the horizontal axis indicates time in each example. A positive value V G_ON of the voltage (e.g., +15 V) corresponds to an ON state (forward conduction state) and a negative or zero voltage value V G_OFF( e.g., -8 V or -15 V) corresponds to an OFF state (forward blocking state) of the IGBT 1. While the voltage values V G_ON, V G_OFF, which correspond to these states, may be identical for both the first control signal 13- 21 and the second control signal 13- 22, the timings of changing the values from one to another to cause a switching operation may be different between the first control signal 13- 21 and the second control signal 13- 22.According to example (1), the second IGBT region 1- 22 is primarily used to improve the turn-off process. For example, the second IGBT region 1- 22 is turned on with a time delay t delay e.g., shortly before the first IGBT region 1- 21 is turned off. The second IGBT region 1- 22 remains in the ON state while the first IGBT region 1- 21 is turned off. As explained above, the load current is then temporarily conducted--completely or only partially--depending on the load current level--by the second IGBT region 1-22. The IGBT 1 is then de-saturated (see time period t desat), until it is completely turned off, based also on changing the second control signal 13-22 to the V G_OFF- value. Depending on the application, as illustrated in example (3), the delay t delay, with which the second IGBT region 1- 22 is turned on, may be reduced or even switched to a negative value, cf. example (2), which means that the second IGBT region 1- 22 is turned on before the first IGBT region 1- 21 is turned on. Examples (2) and (3) may be advantageous for a low ON state, but lead to higher turn-off losses. Example (2) may allow better control of the turn-on process. However, in each of the three examples, the second control signal 13- 22 is provided such that the second IGBT region 1- 22 is in the forward conduction state while the first IGBT region 1- 21 is switched to the forward blocking state based on the first control signal 13- 21; for example, the second IGBT region 1- 22 is turned off after the first IGBT region 1- 21 is turned off to allow the IGBT 1 to de-saturate.FIG. 10 schematically and exemplarily illustrates a circuit 1000 according to one or more embodiments. The circuit 1000 includes an IGBT 1 according to any of the above-described embodiments and a MOSFET 500 connected in parallel with the IGBT 1. For example, the first load terminal 11 of the IGBT 1 is electrically connected to a first load terminal 511 of the MOSFET 500, and the second load terminal 12 of the IGBT 1 is electrically connected to a second load terminal 512 of the MOSFET 500.In one example, the IGBT 1 has an RC-IGBT configuration, e.g., as exemplarily described above. Further, the MOSFET 500 may be based on a wide band gap semiconductor material. For example, the MOSFET 500 is a silicon carbide, SiC, MOSFET. However, the IGBT 1 may be based on silicon, Si. In general, instead of 500, a unipolar transistor may be placed, which could alternatively be a GaN HEMT as an alternative to a MOSEFT.The MOSFET 500 may be controlled based on the first control signal 13- 21. To this end, a control terminal 513 of the MOSFET 500 may be electrically connected to the first control terminal 13-A of the IGBT 1.The design of the circuit 500 as explained above includes the realization that in such an arrangement the switching losses can be mainly limited to the IGBT 1, in particular in the case of example (2) of the above described operating method. In the case of an RC-IGBT configuration of the IGBT 1, the RC functionality may also serve to take over a reverse current in an overload case.In the above, embodiments related to IGBTs and respective operation methods have been explained. For example, these IGBTs are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g. the semiconductor body and its regions / zones, e.g. regions etc., may be a monocrystalline Si region or a monocrystalline Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.However, it is to be understood that the semiconductor body and its regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), Aluminium gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP) and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are mainly used at present.Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, are used to facilitate the description to explain the positioning of an element relative to a second element. These terms are intended to include other orientations of the respective device in addition to the various orientations depicted in the respective figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. Like terms may refer to like elements throughout the specification.As used herein, the terms "comprising," "including," "including," "comprising," "having," and the like are open ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features.In view of the above range of variations and applications, it is to be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Rather, the present invention is to be limited only by the following claims and their legal equivalents.

Claims

IGBT (1) comprising, in a single chip, an active area (1-2) configured to conduct a forward load current between a first load terminal (11) at a front side (110) of a semiconductor body (10) of the IGBT (1) and a second load terminal (12) at a back side (120) of the semiconductor body (10), wherein the active area (1-2) is divided into at least: - a first IGBT area (1-21) at least 90% of which are configured to conduct the forward load current based on a first control signal (13-21); - a second IGBT area (1-22) at least 90% of which are configured to conduct the forward load current based on a second control signal (13-22); wherein: - a first MOS channel conductivity to area ratio is determined by a total channel width in the first IGBT region (1-21) divided by a total lateral area of the first IGBT region (1-21); and - a second MOS channel conductivity to area ratio is determined by a total channel width in the second IGBT region (1-22) divided by a total lateral area of the second IGBT region (1-22); and - the second MOS channel conductivity to area ratio is less than 80% of the first MOS channel conductivity to area ratio.IGBT (1) comprising, in a single chip, an active region (1-2) configured to conduct a forward load current between a first load terminal (11) at a front side (110) of a semiconductor body (10) of the IGBT (1) and a second load terminal (12) at a back side (120) of the semiconductor body (10), wherein the active region (1-2) is divided into at least: - a first IGBT region (1-21) including first MOS channels having a first threshold voltage, wherein at least 90% of the first IGBT region (1-21) is configured to conduct the forward load current based on a first control signal (13-21); a second IGBT region (1-22) including second MOS channels having a second threshold voltage that is at least 115% of the first threshold voltage, wherein at least 90% of the second IGBT region (1-22) is configured to conduct the forward load current based on a second control signal (13-22).IGBT (1) comprising, in a single chip, an active area (1-2) configured to conduct a forward load current between a first load terminal (11) at a front side (110) of a semiconductor body (10) of the IGBT (1) and a second load terminal (12) at a back side (120) of the semiconductor body (10), wherein the active area (1-2) is divided into at least: - a first IGBT area (1-21) at least 90% of which are configured to conduct the forward load current based only on a first control signal (13-21); and - a second IGBT region (1-22), at least 90% of which are configured to conduct the forward load current based on a second control signal (13-22), - wherein a saturation current of the forward load current, wherein only the second IGBT region (1-22) is in a forward conducting state, is at most three times (twice) a nominal value for the forward load current of the IGBT (1).The IGBT (1) according to one or more of the preceding claims, further comprising a body region (102) extending in both the first IGBT region (1-21) and the second IGBT region (1-22), wherein an average dopant dose of the body region in the second IGBT region (1-22) is at least 120% of the average dopant dose of the body region in the first IGBT region (1-21).The IGBT (1) according to one or more of the preceding claims, wherein the second IGBT region (1-22) is configured to conduct temporarily, while the second control signal (13-22) corresponds to a nominal ON state of the IGBT (1) and while the first control signal (13-21) transitions to or corresponds to an OFF state of the IGBT (1), at most three times the nominal forward load current of the IGBT.The IGBT (1) according to one or more of the preceding claims, wherein the second control signal (13-22) is independent of the first control signal (13-21).The IGBT (1) according to one or more of the preceding claims, wherein at least one of the following applies: - the sum of the first IGBT region (1-21) and the second IGBT region (1-22) is at least 80% of the active region (1-2); - each of the first IGBT region (1-21) and the second IGBT region (1-22) is at least 30% of the active region (1-2).The IGBT (1) according to one or more of the preceding claims, wherein the first IGBT region (1-21) is spatially separated from the second IGBT region (1-22), and wherein optionally: - the first IGBT region (1-21) is a first contiguous region; and / or - the second IGBT region (1-22) is a second contiguous region.The IGBT (1) according to one or more of the preceding claims, further comprising, in the semiconductor body (10), a drift region (100) of a first conductivity type, wherein the drift region (100) is shared by both the first IGBT region (1-21) and the second IGBT region (1-22).The IGBT (1) according to claim 9, further comprising, in electrical connection with the second load terminal (12), a back side emitter (108) coupled to the drift region (100), wherein the back side emitter (108) is configured according to the separation of the active region (1-2) into at least the first IGBT region (1-21) and the second IGBT region (1-22).The IGBT (1) according to one or more of the preceding claims, wherein the IGBT (1) has an RC-IGBT configuration, and wherein - the first IGBT region (1-21) has an IGBT-only configuration for conducting only the forward load current; - the second IGBT region (1-22) has an RC-IGBT configuration for conducting both the forward load current and a reverse load current; and wherein optionally - the IGBT (1) further comprises an IGBT-only region (1-23), at least 90% of which are configured to conduct only the reverse load current.The IGBT (1) according to claim 11, wherein the back side emitter (108) is configured with: - a first portion (108-21) of a second conductivity type in a portion of the active region (1-2) where the first IGBT region (1-21) is present; and - a second portion (108-22) comprising both first sub-portions (108-221) of a first conductivity type and second sub-portions (108-222) of the second conductivity type in a portion of the active region (1-2) where the second IGBT region (1-22) is present; and optionally, when the diode-only region (1-23) is implemented, with - a third portion (108-23) of the first conductivity type in a portion of the active region (1-2) where the diode-only region (1-23) is present.The IGBT (1) according to claim 12, wherein the first portion (108-21) of the back side emitter (108) has an average dopant dose of at least 5 * 10 12 cm -2 with respect to its horizontal surface.The IGBT (1) according to one or more of the preceding claims 10 to 13, further comprising a field stop region (107) of the first conductivity type coupled to both the drift region (100) and the back side emitter (108), wherein the dopant concentration of the field stop region (107) is greater than the dopant concentration of the drift region (100).IGBT (1) according to one or more of the preceding claims, further comprising, between the first load terminal (11) and the drift region (100), a trench mesa pattern, wherein the trench mesa pattern is configured according to the separation of the active region (1-2) into at least the first IGBT region (1-21) and the second IGBT region (1-22), and wherein optionally - a pitch of the trench mesa pattern in the first IGBT region (1-21) is identical to a pitch of the trench mesa pattern in the second IGBT region (1-22); and / or - a mesa width in the trench mesa pattern in the first IGBT region (1-21) is identical to a mesa width in the trench mesa pattern in the second IGBT region (1-22); and / or - a trench width in the trench mesa pattern in the first IGBT region (1-21) is identical to a trench width in the trench mesa pattern in the second IGBT region (1-22).The IGBT (1) according to claim 15, wherein the trench mesa pattern comprises: - first control trenches (14-21) arranged in the first IGBT region (1-21) and configured to receive the first control signal (13-21), optionally wherein a subset of the first control trenches (14-21) is arranged in the second IGBT region (1-22); and - second control trenches (14-22) arranged in the second IGBT region (1-22) and configured to receive the second control signal (13-22).The IGBT (1) according to claim 15 or 16, wherein the trench mesa pattern comprises: - source trenches (16) electrically connected to the first load terminal (11) and arranged at least in the first IGBT region (1-21).The IGBT (1) according to claim 4 and one or more of the preceding claims 15 to 17, wherein the trench mesa pattern comprises: - first type mesas (17) arranged in both the first IGBT region (1-21) and the second IGBT region (1-22), wherein each first type mesas (17) comprises a source region (101) of the first conductivity type and a portion of the body region (102) of the second conductivity type, wherein both the source region (101) and the body region (102) are electrically connected to the first load terminal (11), and wherein at least the body region (102) isolates the source region (101) from the drift region (100).The IGBT (1) according to claim 18, wherein the percentage area occupied by the source region (101) in the first IGBT region (1-21) is greater than the percentage area occupied by the source region (101) in the second IGBT region (1-22).The IGBT (1) according to one or more of the preceding claims 15 to 19, further comprising a barrier region (105) of the first conductivity type coupling the trench mesa pattern in the first IGBT region (1-21) to the drift region (100), wherein the dopant concentration of the barrier region (105) is greater than the dopant concentration of the drift region (100), and wherein the barrier region (105) optionally does not extend into the second IGBT region (1-22).A method of operating an IGBT (1) according to any of the preceding claims 1 to 19, the method comprising: - controlling the first IGBT region (1-21) based on the first control signal (13-21); and - controlling the second IGBT region (1-22) based on the second control signal (13-22).The method of claim 21, wherein the second control signal (13-22) is provided such that the second IGBT region (1-22) is in a forward conduction state while the first IGBT region (1-21) is switched to a forward blocking state based on the first control signal (13-21).A circuit (1000) comprising: - an IGBT (1) according to any one of the preceding claims 1 to 20; - a MOSFET (500) connected in parallel with the IGBT (1).The circuit (1000) of claim 23, wherein at least one of: - the IGBT (1) has an RC-IGBT configuration; - the MOSFET (500) is based on a wide band gap semiconductor material.The circuit (1000) of claim 23 or 24, wherein the MOSFET (500) is controlled based on the first control signal (13-21).

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