Method for accessing a data block of a number of data blocks stored in a storage unit of a computing unit

Abstract

The invention relates to a method for accessing a data block of a number of data blocks stored in a storage unit of a computing unit, comprising: activating (222) a safe operating mode of the computing unit (100); in the safe operating mode of the computing unit, accessing (223) the data block; if the access (223) is a read access, reading data from the data block and subsequently writing the data to the data block; if the access (223) comprises a write access, reading first data from the data block, removing the first data from a check value associated with the data block, writing second data to the data block, adding the second data to the check value associated with the data block; and checking (224) the check value associated with the data block.

Description

The present invention relates to a method for accessing a data block of a number of data blocks stored in a memory unit of a computing unit, and to a computing unit and a computer program for carrying it out.BACKGROUND OF THE INVENTIONIn a computing unit such as a microcontroller or a system-on-a-chip (SoC), a functionally reliable execution platform can be implemented (referred to in English as "safe island", "vital modules", "safe backbone" or "safe execution platform", for example) in order to enable software to be executed at the highest safety level with respect to operational safety or functional safety (safety). For example, this safety level in the automotive sector may be ASIL-D, the highest safety requirement level for safety-relevant systems in motor vehicles according to the safety standards of ISO 26262 or the ASIL (Automotive Safety Integrity Level) defined therein.Such a functionally reliable execution platform can be realized, for example, by providing two identical processor cores and operating them in the so-called lockstep method, wherein the two cores execute the same processes and plausibilize their results with respect to one another, and wherein an error signal can be output in the event of detected deviations. The cores usually have separate clock trees and separate areas on the respective chip. Program code can be stored, for example, in an embedded NOR flash memory and data in an embedded static ROM memory.However, such a lockstep concept with an additional, redundant processor core is associated with high energy consumption and high space requirement. Furthermore, the lockstep concept cannot be implemented equally well for all processor types. For example, the lockstep concept may be well suited for medium-power cores, which are used, for example, for engine control or for controlling brake systems in vehicles. However, at higher powers, the lockstep method can often scale poorly. High-performance cores can often only be operated to a limited extent in parallel lockstep operation. Also, NOR flash memory often cannot scale to nodes below 28 nm and requires more area than NAND flash. Embedded static RAM may usually comprise not more than 10 MiB (Mebibyte).Functionally reliable execution platforms based on the lockstep principle are therefore often suitable only to a limited extent for systems with large program code and large amounts of data, as is the case, for example, in the course of autonomous driving.Disclosure of the InventionAccording to the invention, a method for accessing a data block of a number of data blocks stored in a memory unit of a computing unit, and a computing unit and a computer program for carrying it out are proposed having the features of the independent patent claims. Advantageous embodiments are the subject matter of the dependent claims and of the following description.The invention makes it possible to access data in the computing unit in a secure manner with regard to operational safety or functional safety ("safety"). If security is mentioned in the present context, this is to be understood in particular in the sense of operational security or functional security, which is referred to in English as "safety", in contrast to information-technology security or information security, which is referred to in English as "security".The memory unit of the computing unit is in particular a nonvolatile memory unit, e.g. a (NAND) flash memory. Each data block of the number of data blocks has a predefined or predeterminable number of bytes in each case. Particularly expediently, each data block of the number of data blocks is assigned a respective check value and the number of data blocks is stored together with the corresponding number of check values in the memory unit.Within the scope of the present method, a safe operating mode of the computing unit is activated or the computing unit is operated in a safe operating mode. For example, an activation command for activating this safe operating mode can be read in and executed by a processor unit of the computing unit. In particular, the computing unit can thus change from a normal, regular operating mode to the safe operating mode.In the safe operating mode of the computing unit, a respective data block of the number of data blocks is accessed in a reading and / or writing manner.If the accessing is a read accessing, data is read from the data block and then written into the data block. The test value associated with the data block is expediently not changed in this case. If the read data is corrupted, for example while held in a register, this error is transferred by writing to the data block. By checking the check value, this error can be detected.If the accessing comprises a writing accessing, first data is read in from the data block and the first data is removed from the check value associated with the data block. The test value is thus expediently changed depending on the first data. Further, second data is written into the data block, and the second data is added to the check value associated with the data block. The test value is thus expediently changed again depending on the second data. By this change of the check value, the access to the data block can be advantageously tracked. If the access is a writing access, the second data can be independent of the first data, for example. If the access comprises a reading and a writing access, the first data can be processed to the second data, for example.Furthermore, in the safe operating mode, the test values associated with the data block are checked. In the safe operating mode, each check value stored in the memory unit is particularly expediently checked, in particular at least once. For example, the respective check value can be checked in the course of access to the respective data block. In particular, the individual check values can also be effected independently of or in addition to the accesses to the data blocks. For example, the check of the check values in the safe operating mode can be carried out as a separate routine or function, e.g. at predetermined times or in response to predetermined events or predetermined commands.The invention is based on the idea of providing specific, selected data or data blocks with a check value in each case, so that these selected data can be accessed in a secure manner in the secure operating mode. By checking the check values, the individual data blocks can expediently be checked for correctness and integrity and errors in or manipulations on the individual data blocks can be detected. Thus, in the safe operation mode, erroneous or manipulated data can be prevented from being accessed. If an error is detected during the check value check, a predefined measure can be carried out, for example an error message can be output or an entry can be created in an error memory or the system can optionally also be stopped or transferred into a safe state.The arithmetic unit can in particular also be operated in a normal, regular operating mode, wherein the individual data blocks of the number of data blocks are read also in this regular operating mode, but in particular each independently of the respective test value of the individual data blocks or without the test values of the individual data blocks being checked. In this regular operating mode, the data blocks can thus be accessed in particular only in a regular, non-secure manner.By checking the check values, it is made possible in particular to perform accesses to the predetermined data blocks in an insecure memory in a secure manner in the secure operating mode, wherein an insecure memory is to be understood as a normal, regular memory unit which is not protected by separate, additional measures. Since the predefined number of data blocks can be accessed in a secure manner in the secure operating mode, these data blocks of the predefined number of data blocks are also referred to as secure data or secure data blocks in the present context. Advantageously, further data or data blocks for which no check value is determined can be stored in the memory unit. Such data blocks are thus not part of the predefined number of data blocks and in the present context may also be referred to as normal data or normal data blocks. These normal data blocks can be accessed in the regular operating mode as well as in the secure operating mode only in a normal, non-secure manner.The safe operating mode allows a functionally safe execution platform ("Safe Island", "Vital Modules", "Safe Backbone" or "Safe Execution Platform") to be implemented in a low-complexity, energy-saving and space-saving manner. In the safe operating mode, it may be possible to execute software at a high or highest safety level, for example at the highest safety requirement level ASIL-D according to the safety standards of ISO 26262 in the automotive sector. In particular, no special hardware units are required for realizing the safe operating mode; conventional memory units and buses can be used, for example. Furthermore, in particular, no implementation of error detection code (EDC) or error correction code (ECC) in hardware is required. For example, a large external RAM memory may be used and connected to the processor unit via a conventional standard interface, e.g., via a JEDEC LPDDR interface. Further, for example, a conventional external NAND flash may be used to write program code and initialization data to the RAM memory. The safe operating mode can expediently be activated and deactivated as required at any time. Furthermore, for the safe operating mode, in particular no embedded NOR flash memory and embedded static ROM memory are required. Particularly expediently, in the safe operating mode, it is possible to detect errors in data paths, in a cache memory and a data memory within the CPU of the computing unit without additional hardware. Mixed secure and non-secure accesses, instructions, and data may be provided with a defined interface. Protection of the predefined number of data blocks can be made possible from the compiler to the CPU.According to one embodiment, the check value is written into the memory unit of the computing unit when the accessing comprises a writing accessing. The check value changed by removing the first data and adding the second data is thus stored together with the second data in the storage unit. The check value can be written into the memory unit, for example, in the course of the writing access, or else decoupled in time from the writing access. For the latter case, the check value can, for example, first be buffered in a cache memory of the arithmetic unit. For example, the check value may be changed accordingly and written to the memory unit when the cache memory is emptied.According to one embodiment, a check value is determined or created or assigned for the predefined number of data blocks. Each of these data blocks has a predefined or predeterminable number of bytes.Each individual data block of the predetermined number of data blocks is assigned an individual, unique check value. For example, the check values can each be calculated according to a cyclic redundancy check (CRC). The number of data blocks and the respective determined check values of the individual data blocks are stored in the memory unit of the arithmetic unit. These steps of determining the test values and storing the data blocks and the test values in the memory unit are carried out once, in particular at a first point in time, in particular before the arithmetic unit is put into operation or before a regular operation of the arithmetic unit. Expediently, these steps are carried out in the course of a compilation process with the aid of a compiler. At a second time occurring after the first time, in particular after the arithmetic unit has been put into operation, in particular at the runtime of the arithmetic unit, the data blocks can be accessed.According to one embodiment, a respective identifier or attribute is added to a memory address of each data block of the number of data blocks, in particular during the compilation process. Expediently, these added identifiers allow the predefined number of secure data blocks to be distinguished from normal data blocks. If a pointer points to data at a respective memory address in the safe operating mode, it can be detected on the basis of the memory address whether the respective data is a normal data block or a safe data block. If the memory address has a respective identifier, the respective data block is advantageously handled in a secure manner. For example, a specific bit in the memory address may have a specific value as a corresponding identifier. Expediently, the respective identifier is added to a virtual memory address of the respective data block. This virtual memory address is converted, for example, by a memory management unit (MMU) into a real, physical memory address. In this way, there is no particular limitation on a layout of the physical memory.According to one embodiment, the number of data blocks is stored in at least one predefined memory area of the memory unit at a first memory area address or beginning at this first memory area address. The check values are stored in the at least one memory area at a second memory area address or starting at this second memory area address. Expediently, a first data block of the number of data blocks is stored in the memory area at the first memory area address. Each further data block is expediently stored in the memory area in each case with a respective offset to the first memory area address. The first memory area address thus points in particular to this first data block. The second memory area address correspondingly expediently points to a first of the check values. The secure data blocks are thus stored in a fixed schema with two characterizing memory addresses in the memory unit. In this way, access to the data blocks and checking of the check values in the secure operating mode can be made simple.According to one embodiment, the removal of the first data from the check value associated with the data block comprises a determination of a first characteristic value of the first data, in particular a hash value. The test value is changed depending on the determined first characteristic value. For example, the first characteristic value can be subtracted from the test value.According to one embodiment, adding the second data to the check value associated with the data block comprises determining a second characteristic value of the second data, in particular a hash value, and changing the check value depending on this second characteristic value. For example, the second characteristic value can be added to the test value.By changing the test value in this way depending on the first or second characteristic value, each writing access to the data block can be tracked. Such a first or second characteristic value is in particular unique for the respective first or second data.For example, the first or second characteristic value can be determined individually for each byte of the respective first or second data.According to one embodiment, in the safe operating mode, the respective data block is accessed with the aid of one or more commands of different command categories. For example, individual commands can be assigned to a respective category by a respective predefined value. Such commands of different command categories make it possible in particular to access the secure data blocks in the secure operating mode in a secure manner.By means of a write command of a first command category, data can be written into a data block of the predefined number of data blocks without changing the check value associated with the respective data block. Furthermore, by means of this write command of the first command category, data can also be written into a normal data block to which no check value is assigned, that is to say into a data block which does not belong to the predefined number of data blocks. By means of a read command of the first command category, data can be read in from a data block of the predefined number of data blocks without changing the test value associated with the respective data block. Furthermore, by means of this read command, data from normal data blocks that do not belong to the predefined number of data blocks can also be read in. These commands of the first category can be, for example, regular read and write commands, which are also used in the regular operating mode. By means of these commands, data blocks are accessed, in particular independently of the test values.By means of a write command of a second command category, data can be written into a data block of the predefined number of data blocks without changing the check value associated with the respective data block. By means of a read command of the second command category, data are read in from a data block of the predefined number of data blocks and the check value associated with the respective data block is changed in a first manner. The instructions of this second instruction category are used, in particular, to access the predefined number of secure data blocks exclusively. In particular, when such a second category instruction points to a memory address of a normal data block, it is not performed.By means of a write command of a third command category, data is written into a data block of the predefined number of data blocks and the check value associated with the respective data block is changed in a second manner. By means of a read command of the third command category, data are read in from a data block of the predefined number of data blocks and the check value associated with the respective data block is changed in a third manner. The instructions of the third instruction category are also used, in particular, to access the predefined number of secure data blocks exclusively. In particular, when such a third category instruction points to a memory address of a normal data block, it is not performed.According to an embodiment, in the secure operating mode, the reading and writing of the data when the accessing is a reading accessing, as well as the reading of the first data and the writing of the second data when the accessing comprises a writing accessing are performed according to a first time request. The changing of the test value, i.e. the removal of the first data from the test value associated with the data block and the addition of the second data to the test value associated with the data block, take place according to a second time requirement. Specifically, a processing order for appropriately changing the check value is prepared, and this processing order is processed according to the second time request. According to the first time requirement, the respective data is accessed in particular as directly as possible or as quickly as possible with a slight or smallest possible delay. According to the second time requirement, the check values are not necessarily changed immediately, but may be processed with a delay as needed. In particular, a respective test value is changed according to the second time requirement before this test value is checked.According to one embodiment, if the accessing comprises a writing accessing, the check value associated with the data block is read in and this read-in check value is stored together with information relating to the respective data block in a further memory unit, in particular in a volatile memory unit, in particular in a memory unit within the processor unit of the computing unit, in particular in a check value cache, in particular in a cache memory. The check value stored in this volatile memory unit can then be changed accordingly, i.e. the first data is removed in particular from the check value stored in the volatile memory unit and the second data is added in particular to the data block stored in the volatile memory unit. The correspondingly changed check value can be written back into the memory unit from the volatile memory unit. For example, the check values can be stored together with the memory address of the respective data block, with an offset of the respective data block in the respective memory area of the memory unit and with a memory address of the check value as the information relating to the respective data block in the volatile memory unit. By storing the check values and the corresponding information, the check values can be processed in a simple and efficient manner according to the second time requirement.According to one embodiment, a table is also created, in particular in the course of the compilation process, which has a memory address of a first data block of the number of data blocks, e.g. the virtual memory address of the first data block, and furthermore a memory address of a first check value, which is stored in particular directly behind a last data block of the number of data blocks. In the safe operating mode, accessing any data block of the number of data blocks comprises checking whether the memory address of the respective data block to be accessed is stored in the table. If this is the case, the respective data block is expediently accessed. If the memory address is not stored in the table, a predefined measure can be carried out, for example, an error message can be output. The table can also be used when a respective check value is to be written to the volatile memory unit. For this purpose, it can be checked whether there is an entry for the respective data block in the table. If this is the case, the corresponding entry can be created in the volatile memory unit.According to one embodiment, the checking value associated with the data block is checked upon calling a checking command. In particular, only a single check value is checked upon the calling of such a checking command. Expediently, the checking command is repeatedly called up in order to check different check values one after the other, in particular until all check values have been checked. In particular, this repeated calling of the checking command is carried out within a predetermined error detection time. Expediently, a check value check or integrity check therefore does not take place with each access to secure data, but in particular only once within a predefined error detection tolerance interval by means of the respective check command.According to one embodiment, the checking value associated with the data block is checked according to a predefined frequency and / or according to a predefined sequence. For example, it is thus possible to specify which of the data blocks is next checked. Furthermore, for example, individual data blocks can be checked more frequently if necessary than other data blocks. The respective frequency and sequence can be predefined by a user, for example.According to one specific embodiment, the arithmetic unit has multiple hardware and / or software units that can access the memory unit or the number of data blocks. These multiple units are synchronized or process synchronized with respect to read and write accesses to the number of data blocks. In this way, it is possible in particular to prevent data of the respective data block from being changed during the checking of a respective check value.According to an embodiment, the computing unit includes a processor unit based on an Instruction Set Architecture (ISA). An instruction set generally refers to the entirety of machine instructions that a processor unit can execute. The RISC-V instruction set architecture is based on the so-called Reduced Instruction Set Computer (RISC) principle, according to which the instruction set comprises a small number of instructions, usually below 100, which can be executed easily and quickly by the processor unit, respectively, whereby a simplified processor design, a high processor clock and a fast execution speed can be achieved, in contrast to the so-called Complex Instruction Set Computing (CISC) architecture, which provides an instruction set with a high number of instructions (above 100), by which a respective processor can execute complex processes, which is however associated with a complex processor design. The RISC-V instruction set architecture is an open source and easily allows changes and extensions to the instruction set. RISC-V processors or generally processors with a modifiable instruction set architecture are particularly suitable for implementing the safe operating mode, since instructions required for executing the safe operating mode, for example the read and write instructions of the different instruction categories, can be integrated into the instruction set in a simple manner.The method is particularly preferably suitable for use in the vehicle sector. The computing unit can be designed in particular as a microcontroller or control unit in a (motor) vehicle. For example, the method is particularly suitable for computing units with high-performance cores and for systems with large program code and large amounts of data, as are used for autonomous driving, for example. Processes executed by the computing unit can comprise, for example, safety-critical functions which are executed for safe operation and for control of the vehicle, for example in the course of engine control, in the course of driving assistance functions or also in the course of autonomous driving etc. Safety or fail-safe and integrity of the control unit can be increased by the present method. In particular, safety requirements in the (motor) vehicle sector can be fulfilled by the method, as are specified, for example, in the standard ISO 26262 or, in particular, by the so-called "Automotive Safety Integrity Level" (ASIL), a safety requirement level specified by ISO 26262 for safety-relevant systems in motor vehicles.A computing unit according to the invention, e.g. a control device of a motor vehicle, is configured, in particular by programming, to carry out a method according to the invention.The implementation of a method according to the invention in the form of a computer program or computer program product with program code for carrying out all method steps is also advantageous since this causes particularly low costs, in particular if an executing control device is also used for further tasks and is therefore present in any case. Finally, a machine-readable storage medium is provided with a computer program stored thereon, as described above. Suitable storage media or data carriers for providing the computer program are, in particular, magnetic, optical and electrical memories, such as hard disks, flash memories, EEPROMs, DVDs, among others. Download of a program via computer networks (Internet, intranet, etc.) is also possible. Such a download can be effected in a wired or wired or wireless manner (e.g. via a WLAN network, a 3G, 4G, 5G or 6G connection, etc.).Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawing.The invention is schematically illustrated in the drawing on the basis of exemplary embodiments and is described below with reference to the drawing.Brief Description of the DrawingsFIG. 1 schematically shows a computing unit which is configured to carry out an embodiment of a method according to the invention. FIG. 2 schematically shows an embodiment of a method according to the invention as a block diagram. FIG. 3 schematically shows a memory unit of a computing unit which is configured to carry out an embodiment of a method according to the invention. FIG. 4 schematically shows a memory unit of a computing unit which is configured to carry out an embodiment of a method according to the invention.Embodiment(s) of the InventionIn FIG. 1, a computing unit is schematically illustrated and denoted by 100, which can be embodied, for example, as a system-on-a-chip (SoC). For example, the SoC 100 can be provided for a motor vehicle and integrated into a control device of the vehicle, for example in order to carry out safety-critical functions for safe operation of the vehicle, e.g. in the course of engine control, in the course of driving assistance functions, in the course of autonomous driving, etc.In order to ensure safety and integrity of the control unit, in order to be able to execute software at the highest safety level and in order to be able to meet safety requirements of the (motor) vehicle area, in particular according to the ASIL-D safety requirement level of the standard ISO 26262, the SoC 100 can be operated in a safe operating mode in which special data can be accessed safely, according to one embodiment of a method according to the invention. In this way, a functionally reliable execution platform 110 ("Safe Island", "Vital Modules", "Safe Backbone" or "Safe Execution Platform") is realized in the SoC 100.For this functionally safe execution platform 110 or for executing the safe operating mode, a processor unit 111, a cache logic unit 112 and a timer 113 are provided in the example shown. The processor unit 111 may be conveniently (but not by way of limitation) a processor core based on a RISC-V instruction set architecture. This RISC-V processor 111 and the cache logic unit 112 are linked, for example, via RAM and cache memories 121 to an interconnect unit ("interconnect") 120 of the SoC 100 as further elements of the functionally secure execution platform 110. For example, a flash memory unit 140, e.g., a NAND flash memory, may be connected to the connection unit 120 via an interface 141, and a RAM memory unit 150, e.g., an LPDDR RAM, may be connected to the connection unit via a RAM controller 151. The SoC 100 may further include one or more further processor cores 130 with associated RAM and cache memory 131 coupled to the interconnect unit 120. Furthermore, a memory unit 122 as a further element of the functionally secure execution platform 110 for a boot process (boot flash memory) and a peripheral bus 160 can be connected to the connection unit 120. A plurality of peripheral units can be connected to the peripheral bus 160, for example an analog-to-digital converter 161, a serial peripheral interface (SPI) bus system 162, a direct memory access (DMA) unit 163, a timer 164 and a further field bus system 165, for example a Flexray field bus. It goes without saying that fewer or even further peripheral units can also be provided, indicated by reference sign 166. An external monitoring unit 180 for detecting and managing a fault or a failure of the SoC 100 ("watchdog"), for example, can be connected via the serial bus system 162. Further, the SoC 100 may include an Error Management Module (EMM) 170 for managing issued error messages.In FIG. 2, an embodiment of a method according to the invention is shown as a schematic block diagram.First, a compilation process 210 is performed by a compiler, during which executable code and data for the SoC 100 are generated and stored therein. At a later time, the SoC 100 is put into operation and can access the data stored during the compile process 210 during runtime 220.During the compilation process 210, in a step 211, a check value for a predefined number N of data blocks is determined in each case, and in a step 212, the number of data blocks and the respective determined check values are stored in a memory unit of the SoC 100, for example in the flash memory unit 140.In a step 213, a flag or attribute is added to a virtual memory address of each data block of the number of data blocks.In a step 214, a table is created in which in each case a memory address of the first data block of the number of data blocks is stored, for example in each case the virtual memory address. This table is also referred to as a secure data table below.Since each data block is thus protected by a check value, these data blocks of the predefined number of data blocks are also referred to as secure data or secure data blocks. Furthermore, further data blocks for which no check value is determined can also be stored in the storage unit 140 during the compilation process. Such data blocks may also be referred to as normal data or normal data blocks in the present context. After startup, the SoC 100 can be operated in a regular operating mode and in a safe operating mode at its runtime 220. In the regular mode of operation, both the normal data and the secure data are accessed in the same normal manner. In the secure mode of operation, the normal data blocks are also accessed in this normal manner. In the safe operating mode, the secure data blocks are accessed in particular in a different, secure manner, expediently with the aid of commands of specific command categories.The determined test values serve in particular for detecting errors, but not for correcting errors. Without a correction function, the test values can be provided in a very storage-efficient manner. For example, a check value having a number B check of bits may be used to protect a data block having N block bytes. N block is in particular a power of 2 and can be, for example, in the range between approximately 256 and 16384. The smaller the value of N block the faster the checking of the respective check value can be carried out and the less long the corresponding data can be blocked before other accesses. The larger the value of N block the less memory is required for the check values, and the less frequently a check value check can be performed. Conveniently, the value N block may be set by a user with a compiler option.In particular, the check values are not visible to a programmer and cannot be legally retrieved. For a data segment, the compiler may conveniently assign a necessary space to the check values and automatically initialize them. At the beginning of runtime 220, this initialized data is copied from read-only memory 140 to read / write memory, e.g., 150, by the boot code. For a.bss segment ("block start by signal", bss), this assignment is expediently likewise effected by a startup code. For a heap and stack, the allocation is conveniently performed by a library's allocation function at runtime.By means of the added flag, the secure data can be distinguished from the normal data. If the respective virtual memory address has a respective identifier, the respective data are securely handled in the secure operating mode. Normal data whose virtual memory address does not have such a flag is accessed in the secure operation mode and in the regular operation mode in the same conventional manner.For example, as such a flag, a particular bit in the virtual memory address may have a particular value. For example, if a most significant bit (MSB) in the virtual memory address is '0', it may be a normal data block. If the MSB bit in the virtual memory address has the value '1', it can be a secure data block, for example.Further, the tag may also be added, for example, in a series of areas or segments of the virtual memory address. For example, log 2( N block) LSBs ("least significant bit", LSB, bit with a lowest significance) can be neglected, since secure data blocks expediently always begin at a boundary of a block with N block bytes.For example, the number of data blocks is stored in at least one predefined memory area of the memory unit 150 at a first memory area address A block or beginning at this first memory area address. The check values are stored in the at least one memory area at a second memory area address A check or starting at this second memory area address.The first memory area address A block thus points in particular to a first data block of the N data blocks. The second memory area address A check points in particular to a first check value, which follows in particular a last of the N data blocks.A data block expediently always starts with an integer multiple of the block size N block. That is, the log 2( N block) are LSB bits of A b-lock and A check0.The following applies in particular to the number of data blocks:The data blocks in particular each begin at:An offset of a respective data block to the first memory address is given by:The test value associated with a respective data block is stored in particular in: Corresponding calculations can be implemented in hardware in a simple manner, for example.The individual, secure data blocks can each be secure initialized data, secure uninitialized or uninitialized data, secure heap data or data in a heap data structure or secure stack data or data of a stack or stack data structure.Secure initialized data are located in particular in the data segment. They take up space in the executable binary file. Since the virtual memory addresses of the secure data have the respective special identifier, they are accommodated in an additional segment in order to be able to meet this criterion. The compiler initializes these secure data and their check values. In addition, the compiler generates an entry for the secure data table.The secure uninitialized data are located in particular in the.bss segment. These data are in particular all zero in each case and do not occupy any space in the executable binary file. A Startup code reserves space on the heap and initializes the check values. This memory location meets the criteria for secure data, i.e. the respective virtual memory addresses each have a corresponding identifier. The addresses for accessing this data are generated by the compiler and are moved into this area. The compiler may also generate fixed addresses and the reserved area may be mapped to the existing physical memory by a memory management unit (MMU). The start-up code also creates an entry for the secure data table.The data of the heap data structure is reserved, for example, at runtime 220 by memory management calls in a security memory library. For the secure mode of operation, the compiler generates calls to this security storage library that provide addresses to secure data. The security storage library also reserves space for the check values, for example, and arranges the secure data in blocks. For the regular mode of operation, the compiler generates standard calls in a standard storage library that provides addresses to normal data without a check value. The secure storage library also updates the secure data table.For example, secure stack data is treated as secure uninitialized data. The Startup code reserves space on the heap, for example, and initializes the check values. This space meets the criteria for secure data, i.e. the respective virtual memory addresses each have a corresponding identifier. For example, a stack pointer is set behind this location to operate downward. Since the secure stack data belongs in particular to the secure non-initialized data, no entry is required for the table of the secure data. Any number of stacks of any size may be re-allocated at start-up or run-time. When transitioning from the normal operating mode to the safe operating mode, the stack memory may be switched from normal data to safe data and vice versa when returning. This can be done by the security library.The secure data blocks are thus stored in the memory unit 150 in one or more memory areas which each begin with a data block at the first memory area address A block and end with the associated check value at the second memory area address A check. Each of these secure storage areas is fully written with A block and A check and constitutes an entry in the secure data table.The size of the generated table, i.e. the number of secure storage areas, should be kept small. In particular, there is only one memory area in which all secure data are stored. This memory area is in particular large enough to hold all data that a program executed in the SoC 100 could ever request, e.g. several gigabytes. At start-up, in particular only a small part of this area is provided with physical memory. The remainder is reserved only and may never be actually assigned. Ideally, the table may contain only a few entries and is located within the processor unit 111. This makes a very fast search possible.After the compilation process 210 has been completed and the SoC 100 has been put into operation, the SoC 100 is first operated in the regular operating mode at its runtime 220 in a step 221. In a step 222, the safe operating mode is activated, e.g. by reading in and executing an activation command.In this safe operating mode, in a step 223 individual data blocks of the number of data blocks stored in the memory unit 150 are accessed in a reading and / or writing manner. In a step 224, the check values stored in the memory unit 150 are checked.If accessing a respective data block is a read access, data is read from the data block and subsequently written to the data block without changing the check value associated with the data block. If the accessing includes writing accessing, first data is read from the data block and this first data is removed from the check value associated with the data block. Further, second data is written into the data block, and the second data is added to the check value associated with the data block. If the accessing is a reading and writing accessing, the first data is processed to the second data, for example.If the accessing of a respective secure data block thus comprises a writing accessing, the check value associated with the data block is changed. For this purpose, in particular a first characteristic value of the first data, in particular a first hash value, is determined and the check value associated with the data block is changed depending on the first characteristic value. In particular, the first hash value is subtracted from the check value. Furthermore, in particular a second characteristic value of the second data, in particular a second hash value, is determined and the check value associated with the data block is changed depending on the second characteristic value. In particular, the second hash value is added to the check value.In the safe operating mode, the access to secure data blocks is effected with the aid of commands of different command categories.The respective data blocks can be accessed according to a first time request, in particular as directly as possible or with a low or as little delay as possible. For changing the respective check values, a processing sequence can be created, which is processed according to a second time request.For example, a respective check value can be initialized together with the respective data block. An initial value of the check value may be any value. When accessing the respective data block, the respective check value can be changed, for example, by subtracting the hash value of each byte during loading from the check value and adding the hash value of each byte to the check value during storage. The check value is in particular practically never zero, in particular also not for data blocks with the value zero.The hash value is calculated separately for each byte, for example, and may be as long as B check bits or shorter. For example, the respective offset (<store address>-A block) can be included for each hash value. Without this address information, false addressing could be missed. The use of this offset within the respective memory area is transparent to the MMU in particular and can avoid problems in the assignment of virtual to physical addresses.The hash value is calculated per byte, for example, and uses the address of the byte. In longer words, 16, 32, 64,... Bits may be the hash for each byte simultaneously with 2, 4, 8,... Hash Units can be calculated. The check value can be changed by means of its sum. The sum thereof can be added to the check value in the case of a write access and subtracted from the check value in the case of a read accessA corresponding hash algorithm for determining the hash values is in particular configured such that the check value changes to more than 99% of all possible single- and multi-bit errors within the data block. This applies in particular to white noise, all 0, all 1 and all regular patterns with respect to data and / or address.Since the offset for each address yields a different value, a respective hash value is desirably never zero. The hash value is in particular always explicitly initialized, even for all data blocks with the value zero.In order to change a respective check value depending on a respective characteristic or hash value, the respective check value can be read in from the memory unit 150 and stored in a check value cache, e.g. within the processor unit 111. In particular, the respective check value is stored in this check value cache together with information relating to the respective data block which is accessed.For example, the memory address of the associated data block can be stored as respective information in the check value cache, in particular without the lower log 2( N block) bits, which are always zero in particular. This address is the key for the check value cache to find a table entry. Furthermore, for example, the address offset of the respective block to the first memory area address A block, the current check value with B check bits and the virtual address from which the check value is read in and from which the changed check value is stored are stored in the check value cache as information.When a cache entry is deleted, only the check value changed accordingly is stored in the storage unit 150. The rest of the entry is lost and reconstructed when the respective check value is loaded again. To this end, the table generated in step 214 may be searched for an entry that matches the indicated effective data address. If nothing is found, this is an addressing error and, for example, initiates an exception (exception). This is an additional control mechanism which is expediently provided in the safe operating mode. The entry found is used to calculate the data block address, the offset to the first block and the address of the check value. The respective check value is then loaded into the check value cache. Conveniently, each time a check value cache entry is created, the table generated in step 214 is searched.A corresponding plurality of requests for changing the respective test values can be generated by a plurality of load and store accesses. In particular, there is no need to delay a respective load or store operation until the respective test value is determined. Corresponding accesses may be performed as quickly as possible according to the first time request.A respective check value should be changed accordingly according to the second time request, in particular until it is checked, so that in particular a great amount of time can be available to carry out the change. Therefore, all requests to change the check values may be fed into the execution order as a separate processing path.For example, requests for ascertaining a check value can be entered into the processing sequence. During the course of processing, the respective hash value can then be calculated for each byte. The respective check value may be loaded into the cache if it is not present there, possibly after storing another cache entry, and may then be changed by means of the calculated hash value.In the safe operating mode, new or extended commands can be available, in particular in comparison with the regular operating mode. In particular, access to secure data relates to commands that use an in particular extended load / store unit of the core. For example, all load and store instructions for signed and unsigned integers of arbitrary width, floating point numbers of arbitrary precision, vectors of arbitrary size, and any other data, particularly except atomic instructions, may use an additional variable, e.g., a Hint value, with, for example, three possible values. These three possible values make it possible to distinguish between three command categories in particular. The hint value is advantageously taken into account only in the safe operating mode. In the regular operating mode, in particular, a standard read or write command is always used.A first instruction category may be defined, for example, when the Hint variable is not assigned a concrete value ("no hint"). This first instruction category can comprise, in particular, a standard read and write instruction ("no hint load", "no hint store"). By means of this read or write command of the first command category, secure data blocks can be accessed accordingly without changing their check values. Furthermore, normal data can also be accessed by means of this read or write command.A second instruction category can be defined, for example, by a first specific value of the Hint variable, for example, by the value "EXCL", and can relate, for example, to accesses exclusively or exclusively to secure data. By means of a write command of the second command category ("EXCL store"), in particular only secure data blocks are stored without changing their check values. In particular, only secure data blocks are read in by means of a read command of the second command category ("EXCL load"), and their respective test value is changed in a first manner, for example by subtracting the hash value from the test value. The instructions of this second instruction category in particular do not take any action or are not executed if the respective memory address points to normal data.A third command category can be defined, for example, by a second specific value of the Hint variable, e.g., by the value "SAFE", and can also relate, for example, to accesses exclusively to secure data. By means of a write command of the third command category ("SAFE store"), in particular only secure data blocks are stored and their respective check value is changed in a second manner, e.g. by calculating the current hash value and by adding this value to the check value in the cache. In particular, only secure data blocks are read in by means of a read command of the third command category ("SAFE load"), and their respective check value is changed in a third manner, for example by calculating the current hash value and by subtracting this value from the check value in the cache.The calculation of the hash value and the change of the check value may be delayed according to the second time request while the next read or write commands are already executed, so that speed degradation does not occur.In particular, a corresponding Hint value may be integrated into all read and write instructions defined in the instruction set architecture. If this is not possible, for example because a code space is full, instruction categories can also be defined in another way, for example by means of prefix instructions.For example, instead of a simple read instruction, the secure mode compiler may generate code from the following instructions: load data from the memory 150 using a first instruction category read instruction ("no hint load"); use the data without altering it; store the data in the memory 150 using a second instruction category write instruction ("EXCL store"). The respective test value is not changed in this case. If the data is corrupted during loading and holding in a register, this error is transferred to memory 150 by the "EXCL store" instruction at the final store and detected at the next check of the respective check value. In the regular mode of operation or when loading normal data, the "EXCL store" command does not cause anything.For example, instead of a simple memory instruction, the secure mode compiler may generate code from the following instructions: load first data using a read instruction of the second instruction category ("EXCL load"); store second data using a write instruction of the third instruction category ("SAFE store"). The "EXCL load" command serves in particular only to subtract the hash of the old value, i.e. the first hash value of the first data, from the check value, wherein the destination register can be x0, for example. The "SAFE store" command writes the new, second data and adds its new hash value, i.e. the second hash value of the second data, to the check value. In the regular mode of operation, the "EXCL load" command does not cause anything and the storage operates normally.For example, the compiler for the safe operating mode can generate code from the following instructions when a value is to be loaded, changed and then stored again: loading first data by means of a read instruction of the third instruction category ("SAFE load"); using and changing the data, whereby the second data is generated in particular from the first data; storing the changed, second data by means of a write instruction of the third instruction category ("SAFE store").Furthermore, in the regular operating mode and in the safe operating mode, further commands can be used in each case. For example, a load and reserve ("load and reserve") command and a conditional store ("store conditional") command can be used for a de-lock-free synchronization of a plurality of bus masters. These commands can also be used in the safe operating mode. For example, if these instructions address secure data, additional actions may be taken. For example, the load and reserve command can establish a "reservation context" in the safe operating mode, which also contains the hash value of the loaded value. In the safe operating mode, the conditional memory command can be used to add, for example, the hash value of the stored value minus the hash value in the reservation context to the check value.Furthermore, for example, atomic commands can be used, by means of which accesses to data can be carried out without other processes being able to access this data during this access. For example, these atomic instructions may include in the RISC-V-ISA AMOSWAP, AMOADD, AMOAND, AMOOR, AMORR, AMOMAX, AMOMAXU, AMOMIN, AMOMINU (combination of prefix AMO with a regular command SWAP, ADD, AND, etc.). All of these instructions access data in an atomic, noninterruptable manner. These commands can also be used in particular in the safe operating mode. If these commands address secure data in the secure mode of operation, for example, the hash value of the stored value minus the hash value of the loaded value is added to the check value.Further, a check value can be loaded from the check value cache into the destination register by means of a secure check value load instruction ("SAFLDCHK"). For example, this SAFLDCHK instruction can be used for the stack memory, for checking the check values and for debugging. If the respective check value is not present in the check value cache, it is loaded. If the check value cache is full, another check value is first stored.Further, a secure check value write instruction ("SAFSTCHK") may be used to write a check value from a source register to the check value cache. This command can also be used, for example, for the stack memory, for checking the check values and for debugging. If the respective check value is not present in the cache, it is loaded. If the check value cache is full, another check value is first stored.Furthermore, by means of a flush instruction, all check values or even only certain check values can be emptied from the check value cache into the memory 150.For example, to initialize a new data block, i.e., when allocating the data block on the heap, the security storage library may use the following command sequence: create a check value cache entry and initialize the check values using a SAFSTCHK command; store all data in the data block using a SAFE store command. In particular, no gap is left behind in this case.In order to check an individual check value of the check values stored in the memory unit 150, a check command is called up and executed. This checking command can be implemented, for example, as a separate routine or function, for example by means of a check-run or check-walk function, which can be implemented in the security storage library.Based on the secure data table, a data block is compared with its check value each time the checking command or the checkwalk function is called. If they do not match, the function returns an error and the caller can decide how to react.Each call to the checking command or to the checkwalk function checks a data block, that is to say N block bytes. The larger N block the longer this can take. This is important because the data block and its check value must not change during execution of the check command, otherwise an erroneous error would be returned. On a system with only one core, this could be caused by an interrupt (interrupt). On a multi-core system, this may be caused by an interrupt or other core. The avoidance of such conflicts is incumbent to the user.Since each call to the verify command verifies only one data block, many calls are required until all secure data blocks are verified. This occurs in particular within the fault detection time.The security storage library can provide, for example, supporting functions and data, e.g. how often the checking command is to be called and which data block is to be checked next.For example, a sequence and a frequency can thus be predefined, according to which individual test values are checked. In this way, it is possible, for example, to check data blocks in a user-defined order or to check some data blocks more frequently than others. This can help the user minimize access collisions and optimize the system.To check a data block or a check value, the checkwalk function first reads in the respective check value of the respective data block with a normal read command, for example. Then the function passes through the data block and reads it in completely, for example by means of a "SAFE load" command. Finally, the check value should correspond to the init value of the check value. In order to be as fast as possible, the test run can be carried out on a 32-bit architecture with 32-bit "SAFE load" commands and on a 64-bit architecture with 64-bit "SAFE load" commands.During the checking of a check value, the data of the respective data block must not change. For this purpose, various hardware and / or software units of the SoC 100, which can each access the storage unit 150 or the secure data blocks stored there, are synchronized or process-synchronized with respect to reading and writing accesses to the secure data blocks.For example, if two non-process synchronized cores, each in the safe mode of operation, write different values to the same address in memory 150, a respective first memory access could be overwritten by a respective second memory access, while the respective check value reflects both memory accesses. During the next check of the check value, an error would then be detected.Read access from non-process synchronized cores could also result in such an error if the corresponding read access ends with an "EXCL store" command. If another non-process synchronized core changes the respective data block during this read access, this change could be lost but would be included in the check value. This would lead to an error in the next check of the check value.Such errors can be avoided by the process synchronization of corresponding units. For example, corresponding units can be synchronized by means of a mutex or semaphore method.In a step 225, the safe operating mode is ended and the SoC 100 changes back to the regular operating mode. For example, the SoC 100 may transition to the regular operation mode upon an interrupt command. When an interrupt command occurs, the CPU stores its context and enters the regular mode of operation, particularly including the stack memory. After the interrupt, the context is restored.In FIG. 3, the storage unit 150 of the SoC 100 is schematically illustrated. FIG. 3 shows, for example, a memory area 300 of the memory unit 150 in which three data blocks 311, 312, 313 and three associated check values 321, 322, 323 are stored. 331 denotes the first memory area address A block starting from which the three data blocks 311, 312, 313 are stored. 332 denotes the second memory area address A check starting from which the check values 321, 322, 323 are stored.Also in FIG. 4, the storage unit 150 of the SoC 100 is schematically illustrated. FIG. 4 shows, for example, a memory area 400 of the memory unit 150 in which, starting at the first memory area address A block431 secure initialized data 411, secure uninitialized data 412, secure stack data 413, 414, 415, secure heap data 416 and a reserved, unused secure heap memory 417 are provided. Beginning at the second memory area address A check432 the check values 421 for the initialized data 411, for the non-initialized data 412, for the stack data 413, 414, 415 and for the heap data 416 are stored. Further, storage space for the check values 422 is reserved for the unused heap 417.

Claims

Method for accessing a data block of a number of data blocks stored in a memory unit (150) of a computing unit (100), comprising: activating (222) a secure operating mode of the computing unit (100); in the secure operating mode of the computing unit, accessing (223) the data block; if the accessing (223) is a read accessing, reading data from the data block and subsequently writing the data into the data block; if the accessing (223) comprises a write accessing, reading first data from the data block, removing the first data from a check value associated with the data block, writing second data into the data block, adding the second data to the check value associated with the data block; checking (224) the check value associated with the data block.The method of claim 1, further comprising: when the accessing (223) comprises writing accessing, writing the check value to the storage unit (150) of the computing unit (100).Method according to Claim 1 or 2, further comprising: determining (211) in each case one check value for the number of data blocks; storing (212) the number of data blocks and the respective determined check values in the storage unit (150) of the arithmetic unit (100).The method of claim 3, further comprising: adding (213) each a tag to a memory address of each data block of the number of data blocks.Method according to claim 3 or 4, wherein storing (212) the number of data blocks and the respective determined test values in the memory unit of the computing unit comprises: storing the number of data blocks in at least one memory area of the memory unit (150) at a first memory area address; storing the test values in the at least one memory area of the memory unit (150) at a second memory area address.Method according to one of the preceding claims, wherein the removal of the first data from the test value associated with the data block comprises: determining a first characteristic value, in particular a hash value, of the first data; changing the test value associated with the data block depending on the at least one determined first characteristic value; and / or wherein the addition of the second data to the test value associated with the data block comprises: determining a second characteristic value, in particular a hash value, of the second data; changing the test value associated with the data block depending on the at least one determined second characteristic value.Method according to one of the preceding claims, wherein, in the safe operating mode of the arithmetic unit (100), the accessing (223) takes place with the aid of one or more of the following commands of different command categories: a write command of a first command category in order to write data into a data block of the predefined number of data blocks without changing the check value associated with the respective data block or in order to write data into a data block which does not count to the predefined number of data blocks; a read command of the first command category in order to read data from a data block of the predefined number of data blocks without changing the check value associated with the respective data block or in order to read data from a data block which does not count to the predefined number of data blocks; a write command of a second command category for writing data into a data block of the predetermined number of data blocks without changing the test value associated with the respective data block; a read command of the second command category for reading data from a data block of the predetermined number of data blocks and for changing the test value associated with the respective data block in a first manner; a write command of a third command category for writing data into a data block of the predetermined number of data blocks and for changing the test value associated with the respective data block in a second manner; a read command of the third command category for reading data from a data block of the predetermined number of data blocks and for changing the test value associated with the respective data block in a third manner.The method of any preceding claim, wherein in the secure mode of operation, reading the data from the data block and writing the data to the data block when accessing is read accessing, and reading the first data from the data block and writing the second data to the data block when accessing comprises write accessing are according to a first time request; and wherein in the secure mode of operation, removing the first data from the check value associated with the data block and adding the second data to the check value associated with the data block when accessing comprises write accessing are according to a second time request.Method according to one of the preceding claims, further comprising, if the accessing (223) comprises writing accessing: reading in the test value associated with the data block; storing the read-in test value together with information relating to the respective data block in a further memory unit, in particular in a volatile memory unit, in particular in a memory unit within a processor unit (111) of the computing unit (100), in particular in a test value cache, in particular in a cache memory.Method according to one of the preceding claims, further comprising: creating (214) a table having a memory address of a first data block of the number of data blocks and a memory address of a first check value, in particular directly behind a last data block of the number of data blocks; wherein in the safe operating mode the accessing (223) of the data block comprises: checking whether the memory address of the respective data block is stored in the table.Method according to one of the preceding claims, wherein the checking (224) of the check value associated with the data block takes place upon a calling of a checking command and / or according to a predetermined frequency and / or according to a predetermined sequence.Method according to one of the preceding claims, wherein the computing unit (100) has a plurality of units which can access the data block, accesses of these plurality of units to the data block being synchronized.Arithmetic unit which is designed to carry out all method steps of a method according to one of the preceding claims, in particular having a processor unit (111) which is based on a RISC-V instruction set architecture.A computer program that causes a computing unit to perform all method steps of a method according to any one of claims 1 to 12 when executed on the computing unit.A machine readable storage medium having stored thereon a computer program according to claim 14.

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