Prediction of chip failure probabilities on a wafer

Abstract

The invention relates to a method (100) for training a machine learning system to predict chip failure probabilities on a wafer. The method is based on a prediction (103) of final test yields depending on wafer-level test measurements by the machine learning system, wherein the machine learning system predicts the chip failure probabilities depending on the wafer-level test measurements and the predicted failure probabilities are aggregated to the predicted final test yield, and a training (104) of the machine learning system such that a mathematical difference between predicted final test yields and final test yield from a training data set is minimized.

Description

[0001] The invention relates to a method for training a machine learning system for predicting failure probabilities of chips on a wafer and to a method for predicting failure probabilities of the chips using the trained machine learning system. State of the art

[0002] It is generally known that machine learning (ML) and machine learning methods can be suitable for predicting defects in components during production.

[0003] Currently, predicting the failure probability or defect probability of an individual semiconductor chip during final testing based on wafer-level measurements is not possible due to the loss of traceability between processes. In particular, the connection between an individual chip for which wafer-level measurements were taken and the corresponding final test is lost after the wafer is dicing, making the training of supervised models impossible.

[0004] It is therefore an object of the invention to provide a prediction of the probability whether an individual chip is defective based on test measurements at wafer level. Advantage of the invention

[0005] By predicting the failure probability, chips with a high failure probability can be removed early in the manufacturing process or, depending on the failure probabilities of all chips in a batch, an intelligent combination of chips in the final product with a low failure probability of the final product can be determined.

[0006] Thus, these inventions can reduce waste, rework, and additional costs associated with manufacturing and shipping defective products. By detecting and correcting defects early, manufacturers can improve product quality and reduce scrap rates. Disclosure of the invention

[0007] In a first aspect, the invention relates to a method for training a machine learning system to predict failure probabilities of the chips on a wafer during the final-level test or, in particular, later during operation of the chips.

[0008] The method begins by providing a training data set comprising wafer-level test measurements and an associated final test yield for each of a plurality of wafers. The final test yield can be understood as the ratio of the number of chips on the wafer that passed the final test to the total number of chips on the wafer tested in the final test.

[0009] The following steps are then repeated several times: Drawing a preferably complete wafer-level batch of wafer-level test measurements and the corresponding FT batch of final test yields, especially for an iteration / batch.

[0010] Predictions of the final test yields depending on the wafer-level test measurements by the machine learning system, whereby the machine learning system predicts the failure probabilities of the chips depending on the wafer-level test measurements and the predicted failure probabilities are aggregated to the predicted final test yields.

[0011] Training the machine learning system in such a way that a mathematical difference between the predicted final test yield and the assigned final test yield is minimized.

[0012] What is surprising here is that the actually simplified training task of yield prediction is used to learn during training which chips will have a high or low probability of failure and that this essentially corresponded to the actual probability of failure on a validation data set.

[0013] The invention of the first aspect can be used to color defective chips at an early stage of the manufacturing process, preventing the chip from being further processed or removed after dicing (= cutting the individual chips from the wafer). Another application is the use of failure probability to perform intelligent sorting, in which chips with a high failure probability are packaged together, reducing the risk of multiple good chips being packaged with a single bad chip, leading to the elimination of the entire package.

[0014] Furthermore, within the scope of the invention, it is conceivable that the assignment of the components to the functional units comprises a sorting into at least two or three different classes according to the probability of the occurrence of the failure or defect.

[0015] Furthermore, it is advantageous if, within the scope of the invention, the assignment of components to functional units is carried out in such a way that the components are grouped into functional units depending on their class, so that preferably each of the functional units only contains components of the same class. This increases the probability that the entire functional unit will contain more than one defective component during sorting and, in particular, disposal.Alternatively or additionally, it is possible that the assignment of the components to the functional units is carried out in such a way that the components are grouped together depending on their probability of failure in the functional unit, so that the probability is preferably maximized that in the event of a failed functional unit, more than one defective component in the functional unit is responsible for this failure.

[0016] The invention also relates to a computer program, in particular a computer program product, comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. Thus, the computer program according to the invention provides the same advantages as those described in detail with reference to a method according to the invention.

[0017] The invention also relates to a data processing device configured to carry out the method according to the invention. The device can be, for example, a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. A non-volatile data memory can also be provided, in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0018] The invention may also provide a computer-readable storage medium comprising the computer program according to the invention. The storage medium is designed, for example, as a data storage device such as a hard disk and / or a non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0019] Furthermore, the method according to the invention can also be implemented as a computer-implemented method.

[0020] Further advantages, features, and details of the invention will become apparent from the following description, which describes embodiments of the invention in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. They show: Fig. 1 a schematic visualization of a method, a device, a storage medium and a computer program according to embodiments of the invention.

[0021] During semiconductor wafer manufacturing, the wafers are inspected after various production steps. Before the wafer is cut into individual chips and packaged into the final product, the "finished" wafers are inspected in what is known as wafer-level testing, or EWS (= Electrical Wafer Sorting). During this step, the position of the individual chips on the wafer is still known.

[0022] After dicing and packaging, the wafers are tested again in the so-called final test. Since the wafer position is lost after the dicing process, it is no longer possible to trace the chips back to their original coordinates, making the training of supervised machine learning models impossible. Even if the individual chip position is lost, the information about which wafer as a whole belongs to the test lot is still available.

[0023] In the following, a method is proposed that enables the prediction of failure probability in the final test of individual chips based on wafer-level measurements.

[0024] This involves using a neural network architecture that receives a series of wafer-level measurements as input and predicts a failure probability for each chip on the wafer (e.g., by using a sigmoid activation function in the last layer). For each matching set of wafers and final test lots, an average of the chip predictions can be calculated to obtain a yield of the chips on the wafer.

[0025] For this purpose, the neural network is trained so that it can predict the yield of chips after the final test. The training is carried out according to Fig. 1.

[0026] Fig.Figure 1 illustrates, according to embodiments of the invention, a method 100 for training a machine learning system, in particular a neural network, to predict failure probabilities of chips on a wafer. Also shown are a computer program 20, a storage medium 40, and a device 10 for data processing according to embodiments of the invention.

[0027] The method 100 begins with providing 101 a training data set comprising wafer-level test measurements at chip level and an associated final test yield of a plurality of wafers.

[0028] The following steps are then executed several times until a specified termination criterion is met: Drawing 102 a plurality of wafer-level test measurements and respective associated final test yields,

[0029] Predictions 103 of the final test yields depending on the wafer-level test measurements by the machine learning system, wherein the machine learning system predicts the failure probabilities of the chips depending on the wafer-level test measurements and the predicted failure probabilities are aggregated to the predicted final test yields.

[0030] The drawn wafer-level measurements are processed as input by the machine learning system, in particular propagated by the neural network to obtain a failure probability for each chip.

[0031] All failure probabilities are then aggregated into a single lot yield (e.g. by using the average).

[0032] Training 104 of the machine learning system such that a mathematical difference between the predicted final test yield and the assigned final test yield is minimized. The training can be performed using known training methods based on the error between the predicted and true final test lot yield.

[0033] After training, the neural network can be used to predict a failure probability for each chip in the final test.

Claims

[1] A method (100) for training a machine learning system to predict failure probabilities of chips on a wafer, comprising the following steps: Providing (101) a training data set comprising wafer-level test measurements from a plurality of wafers and an associated final test yield; Repeat the steps several times: Drawing (102) a plurality of wafer-level test measurements and respective associated final test yields, Predictions (103) of the final test yields depending on the wafer-level test measurements by the machine learning system, wherein the machine learning system determines the failure probabilities of the chips on the wafer depending on the wafer-level test measurements and the determined failure probabilities are aggregated to the predicted final test yields, and Training (104) the machine learning system such that a mathematical difference between the predicted final test yield and the assigned final test yield is minimized. [2] The method (100) of claim 1, wherein the machine learning system comprises a topography configured to receive the wafer-level measurements as input and output a failure probability for each chip on the wafer as output. [3] The method (100) of any preceding claim, wherein the machine learning system is a neural network and an activation function of an output layer of the neural network is a sigmoid activation function. [4] Method (100) according to one of the preceding claims, wherein the aggregation of the predicted failure probabilities to the predicted final test yield is carried out by calculating an average of the predicted failure probabilities. [5] A method for predicting failure probabilities of chips on a wafer, wherein the trained machine learning system according to any one of the preceding claims is used to predict a failure probability in the final test for each chip on said wafer, depending on wafer-level test measurements of a currently processed wafer. [6] Method according to claim 5, wherein those chips for which a failure probability greater than a predetermined first threshold was predicted are sorted out and / or those chips for which a failure probability less than a predetermined second threshold was predicted are installed in a final product with other chips less than the predetermined second threshold. [7] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause the computer (10) to carry out the method (100) according to one of claims 1 to 6. [8] Device (10) for data processing, which is arranged to carry out the method (100) according to one of claims 1 to 6. [9] A computer-readable storage medium (40) comprising instructions which, when executed by a computer (10), cause the computer (10) to carry out the method (100) according to any one of claims 1 to 6.

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