Microelectronic component and method for manufacturing a microelectronic component

Abstract

Microelectronic component (100, 200, 300) with a metallic conductor (106, 206, 306) on a first dielectric layer (104, 204, 304), wherein the metallic conductor (106, 206, 306) has a polygonal, in particular rectangular, cross-section, and the metallic conductor (106, 206, 306) has a region (107, 207, 307) with a corner, the corner facing away from the first dielectric layer (104, 204, 304), characterized in that at least one second layer (109, 209, 309) with a second permittivity and a second conductivity is arranged on the region (107, 207, 307) with the corner, and on the second layer (109, 209, 309) a fourth layer (111, 211, 311) is arranged with a fourth permittivity and a fourth conductivity, wherein the second permittivity has a higher value than the fourth permittivity and the second conductivity has a higher value than the fourth conductivity.

Description

[0001] The invention relates to a microelectronic component and a method for producing a microelectronic component. State of the art

[0002] Galvanic isolation is used for data transmission between different voltage domains in the high-voltage range. The data transmission itself can be optical and, with integrated galvanic isolation, inductive or capacitive. In the automotive sector, the respective coils of the inductor or the plates of the capacitors are temporarily at very different electrical potentials. The difference in potentials is in the range above 500 V.

[0003] Galvanic isolation is integrated either directly into the semiconductor technology of the ASIC or as a separate chip in a system-in-package. The maximum load capacity and lifetime of the isolation are defined by the maximum electric field within the isolation structure.

[0004] The disadvantage here is that weak points arise at the corners and edges of the conductive materials due to field enhancements.

[0005] The document US 929 96 97 B2 describes galvanic isolation using a capacitor in which an insulating layer is arranged below the upper plate of the capacitor.

[0006] The disadvantage here is that a slow onset of degradation above the metallic plate impairs the service life of the component.

[0007] The document DE 10 2013 206 899 A1 describes the rounding of corners and edges.

[0008] The disadvantage here is that only thick metal layers can be processed.

[0009] The object of the invention is to overcome these disadvantages. Disclosure of the invention

[0010] The microelectronic component comprises a metallic conductor on a first dielectric layer, wherein the metallic conductor has a polygonal, in particular rectangular, cross-section, and the metallic conductor has a region with a corner, wherein the corner faces away from the first electrical layer. According to the invention, at least one second layer with a second permittivity and a second conductivity is arranged on the region with the corner. A fourth layer with a fourth permittivity and a fourth conductivity is arranged on the second layer, wherein the second permittivity has a higher value than the fourth permittivity and the second conductivity has a higher value than the fourth conductivity. In other words, a metal edge or corner is surrounded by a field-reducing multilayer system.

[0011] The advantage here is that the electric field at the metal edge is low, thus increasing the lifetime of the component.

[0012] In a further development the corner is rounded.

[0013] The advantage here is that the electric field at the metal edge is further reduced.

[0014] In a further embodiment, the metallic conductor is arranged within a high-voltage area and the corner faces a low-voltage area.

[0015] The advantage of this is that the component's dielectric strength in the high-voltage range is increased. Furthermore, the component's service life at high voltages is significantly improved.

[0016] In a further development, a third layer having a third permittivity and a third conductivity is arranged in regions on the at least one second layer, wherein the third permittivity has a value between the second permittivity and the fourth permittivity and the third conductivity has a value between the second conductivity and the fourth conductivity.

[0017] The advantage here is that electric fields are reduced, particularly at curves, corners and edges of the at least one second layer, thereby increasing the reliability of the component.

[0018] In a further embodiment, the third layer is arranged in regions on a sixth dielectric layer, wherein the sixth dielectric layer is arranged between the metallic conductor and the first dielectric layer.

[0019] The advantage of this is that electric fields are reduced, particularly at curves, corners, and edges of the at least one second layer. Furthermore, field-enhancing corners in the third layer are avoided, further increasing the reliability of the component.

[0020] In a further development, at least one second layer has defects.

[0021] The advantage here is that a Poole-Frenkel conduction mechanism is used, which drastically reduces the electric field at the edge.

[0022] In a further embodiment, the second layer comprises SiN.

[0023] The advantage here is that charges introduced as a result of high voltage loads and the associated field stresses can flow away. Furthermore, SiN is a widely used material in semiconductor processing.

[0024] In a further embodiment, the metallic conductor is part of a capacitor.

[0025] In a further embodiment, the metallic conductor is part of a coil.

[0026] The method according to the invention for producing a microelectronic component with a metallic conductor on a first dielectric layer, wherein the metallic conductor has a polygonal, in particular rectangular, cross-section, and the metallic conductor has a region with a corner, wherein the corner faces away from the first dielectric layer, comprises applying a second layer with a second permittivity and a second conductivity to the region with the corner by means of CVD, PE-CVD, HDP-CVD, ALD or electroless galvanic deposition, and applying a fourth layer with a fourth permittivity and a fourth conductivity by means of CVD, PE-CVD, HDP-CVD, ALD or electroless galvanic deposition, wherein the second permittivity has a higher value than the fourth permittivity and the second conductivity has a higher value than the fourth conductivity.

[0027] The advantage here is that the production of the multi-layer system is simple.

[0028] Further advantages arise from the following description of embodiments and the dependent patent claims. Short description of the drawings

[0029] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. They show: Fig. 1a a microelectronic component according to the invention, Fig. 1b shows a section of a first embodiment of the microelectronic component, Fig. 2 shows a section of a second embodiment of the microelectronic component, and Fig. 3 shows a section of a third embodiment of the microelectronic component.

[0030] Fig. 1a shows a microelectronic component 100 according to the invention. The microelectronic component 100 has a high-voltage region 101 and a low-voltage region 102. The microelectronic component 100 comprises a semiconductor substrate 103, for example made of silicon. Alternatively, the semiconductor substrate 103 can comprise wide bandgap materials such as SiC or GaN. A first dielectric layer 104 is arranged on the semiconductor substrate 103, which is located, for example, at reference potential, i.e., ground. A capacitor is shown, by way of example, in the high-voltage region 101 for galvanic isolation. Alternatively, however, a coil, not shown here, can also be provided. Therefore, a first metallic plate 105 is arranged within the first dielectric layer. A metallic conductor 106 with a rectangular cross-section is arranged vertically spaced from the first metallic plate 105.The metallic conductor 106 has a region 107 with a corner or edge of the metallic conductor 106. The corner or edge faces away from the first dielectric layer 104 and toward the low-voltage region 102 or a ground connection 114. The low-voltage region 102 comprises various components 115. In this exemplary embodiment, the metallic conductor 106 is electrically connected using a high-voltage connection 116. Polyimide 117 is arranged in regions above the region 107. The polyimide 117 is mechanically separated from the high-voltage connection 116 by a molding compound 118.

[0031] Fig. 1b shows a section of a first embodiment of the microelectronic component 100. The section shows the area 107 of Fig. 1a. A sixth dielectric layer 110 is arranged on the first dielectric layer 104. A fifth dielectric layer 108 is arranged on the sixth dielectric layer 110. A metallic conductor 106 with a rectangular cross-section is arranged in regions on the fifth dielectric layer 108. The metallic conductor comprises a corner or edge facing away from the first dielectric layer 104. It is located on an upper side of the metallic conductor 106. A second layer 109 with a second permittivity and a second conductivity is arranged in regions on the metallic conductor 106. A fourth layer 111 with a fourth permittivity and a fourth conductivity is arranged on the second layer 109. The second permittivity is greater than the fourth permittivity. The second conductivity is also greater than the fourth conductivity.The second layer 109 comprises, for example, SiN, and the fourth layer 111 comprises, for example, SiO2. The fourth layer 111 functions as a passivation layer. A top passivation layer 112 is arranged on the fourth layer 111 and comprises, for example, SiON. The sixth dielectric layer 110 comprises, for example, SiON, and the fifth dielectric layer 108 comprises, for example, SiN.

[0032] Fig. Figure 2 shows a section of a second embodiment of the microelectronic component. The section shows the region 207, which is located at the location of the region 107 in Fig. 1a. Identical rear reference numerals of the Fig. 2 correspond to the characteristics of Fig. 1b. A third layer 213 is arranged between the second layer 209 and the fourth layer 211, with the third layer 213 being flush with the second layer 209 toward the low-voltage region. The third layer 213 has a third permittivity and a third conductivity. The value of the second permittivity is greater than the value of the third permittivity, and the value of the third permittivity is greater than the value of the fourth permittivity. The second conductivity is greater than the third conductivity, and the third conductivity is greater than the fourth conductivity.

[0033] In an alternative embodiment, the permittivity may decrease continuously from the second layer 209 to the fourth layer 211, so that no permittivity jumps occur at the layer transitions between the second layer 209, the third layer 213 and the fourth layer 211.

[0034] In both the first embodiment and the second embodiment, the etching of the second layer 109 and 209 and the third layer 213 takes place together after the structuring of the metallic layer 106 and 206.

[0035] Fig. Figure 3 shows a section of a third embodiment of the microelectronic component. The section shows the region 307, which is located at the location of the region 107 in Fig. 1a. Identical rear reference numerals of the Fig. 3 correspond to the characteristics of Fig. 2. The third layer 313 is not flush with the second layer 309, since the third layer 313 is deposited on the second layer 309 after the second layer 309 has been patterned. This also protects the corner or edge of the second layer 309 from high fields.

[0036] The second layer 109, 209, and 309 can be metallic, for example. Alternatively, the second layer 109, 209, and 309 can contain impurities, so that a Poole-Frenkel conduction mechanism can be generated during operation of the microelectronic component 100. Alternatively, the second layer 109, 209, and 309 can comprise SiN.

[0037] The third layer 213 and 313 comprises, for example, SiON.

[0038] The invention can also be applied to metallic conductors with a rectangular or polygonal cross-section in the low-voltage region 102 or at the ground connection 114. Furthermore, the invention can be applied in deeper layers, for example, in lower metal levels within the first dielectric layer.

[0039] The high-voltage component can comprise both a capacitor and a coil. This means that the applicability of the invention is not limited to capacitive couplers, but can also be used for inductive couplers or a combination of both.

[0040] The structures according to the invention can be used both in a chip that exclusively contains galvanic isolation structures, e.g. for signal transmission from the high-voltage to the low-voltage side or vice versa, and in a chip that additionally contains further electrical components, such as resistors, capacitors, coils and transistors.

[0041] Furthermore, there is no restriction on the number of conductive metal layers present in the chip.

[0042] Furthermore, the invention can also be used for other conductive layers, such as polysilicon. The conductive layers can have any three-dimensional shape. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 929 96 97 B2

[0005] DE 10 2013 206 899 A1

[0007]

Claims

[1] Microelectronic component (100, 200, 300) with a metallic conductor (106, 206, 306) on a first dielectric layer (104, 204, 304), wherein the metallic conductor (106, 206, 306) has a polygonal, in particular rectangular, cross-section, and the metallic conductor (106, 206, 306) has a region (107, 207, 307) with a corner, wherein the corner faces away from the first dielectric layer (104, 204, 304), characterized by that at least one second layer (109, 209, 309) with a second permittivity and a second conductivity is arranged on the region (107, 207, 307) with the corner, and a fourth layer (111, 211, 311) with a fourth permittivity and a fourth conductivity is arranged on the second layer (109, 209, 309), wherein the second permittivity has a higher value than the fourth permittivity and the second conductivity has a higher value than the fourth conductivity. [2] Microelectronic component (100, 200, 300) according to claim 1, characterized by that the corner is rounded. [3] Microelectronic component (100, 200, 300) according to one of claims 1 or 2, characterized by that the metallic conductor (106, 206, 306) is arranged within a high-voltage area (101) and the corner faces a low-voltage area (102). [4] Microelectronic component (100, 200, 300) according to one of the preceding claims, characterized by in that a third layer (213, 313) having a third permittivity and a third conductivity is arranged in regions on the at least one second layer (209, 309), wherein the third permittivity has a value between the second permittivity and the fourth permittivity and the third conductivity has a value between the second conductivity and the fourth conductivity. [5] Microelectronic component (300) according to claim 4, characterized bythat the third layer (313) is arranged in regions on a sixth dielectric layer (310), wherein the sixth dielectric layer (310) is arranged between the metallic conductor (306) and the first dielectric layer (304). [6] Microelectronic component (100, 200, 300) according to one of the preceding claims, characterized by that the at least one second layer (109, 209, 309) has defects. [7] Microelectronic component (100, 200, 300) according to one of the preceding claims, characterized by that the at least one second layer (109, 209, 309) comprises SiN. [8] Microelectronic component (100, 200, 300) according to one of the preceding claims, characterized by that the metallic conductor (106, 206, 306) is part of a capacitor. [9] Microelectronic component (100, 200, 300) according to one of the preceding claims, characterized bythat the metallic conductor (106, 206, 306) is part of a coil. [10] A method for producing a microelectronic component with a metallic conductor on a first dielectric layer, wherein the metallic conductor has a polygonal, in particular rectangular, cross-section, and the metallic conductor has a region with a corner, wherein the corner faces away from the first dielectric layer, comprising the step: • Applying a second layer with a second permittivity and a second conductivity to the area with the corner by means of CVD, PE-CVD, HDP-CVD, ALD or electroless galvanic deposition, and • Applying a fourth layer having a fourth permittivity and a fourth conductivity to the region with the corner by means of CVD, PE-CVD, HDP-CVD, ALD or electroless electrodeposition, wherein the second permittivity has a higher value than the fourth permittivity and the second conductivity has a higher value than the fourth conductivity.

Images