TRANSISTOR DEVICE AND METHOD

Abstract

A transistor device and a method for fabricating source regions of a transistor device are disclosed. The transistor device comprises a semiconductor body (100) with a plurality of mesa regions (110); and a plurality of transistor cells (1), each formed in one of the plurality of mesa regions (110). Each transistor cell (1) comprises: a source region (11) of a first doping type, a gate region (21) of a second doping type that is complementary to the first doping type and spaced apart from the source region (11), a channel region (12) of the first doping type, and a transition region (3) that is distinct from the source region (11) and the gate region (21). The transition area (3) is located between the source area (11) and the gate area (21) and borders both the source area (11) and the gate area (21).

Description

[0001] This disclosure relates generally to a transistor device, in particular a JFET (Junction Field-Effect Transistor).

[0002] A JFET is a self-conducting transistor device that can contain a plurality of transistors, each formed in a plurality of mesa regions, and each mesa region comprising a source region of a first doping type and a gate region of a second doping type that is complementary to the first doping type. The JFET can be switched on or off by applying a suitable drive voltage between the source and gate regions.

[0003] There is a need for a JFET with low leakage current.

[0004] An example concerns a transistor device. The transistor device comprises a semiconductor body containing a plurality of mesa regions and a plurality of transistor cells, each formed within one of the plurality of mesa regions. Each transistor cell comprises a source region of a first dopant type, a gate region of a second dopant type that is complementary to the first dopant type and spaced apart from the source region, a channel region of the first dopant type, and a transition region that is distinct from both the source region and the gate region, with the transition region being situated between the source region and the gate region and bordering both the source region and the gate region.

[0005] Another example involves a process. The process includes forming trenches in a first surface of a semiconductor body, creating mesa regions of the semiconductor body, with each mesa region located between adjacent trenches. Trench formation involves an etching process using an etch mask formed over the first surface, forming sacrificial plugs in the trenches so that the sacrificial plugs fill the trenches and extend vertically beyond the first surface, removing the etch mask to expose the sidewalls of the sacrificial plugs, forming spacers on the sidewalls of the sacrificial plugs, and forming source regions of a first dopant type in the mesa regions.Forming the source regions involves implanting dopant atoms of the first doping type into the first surface using the sacrificial plugs and spacers as an implantation mask.

[0006] Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are depicted. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. Fig. Figure 1 illustrates an example of a transistor device comprising a plurality of transistor cells, each arranged in a plurality of mesa regions of a semiconductor body, each comprising a source region, a gate region, a channel region, and a transition region situated between the source region and the gate region; Fig. Figure 2 illustrates an example of the transistor device in which the mesa regions are elongated regions; Fig. Figure 3 illustrates an example of the transistor device in which the mesa regions are columnar regions; Fig. Figure 4 schematically illustrates an example of a transistor device, which further includes a drift region and a drain region adjacent to the drift region; Fig. Figure 5 illustrates an example of a channel region of the transistor cells; Fig. 6- Fig. Figure 11 shows detailed views of a section of a transistor cell to illustrate various examples of the transition region; Fig. Figure 12 illustrates an example of a transistor device, which further includes gate electrodes and a source electrode; Fig. Figure 13 illustrates a top view of the entire transistor device according to an example; Fig. 14A- Fig. 14E illustrates an example of a procedure for forming the source regions; Fig. Figure 15 illustrates an example of a procedure for forming the gate regions; Fig. 16 illustrates an example of a procedure for forming sections of the canal areas; Fig. 17 illustrates an example of a procedure for forming sections of the canal regions and for forming first regions of the transition regions using the same implantation processes; Fig. Figure 18 illustrates another example of a procedure for forming initial areas of the transition regions; and Fig. Figure 19 illustrates an example of a transition area created by a combination of the procedure according to Fig. 15 and one of the procedures according to Fig. 17 and Fig. 18 is formed.

[0007] The following detailed description refers to the accompanying drawings. The drawings form part of the description and show examples of how the invention can be used and implemented for illustrative purposes. It is understood that the features of the various embodiments described herein can be combined unless expressly stated otherwise.

[0008] Fig. Figure 1 schematically illustrates an example of a transistor device implemented as a JFET. In particular, it illustrates Fig. 1 a section of a semiconductor body 100 in which active device regions of the JFET are integrated. The semiconductor body 100 contains, for example, monocrystalline silicon (Si) or monocrystalline silicon carbide (SiC).

[0009] With reference to Fig. 1 The semiconductor body 100 comprises a plurality of mesa regions 110 and a plurality of trenches 120. Each of the trenches extends from a first surface 101 of the semiconductor body 100 into the semiconductor body 100. Each mesa region 110 is defined by trenches 120 adjacent to the mesa region 110 and is arranged between adjacent trenches of the plurality of trenches 120.

[0010] The transistor device further comprises a plurality of transistor cells 1, which can also be referred to as control cells or head structure cells of the transistor device. Each transistor cell 1 is formed in one of the plurality of mesa regions 110. Furthermore, each transistor cell 1 comprises a source region 11 of a first doping type, a gate region 21 of a second doping type, which is complementary to the first doping type and spaced apart from the source region 11, a channel region 12 of the first doping type, and a transition region 3. The transition region 3 is distinct from the source region 11 and the gate region 21, is located between the source region 11 and the gate region 21, and borders both the source region 11 and the gate region 21.The transition region 3 can also be described as a voltage-absorbing region, a leakage current-reducing region, or a source-gate drift region, and / or exhibit the function thereof. Details of the function and implementation of transition region 3 are explained below.

[0011] According to one example, transition area 3, which differs from source area 11 and gate area 21, includes the following: (a) at least one of the doping type and concentration of transition area 3 differs from the respective doping type and concentration of source area 11; and (b) at least one of the doping type and concentration of transition area 3 differs from the respective doping type and concentration of gate area 21. Details of transition area 3 and various examples for implementing transition area 3 are explained below.

[0012] Unless otherwise specified, the doping concentration of a particular region, as used herein, is the peak doping concentration (or maximum doping concentration) of that region. Thus, the doping concentration of transition region 3, which differs from the doping concentration of source region 11 or gate region 21, implies that the peak doping concentration of transition region 3 differs from the peak doping concentration of source region 11 or gate region 21.

[0013] In particular, the peak doping concentration refers to the effective peak doping concentration. In a region containing dopant atoms of the first dopant type and dopant atoms of the second dopant type, the doping type of the region is given by the dopant type of those dopants that predominate in that region. The effective peak doping concentration is given by the peak doping concentration of the predominant dopants minus the peak doping concentration of the non-predominant dopants. Assuming that the dopants of the first dopant type predominate, the effective doping is first-type doping, and the peak doping concentration is given by the peak doping concentration of the first-type dopants minus the peak doping concentration of the second-type dopants.

[0014] According to a Fig. In the illustrated example 1, the transistor device further includes a drift region 13 of the first doping type, which adjoins the channel regions 12 of the plurality of transistor cells 1 in a vertical direction z of the semiconductor body 100. The “vertical direction z” is a direction that is essentially perpendicular to the first surface 101 of the semiconductor body 100.

[0015] The source regions 11 of transistor cells 1 are connected to a source node S of the transistor device, the gate regions 21 are connected to a gate node G of the transistor device, and the drift region 13 is connected to a drain node D of the transistor device. Connections between the source regions 11 and the source node S, connections between the gate regions 21 and the gate node G, and a connection between the drift region 13 and the drain node D are shown in Fig. Figure 1 is only schematically illustrated. Examples of implementing these connections are explained below.

[0016] With reference to Fig. Each of the mesa regions 110 comprises an upper surface, which is a section of the first surface 101 of the semiconductor body 100, and sidewalls 103. The sidewalls 103 of a mesa region 120 are simultaneously sidewalls of the trenches 120 that form (define) the respective mesa region 110. Each of the trenches 120 further comprises a bottom 102, which is a surface of the trench 120 spaced from the upper surfaces 101 of the mesa regions 110 in the vertical direction z.

[0017] According to one example, the source region 11 of each transistor cell borders the upper surface 101 of the mesa region 110 in which the respective transistor cell 1 is integrated. Furthermore, the gate region 21 of each transistor cell 1 borders a respective side wall 103 of the mesa region 110 in which the respective transistor cell 1 is integrated. For the purpose of illustration and explanation only, it is assumed that the gate region 21 of a transistor cell 1 borders exactly one of the side walls 103 of a mesa region. In this example, two or more transistor cells 1 can be formed within a mesa region 110, with the source regions 11 of the two or more transistor cells being formed by a continuous doped region of the first doping type.

[0018] In the Fig. In the illustrated example 1, the gate regions 21 of two transistor cells 1 are formed along opposite side walls 103 of a mesa region 110. In this example, the channel regions 12 of the two transistor cells 1 are formed by a continuous doped region of the first doping type. However, implementing the transistor cells in this way is only one example. It is also possible to implement the transistor device such that a mesa region 110 contains the gate region 21 and the corresponding channel region 12 of only one transistor cell, such that a gate region 21 is formed along only one side wall 103 of the mesa region 110, and the channel region 12 adjoins the opposite side wall 103 of the mesa region 110.

[0019] In the Fig. In the illustrated example 1, the mesa regions 110 are spaced apart from each other in a first lateral direction x of the semiconductor body 100. In a second lateral direction y perpendicular to the first lateral direction x, the mesa regions 110 can be implemented in various ways.

[0020] According to a Fig. In the illustrated example 2, at least some or all of the mesa areas 110 are elongated in the second lateral direction y. For example, at least some or all of the mesa areas 110 are striated. The trenches 120 adjacent to the elongated mesa areas 110 may also be elongated, e.g., striated.

[0021] According to another in Fig. In the illustrated example 3, the mesa areas 110 are columnar. The mesa areas 110 can, for example, be surrounded by at least three (e.g., four or six) ditches 120 in the horizontal plane. In the Fig. In the illustrated example 3, a cross-section of the mesa areas 110 in the horizontal plane parallel to the first surface 101 is rectangular. However, this is only one example. Other types of cross-sections (e.g., hexagonal, elliptical, in particular circular or triangular) are also possible. A gate area 21 can be formed along each of the side walls 103 of each mesa area 110. This is shown on the left side in Fig. Figure 3 illustrates this. According to another example, gate areas are formed only along two opposite side walls 103. This is shown on the right in Figure 3. Fig. 3 illustrated.

[0022] The transistor device can be operated in an on-state or an off-state. In the on-state, there is a conducting channel in each of the channel regions 12, so that a current can flow in the transistor device between the drain node D and the source node S when a corresponding voltage is applied between the drain and source nodes D and S. In the off-state, the channel regions 12 are depleted of charge carriers, so there are no conducting channels between the source regions 11 and the drift region 13.

[0023] The operating state (on or off) of the transistor device can be controlled by appropriately selecting a voltage level of a drive voltage (gate-source voltage) applied between the gate node G and the source node S. The channel region 12 of each transistor cell 1 adjoins the gate region 21 of the respective transistor cell 1 and is electrically coupled to the source region 11 either directly or via the transition region 3. The latter can involve the channel region 12 being adjacent to the source region 11 or being coupled to the source region 11 via the transition region 3. Examples of coupling the channel region 12 to the source region 11 via the transition region 3 are explained below.

[0024] Since the channel region 12 of each transistor cell 1 borders the gate region 21 and is coupled to the source region 11, a space charge region (depletion region) in the channel region 12 can be controlled by the gate-source voltage. In the off state of the transistor device, the gate-source voltage is such that a space charge region (depletion region), starting at a PN junction formed between the channel region 12 and the gate region 21, extends into the channel region 12 to such an extent that the channel region 12 is completely depleted of charge carriers.

[0025] A gate-source voltage level that switches off the transistor device is referred to below as the threshold voltage. The threshold voltage depends, among other things, on the dopant dose in channel region 12 in a direction perpendicular to the PN junction formed between channel region 12 and gate region 21, and on the dopant profile of dopant atoms in the channel region in the direction perpendicular to the PN junction. The dopant dose is the integral of the dopant concentration of channel region 21 in the direction perpendicular to the PN junction. As an example, the threshold voltage is between 5 V and 20 V.

[0026] The polarity of the threshold voltage depends on the conductivity type of the transistor device. In one example, the transistor device is an N-type. In this example, the first doping type, which is the doping type of the source and channel regions 11, 12 and the drift region 13, is an N-type, and the second doping type, which is the doping type of the gate region 21, is a P-type. In another example, the transistor device is a P-type. In this example, the first doping type, which is the doping type of the source and channel regions 11, 12 and the drift region, is a P-type, and the second doping type, which is the doping type of the gate region 21, is an N-type. In an N-type transistor device, the threshold voltage is negative. In a P-type transistor device, the threshold voltage is positive.

[0027] With reference to the foregoing, the side wall 103 of each mesa area 110 can simultaneously be the side wall of the trench 120 adjoining the mesa area 110. According to a Fig. In the illustrated example 1, gate regions 21 of adjacent transistor cells 1, formed along opposite side walls of each trench 120, extend into the drift region 13 and along the bottom 102 of the trench 120. The gate regions 21 of the adjacent transistor cells 1 adjoin each other below the trench bottom 102 and form a PN junction with the drift region 13. Thus, in the off state of the transistor device, depletion regions (space charge regions) extend not only in the channel regions 12 of the transistor cells 1, but also in the drift regions 13 starting at the PN junctions between the gate regions 21 and the drift regions 13. According to one example, the section of gate areas 21 formed below the trench floor includes a more highly doped area 22, which has a doping concentration higher than the doping concentration of the rest of gate areas 21.

[0028] With reference to the foregoing, the semiconductor body 100 comprises, for example, monocrystalline Si or monocrystalline SiC. While the basic topology of the transistor device is independent of the type of semiconductor material of the semiconductor body 100, the doping concentrations of the individual active device regions and dimensions may differ depending on whether the transistor device is implemented based on Si or based on SiC. In the following, unless otherwise specified, absolute values ​​of doping concentrations and dimensions refer to a transistor device implemented based on a SiC semiconductor body 100.

[0029] For example, the doping concentration of gate regions 21 is higher than 1E18 cm³. -3 The doping concentration of gate regions 21, for example, is between 1E18 cm³. -3 and 1E19 cm -3selected. According to one example, the doping concentration of source areas 11 is higher than 1E19 cm. -3 The doping concentration of source areas 11, for example, is between 1E19 cm³. -3 and 1E21 cm -3 selected.

[0030] According to one example, the drift area 13 is connected to the drain node D via a drain area 14. This is shown in Fig. Figure 4 illustrates a vertical cross-sectional view of a section of the semiconductor body 100. Details of the transistor cells 1 are shown in Fig. 2 not illustrated.

[0031] With reference to Fig. 4. The drain region 14 can form a second surface 104 opposite the first surface 101 of the semiconductor body 100. In this example, the drain node D can be formed by metallization on the second surface 104. However, this is only one example. According to another example (not illustrated), the drain region 14 is a buried layer within the semiconductor body 100 and is located at a position opposite the surface 101. Fig. 2 is spaced apart from the illustrated position and is spaced apart from the transistor cells 1, connected to a drain node on the first surface 101 of the semiconductor body 100.

[0032] Drain area 14 is of the first doping type, meaning it has the same doping type as drift area 13 and a higher doping concentration. For example, the doping concentration of drift area 13 is between 1E14 cm -3 and 1E17 cm -3selected. The doping concentration of drain area 14, for example, is at least 1 x 18 cm³. -3 .

[0033] The voltage blocking capability of the transistor device, which is the maximum voltage the transistor device can withstand in the off state, depends, among other things, on the length of the drift region 13. The length of the drift region 13 is essentially its dimension in the vertical direction z. For example, the voltage blocking capability of the transistor device is between 600 V and 1200 V, and the length of the drift region is between 3 and 8 micrometers.

[0034] Mesa widths w, which are the dimensions of the mesa areas 110 in the first lateral direction x, are, for example, between 0.3 micrometers and 2 micrometers. Trench depths d, which are the dimensions of the trenches 120 in the vertical direction z, are, for example, selected between 0.5 micrometers and 3 micrometers. The trench depths d are essentially equal to the heights h of the mesa areas 110.

[0035] According to one example, the channel region 12 is an essentially homogeneously doped semiconductor region.

[0036] According to another in Fig. In the 5 illustrated example, the channel region 12 of each transistor cell 1 comprises two differently doped regions: a first region 121, adjacent to the gate region 21, and a second region 122, adjacent to the first region 121 and separated from the gate region 21 by the first region 121. Each of the first and second regions 121, 122 is a doped region of the first doping type. The first region 121 has a higher doping concentration than the second region 122. According to one example, the doping concentration of the first region 121 is at least 5 times or at least 10 times the doping concentration of the second region 122. According to another example, the doping concentration of the first region 121 of the channel region 12 is between 1E17 cm⁻¹. -3 and 1E18 cm -3 selected.

[0037] According to one example, a third region 123 is arranged in the middle of each mesa region 120 between the second regions 122 of two transistor cells 1 formed in the same mesa region 120. The doping concentration of the third region 123 is, for example, less than 10 -1 The third region 123 is a doped region of the first doping type (0.1 times the doping concentration of the first region 121) and is selected, for example, between 0.01 times and 0.1 times the doping concentration of the first region 121.

[0038] According to an example that was in Fig. As illustrated in dashed lines in Figure 5, the transistor device is a superjunction transistor device. In this example, the transistor device includes a plurality of compensation regions 15 of the second doping type, each of the compensation regions 15 adjacent to a respective gate region 21 and adjacent to a respective section of the drift region 13. Doping concentrations of the compensation regions 15 can be in the same range as the doping concentration of the drift region 13. In a superjunction device, the doping concentration of the drift region 13 can be higher than in a non-superjunction transistor device and can be as high as 1E18 cm⁻¹. -3 In the vertical direction z of the semiconductor body 100, the compensation regions 15 can extend to the drain region 15 or can end at a distance from the drain region 14 (in Fig. 5 not illustrated).

[0039] Fig. 6- Fig. 11 illustrate various examples for implementing transition area 3. Each of the Fig. 6- Fig. 11 a vertical cross-sectional view of a section of a mesa area 120, wherein the illustrated section includes a section of the upper surface 101 and a section of a side wall 103 of a mesa area 120.

[0040] With reference to the above, transition region 3 differs from source region 11 and gate region 21. By way of example, transition region 3 is region 31 of a first doping type, which has a lower doping concentration than source region 11. Region 31 of the first doping type will henceforth be referred to as first region 31. In this example, the doping concentration of transition region 3 differs from the doping concentration of source region 11, and at least the doping type of transition region 3 differs from the doping type of gate region 21. According to one example, the doping concentration of the first region 31 is less than a predefined first percentage of the doping concentration of source region 11. According to one example, the first percentage is less than 10% (0.1), less than 1% (0.01), or less than 0.1% (0.001).As explained above, the doping concentration as used herein is the peak doping concentration, so the peak doping concentration of the first area 31 may be less than the predefined first percentage of the peak doping concentration of the source area 11.

[0041] Several examples of implementing transition region 3 as a region 31 of the first doping type are in Fig. 6-8 illustrated.

[0042] According to a Fig. In the illustrated example 6, transition region 3 extends in the lateral direction x to the mesa sidewall 103, such that gate region 21 borders transition region 3 in the vertical direction z. Furthermore, transition region 3 is located between source region 11 and channel region 12. It is possible that transition region 3 directly borders at least one of source region 11 and channel region 12. In some examples, transition region 3 directly borders both source region 11 and channel region 12.

[0043] Fig. Figure 7 illustrates a modification of the in Fig. 6 illustrated examples. In the example according to Fig. 7 the gate area 21 extends along the side wall 103 to the upper surface 101, so that the gate area 21 borders the transition area 3 in the lateral direction x.

[0044] In the Fig. 6 and Fig. In the seven illustrated examples, transition region 3 has a doping concentration that differs from the doping concentration of channel region 12. Transition region 3 can have a doping concentration that is higher or lower than the doping concentration of channel region 12. The latter implies that the doping concentration of transition region 3 is higher or lower than the doping concentration of both the first region 121 and the second region 122 of channel region 12.

[0045] However, implementing transition region 3 with a doping concentration that differs from the doping concentration of channel region 12 is only one example. According to another in Fig. In the example illustrated in Figure 8, the transition region 3, formed between the source region 11 and the gate region 21, has the same doping concentration as the channel region 12. In particular, in the example shown in Figure 8, the transition region 3 has the same doping concentration as the channel region 12. Fig. Example 8 illustrated that transition area 3 has the same doping concentration as the first area 121 of canal area 12.

[0046] According to another example, transition area 3 is area 32 of a second doping type, which has a lower doping concentration than gate area 21. The area of ​​the second doping type is referred to below as second area 32. In this example, the doping concentration of transition area 3 differs from the doping concentration of gate area 21, and at least the doping type of transition area 3 differs from the doping type of source area 11. According to another example, the doping concentration of second area 32 is less than a predefined second percentage of the doping concentration of gate area 21. According to another example, the second percentage is less than 50% (0.5), less than 33% (0.33), less than 20% (0.2), or even less than 10% (0.1).As explained above, the doping concentration as used herein is the peak doping concentration, so the peak doping concentration of the second area 32 may be less than the predefined second percentage of the peak doping concentration of the gate area 21.

[0047] Fig. Figure 9 illustrates an example where transition region 3 is a second region 32. In this example, source region 11 extends in the lateral direction x to side wall 103. Transition region 3 borders source region 11 in the vertical direction z, such that transition region 3 is located between source region 11 and gate region 21 in the vertical direction z.

[0048] According to further examples that are in Fig. 10 and Fig. As illustrated in Figure 11, transition region 3 includes a first region 31 and a second region 32. In each case, the first region 31 borders the source region 11, and the second region 32 borders the gate region 21. The first and second regions 31, 32 are adjacent to each other, thus forming a PN transition between the first and second regions 31, 32.

[0049] The in Fig. The 10 illustrated example is a modification of the one in Fig. 6 illustrated examples. In which in Fig. In the illustrated example 10, the first region 31 extends to the side wall 103 in the lateral direction x and is located between the source region 11 and the channel region 12. The second region 32 is located between the first region 31 and the gate region 21 in the vertical direction z and borders the side wall 103.

[0050] The in Fig. The 11th illustrated example is a modification of the one in Fig. 7 illustrated example. In the one in Fig. In the illustrated example 11, the second region 32 extends to the upper surface 101 along the side wall 103. The first region 31 is located between the second region 32 and the source region 11 in the lateral direction x. Furthermore, the first region 31 is located between the source region 11 and the channel region 12.

[0051] According to an example, in the Fig. 9 to Fig. In the 11 illustrated examples, the second region 32 is restricted to the upper half of the mesa region 110. That is, the distance between a lower end of the second region 32 and the upper surface 101 is less than 50% of the height h of the mesa region 110. The “lower end” of the second region 32 is the end of the second region 32 that faces away from the upper surface 101.

[0052] Referring to the above, in the on-state of the transistor device a current can flow between the drain and source nodes D, S via the drift region 13, the channel regions 12 and the source regions 11, with each channel region 12 being coupled to the respective source region 11.

[0053] Canal area 12 can be directly connected to source area 11. That is, canal area 12 can border source area 11. Examples of directly connecting source area 11 to canal area 12 are shown in Fig. 8 and Fig. 9 illustrates.

[0054] Alternatively, canal area 12 is connected to source area 11 via the first area 31 of transition area 3. Examples of connecting canal area 12 to source area 11 via the first area 31 are given in Fig. 6- Fig. 7 and Fig. 10- Fig. 11 illustrated.

[0055] In one example, transition region 3 is implemented such that a minimum distance d between source region 11 and gate region 21 is at least 100 nanometers (nm), at least 150 nm, or at least 200 nm. In another example, the minimum distance is selected to be between 100 nanometers and 500 nanometers. In yet another example, the minimum distance d is less than 600 nanometers.

[0056] Regardless of the specific way in which transition region 3 is implemented, there is a PN transition on the path along the shortest distance d between source region 11 and gate region 21. Thus, the doping concentration of source region 11 decreases from its peak doping concentration as a starting value along this path in the direction of gate region 21. Equivalently, the doping concentration of gate region 21 decreases from its peak doping concentration as a starting value along this path in the direction of source region 11.

[0057] For example, the shortest distance d between source area 11 and gate area 21 is the shortest distance between a first position where the doping concentration of source area 11 has decreased to the first percentage point of its peak doping concentration, and a second position where the doping concentration of gate area 21 has decreased from its peak doping concentration to the second percentage point of its doping concentration. In other words, a boundary between source area 11 and transition area 3 is located at the first position, and a boundary between gate area 21 and transition area 3 is located at the second position.Between the first and second positions, transition area 3 has a doping concentration of the first doping type and lower than the first percentage of the peak doping concentration of source area 11 and / or a doping concentration of the second doping type and lower than the second percentage of the peak doping concentration of gate area 21.

[0058] According to another example, the distance between source area 11 and gate area 21 is less than 40% or less than 30% of the mesa width w.

[0059] For example, the width of source area 11, which is a dimension of source area 11 in the lateral direction x, is less than 30%, less than 25%, or less than 20%. The width of source area 11 is, for example, at least 10% of the mesa width w.

[0060] According to one example, the source area 11 is located essentially in the center of the mesa area 110, such that the distance between the source area 11 and each of the two opposite side walls 103 is essentially the same. However, this is only one example. It is also possible to implement the source area 11 such that it is spaced from both side walls 103, but has different distances to the two opposite side walls 103.

[0061] The presence of the transition region 3 between the source region 11 and the gate region 21 is advantageous with regard to reducing leakage current in the transistor device. This is explained below.

[0062] For the sake of clarity, it is assumed that transition region 3 is omitted, so that source region 11 borders gate region 21. Based on the foregoing, gate region 21 can have a doping concentration higher than 1 x 18 cm⁻¹. -3 is, and source area 11 can have a doping concentration higher than 1E19 cm -3If source region 11 borders gate region 21, a PN transition is formed directly between them. Within the PN transition region, the doping concentration changes from the first-type doping concentration of source region 11 to the second-type doping concentration of gate region 21. The dimension (length) of the region where this change in doping concentration occurs can range from a few nanometers to several tens of nanometers, such as approximately 30 nanometers. This is significantly shorter than the minimum distance d between source region 11 and gate region 21 when a transition region 3 is present.

[0063] In the off state of the transistor device, the PN junction between source region 11 and gate region 21 is reverse-biased. Due to the high doping concentrations of source region 11 on one side and gate region 21 on the other, the reverse bias of the PN junction can cause band-to-band tunneling (BTBT), which is a source of leakage current between gate node G and source node S in the off state of the transistor device. Furthermore, the formation of the highly doped source and gate regions 11, 21 inevitably leads to crystal damage in the crystal lattice of the semiconductor body 100. If the PN junction is reverse biased, a space charge region (depletion region) expands in the source and gate regions 11, 21 on both sides of the PN junction.Crystal damage located in positions covered by the depletion region can act as generation centers for charge carriers, so such crystal damage is another source of leakage current between the gate node G and the source node S in the off state.

[0064] In the transistor device described above, where the transistor cells 1 include the transition region 3, the change in doping from the first doping type to the second doping type is smoother or more uniform compared to the situation without a transition region 3. Due to this gradual change, less BTBT occurs. Additionally, less charge carrier generation due to crystal damage near the PN junction may occur. Depending on the implementation of the transition region 3, a PN junction is formed between the first region 31 and the gate region 21 (see, for example, Figure 1). Fig. 6- Fig. 8), between the second areas 32 and the Source area 11 (see e.g. Fig. 9) or between the first and second areas 31, 32 (see e.g. Fig. 10- Fig. 11). In each case, at least one of the two regions forming the PN junction has a doping concentration lower than that of the respective region in the hypothetical case where the source region 11 borders the gate region 21, thus reducing both BTBT and charge carrier generation due to crystal damage. Furthermore, at a PN junction formed between doped regions with significantly different doping concentrations, the space charge region extends mainly in the doped region with the lower doping concentration, so that any crystal damage that may be present in the more highly doped region cannot be covered by the space charge region and is therefore ineffective in generating a leak current.

[0065] With reference to the above, the source regions 11 of the individual transistor cells 1 are connected to the source node S, and the gate regions 21 are connected to the gate node G. An example of connecting the source regions 11 to the source node S and the gate regions 21 to the gate node G is shown in Fig. 12 illustrated.

[0066] Fig. Figure 12 illustrates a vertical cross-sectional view of a section of the semiconductor body 100. In the Fig. In the illustrated example 12, the source regions 11 of the transistor cells are connected to a source electrode (source metallization) 41, which forms the source node S or is connected to the source node S. The source electrode 41 is connected to each of the source nodes 11. The material of the source electrode 41 and the doping concentration of the source regions 11 are matched to each other so that ohmic contacts are formed between the source electrode 41 and the source regions 11. Doping concentrations of the source regions 11 higher than 1E19 cm⁻¹ -3As explained above, these are sufficient to achieve ohmic contacts. The source metallization 41 comprises a metal, such as copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), or an alloy, such as an alloy containing two or more of copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), or the like. For example, the source metallization 41 comprises a first layer of an electrically conductive material in contact with the source regions 11, and a second layer above the first layer. The second layer comprises a material different from the first layer.

[0067] With reference to Fig. In Figure 12, the gate regions 21 are connected to gate electrodes 51 formed in the trenches 120. The gate electrodes 51 are connected to the gate node G, so that the gate regions 21 are connected to the gate node G via the gate electrodes 51. An example of connecting the gate electrodes 51 to the gate node G is shown in Figure 12. Fig. 13 illustrated.

[0068] Each gate electrode 51 is formed in a respective trench 120 such that the gate electrode 51 covers at least sections of the side walls 103 and / or sections of the bottom 102 of the trench 120. In the Fig. In the illustrated example 12, the gate electrode 51 covers both the bottom 102 and sections of the side walls 103 of the respective trench. However, this is only one example.

[0069] According to another example, which is in Fig. As illustrated in dashed lines in Figure 12, the gate electrode 51 essentially only covers the bottom 102 of the respective trench 120 in order to connect the gate electrode 51 to the gate areas 21 formed under the bottom 102 and along the side walls 103 adjacent to the respective trench bottom 102.

[0070] According to one example, the doping concentrations of the gate regions 21 are high enough to form the gate regions 21 and the gate electrode 51 and to establish contact between them. The gate electrodes 51 comprise a highly doped polycrystalline semiconductor material, such as polysilicon. According to another example, the gate electrodes 51 comprise a metal selected from the same group of metals as the source metallization 4 described above. In this way, each of the gate electrodes 51 is electrically connected to the gate regions 21 adjacent to the side walls 103 and the bottom 102 of the trench 120 in which the gate electrode 51 is formed.

[0071] The gate electrodes 51 are electrically isolated from the source metallization 41 by insulating layers 42 formed between the source metallization 41 and the gate electrodes 51.

[0072] Fig. Figure 13 shows a top view of the transistor device according to one of the examples explained above. In particular, it shows Fig. Figure 13 shows a top view of the semiconductor body 100 with the source metallization 41. Examples of the gate electrodes 51 and their position under the source metallization 41 are shown in Figure 13. Fig. Figure 13 is illustrated in dashed lines. In this example, the gate electrodes 51 extend below and beyond the source metallization 42 and are connected to a gate runner 52. The gate runner 52 is formed above the insulating layer 42 and is connected to a gate pad 53. The gate pad 53 is connected to, or forms, the gate node G of the transistor device.

[0073] In some of the examples, such as the one in Fig. 6- Fig. 8 and Fig. 10- Fig. As illustrated in the 11 examples previously explained herein, the Source Area 11 is spaced apart from the side walls 103 of the Mesa Area 110 in which the Source Area 11 is formed. Fig. Figures 14A-14E illustrate an example of a self-aligned process for forming source regions 11 spaced from sidewalls 103 of the mesa regions 110. Each of the Fig. Figures 14A-14E illustrate a vertical cross-sectional view of a section of the semiconductor body 100 at different stages of the manufacturing process.

[0074] Fig. Figure 14A illustrates the semiconductor body 100 after the formation of the trenches 120 in the first surface 101. Forming the trenches 120 involves creating an etch mask 201 over the first surface 101. The etch mask 201 includes openings where the surface 101 is not covered. Etching the trenches 120 involves etching the trenches 120 in the openings, i.e., in those sections of the surface 101 that are not covered by the etch mask 201. The etch mask 201 is, for example, an oxide hard mask. According to another example, the etch mask 201 includes a stack of layers made of different materials, one of which may be an oxide hard mask layer.

[0075] With reference to Fig. In section 14B, the method further includes forming sacrificial plugs 211 in the trenches 120 such that the sacrificial plugs 211 fill the trenches 120 and extend in the vertical direction z beyond the first surface 101, so that the sacrificial plugs 211 abut the sidewalls of the openings of the etching mask 201. The material of the sacrificial plugs 211 differs from the material of the etching mask 201 and the material of the semiconductor body 100 such that the sacrificial plugs 211 can be selectively etched relative to the material of the etching mask 201 and the material of the semiconductor body 100, while the material of the sacrificial plugs 211 is not damaged or only slightly damaged. The sacrificial plugs 211 can comprise a polycrystalline semiconductor material, such as polysilicon.

[0076] With reference to Fig. 14C, the etching mask 201 is removed after the sacrificial plugs 211 have been formed. As shown in Fig. As can be seen in Figure 14B, the sidewalls of the openings of the etching mask 21 are substantially aligned with the sidewalls of the trenches 120 and therefore with the sidewalls of the mesa areas 110 defined by the trenches 120. Consequently, after the removal of the etching mask 201, the sidewalls 212 of the sacrificial plugs 211, which extend beyond the first surface 101, are substantially aligned with the sidewalls 103 of the mesa areas 110.

[0077] With reference to Fig. Method 14D further includes the formation of spacers 221 on the side walls 212 of the sacrificial plugs 211. The formation of the spacers 221 can involve depositing a spacer layer over (e.g., on) the sacrificial plug 211 and on the side walls 212 of the sacrificial plug 211 and on the first surface 101 of the semiconductor body 100, and removing sections of the spacer layer in an anisotropic etching process, leaving the spacers 221 on the side walls 212 of the sacrificial plugs. The spacer layer is, for example, an oxide layer.

[0078] With reference to Fig. In 14E, the method further includes an implantation process in which dopant atoms of the first dopant type are implanted into those sections of the first surface 101 that are not covered by the spacers 221. In this way, source regions 11 are formed in the upper surfaces 101 of the mesa regions 110 at positions spaced from the side walls 103 of the mesa regions 110. The distance between the source region 11 and the side walls 103 is defined by the dimensions of the spacers 221 in the lateral direction x. According to an example, the dimensions of the spacers 221 in the lateral direction x are such that the source region 11 is formed at a position spaced between 200 nm and 400 nm, in particular between 250 nm and 350 nm, from the side walls 103.

[0079] In addition to implanting dopant atoms of the first doping type, the formation of the source regions 11 can involve a thermal process in which the implanted dopant atoms of the first doping type are activated.

[0080] Examples of the formation of Gate Areas 21 and Canal Areas 12 are given below with reference to the Fig. 15 and Fig. 16 explained. Each of the Fig. 15 and Fig. Figure 16 illustrates a vertical cross-sectional view of a section of the semiconductor body 100 during the respective manufacturing process.

[0081] With reference to Fig. 15 includes the formation of the gate regions 21 along the bottom 102 and the side walls 103 of the trenches 120 and the implantation of dopant atoms of the second doping type into the bottom 102 and the side walls 103. Different processes are possible for the formation of the gate regions 21 along the side walls 103 and along the bottom 102.

[0082] According to one example, only inclined implantation processes are used to form the gate regions 21. In this example, implantation angles are set such that in a first inclined implantation process, dopant atoms are implanted into one of the two opposite side walls 103 and the bottom 102, and in a second implantation process, dopant atoms are implanted into the other of the two opposite side walls 103 and the bottom 102. In this way, a higher dopant dose is implanted into the bottom 102, resulting in the more highly doped region 22.

[0083] In addition to implanting dopant atoms into soil 102 using two inclined implantation processes, dopant atoms can be implanted into soil 102 using a non-inclined (vertical) implantation process.

[0084] According to another example, dopant atoms are implanted into the base 102 using a non-tilted implantation process, dopant atoms are implanted into one of the two opposite sidewalls using a first inclined implantation process, and dopant atoms are implanted into the other of the two opposite sidewalls 103 using a second inclined implantation process. In this example, the implantation angles in the first and second inclined implantation processes are set such that dopant atoms are either not implanted into the base 102 or are implanted only to a negligible extent.

[0085] In addition to implanting the second type of dopant atoms, the formation of the gate regions 21 may involve a thermal process in which the implanted dopant atoms are activated.

[0086] With reference to Fig. 15 An implantation mask can be formed over (e.g., on) the upper surfaces 101 of the mesa regions 110 prior to the implantation process, the implantation mask protecting the upper surfaces 101 from the implantation of dopant atoms. According to one example, the etching mask 201 used to form the trenches 120 is used as the implantation mask.

[0087] With reference to Fig. 16 can involve the formation of the channel region 12, in particular the formation of the first regions 121 of the channel regions 12, and the implantation of dopant atoms of the first dopant type into the side walls 103 of the trenches 120 using inclined implantation processes. According to one example, implantation angles in the implantation processes for forming the first regions 121 are selected such that dopant atoms are implanted into the side walls 103 and the upper surface 101, but are not implanted into the bottom 102, or are implanted into the bottom 102 only to a negligible extent.

[0088] According to one example, the implantation doses for forming the first regions 121 of the channel regions 12 are significantly lower than the implantation doses for forming the gate regions 21. In this example, the implantation angles in the process for forming the first regions 121 do not necessarily need to be adjusted such that dopant atoms are not implanted into the bottom 102. This is because the second-type dopant atoms implanted into the bottom 102 to form the gate regions 21 can strongly predominate over the first-type dopant atoms implanted into the bottom 102 during the formation of the first regions 121, so that gate regions 21 with an effective doping concentration of the second dopant type are formed along the trench bottoms 102.

[0089] In addition to implanting the dopant atoms of the first type, the formation of the first regions 121 may involve a thermal process in which the implanted dopant atoms are activated.

[0090] The formation of the optional third regions 123 can involve a further inclined implantation process in which first-type dopant atoms are implanted into the sidewalls 103 of the mesa regions 110. Optionally, an implantation mask, such as the etching mask 201, formed over (e.g., on) the upper surfaces 101 of the mesa regions 110, protects the upper surfaces 101 from the implantation of dopant atoms.

[0091] Fig. Figure 17 illustrates an example of a procedure in which the same implantation processes are used to form the transition regions 3 and the first regions 121 of the canal regions 12. With reference to Fig. 17 This method includes inclined implantation processes after removal of the etching mask 201. The inclined implantation processes comprise at least two inclined implantation processes, wherein in each of these inclined implantation processes dopant atoms of the first type are implanted into one of the side walls 103 of the mesa regions 110 and into the upper surface 101, wherein dopant atoms implanted into the side walls 103 form the first regions 121 of the channel regions 12 and dopant atoms implanted into the upper surface 101 form the transition regions 3, in particular the first regions 31 of the transition regions 3. According to an example, implantation angles in the two implantation processes are selected such that dopant atoms are not implanted into the base 100 or are implanted into the base 102 only to a negligible extent.

[0092] Another example of the formation of transition areas, in particular the first areas 31 of the transition areas, is in Fig. 18A- Fig. Figure 18C illustrates this. Each of these figures shows a vertical cross-sectional view of the semiconductor body 100 at different stages of the manufacturing process.

[0093] With reference to Fig. In 18A, the process involves a surface-wide implantation in which dopant atoms of the first type are implanted into the first surface 101 of the first semiconductor body 100 to form a doped region 310 of the first doping type along the first surface 101. This implantation process takes place before the formation of the trenches 120.

[0094] With reference to Fig. 18B-18C includes forming the trenches 120 and forming the etching mask 201 over the first surface 101 (see Fig. 18B) and etching the trenches using the etching mask 201 (see Fig. 18C). The sections of the doped area 310 remaining after the formation of the trenches 120 constitute the first areas 31 of the gate-source drift areas 3. The source areas 11 can be determined using the process according to the Fig. 14A-14E are formed after the formation of transition areas 3.

[0095] Some of the processes described herein can have the effect of both dopant atoms of the first dopant type and dopant atoms of the second dopant type being implanted into the same region of mesa area 110. Referring to the Fig. The illustrated example 15 can involve the formation of the gate regions 21 and the implantation of dopant atoms of the second type into the side walls 103. Furthermore, with reference to the [reference to the following] Fig. 17 and Fig. The 18 illustrated examples include the formation of the transition region 3 and the implantation of dopant atoms of the first type into the upper surface 101 of the mesa regions 110. Thus, combining the procedure according to Fig. 15 using one of the procedures according to the Fig. 17 and Fig. 18 to a transition region 3, which in a corner region of the mesa region 110 contains dopant atoms of the first doping type and dopant atoms of the second doping type. A “corner region” of the mesa region 110 is a region that borders both the upper surface 101 and a side wall 103.

[0096] A transition area 3, which consists of a combination of the process according to Fig. 15 and one of the processes according to the Fig. 17 and Fig. 18 is in Fig. 19 illustrated in more detail. With reference to Fig. 19 The transition region 3 includes a first region 31, which results from the implantation of dopant atoms of the first type into the upper surface 101 in one of the processes according to the Fig. 17 and Fig. 18, and a third region 33. The third region 33 is located in the corner region of mesa region 110, borders the first region 31 and the gate region 21, and contains dopant atoms of the first type, which result from one of the processes according to the Fig. 17 and Fig. 18 result, and dopant atoms of the second type, which result from the process according to Fig.15. The effective doping concentration of the third region 33 is either of the first doping type or of the second doping type. According to an example, the third region 33 is of the second doping type. Due to the presence of atoms of the first doping type in the third region 33, the effective doping concentration of the third region 33 is lower than the effective doping concentration of the adjacent gate regions 21. Thus, the third region 33 is a second region 32 of the type described above, that is, a doped region of the second doping type, which has a lower doping concentration than the gate region 21. The third region 33 is spaced from the source region 11 and separated from the source region 11 by the first region 31, which is located between the source region 11 and the third region 33. Some aspects of the transistor device and the procedure described above are briefly summarized below.

[0097] According to one example, the transistor device comprises a semiconductor body with a plurality of mesa regions; and a plurality of transistor cells, each formed within one of the plurality of mesa regions. Each transistor cell comprises a source region of a first dopant type; a gate region of a second dopant type, complementary to the first dopant type and spaced apart from the source region; a channel region of the first dopant type; and a transition region distinct from both the source region and the gate region. The transition region is situated between the source region and the gate region and is adjacent to both.

[0098] The transition region may include a first region of the first doping type adjacent to the source region, where the peak doping concentration of the first region is less than a first percentage of the peak doping concentration of the source region. For example, the first percentage is less than 10%, less than 1%, or less than 0.1%. In one example, the first region borders the gate region.

[0099] In addition to or as an alternative to the first area, the transition area may include a second area of ​​the second doping type adjacent to the gate area, where the peak doping concentration of the second area is less than a second percentage of the peak doping concentration of the gate area. The first percentage is less than 50%, less than 33%, less than 20%, or less than 10%.

[0100] In one example, the transition region is free of the first region, so the second region borders the source region. In another example, the transition region includes both the first and second regions, with the second region bordering the first.

[0101] For example, the shortest distance between the source region and the gate region via the transition region is at least 100 nanometers, at least 150 nanometers, or at least 200 nanometers. The shortest distance between the source region and the gate region via the transition region can be the shortest distance between a first position in the source region where the doping concentration is equal to the first percentage point of the peak doping concentration of the source region, and a second position in the gate region where the doping concentration is equal to the second percentage point of the peak doping concentration of the gate region.

[0102] The canal area can border the gate area and be connected to the source area.

[0103] According to one example, the transistor device further includes a drift region of the first doping type, which is adjacent to the channel regions of the transistor cells. Furthermore, a drain region of the first doping type can be adjacent to the drift region and separated from the channel regions of the transistor cells by the drift region.

[0104] A source electrode can be ohmically connected to the source regions of the transistor cells.

[0105] For example, the peak doping concentration of the source area is higher than 1E19 cm. -3 According to one example, the peak doping concentration of the gate region is higher than 1E18 cm³. -3 .

[0106] According to one example, the method involves forming trenches in a first surface of a semiconductor body, creating mesa regions of the semiconductor body, with each mesa region located between adjacent trenches. The formation of the trenches involves an etching process using an etch mask formed over the first surface. The method further involves forming sacrificial plugs in the trenches, such that the sacrificial plugs fill the trenches and extend beyond the first surface in a vertical direction of the semiconductor. The etch mask is then removed, exposing the sidewalls of the sacrificial plugs. Spacers are formed on the sidewalls of the sacrificial plugs, and source regions of a first dopant type are formed in the mesa regions.Forming the source regions involves implanting dopant atoms of the first doping type into the first surface using the sacrificial plugs and spacers as an implantation mask.

[0107] The process can further include the formation of at least one gate region of a second dopant type, complementary to the dopant type in each of the mesa regions. The formation of the at least one gate region can involve the implantation of dopant atoms of the second dopant type into the respective mesa region via a sidewall prior to the formation of the sacrificial plugs.

[0108] Furthermore, the method can involve the formation of at least one channel region of the first doping type in each of the mesa regions. The formation of the at least one channel region can involve the implantation of dopant atoms of the second doping type into the respective mesa region via a sidewall prior to the formation of the sacrificial plugs.

[0109] According to one example, the procedure further includes the removal of the sacrificial plugs, wherein the formation of the at least one channel region involves the implantation of dopant atoms of the first dopant type into the respective mesa region via a side wall of the respective mesa region after the removal of the sacrificial plugs.

[0110] Furthermore, at least one transition region can be formed in each of the mesa regions. For example, forming the at least one transition region involves forming a first region of the first dopant type in the respective mesa region. Forming the first region can involve implanting dopant atoms of the first dopant type into the semiconductor body via the first surface prior to etching the mask.

[0111] According to another example, the procedure further involves the removal of the sacrificial plugs, wherein the formation of the first region involves the implantation of dopant atoms of the first dopant type via the first surface into the respective mesa region after the removal of the sacrificial plugs.

[0112] The formation of the at least one canal region and the first region of the transition region may involve the formation of the at least one canal region and the first region of the transition region using the same implantation processes.

Claims

[1] Transistor device comprising: a semiconductor body (100) comprising a plurality of mesa regions (110); and a plurality of transistor cells (1) each formed in a respective one of the plurality of mesa regions (110), wherein each transistor cell (1) comprises: a source region (11) of a first doping type; a gate region (21) of a second doping type complementary to the first doping type and spaced from the source region (11); a channel region (12) of the first doping type; and a transition region (3) which is different from the source region (11) and the gate region (21), wherein the transition region (3) is arranged between the source region (11) and the gate region (21) and adjoins both the source region (11) and the gate region (21). [2] Transistor device according to claim 1, wherein the transition region (3) comprises a first region (31) of the first doping type, which adjoins the source region (11), wherein a peak doping concentration of the first region (31) is less than a first percentage of the peak doping concentration of the source region (11). [3] The transistor device of claim 2, wherein the first percentage is less than 10%, less than 1%, or less than 0.1%. [4] The transistor device of claim 2 or 3, wherein the first region (31) is further adjacent to the gate region (21). [5] Transistor device according to one of claims 1 to 4, wherein the transition region (3) comprises a second region (32) of the second doping type, which adjoins the gate region (21), wherein a peak doping concentration of the second region (32) is less than a second percentage of a peak doping concentration of the gate region (21). [6] The transistor device of claim 5, wherein the second percentage is less than 50%, less than 33%, less than 20%, or less than 10%. [7] The transistor device of claim 5 or 6, wherein the second region (32) further adjoins the source region (11). [8] Transistor device according to one of the preceding claims, wherein the transition region (3) comprises both the first region (31) and the second region (32), wherein the second region (32) is adjacent to the first region (31). [9] Transistor device according to one of the preceding claims, wherein a shortest distance between the source region (11) and the gate region across the junction region (3) (21) is at least 100 nanometers, at least 150 nanometers or at least 200 nanometers. [10] The transistor device of claim 9, wherein the shortest distance between the source region (11) and the gate region (21) across the junction region (3) is the shortest distance between a first position in the source region (11) at which the doping concentration is equal to the first percentage of the peak doping concentration of the source region (11) and a second position in the gate region (21) at which the doping concentration is equal to the second percentage of the peak doping concentration of the gate region (21). [11] A transistor device according to any one of the preceding claims, wherein the channel region (12) is adjacent to the gate region (21) and is connected to the source region (11). [12] A transistor device according to any one of the preceding claims, further comprising: a drift region (13) of the first doping type, which borders the channel regions (12) of the transistor cells (1). [13] The transistor device of claim 12, further comprising: a drain region (14) of the first doping type, which adjoins the drift region (13) and is separated from the channel regions (12) of the transistor cells (1) by the drift region. [14] Transistor device according to one of the preceding claims, further comprising a source electrode (42) which is ohmically connected to the source regions (11) of the transistor cells (1). [15] A transistor device according to any one of the preceding claims, wherein the peak doping concentration of the source region (11) is higher than 1E19 cm -3 is. [16] A transistor device according to any one of the preceding claims, wherein the peak doping concentration of the gate region (11) is higher than 1E18 cm -3 is. [17] Method comprising: Forming trenches (120) in a first surface (101) of a semiconductor body (100) such that mesa regions (110) of the semiconductor body (100) are formed, each mesa region (110) being located between adjacent trenches (120), wherein forming the trenches (120) includes an etching process using an etch mask (201) formed over the first surface (101); Forming sacrificial plugs (211) in the trenches (120) such that the sacrificial plugs (211) fill the trenches (120) and extend beyond the first surface (101) in a vertical direction of the semiconductor (100); Removing the etching mask (201) so that side walls (212) of the sacrificial plugs (211) are exposed; Forming spacers (221) on the side walls (212) of the sacrificial plugs (211); and Forming source regions (11) of a first doping type in the mesa regions (110), wherein forming the source regions (11) comprises implanting dopant atoms of the first doping type into the first surface (101) using the sacrificial plugs (210) and the spacers (221) as an implantation mask. [18] The method of claim 17, further comprising: Forming at least one gate region (21) of a second doping type complementary to the doping type in each of the mesa regions (110). [19] The method of claim 18, wherein forming the at least one gate region (21) comprises implanting dopant atoms of the second doping type via a sidewall (103) of the respective mesa region (110) into the respective mesa region (110) prior to forming the sacrificial plugs (211). [20] A method according to any one of claims 17 to 19, further comprising: Forming at least one channel region (121) of the first doping type in each of the mesa regions (110). [21] The method of claim 20, wherein forming the at least one channel region (121) comprises implanting dopant atoms of the second doping type via a sidewall (103) of the respective mesa region (110) into the respective mesa region (110) prior to forming the sacrificial plugs (211). [22] Method according to claim 20, the method further comprising removing the sacrificial plugs (211), and wherein forming the at least one channel region (121) comprises implanting dopant atoms of the first doping type via a sidewall (103) of the respective mesa region (110) into the respective mesa region (110) after removing the sacrificial plugs (211). [23] A method according to any one of claims 17 to 22, further comprising: Forming at least one transition region (3) in each of the mesa regions (110). [24] The method of claim 23, wherein forming the at least one transition region (3) comprises forming a first region (31) of the first doping type in the respective mesa region (110). [25] Method according to claim 24, wherein forming the first region (31) comprises implanting dopant atoms of the first doping type via the first surface (101) into the semiconductor body (100) prior to forming the etch mask (201). [26] Method according to claim 23, the method further comprising removing the sacrificial plugs (211), and wherein forming the first region (31) comprises implanting dopant atoms of the first doping type via the first surface (101) into the respective mesa region (110) after removing the sacrificial plugs (211). [27] The method of claims 22 and 26, wherein forming the at least one channel region (121) and the first region (31) of the transition region (3) comprises forming the at least one channel region (121) and the first region (31) of the transition region (3) using the same implantation processes.

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