ANALOG-TO-DIGITAL CONVERTER

Abstract

An analog-to-digital converter for converting an analog signal into a digital signal by sampling the analog signal to generate the digital signal, wherein the analog-to-digital converter is configured to acquire a first sample having a first plurality of bits representative of the digital signal, to determine one or more variable bit positions in the first plurality of bits, to determine one or more static bit positions in the first plurality of bits, and to acquire a second sample after the first sample has been acquired, wherein the second sample has a second plurality of bits representative of the digital signal, wherein for acquiring the second sample, the bit values ​​of at least some of the variable bit positions are generated by sampling the analog signal.and the bit values ​​of each of the one or more static bit positions are set to the same bit value as the bit value of the corresponding bit position in the first sample.

Description

[0001] The present disclosure relates to an analog-to-digital converter. More particularly, the present disclosure relates to an analog-to-digital converter for converting an analog signal into a digital signal by sampling the analog signal to generate the digital signal. BACKGROUND

[0002] Fig. 1 is a schematic diagram of an analog-to-digital converter (ADC) 100. The ADC 100 is a successive approximation register (SAR) ADC that uses oversampling (OVS).

[0003] OVS is a process in which an input signal is repeatedly digitized to obtain data at a sampling frequency higher than the Nyquist rate. OVS can be used to increase the signal-to-noise ratio (SNR) and increase the effective resolution of the sampled data.

[0004] The effective resolution is described by the effective number of bits (ENOB). For example, a system may have a resolution of 8 bits, but due to noise, only 6 bits remain unaffected by noise, resulting in an ENOB of 6 bits. Noise is believed to be the primary factor affecting ENOB.

[0005] The SAR ADC 100 includes a digital-to-analog converter (DAC) 102, a sample and hold circuit 104, a comparator 106, a SAR logic circuit 108, and an accumulator 110.

[0006] The SAR-ADC 100 receives an input voltage Vin, i.e., an analog signal to be converted. The SAR-ADC 100 also receives a reference voltage Vref.

[0007] In operation, sample-and-hold circuit 104 receives the input voltage Vin. The input voltage Vin is sampled and held at a fixed value for a specified period of time. At a later time, the input voltage Vin is then sampled and held again, repeating the process so that an output signal provided by circuit 104 comprises a series of constant voltage values ​​over successive periods of time representative of the input voltage Vin.

[0008] In operation, comparator 106 compares the input voltage Vin processed by circuit 104 with the output of DAC 102. SAR logic circuit 108 provides a digital code representative of the input voltage Vin to DAC 102. DAC 102, using reference voltage Vref, converts the digital code into an analog value, which is provided to comparator 106.

[0009] The most common SAR ADC structure uses sample and hold and DAC blocks combined in a capacitive DAC block. This DAC uses the principle of charge redistribution, while the sampling and conversion logic of the ADC remains the same as in the circuit of Fig. 1.

[0010] The successive approximation process involves generating the bits of the digital code representing the input voltage Vin sequentially. For example, the most significant bit (MSB) is generated first, with subsequent processing used to determine additional bits of incrementally lower significance, so that with each determined bit, the signal becomes more accurate in generating the digital signal representative of the analog signal (the input voltage Vin).

[0011] The operation of the SAR ADC is well known to those skilled in the art. Accumulator 110 stores each sample from the process and then calculates the result.

[0012] Well-known ADCs that use oversampling are described in: 1. STMicroelectronics, "STM32L4+ Series advanced Arm®-based 32-bit MCUs," RM0432 Reference Manual Rev 9, June 2021, pp. 670-671. https: / / www.st.com / resource / en / reference_manual / rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf (accessed January 10, 2023) 2. Analog Devices, Inc., “4-Channel, 4 MSPS, 16-Bit / 14-Bit / 12-Bit, Dual, Simultaneous Sampling SAR ADCs,” AD7386 / AD7387 / AD7388 Datasheet rev. A, 2019, p. 37 https: / / www.analog.com / media / en / technical-documentation / datasheets / ad7386-7387-7388.pdf (accessed January 10, 2023)

[0013] The disadvantage of these devices is the longer time to obtain the oversampling result compared to a typical sampling process and the resulting higher power consumption when using an oversampling unit. SUMMARY

[0014] It is desirable to provide an ADC that has an advantage over known ADC designs.

[0015] In particular, it is desirable to provide an ADC (such as an oversampling ADC) that is faster and has reduced power consumption compared to known systems.

[0016] According to a first aspect of the disclosure, an analog-to-digital converter is provided for converting an analog signal into a digital signal by sampling the analog signal to generate the digital signal, wherein the analog-to-digital converter is configured to acquire a first sample value having a first plurality of bits representative of the digital signal, determine one or more bit positions in the first plurality of bits that are variable, determine one or more bit positions in the first plurality of bits that are static, and acquire a second sample value after the first sample value has been acquired, wherein the second sample value has a second plurality of bits representative of the digital signal, wherein for acquiring the second sample value, the bit values ​​of at least a portion of the one or more bit positions that are variable are generated by sampling the analog signal,and the bit values ​​of the one or more bit positions that are static are set to the same bit value as the bit value of the corresponding bit position in the first sample.,

[0017] Optionally, the sampling of the analog signal to generate the digital signal includes oversampling.

[0018] Optionally, the analog-to-digital converter is configured to determine which of the one or more bit positions in the first plurality of bits that are variable require a measurement, and for acquiring the second sample value, the bit values ​​of each of the one or more bit positions that require a measurement are generated by sampling the analog signal.

[0019] Optionally, the analog-to-digital converter is configured to receive a number of noise bits and to determine the one or more bit positions in the first plurality of bits that are variable using the first sample value and the number of noise bits.

[0020] Optionally, the noise bits are representative of the peak-to-peak noise of the digitized input signal.

[0021] Optionally, the analog-to-digital converter is configured to determine the one or more bit positions in the first plurality of bits that are variable using the first sample and the number of noise bits, by determining a noise range for the first sample and assessing which of the bit positions of the first sample are variable over the noise range.

[0022] Optionally, the analog-to-digital converter is configured to determine the noise range for the first sample by determining an upper noise estimate of the first sample by adding the peak-to-peak noise to the first sample and determining a lower noise estimate of the first sample by subtracting the peak-to-peak noise from the first sample.

[0023] Optionally, the analog-to-digital converter is configured to determine which of the one or more bit positions in the first plurality of bits that are variable require a measurement, and for acquiring the second sample value, the bit values ​​of each of the one or more bit positions that require a measurement are generated by sampling the analog signal.

[0024] Optionally, the number of bit positions requiring measurement is equal to the number of noise bits plus two.

[0025] Optionally, the bit positions that are variable include the noise bits, a double noise bit, transmission bits, and a full noise bit, and the bit positions that require measurement are the noise bits, the double noise bit, and the full noise bit.

[0026] Optionally, the bit positions of the noise bits are the least significant bits.

[0027] Optionally, the double noise bit has a bit position that is one bit position to the left of the noise bits.

[0028] Optionally, the transmit bits are the bits to the left of the double noise bit with the same bit values ​​as the double noise bits and to the right of the next bit with a different value, where the next bit with a different value is the full noise bit.

[0029] Optionally, the analog-to-digital converter is configured to acquire the second sample value, the bit values ​​of each of the noise bits, the double noise bit, and the full noise bit are generated by sampling the analog signal, and the values ​​of the transmission bits are set to the inverted value of the full noise bit.

[0030] Optionally, the analog-to-digital converter is an analog-to-digital converter with a successive approximation register.

[0031] Optionally, the analog-to-digital converter comprises a sample and hold circuit configured to receive an input voltage, a digital-to-analog converter configured to receive a reference voltage, a comparator configured to receive a first signal from the digital-to-analog converter and a second signal from the sample and hold circuit, and a SAR logic circuit configured to receive a comparator output signal from the comparator and to provide an SAR output signal to the digital-to-analog converter.

[0032] Optionally, the analog-to-digital converter comprises an accumulator configured to store the first sample value and to calculate a result of the oversampling method using the first sample value.

[0033] Optionally, the analog-to-digital converter comprises a controller configured to receive the first sample, determine the one or more bit positions in the first plurality of bits that are variable, determine one or more bit positions in the first plurality of bits that are static, and control the SAR logic circuit such that, for acquiring the second sample, the bit values ​​of at least a portion of the one or more bit positions that are variable are generated by sampling the analog signal and the bit values ​​of each of the one or more bit positions that are static are set to the same bit value as the bit value of the corresponding bit positions in the first example.

[0034] Optionally, the controller is configured to determine which of the one or more bit positions in the first plurality of bits that are variable require a measurement and to control the SAR logic circuit such that, for acquiring the second sample value, the bit values ​​of each of the one or more bit positions that require a measurement are generated by sampling the analog signal.

[0035] Optionally, the controller is configured to receive a number of the noise bits and to determine the one or more bit positions in the first plurality of bits that are variable using the first sample value and the number of noise bits.

[0036] Optionally, the noise bits are representative of the peak-to-peak noise of the digitized input signal.

[0037] Optionally, the controller is configured to determine the one or more bit positions in the first plurality of bits that are variable using the first sample and the number of noise bits by determining a noise range for the first sample and assessing which of the bit positions of the first sample are variable over the noise range.

[0038] Optionally, the controller is configured to determine a noise range for the first sample by determining an upper noise estimate of the first sample by adding the peak-to-peak noise to the first sample and determining a lower noise estimate of the first sample by subtracting the peak-to-peak noise from the first sample.

[0039] Optionally, the analog-to-digital converter comprises an accumulator configured to store the first sample value and the second sample value and to calculate a result of the oversampling method using the first and the second sample value.

[0040] Optionally, the analog-to-digital converter is configured to acquire a third sample after acquiring the second sample, the third sample having a third plurality of bits representative of the digital signal.

[0041] Optionally, the analog-to-digital converter is configured to acquire a fourth sample after acquiring the third sample, the fourth sample having a fourth plurality of bits representative of the digital signal.

[0042] Optionally, the third and / or fourth sample are acquired using one or more of the features described with respect to the second sample of the first aspect.

[0043] According to a second aspect of the disclosure, a method is provided for converting an analog signal into a digital signal using an analog-to-digital converter by sampling the analog signal to generate the digital signal, the method comprising acquiring a first sample having a first plurality of bits representative of the digital signal, determining one or more bit positions in the first plurality of bits that are variable, determining one or more bit positions in the first plurality of bits that are static, and acquiring a second sample after acquiring the first sample, the second sample having a second plurality of bits representative of the digital signal, wherein for acquiring the second sample, the bit values ​​of at least a portion of the one or more bit positions that are variable,generated by sampling the analog signal, and the bit values ​​of each of the one or more bit positions that are statistical are set to the same bit value as the bit value of the corresponding bit position in the first sample.

[0044] It will be appreciated that the method of the second aspect may comprise providing and / or using features set out in the first aspect and may comprise other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The disclosure will now be described in more detail by way of example and with reference to the accompanying drawings, in which: Fig. 1 is a schematic diagram of an analog-to-digital converter (ADC) 100; Fig. 2(a) is a schematic diagram of an ADC according to a first embodiment of the present disclosure, Fig. Figure 2(b) is a diagram showing the analog signal and the samples 208 that form the digital signal; Fig. 3(a) is a table showing a first sample and an estimate of possible subsequent samples based on an estimate of the noise, Fig. 3(b) the first sample of Fig. 3(a) shows; Fig. 4 is a schematic diagram of an ADC according to a second embodiment of the present disclosure; Fig. 5 is a flowchart showing the operation of the ADC of Fig. 4 describes; Fig. 6(a) is a diagram showing an output for a 2-bit ADC, Fig. Figure 6(b) is a diagram showing an output for a 3-bit ADC, and Fig. 6(c) is a diagram showing four transformations of the signal with noise; and Fig. Figure 7 is a graph showing example results of an accumulator with a 2-bit ADC using oversampling. DETAILED DESCRIPTION

[0046] Fig. 2(a) is a schematic diagram of an ADC 200 for converting an analog signal 202 into a digital signal 204 using a sampling operation and in accordance with a first embodiment of the present disclosure.

[0047] Fig. Figure 2(b) is a diagram showing the analog signal 202 varying over an oversampling period 205 and the samples 208 forming the digital signal 204 with one bit of noise.

[0048] In operation, the ADC 200 acquires a first sample having a first plurality of bits representative of the digital signal 204.

[0049] The ADC 200 then determines which bit positions in the first plurality of bits are variable and which positions are static before acquiring a second sample. The second sample comprises a second plurality of bits representative of the digital signal 204.

[0050] The ADC 200 may determine which bit positions in the first plurality of bits are variable within a sampling period and which positions are static before acquiring a second sample. The sampling period may be an oversampling period if the sampling of the analog signal 202 to generate the digital signal 204 involves oversampling.

[0051] For acquiring the second sample value, the bit values ​​of at least a portion of the one or more bit positions that are variable are generated by sampling the analog signal 202.

[0052] It is obvious that the description focuses on acquiring the second sample. However, further embodiments of the present disclosure may include acquiring at least one subsequent sample using the same methods described with respect to the second sample. All samples may be acquired in a single sampling period, for example, in an oversampling period. Preferably, an oversampling period comprises acquiring four or more samples.

[0053] During operation, the ADC 200 determines bit positions in the first plurality of bits that are static because they do not change, or are unlikely to change, between samples. To acquire the second sample, the bit values ​​of all static bit positions are set to the same bit value as the corresponding bit position in the first sample.

[0054] In a specific embodiment, all variable bit values ​​may be generated by sampling. For example, the first sample may have the following 8 bits: 10010101. During operation, the ADC 200 would determine which bit positions of the 8 bits are variable. For example, in the present case, the two least significant bits may be considered variable. The remaining bits may be considered static.

[0055] Therefore, when acquiring the second sample, only the two least significant bits are sampled. The remaining bits can be the same as the corresponding bits of the first sample. The resulting second sample can be 10010111.

[0056] In an alternative embodiment, only a subset of variable bit values ​​may be generated by sampling, while the other variable bit values ​​are determined in another way.

[0057] For example, it may be possible to derive the bit value of a variable bit based on the value of another bit in a different bit position. This is possible due to the binary-weighted structure of the ADC's successive approximation register. In this case, a measurement or determination of the other bit may be sufficient to know the value of the variable bit, making the measurement of the variable bit unnecessary.

[0058] For example, it may be possible to derive the bit value of a plurality of variable bits based on the value of a plurality of other bits in other bit positions. This is possible due to the binary-weighted structure of the ADC's successive approximation register. In this case, measuring or determining the other bits may be sufficient to know the value of the variable bits, making measuring the variable bits unnecessary.

[0059] This is in Fig. 2(b) 208, 210. The variable bit 210 must be measured, while all other bits can be derived based on the value of bit 210.

[0060] For example, the first sample may have the following 8 bits: 10010101. During operation, the ADC 200 would determine which bit positions of the 8 bits are variable. For example, in this case, the two least significant bits may be considered variable. The remaining bits may be considered static.

[0061] The variable bits are the two rightmost bits, "01." Through analysis or other means, it can be known that the leftmost variable bit always has an inverted value of the rightmost variable bit. Therefore, only measuring one of these two bits is necessary to know the value of the other.

[0062] Therefore, when acquiring the second sample, only the least significant bits are sampled. The static bits can be the same as the corresponding bits of the first sample, and the leftmost variable bit can be the inverted value of the rightmost variable bit. The resulting second sample can be 10010110.

[0063] In a specific embodiment, ADC 200 may be configured to determine which of the variable bits require measurement. In operation, the second sample may then be acquired using sampling only for the bits that require measurement, while the other variable bits are determined in another way.

[0064] It will be appreciated that in further embodiments, the methods described herein may be applied to acquiring a subsequent sample or samples after the second sample, wherein only the variable bits are determined for acquiring each new sample.

[0065] Since it is not necessary to sample the analog signal 202 to generate all the bits of the second sample, there is a reduction in the sampling time and also the power consumption requirements of the ADC 200 compared to the ADC 100.

[0066] The sampling process may include oversampling and may provide "fast OVS." The proposed "fast OVS" method and apparatus enable a reduction in data acquisition time and power consumption of an ADC operating in the oversampling mode.

[0067] In a specific embodiment, the ADC 200 may receive a number of noise bits 206. The number of noise bits 206 is a number that indicates the number of bits susceptible to noise. The number of noise bits 206 may be a user-defined value. The noise bits may be representative of the maximum noise of the ADC 200. For example, the noise bits may represent the expected peak-to-peak noise of the entire system in the worst case, for example, the digitized input signal. The user may analyze the system to determine the expected maximum noise level and then use this information to set the number of noise bits 206.

[0068] The noise can originate not only from the ADC 200, but also from other sources (PCB, external components, etc.). The input signal itself can also contain noise.

[0069] The ADC 200 may be configured to determine the one or more bit positions in the first plurality of bits that are variable using the first sample value and the number of noise bits 206.

[0070] The conditions for conventional OVS, as in relation to Fig. 1, as well as for the “fast OVS” method, with respect to the ADCs of the present disclosure, are: 1) The result of the conversion when generating the digital signal 204 contains noise 2) The analog signal 202 is treated as a constant over the oversampling period

[0071] The oversampling period refers to a period of time over which the oversampling process is performed. For example, both the first and second samples, as described previously, can be acquired in a single oversampling period.

[0072] In the ADC 200, the noise amplitude preferably does not exceed the selected noise parameter (number of noise bits) during an oversampling period.

[0073] To increase the resolution by one bit using OVS, the OVS ratio K OVS at least four (four samples): KOVS=4N where N is the desired number of additional resolution bits.

[0074] For example, if the resolution of the ADC 200 is 10 bits and the desired result resolution is 12 bits, then the OVS ratio K OVS = 16 samples (using equation (1)). The analog signal 202 should be sampled 16 times to obtain the 12-bit result.

[0075] Fig. Figure 2(b) is a diagram showing the analog signal 202 varying over an oversampling period 205 and the samples 208 forming the digital signal 204, with one bit of noise. The idea of ​​the "fast OVS" method of the present disclosure is as follows. The difference between the samples is several ADC counts during an oversampling period when operating in the OVS mode.

[0076] It is not necessary to measure all bits of the result of each sample. It is sufficient to measure only the variable bits that make up the result. However, the variable bit can be any bit of the result, not just the least significant bit, as shown by sample values ​​208. In the present example, an 8-bit ADC samples the signal, which changes by one count between counts 127 and 128.

[0077] In Fig. 2(b), all bits of the result data word are changed, but only one bit (see the column of numbers highlighted by reference numeral 210) can be measured to obtain the result. The "fast OVS" method of the present disclosure provides a method for determining the static bits and the variable bits, some of which are preferably sampled to obtain the result.

[0078] Fig. Figure 3(a) is a table showing a first sample 300 and an estimate of possible subsequent samples based on an estimate of the noise. Fig. 3(b) shows the first sample 300 of Fig. 3(a). This example refers to a SAR ADC using oversampling.

[0079] Returning to the ADC 200, in a specific embodiment, the variable bit positions may be determined by determining a noise range for the first sample and then assessing which of the bit positions are variable across the noise range.

[0080] The noise range can be determined by calculating upper and lower noise estimates, where the upper estimate is determined by adding the peak-to-peak noise to the first sample and the lower estimate is determined by subtracting the peak-to-peak noise from the first sample. As discussed above, the maximum noise for the system can be represented by the noise bits.

[0081] In the present example, the peak-to-peak noise of the acquisition system is 8 counts, which can be represented by 3 bits. Therefore, in this case, there would be 3 noise bits (meaning the number of noise bits is 206). The acquisition system can be a complete device: for example, a PCB with soldered external components, filters, ADC, etc.

[0082] In operation, the ADC 200 can perform a complete sampling / conversion process. Assuming, for example, that the ADC 200 is a 12-bit ADC, the result can be 1010 0011 1010, which is the first sample 300, as shown in Fig. 3(a) and Fig. 3(b) shown.

[0083] Since the subsequent samples can be within a range from (first sample + maximum noise) to (first sample - maximum noise), it can be assumed that the possible noise range is equal to the peak-to-peak noise multiplied by two. The possible range of ADC results that can be obtained during the OVS period, including noise, is Fig. 3(a).

[0084] In the present example, which is Fig. As shown in Figure 3(a), the seven bits starting on the right can vary across the possible noise range. However, only five bits require measurement (denoted by reference numeral 302). In the present example, the number of bits to be sampled is equal to the number of noise bits plus two.

[0085] In the description provided herein, bit positions are described in terms of "right" and "left" based on the conventional method of writing a binary number having a plurality of bits, where the leftmost bit is the most significant bit and the rightmost bit is the least significant bit.

[0086] The bit positions that are variable include noise bits 305, a double noise bit 304, transmit bits 306, and a full noise bit 308. The bit positions that require measurement are noise bits 305, the double noise bit 304, and the full noise bit 308. It is apparent that in further embodiments, the described categories of bit positions may include one or more bits and are not limited to the previously described form. For example, transmit bits 306 were described previously, but in another embodiment, there may be only a single transmit bit.

[0087] The bit positions of the noise bits 305 can be the least significant bits. In this example, the noise bits 305 are the three rightmost bit positions.

[0088] The double noise bit 304 has a bit position that is one bit position to the left of the noise bits 305.

[0089] The transmit bits 306 are the bits to the left of the double noise bit 304 with the same bit values ​​as the double noise bit 304 and to the right of the next bit with a different value, which is the full noise bit 308.

[0090] To acquire the second sample, the bit values ​​of each of the noise bits 305, the double noise bit 304, and the full noise bit 308 are generated by sampling the analog signal 204. The values ​​of the transmit bits 306 are set to the inverted value of the full noise bit 308.

[0091] In summary, and in the present embodiment, the classification of the bits forming the binary number can be described as follows: • Noise bits - correspond to the peak-to-peak noise of the acquisition system in the general case and the ADC noise in the specific case. This can be a user-defined value or the expected worst-case overall system noise. • Double noise bit - After obtaining the first sample, the possible noise range should be multiplied by 2, since the first result obtained may contain both the lower and the upper noise level (see Fig. 3(a)). • Full-noise bit - This bit has the same meaning as the double-noise bit. This bit should be measured due to the SAR structure of the ADC. • Transmit bits - These bits have an inverted value to the full-noise bit. These bits can only be measured once in the first sampling / conversion process. • Skip bits - These are the static bits, as previously described, and are unchanged bits during an oversampling period. These bits are measured only once in the first sampling / conversion process.

[0092] In summary, and in the present embodiment, the variable bits can be divided into the following two types: • Bits that depend on the input signal during an OVS period. These bits are preferably measured. These are noise bits, double noise bits, and full noise bits. • Bits that can be automatically defined (derived) based on previously measured bits. These bits should preferably not be measured. These are transmit bits (the inverted value of the full-noise bit).

[0093] Finally, there are static and variable bits. However, it is preferable not to measure all of the variable bits. Some of them (transmit bits) can be automatically defined based on the previously measured full-noise bit.

[0094] The variable bits may include bits that depend on the input signal and bits that can be defined based on the previously sampled bits.

[0095] An example regarding the variable bits is as follows.

[0096] For example, the ADC samples data, but it is known that the result can only be 151 (b)1001 0111 or 152 (b)1001 1000. Other data is not possible. The values ​​151 and 152 differ by 1, but due to the property of binary numbers, four digits (four bit positions) are changed in a binary representation. Finally, if it is known that the result can be either 151 or 152, it is sufficient to sample only a third bit of the result. In the current example, bit numbering starts at bit zero and counts from right to left. If the sampled bit is 1, all other bits to the right of the sampled bit are zero. Otherwise, if the sampled bit is 0, all other bits to the right of the sampled bit are 1.

[0097] In the case of an integrated circuit, the noise bits can be stored in memory registers. The user can program the number of noise bits or the number of bit positions in the memory registers before device operation. The ADC then uses the value stored in memory to analyze the samples during the oversampling period.

[0098] Fig. Figure 4 is a schematic diagram of an ADC 400 according to a second embodiment of the present disclosure. The ADC 200 is an example of a specific embodiment of the ADC 200. The ADC 400 is a successive approximation register (SAR) ADC.

[0099] The ADC 400 includes a sample and hold circuit 402 configured to receive an input voltage Vin. The ADC 400 includes a DAC 404 configured to receive a reference voltage Vref. The ADC 400 includes a comparator 406 configured to receive a first signal 408 from the DAC 404 and a second signal 410 from the sample and hold circuit 402. The ADC 400 further includes a SAR logic circuit 412 configured to receive a comparator output signal 414 from the comparator 404 and to provide an SAR output signal 416 to the DAC 404.

[0100] The output signal 416 may also be provided to the accumulator and the “fast OVS” logic circuit 412.

[0101] The ADC 400 may include an accumulator 418 to store the first sample. The accumulator 418 may be further configured to store the second sample. The accumulator 418 may be configured to store all samples of a single oversampling period. The accumulator 418 may be configured to calculate a result of the oversampling period using the stored samples.

[0102] An example describing the operation of accumulator 418 is as follows. Four samples are acquired during a fast OVS period. The acquired data: 1st sample is 151, 2nd is 151, 3rd is 152, 4th is 151. At the beginning of the OVS period (before the 1st sample), the accumulator (acc) is equal to 0. After the end of the 1st sample, acc=151. After the end of the 2nd sample, acc = 151+151=302. After the 3rd sample, acc = 302+152=454. After the last 4th sample, acc = 454+151=605. Then, after the 4th sample, the accumulator must also calculate the result of the oversampling, result = acc / 2=302.5 or 303 (rounded).

[0103] The ADC 400 may include a controller 420 configured to receive the first sample, determine the variable and static positions, and control the SAR logic circuit 412 to acquire the second sample, as previously described.

[0104] The controller 420 may be a small state machine executing a simple program (similar to a microcontroller core). Such state machines may be designed using an HDL language.

[0105] The controller 420 may be further configured to determine the bit positions requiring measurement and to control the SAR logic circuit 412 to generate the bit values ​​requiring measurement, as previously described.

[0106] The operation of the ADC 400 can be understood with reference to the description provided above and particularly with respect to the ADC 100 and the ADC 200, as will be apparent to those skilled in the art.

[0107] The controller 420 can be described as a “fast OVS” logic block implemented in a conventional SAR ADC structure, such as the one shown in Fig. 1 shown ADC 100.

[0108] In operation, the "fast OVS" logic block analyzes the first complete sample of the ADC data and then controls the SAR logic block 412 to measure the bits of each incoming data word. However, unlike a conventional SAR ADC, only a few bits that affect the result are measured during an oversampling period. The inputs to the "fast OVS" logic block 420 are the number of noise bits set by the user and the output of the SAR logic block, which provides the first sample of the ADC data.

[0109] The method assumes that only a few bits of the output data word change during an oversampling period. Other bits can be skipped or can be recovered using measured bits. In contrast, the conventional oversampling method requires all bits measured by the ADC to be sampled.

[0110] Fig. 5 is a flowchart 500 illustrating the operation of the ADC 400 of Fig. 4, and can be described as follows: 1. Set the "Noise_bits" value. The valid range is 1, 2, ..., [ADC resolution - 3]. 2. Perform a sampling / conversion operation to obtain the ADC result. Store the result in the accumulator. Then analyze the ADC result and define the bit position: • Find a double noise bit. This bit is the next bit from the left after the noise bits. • Finding transmit bits. These bits are the next bits from the left after the double-noise bit that have the same value as the double-noise bit. It can also happen that there are no transmit bits and the double-noise bit follows the full-noise bit. • Find the full-noise bit. This bit is the first bit from the left after the transmit bits that is not equal to the double-noise bit. • Finding skip bits. These bits are all the next bits to the left of the full-noise bit. These bits are not changed during the oversampling process. It's also possible that no skip bits are present. 3. All subsequent sampling / conversion iterations are performed M times in the loop. Where M = K OVS -1 • Obtaining a sample value (charging the sampling capacitor). • Set the internal DAC of the SAR ADC to the value of the skip bits. • Measure the full noise bit. • Setting the internal DAC to the value of the transmission bits using the condition: ◯ If the full noise bit is 0, all transmission bits = 1. ◯ Otherwise, each of the transmission bits = 0. • Measure all other bits (the double noise bit and the noise bits) using the conventional SAR principle. • Save the result in the accumulator (adding the current sample value to the accumulator data) 4. Calculate the result of the OVS procedure: Result=Acc⋅2NKOVS, where Acc is the accumulator data, K OVS is the oversampling ratio and N is the desired number of additional resolution bits.

[0111] The efficiency of the “fast OVS” method can be evaluated using the equation: Effciency=OVS_TimeFast_OVS_Time, where OVS_Time is the time required to perform a single conventional OVS operation and Fast_OVS_Time is the time required to perform a single fast OVS operation.

[0112] For the 12-bit ADC with sampling time t sample =1 bar, t conversion =12 clock cycles, peak-to-peak noise of 3 bits (8 counts) and oversampling ratio K O-VS =16 Efficiency=(1+12)⋅16(1+12)+(1+5)∗15≈2

[0113] In the current example, the “fast OVS” method allows to acquire data twice as fast and consume twice as little energy as competing devices.

[0114] A brief description of conventional oversampling is provided below.

[0115] In the case of the 2-bit ADC, the four possible output options are: (b)00=0 or (1 / 4)Vref, (b)01=1 or (2 / 4)Vref, (b)10=2 or (3 / 4)Vref, (b)11=3 or (4 / 4)Vref,

[0116] The offset of 1 between the digital code and Vref values ​​is due to the binary number format. Counting starts at zero.

[0117] It is desirable to increase the ADC resolution by 1 bit to obtain a 3-bit result using oversampling.

[0118] Fig. Figure 6(a) is a diagram showing an output for a 2-bit ADC. Fig. Figure 6(b) is a diagram showing the output of a 3-bit ADC. The signal applied to the inputs of the 2-bit ADC and the 3-bit ADC is the same.

[0119] Fig. Figure 6(c) is a diagram showing four conversions of the signal with noise applied to the input of the 2-bit ADC.

[0120] The 2-bit ADC output results are: 0th sample = 3, 1st sample = 3, 2nd sample = 2, 3rd sample = 3 (decimal numbers). Or 0th sample = (4 / 4)Vref, 1st sample = (4 / 4)Vref, 2nd sample = (3 / 4)Vref, 3rd sample = (4 / 4)Vref. To calculate the oversampling result, the sum of the four ADC samples must be divided by four. OVS result = (3 + 3 + 2 + 3) / 2 = 5.5 ≈ 6 (rounded, since the ADC operates on integers) or (7 / 8)Vref.

[0121] The following describes how an accumulator works. Fig.Figure 7 is a graph showing example results of an accumulator with a 2-bit ADC using oversampling.

[0122] The conventional accumulator is a long register that stores the sum of the input data. In embodiments of the present disclosure, the accumulator includes a function for calculating the result of oversampling.

[0123] The accumulator functions regardless of whether the input data is received using regular OVS or fast OVS. The accumulator's job is to sum the data samples and then calculate the OVS result at the end of the OVS period. From the accumulator's perspective, the difference between the regular OVS method and fast OVS is that the second and all subsequent samples of an OVS period reach the accumulator input more quickly when operating in "fast OVS" mode.

[0124] Various improvements and modifications may be made to the above without departing from the scope of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] STM32L4+ Series advanced Arm®-based 32-bit MCUs," RM0432 Reference Manual Rev 9, June 2021, pp. 670-671. https: / / www.st.com / resource / en / reference_manual / rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf (accessed January 10, 2023

[0012] ) 4-Channel, 4 MSPS, 16-Bit / 14-Bit / 12-Bit, Dual, Simultaneous Sampling SAR ADCs", AD7386 / AD7387 / AD7388 Datasheet rev. A, 2019, p. 37 https: / / www.analog.com / media / en / technical-documentation / datasheets / ad7386-7387-7388.pdf (accessed January 10, 2023

[0012]

Claims

[1] An analog-to-digital converter for converting an analog signal into a digital signal by sampling the analog signal to generate the digital signal, the analog-to-digital converter being configured to: Acquiring a first sample having a first plurality of bits representative of the digital signal; Determining one or more bit positions in the first plurality of bits that are variable; Determining one or more bit positions in the first plurality of bits that are static; and Acquiring a second sample after acquiring the first sample, the second sample having a second plurality of bits representative of the digital signal; wherein: for acquiring the second sample: i) the bit values ​​of at least a portion of the one or more bit positions that are variable are generated by sampling the analog signal; and ii) the bit values ​​of each of the one or more bit positions that are static are set to the same bit value as the bit value of the corresponding bit position in the first sample. [2] The analog-to-digital converter according to claim 1, which is configured to: Receiving a number of noise bits; and Determining the one or more bit positions in the first plurality of bits that are variable using the first sample value and the number of noise bits. [3] The analog-to-digital converter according to claim 2, which is configured to: Determining which of the one or more bit positions in the first plurality of bits that are variable require measurement; and for acquiring the second sample value, the bit values ​​of each of the one or multiple bit positions requiring measurement are generated by sampling the analog signal. [4] The analog-to-digital converter according to claim 3, wherein the bit positions that are variable include the noise bits, a double noise bit, transmission bits, and a full noise bit, and the bit positions that require measurement are the noise bits, the double noise bit, and the full noise bit. [5] The analog-to-digital converter of claim 4, wherein the bit positions of the noise bits are the least significant bits. [6] The analog-to-digital converter of claim 5, wherein the double noise bit has a bit position that is a bit position to the left of the noise bits. [7] The analog-to-digital converter of claim 6, wherein the transmit bits are the bits to the left of the double noise bit having the same bit values ​​as the double noise bits and to the right of the next bit having a different value, the next bit having a different value being the full noise bit. [8] The analog-to-digital converter according to claim 7, which is configured to: for acquiring the second sample value, the bit values ​​of each of the noise bits, the double noise bit and the full noise bit are generated by sampling the analog signal; and the values ​​of the transmission bits are set to the inverted value of the full noise bit. [9] The analog-to-digital converter of any preceding claim, wherein sampling the analog signal to generate the digital signal comprises oversampling. [10] The analog-to-digital converter according to claim 9, which is a successive approximation register analog-to-digital converter. [11] The analog-to-digital converter according to claim 10, comprising: a sample and hold circuit configured to receive an input voltage; a digital-to-analog converter configured to receive a reference voltage; a comparator configured to receive a first signal from the digital-to-analog converter and a second signal from the sample and hold circuit; and a SAR logic circuit configured to receive a comparator output signal from the comparator and provide a SAR output signal to the digital-to-analog converter. [12] The analog-to-digital converter of claim 11, comprising an accumulator configured to store the first sample and to calculate a result of the oversampling method using the first sample. [13] A method of converting an analog signal into a digital signal using an analog-to-digital converter by sampling the analog signal to generate the digital signal, the method comprising: Acquiring a first sample having a first plurality of bits representative of the digital signal; Determining one or more bit positions in the first plurality of bits that are variable; Determining one or more bit positions in the first plurality of bits that are static; and Acquiring a second sample after acquiring the first sample, the second sample having a second plurality of bits representative of the digital signal; wherein: for acquiring the second sample: i) the bit values ​​of at least a portion of the one or more bit positions that are variable are generated by sampling the analog signal; and ii) the bit values ​​of each of the one or more bit positions that are static are set to the same bit value as the bit value of the corresponding bit position in the first sample.

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