Methods for building modules
By defining a removal pattern based on the correlation of electrical properties for electronic modules, the method addresses the temperature issues associated with smaller chip sizes, resulting in improved module performance and efficiency.
Patent Information
- Application Number
- DE102023210712
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-10-30
- Publication Date
- 2025-04-30
AI Technical Summary
The reduction in chip size for electronic modules leads to increased temperature issues, which can be exacerbated by dissimilar components, limiting the optimization of module performance.
A method is developed to define a removal pattern that specifies a specific removal path for components on a wafer, taking into account the correlation of electrical properties of the components. This ensures that modules are populated with components that have similar electrical properties, reducing temperature development during operation.
The approach results in modules with reduced temperature optimization during operation, leading to improved performance and efficiency by ensuring similar electrical properties among components.
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Abstract
Description
[0001] The invention relates to a method for constructing modules, each of which is provided with at least two electronic components. Furthermore, the invention relates to a computer program, a device, and a system for this purpose. State of the art
[0002] It is known from the prior art that a picking pattern can be used to optimize the chip removal process in the production of symmetric modules. For example, a die bonder machine is used, which automatically removes chips from a wafer as part of a pick-and-place process and inserts them into the designated modules. The picking pattern defines, for example, the order and orientation of the chips during the pick-and-place process. Symmetric modules can be assemblies or components that have similar chips.
[0003] After wafer production, the chips are typically picked from the wafer and installed into the modules. However, this often results in chip quality degradation due to wafer manufacturing processes (e.g., slicing, polishing, lithography, or etching). Disclosure of the invention
[0004] The subject matter of the invention is a method having the features of claim 1, a computer program having the features of claim 9, a device having the features of claim 10, and a system having the features of claim 11. Further features and details of the invention emerge from the respective subclaims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the computer program according to the invention, the device according to the invention, and the system according to the invention, and vice versa, so that with regard to the disclosure of the individual aspects of the invention, reference is or can always be made to each other.
[0005] The invention particularly relates to a method for constructing modules, each of which is provided with at least two electronic components, in particular semiconductor components, preferably power semiconductors. The modules can be power modules, for example, and the components can be semiconductors such as power semiconductors (e.g., MOSFETs). The modules can be used, for example, for inverters that have multiple power modules.
[0006] One goal may generally be to reduce the size of the components, also referred to as chips. However, reducing chip size also entails an increase in temperature, so this optimization goal is limited by the temperature development on the modules. For example, the components on a module may influence the module's performance, e.g., by influencing temperature development. In particular, a higher temperature is often favored the more dissimilar the components used in the module are. Targeted optimization of the removal pattern to select components with similar electrical properties can help here.
[0007] According to a first method step of the method according to the invention, a removal pattern can first be defined that specifies a specific removal path for component positions on at least one wafer on which the components for constructing the modules are manufactured and / or provided. The removal path can, for example, be digitally stored in order to be retrieved during a removal process, in particular an automated one. Based on the removal path, control commands for at least one motor can, for example, be generated. The removal process can then be initiated according to a further method step. In this case, the components can be removed from the at least one wafer, in particular in an automated manner, along the removal path. The method according to the invention further comprises a further method step in which a construction process - which may also be automated - can be initiated.This allows the modules to be fitted with the removed components. This step can also be automated.
[0008] According to the invention, the removal path can be defined taking into account at least one correlation of electrical properties of the components and the component positions on the at least one wafer. Electrical properties that can be taken into account include, for example, parameters such as RDSON, the threshold voltage VTH, and / or QGD. RDS(ON) stands in particular for "drain-source on-resistance" and can refer to the resistance between the drain and source of a metal-oxide-semiconductor field-effect transistor (MOSFET) in the switched-on state. QGD stands in particular for "gate-drain charge" and can refer to the electrical charge that is redistributed between the gate and drain of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a similar transistor type during the switching process. The electrical properties can, for example, be specific to switching losses and conduction losses.The invention is based in particular on the realization that similar components also lead to more similar switching losses. This is often advantageous. However, the more dissimilar the components are, the more unfavorable the module's operation can be due to temperature development. The discharge path can be defined in particular such that a module is equipped with similar components, so that the temperature can be reduced during module operation.
[0009] Furthermore, within the scope of the invention, it is conceivable that the removal path is defined as a path that runs alternately in opposite directions in order to specify a continuous and / or repeating and / or zigzag-shaped and / or sawtooth-like trajectory on the at least one wafer. In other words, the removal path can be defined, taking into account the at least one correlation between the electrical properties of the components and the component positions on the at least one wafer, by defining the removal path as a path that runs alternately in opposite directions. This has the advantage that components removed successively in the removal process have similar electrical properties due to the removal path defined in this way, possibly even during a transition between two wafers.The modules are thus equipped with components that are electrically similar to achieve temperature optimization during module operation. Furthermore, the picking pattern can influence the process by taking potential defect zones on a wafer into account, thus ensuring that only the highest-quality chips are selected for assembly.
[0010] Furthermore, within the scope of the invention, it may be advantageous for the removal path to be defined as a path that runs circularly from an outer component position to an inner component position of the at least one wafer, in order to specify a continuous and / or spiral trajectory on the at least one wafer. This makes it possible to define the removal path, taking into account the at least one correlation between the electrical properties of the components and the component positions on the at least one wafer, such that components removed successively during the removal process have similar electrical properties.
[0011] Within the scope of the invention, it can be provided that the removal path is defined as a path that includes a change of direction if a transition (from a current wafer) to a subsequent wafer is planned during removal. This makes it possible to define the removal path, taking into account the at least one correlation between the electrical properties of the components and the component positions on the at least one wafer, such that components removed successively during the removal process have similar electrical properties, even during a transition between wafers.
[0012] In a further embodiment, the removal path can be defined as a path that runs circularly with multiple changes of direction on the respective wafer in order to define a continuous, semi-spiral trajectory on the at least one wafer. This also makes it possible to define the removal path, taking into account the at least one correlation between the electrical properties of the components and the component positions on the at least one wafer, such that components removed successively during the removal process have similar electrical properties.
[0013] Furthermore, it can be provided within the scope of the invention that when initiating the removal process, the following steps are repeatedly initiated: - Removing the components along the removal path from a current wafer until the removal of the components for the current wafer is completed, - Performing a transition from the current to a subsequent wafer, - Removing the components along the removal path from the subsequent wafer until the removal of the components for the subsequent wafer is completed.
[0014] Here, the removal path can be defined as a path where the removal of the components ends at the same component position for the current wafer after completion of the removal, where the removal continues for the subsequent wafer. This also allows for exploiting the correlation between the electrical properties of the components and the component positions on the at least one wafer.
[0015] Furthermore, it is advantageous if, within the scope of the invention, a removal machine, e.g., in the form of a die bonder, is controlled for the removal of the components along the removal path. Alternatively or additionally, the electronic components can be embodied as semiconductor components, preferably power semiconductors, with the respective module being equipped with at least three components. Thus, the components can form a functional structure, e.g., for power electronics, which is optimized by the removal pattern according to the invention.
[0016] The invention also relates to a system for constructing modules that are provided with at least two electronic components. The system can comprise a device for defining a removal pattern. As in the method according to the invention, the removal pattern can specify a specific removal path for component positions on at least one wafer. In the system according to the invention, the components can be provided on the at least one wafer for constructing the modules. Furthermore, the system according to the invention can comprise a removal machine for removing the components from the at least one wafer in a removal process. According to the invention, it can be provided that, in the removal process, the components are removed along the removal path, wherein the removal path is defined taking into account at least one correlation between the electrical properties of the components and the component positions on the at least one wafer. Thus, the system according to the invention provides the same advantages as those described in detail with reference to a method according to the invention. The device can also be designed as a data processing device according to the invention.
[0017] The invention also relates to a computer program, in particular a computer program product, comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. Thus, the computer program according to the invention provides the same advantages as those described in detail with reference to a method according to the invention.
[0018] The invention may also provide a data processing device configured to carry out the method according to the invention. The device may, for example, be a computer that executes the computer program according to the invention. The computer may have at least one processor for executing the computer program. A non-volatile data memory may also be provided, in which the computer program is stored and from which the computer program can be read by the processor for execution.
[0019] The invention may also provide a computer-readable storage medium that is part of the system according to the invention and / or has the computer program according to the invention and / or includes instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. The storage medium is designed, for example, as a data storage device such as a hard disk and / or a non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.
[0020] The steps of a method according to the invention can be performed repeatedly and / or automatically and / or computer-assisted. The method can also be implemented as a computer-implemented method.
[0021] Further advantages, features, and details of the invention will become apparent from the following description, which describes embodiments of the invention in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. They show: Fig. 1 a schematic visualization of a method, a system, a storage medium and a computer program according to embodiments of the invention. Fig. 2 a schematic representation of a temperature distribution for the manufactured modules. Fig. 3 A zigzag-shaped removal pattern. Fig. 4 Withdrawal patterns according to embodiments of the invention.
[0022] In Fig. 1 schematically illustrates a system 1 with a device 10, a storage medium 15, and a computer program 20 according to embodiments of the invention. Further illustrated Fig. 1, according to embodiments of the invention, a method 100 for constructing modules 30, each of which is provided with at least two electronic components 50, in particular semiconductor components, preferably power semiconductors. According to a first method step 101, a removal pattern, also referred to as a picking pattern, can first be defined, which specifies a specific removal path 60 for component positions on at least one wafer 40 (cf. Fig. 4, in which exemplary removal paths 60 are shown), on which the components 50 are manufactured and provided for the construction of the modules 30. Then, according to a second method step 102, a removal process can be initiated, in which the components 50 are removed from the at least one wafer 40 along the removal path 60. Furthermore, according to a third method step 103, a construction process can be initiated, in which the modules 30 are provided with the removed components 50, e.g., populated. It can be provided that the removal path 60 is defined taking into account at least one correlation between electrical properties of the components 50 and the component positions on the at least one wafer 40.
[0023] Furthermore, Fig. 1 also shows a system 1 for constructing modules 30 according to embodiments of the invention. The system 1 can comprise a device 10 for defining 101 a removal pattern and a removal machine 70 for removing the components 50 from the at least one wafer 40 in a removal process. In other words, the system 1 can be configured to carry out the method 100 according to the invention.
[0024] The invention is based in particular on the consideration that it cannot simply be assumed that neighboring components 50, hereinafter also referred to as chips, have uncorrelated properties. Rather, the statistics and patterns found in the on-wafer measurement data can be used to define the picking approach and thus reduce the tolerances within the modules. Fig. 2 shows an exemplary diagram in which the temperature T jover the number of modules 30. The diagram shows the distribution for small values of T j and for high values of T j Reduced unit volumes and increased costs. The extreme values of this distribution, in particular, lead to significant cost increases and should therefore be minimized. The chip limit, 201, is also specified as a threshold.
[0025] According to the invention, an improved picking pattern for wafers can be proposed. In Fig. 3 shows exemplary measurements of a quality parameter of a chip as a function of the position of the chip on the wafer. In this figure, curve 301 can represent the quality parameter, i.e., for example, a measured variable or property of the manufactured chip. The quality parameter can accordingly be specific to the manufacturing process and / or a quality of the manufactured chip. This measured variable is, for example, "Qgd," i.e., in particular, a gate-drain charge of the chip, or also R DS(ON). Curve 302 can indicate a radius on the wafer at which the chip is provided. Curve 303 can represent the vertical position of a point on the wafer at which the chip is provided, in a Cartesian coordinate system. The correlation of the electrical property, in particular the quality parameter, with the position of the chips on the wafer is clearly visible in the measurements. The measurements were taken for a conventional zigzag pattern. The "zigzag pattern" in a "wafer's picking pattern" is in particular a specification of the order for selecting or testing chips on a wafer. For example, it is the specification that the chips are selected or tested in a zigzag order across the wafer.
[0026] According to embodiments of the invention, a modification or alternatives to the conventional zig-zag pattern are proposed. Fig. Figure 4 initially shows the conventional zigzag pattern 401. Instead, according to embodiments of the invention, a modified zigzag pattern 402 with alternating y-direction, i.e., with a change of direction, a coil pattern 403, or a half-coil pattern 404 can be defined. Thus, taking the aforementioned correlations into account, new picking patterns, also called extraction patterns, can be defined, and in this way, symmetrical modules can be built, a tighter distribution, and thus higher performance can be achieved.
[0027] In Fig. 4, in the removal pattern 402, the removal path 60 is defined as a path that alternates in opposite directions to define a continuous, repeating, zigzag, or sawtooth trajectory on the at least one wafer 40.
[0028] In the removal pattern 403, the removal path 60 is defined as a path that extends in a circular manner from an outer component position 41 to an inner component position 42 of the at least one wafer 40 in order to define a continuous, spiral trajectory on the at least one wafer 40.
[0029] In the removal pattern 404, the removal path 60 is defined as a path that runs circularly with several changes of direction on the respective wafer 40 in order to specify a continuous, semi-spiral trajectory on the at least one wafer 40.
[0030] The above explanation of the embodiments describes the present invention exclusively by way of examples. Of course, individual features of the embodiments can be freely combined with one another, provided they are technically feasible, without departing from the scope of the present invention.
Claims
[1] Method (100) for constructing modules (30), each of which is provided with at least two electronic components (50), comprising the following steps: - defining (101) a removal pattern which specifies a specific removal path (60) for component positions on at least one wafer (40) on which the components (50) for constructing the modules are provided, - initiating (102) a removal process in which the components (50) are removed from the at least one wafer (40) along the removal path (60), - initiating (103) a construction process in which the modules (30) are provided with the removed components (50), characterized by that the removal path (60) is defined taking into account at least one correlation of electrical properties of the components (50) and the component positions on the at least one wafer (40). [2] Method (100) according to claim 1, characterized by in that the removal path (60) is defined as a path that runs alternately in opposite directions to provide a continuous, repeating, zigzag or sawtooth trajectory on the at least one wafer (40). [3] Method (100) according to one of the preceding claims, characterized by in that the removal path (60) is defined as a path which runs in a circular manner from an outer component position (41) to an inner component position (42) of the at least one wafer (40) in order to predetermine a continuous, spiral trajectory on the at least one wafer (40). [4] Method (100) according to one of the preceding claims, characterized by that the removal path (60) is defined as a path which includes a change of direction when a transition to a subsequent wafer (40) is provided during removal. [5] Method (100) according to one of the preceding claims, characterized by in that the removal path (60) is defined as a path which runs in a circular manner with a plurality of changes of direction on the respective wafer (40) in order to predetermine a continuous, semi-spiral trajectory on the at least one wafer (40). [6] Method (100) according to one of the preceding claims, characterized by that when initiating (102) the removal process, the following steps are repeatedly initiated: - removing the components (50) along the removal path (60) from a current wafer (40) until the removal of the components (50) for the current wafer (40) is completed, - performing a transition from the current to a subsequent wafer (40), - removing the components (50) along the removal path (60) from the subsequent wafer (40) until the removal of the components (50) for the subsequent wafer (40) is completed, wherein the removal path (60) is defined as a path in which the removal of the components (50) ends after completion of the removal at the same component position for the current wafer (40) at which the removal for the subsequent wafer (40) is continued. [7] Method (100) according to one of the preceding claims, characterized by that a removal machine (70) is controlled for the removal of the components (50) along the removal path (60). [8] Method (100) according to one of the preceding claims, characterized by that the electronic components (50) are designed as semiconductor components, wherein the respective module (30) is equipped with at least three components (50). [9] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause the computer (10) to carry out the method (100) according to one of the preceding claims. [10] Device (10) for data processing, which is arranged to carry out the method (100) according to one of claims 1 to 8. [11] System (1) for constructing modules (30) which are provided with at least two electronic components (50), comprising: - a device (10) for defining (101) a removal pattern which specifies a specific removal path (60) for component positions on at least one wafer (40) on which the components (50) for constructing the modules (30) are provided, - a removal machine (70) for removing the components (50) from the at least one wafer (40) in a removal process in which the components (50) are removed along the removal path (60), wherein the removal path (60) is defined taking into account at least one correlation of electrical properties of the components (50) and the component positions on the at least one wafer (40).
Citation Information
Patent Citations
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