DIGITAL CONTROL DEVICE

Abstract

A digital control device for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, generating a filtered digital current fault signal using the digitized current signal and a ripple suppression signal, the ripple suppression signal being provided to reduce ripple in the digital current signal when generating the filtered digital current fault signal, and controlling the switching converter, the control of the switching converter being dependent on the filtered digital current fault signal.

Description

[0001] The present disclosure relates to a digital control device. In particular, the present disclosure relates to a digital control device for a switching converter. BACKGROUND

[0002] Fig. Figure 1(a) is a schematic representation of a digital step-down converter 100 with analog-to-digital converters (ADCs) 102, 104, 106 and a control device 108. The step-down converter 100 includes switches 110, 112, an inductor 114 and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0003] While the power stage and the passive components (the inductor 114 and the capacitor 116) remain the same as in an analog buck converter, the ADC 102 converts the output voltage VOUT into a digital number. This conversion is performed at a specific rate in the time domain: e.g., the digital number VOUT is updated every 1 µs.

[0004] Optionally, the inductor current IL of inductor 114 and the input voltage VIN can also be converted from analog to digital, depending on the digital control method.

[0005] We distinguish between: • The switching frequency (FSW) of the buck converter 100 is, for example, 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage. • The processing frequency of the digital control device 108 (FS), for example, approximately 100 MHz. FS is equal to 1 / TS, where TS is the processing time of the control device 108. FS can optionally also be the sampling frequency of the ADC 102.

[0006] Fig. Figure 1(b) is a schematic representation of a digital step-down converter 118 in average current mode with a control circuit 120.

[0007] The operation of the circuit of Fig. 1(b) is as follows: • The output voltage VOUT is digitized by the ADC 102 to provide a digitized output voltage signal DOUT. This digitized output voltage signal DOUT is compared to a digital reference voltage DREF, which corresponds to the target voltage for the output voltage VOUT. Both values, DOUT and DREF, can be, for example, 8-bit bus values, where the digital code [0; 255] corresponds to the analog range [0.50V; 1.50V]. • A digital fault voltage signal DVERR is equal to DREF-DOUT, which is fed into a digital proportional-integral-derivative (PID) control loop circuit 122 to convert this digitized fault voltage DVERR into a digital setpoint current DITARGET, which is a digital number that specifies the target for setting the analog inductor current IL. If the output voltage VOUT decreases, then the digitized output voltage signal DOUT also decreases, the digital fault voltage signal DVERR increases, and the digital setpoint current DITARGET increases: the digital controller PID 122 requests more inductor current IL to restore the output voltage VOUT. • The digital setpoint current DITARGET can be encoded on multiple bits, e.g., 16 bits, as well as the following signals. The inductor setpoint current DITARGET enters an "inner loop" consisting of (a digital current generation circuit 123; a PIDI circuit 124; a PWM circuit 126; and the power stage 100). This inner loop adjusts the duty cycle MAG / DEMAG so that the analog inductor current IL matches its digital counterpart, the inductor setpoint current DITARGET, on average. • The digital power generation circuit 123 can be the ADC 104, as shown in Fig. 1(a) shown, or can be a “synthesizer” so that it can digitally reproduce the behavior of the inductor current IL depending on the input voltage VIN, the output voltage VOUT, the duty cycle and possibly other parameters. • The inner loop operates as follows: if the digital target current DITARGET is higher than the digital inductor current DIL, the digital current error DIERR increases. The digital current error DIERR passes through an integrator (PID 124) to produce a filtered and amplified version, with the filtered digital current error DIERRF increasing and entering a digital-to-duty converter (the PWM circuit 126) to increase the duty cycle. This results in an increase in the inductor current IL.

[0008] The control circuit 120 also includes addition / subtraction circuits 128, 130 and the logic and gate driver circuit 132.

[0009] Once the inner loop has reached a stable state, the average digital set current is equal to the average digital inductor current, which can be described as follows: <ditarget> = <dil>

[0010] A variable enclosed in “<>” is used to denote an average of the variables. For example, <x>the average of the variables x.

[0011] Fig. Figure 1(c) is a diagram showing the transient response of the digital buck converter 100. Curve 134 shows the output voltage VOUT; curve 136 shows the digital target current DITARGET; curve 138 shows the digital inductor current DIL; curve 140 shows the digital current error DIERR; curve 142 shows the filtered digital current error; and curve 144 shows one duty cycle DUTY. The digital inductor current DIL is the inductor current IL after digitization.

[0012] To simplify the explanation, it is located Fig. 1(c) in the continuous time and data domain (as if it were analog and not digital).

[0013] We imagine a load that reduces the output voltage VOUT at the end of the period T0. • The controller then increases the digital setpoint current DITARGET to raise the output voltage VOUT again. This spontaneously increases the digital current error DIERR (which has this residual ripple inherited from DIL (since DIERR = DITARGET-DIL)). • The filtered digital current error DIERRF increases slowly after the transition. At a certain point, the duty cycle is readjusted for the following period (sampling effect), allowing the inductor current IL (and thus the digital inductor current DIL) to increase, thereby reducing the digital current error DIERR until the average of the digital inductor current DIL equals the desired digital target inductor current DITARGET = 2A (at the end of T2).

[0014] It can be seen that the change in the filtered digital current error DIERRF takes a long time, thus delaying the decision to adjust the duty cycle. This worsens the response time of the buck converter 100. In particular, the time period T1, during which VOUT could continue to decrease, was not utilized. SUMMARY

[0015] It is desirable to provide a digital control device that improves the response time of a switching converter, such as a digital buck converter, in response to a load transition.

[0016] According to a first aspect of the disclosure, a digital control device is provided for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, a filtered digital current fault signal using the digitized current signal and a ripple or...to generate a ripple suppression signal, wherein the ripple suppression signal is provided to reduce ripple in the digital current signal when generating the filtered digital current error signal, and to control the switching converter, wherein the control of the switching converter depends on the filtered digital current error signal.

[0017] Optionally, the switching converter can be a buck converter, a boost converter, or a buck-boost converter.

[0018] Optionally, the energy storage element can be an inductor.

[0019] Optionally, the one or more circuit breakers may include a first circuit breaker and a second circuit breaker.

[0020] Optionally, the digital power signal is received by a digitized power generation circuit.

[0021] Optionally, the digital power generation circuit includes a first analog-to-digital converter configured to detect the current flow through the energy storage element and to digitize the detected current flow to generate the digital power signal.

[0022] Optionally, the digital power generation circuit includes a power synthesizer.

[0023] Optionally, the digital control device is configured to receive a digitized output voltage signal, where the digitized output voltage signal is a digital representation of the switching converter's output voltage.

[0024] Optionally, the digitized output voltage signal is received by a second analog-to-digital converter, which is configured to receive the output voltage and digitize the output voltage to generate the digitized output voltage signal.

[0025] Optionally, the digital control device is configured to generate a digital setpoint current signal using the digitized output voltage signal.

[0026] Optionally, the digital control device includes a first voltage error generation circuit configured to use the digitized output voltage signal and a digital voltage reference signal to generate a digital error signal, and a proportional-integral-differential circuit configured to convert the digital error signal into the digital target current signal.

[0027] Optionally, the first voltage error generation circuit is configured to generate the digital error signal by subtracting the digitized output voltage signal from the digital voltage reference signal.

[0028] Optionally, the digital control device includes a first current fault generation circuit configured to use the digital set current signal and the digital current signal to generate an unfiltered digital current fault signal, and a ripple / ripple suppression circuit configured to receive the unfiltered digital current fault signal and the ripple / ripple suppression signal, and to generate the filtered digital current fault signal by using the ripple suppression signal to reduce the ripple of the unfiltered digital current fault signal.

[0029] Optionally, the first current fault generation circuit is configured to generate the unfiltered digital current fault signal by subtracting the digital set current signal from the digital current signal.

[0030] Optionally, the ripple suppression circuit is configured to generate the filtered digital current error signal by adding the unfiltered digital current error signal to the ripple suppression signal.

[0031] Optionally, the digital control device includes a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current fault signal, and a logic and gate driver circuit configured to receive the PWM signal and generate a gate driver signal for each of the one or more power switches using the PWM signal.

[0032] Optionally, the pulse modulation circuit includes a duty cycle signal generation circuit configured to generate a digital signal using the filtered digital current error signal and an offset signal, and a comparator configured to receive the digital signal and a ramp signal and output the PWM signal based on a comparison between the digital signal and the ramp signal.

[0033] Optionally, the comparator is configured to generate the PWM signal, which includes rising and falling edges that depend on the digital signal crossing the ramp signal.

[0034] Optionally, the offset signal depends on a duty cycle of the switching converter and a maximum value of the ramp signal.

[0035] According to a second aspect of the disclosure, a method for controlling a switching converter, configured to receive an input voltage and generate an output voltage, using a digital control device, is provided. The switching converter comprises one or more power switches and an energy storage element. The method includes receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element; generating a filtered digital current fault signal using the digitized current signal and a ripple suppression signal, wherein the ripple suppression signal is provided to reduce ripple in the digital current signal when generating the filtered digital current fault signal; and controlling the switching converter.the control of the switching converter depends on the filtered digital current error signal.

[0036] It is obvious that the procedure of the second aspect can include the features set out in the first aspect and can incorporate other features described here.

[0037] According to a third aspect of the disclosure, a digital control device is provided for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising a ripple suppression signal generator configured to generate a ripple suppression signal, the digital control device being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, and generating a filtered digital current fault signal using the digitized current signal and the ripple suppression signal, the ripple suppression signal being provided.to reduce ripple in the digitized current signal during the generation of the filtered digital current error signal, and to control the switching converter, wherein the control of the switching converter depends on the filtered digital current error signal, wherein the ripple suppression signal within each signal period includes a rising edge comprising a first nonlinear section, and / or a falling edge comprising a second nonlinear section.

[0038] Optionally, the digital control device includes a sampling circuit configured to sample the digital current signal, with the ripple suppression signal generator configured to generate the ripple suppression signal using the sampled digital current signal.

[0039] Optionally, the ripple suppression signal generator is configured to receive a clock signal, where the clock signal is a periodic digital signal with a switching frequency derived from the switching frequency of the switching converter, and to generate the ripple suppression signal using the clock signal, where the signal period of the ripple suppression signal is equal to the period of the clock signal.

[0040] Optionally, the switching frequency of the switching converter is controlled by the clock signal.

[0041] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal by setting the ripple suppression signal to zero at each transition of the clock signal.

[0042] Optionally, within each signal period, the ripple suppression signal includes the rising edge, which comprises a first linear section, and / or the falling edge, which comprises a second linear section.

[0043] Optionally, the rising edge includes the first linear section, which rises linearly to zero, and the first nonlinear section, which rises nonlinearly from zero, and the falling edge includes the second linear section, which falls linearly to zero, and the second nonlinear section, which falls nonlinearly from zero.

[0044] Optionally, the digital control device includes a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current fault signal, and a logic and gate driver circuit configured to receive the PWM signal and generate a gate driver signal for each of the one or more power switches using the PWM signal, with the ripple suppression signal generator configured to generate the ripple suppression signal using the PWM signal.

[0045] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal using the PWM signal by alternating between the rising edge and the falling edge at each transition of the PWM signal.

[0046] Optionally, the PWM signal includes a magnetization state and a demagnetization state, and the ripple suppression signal generator is configured to generate the ripple suppression signal by generating the falling edge when the PWM signal is in the magnetization state, and generating the rising edge when the PWM signal is in the demagnetization state.

[0047] Optionally, the energy storage element is an inductor with an inductance.

[0048] Optionally, the first linear section of the rising edge is equal to the output voltage divided by the inductance, and the second linear section of the falling edge is equal to the output voltage minus the input voltage divided by the inductance.

[0049] Optionally, the first nonlinear section has an inverse exponential growth profile and the second nonlinear section has an exponential decay profile.

[0050] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal based on an operating state of the switching converter.

[0051] Optionally, the operating state of the switching converter is derived from the control state of the switching converter and / or the actual state of the switching converter.

[0052] Optionally, the control state depends on one or more PWM signals and / or the actual state depends on the switching state of one or more power switches.

[0053] Optionally, the switching converter is a buck-boost converter and the control state depends on two PWM signals.

[0054] Optionally, the digital control device includes a pulse width modulation circuit configured to generate one or more PWM signals using the filtered digital current fault signal, and a logic and gate driver circuit configured to receive one or more PWM signals and generate a gate driver signal for each of the one or more power switches using the one or more PWM signals, wherein the ripple suppression signal generator is configured to generate the ripple suppression signal using the one or more PWM signals.

[0055] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal using one or more PWM signals by alternating between the rising edge and the falling edge at each transition of at least one of the one or more PWM signals.

[0056] Optionally, each of the one or more PWM signals includes a magnetization state and a demagnetization state, and the ripple suppression signal generator is configured to generate the ripple suppression signal by generating the falling edge when at least one of the one or more PWM signals is in the magnetization state, and generating the rising edge when at least one of the one or more PWM signals is in the demagnetization state.

[0057] According to a fourth aspect of the disclosure, a method for controlling a switching converter using a digital control device is provided, wherein the switching converter is configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising a ripple suppression signal generator configured to generate a ripple suppression signal, the method comprising receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element, and generating a filtered digital current error signal using the digitized current signal and the ripple suppression signal, wherein the ripple suppression signal is provided.to reduce ripple in the digitized current signal during the generation of the filtered digital current error signal, and to control the switching converter, wherein the control of the switching converter depends on the filtered digital current error signal, wherein the ripple suppression signal within each signal period includes a rising edge comprising a first nonlinear section, and / or a falling edge comprising a second nonlinear section.

[0058] It is obvious that the procedure of the fourth aspect can include features set out in the third aspect and can incorporate other features described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The revelation is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1(a) a schematic representation of a digital step-down converter, Fig. 1(b) a schematic representation of a digital step-down converter in average current mode with control circuitry is, Fig. 1(c) is a diagram showing the transition behavior of the digital step-down converter; Fig. 2(a) a schematic representation of a digital control device for a switching converter according to a first embodiment of the present disclosure, Fig. 2(b) a schematic representation of a specific embodiment of the in Fig. 2(a) the system shown is, Fig. 2(c) a schematic representation of a further specific embodiment of the in Fig. 2(a) the system shown is, Fig. 2(d) a schematic representation of a further specific embodiment of the in Fig. 2(a) is the system shown; Fig. 3(a) a schematic representation of a specific embodiment of the control device according to a second embodiment of the present disclosure, Fig. 3(b) is a schematic representation of a specific embodiment of the control device according to a third embodiment of the present disclosure; Fig. 4 is a schematic representation of a specific embodiment of the system of the present disclosure according to a fourth embodiment of the present disclosure; Fig. 5(a) is a time diagram that shows simulation results of a practical implementation of the in Fig. The system shown in section 4 demonstrates Fig. 5(b) is another time diagram that shows simulation results of a practical implementation of the in Fig. The system shown in section 4 demonstrates Fig. 5(c) is another time diagram that shows simulation results of a practical implementation of the in Fig. The system shown in section 4 demonstrates Fig. 5(d) is a diagram showing simulation results of a phase response and a gain response for a practical implementation of the circuit of Fig. 4 shows, Fig. 5(e) is a diagram showing a crossing point for the digital signal and the ramp signal, Fig. 5(f) is a schematic representation of an example of a local DLL (delay locked loop) as it can be implemented in each of the described embodiments, Fig. 5(g) is a diagram showing a crossing point for the digital signal and the ramp signal; Fig. 6 is a diagram that shows simulation results for a practical implementation of the system of Fig. 4 shows; Fig. 7(a) is a diagram showing the time-varying digitized inductor current, Fig. 7(b) is a diagram showing the unfiltered digital current error, the ripple suppression signal and the filtered digital current error, Fig. 7(c) a diagram of a negatively idealized ripple suppression signal that uses nonlinear slopes or edges; Fig. 8(a) is a schematic representation of a specific embodiment of the digital control device according to a fifth embodiment of the present disclosure, Fig. 8(b) is a schematic representation of a specific embodiment of the digital control device according to a sixth embodiment of the present disclosure; Fig. 9(a) is a diagram showing the digitized inductor current for sampling, Fig. 9(b) a diagram of the gain and phase relationships using the sampling method compared to an idealized ripple suppression signal and a schematic representation of a simulated circuit; Fig. 10 a schematic representation of a specific embodiment of the digital control device according to a seventh embodiment of the present disclosure; Fig. 11 is a diagram showing waveforms relating to the operation of the system of Fig. 10 refer to; Fig. 12 a schematic representation of a specific embodiment of the digital control device according to an eighth embodiment of the present disclosure; Fig. 13 is a diagram showing waveforms relating to the operation of the system of Fig. 12 refer to; Fig. 14 is a diagram showing the generation of the straight edges that can be used for the straight edge sections of the ripple suppression signal; Fig. 15 a schematic representation of a specific embodiment of the digital control device and the step-down converter according to a ninth embodiment of the present disclosure; Fig. 16 is a diagram that shows simulation results for a practical implementation of the in Fig. The system shown in section 15 is shown; and Fig. 17(a) is a schematic representation of a specific example of a digital control loop proportional-integral-differential circuit, Fig. 17(b) is a schematic representation of a specific example of the ripple suppression signal generator. DETAILED DESCRIPTION

[0060] In Fig. 1(b) the PID 124 acts as a low-pass filter and is used for the following reasons: • It is preferable for the PID 124 to apply a gain. For example, if we have a duty cycle of 50%, we want an inductor current IL = 1A, and the block PWM circuit 126 requires an input-filtered digital current error DIERRF between 0 and 15 to generate / control a duty cycle in [0; 1]. If the PID 124 had a gain of 1, (DITARGET-DIL) would have to be 7 to achieve the 50% duty cycle. Therefore, the digital setpoint current DITARGET would have to be 8 for the digital inductor current DIL = 1A. We see that the two values ​​DITARGET and DIL would be very different. This does not pose a fundamental problem for the function of the buck converter 100, but we lose the advantage of DITARGET-DIL (which could be useful, among other things, for a current limiter applied to DITARGET). Applying the same calculation with a much larger PID 124 gain results in DITARGET being approximately equal to DIL, which is preferable. • The PID 124 must also filter the difference (DITARGET-DIL): in fact, this allows the removal of the ripple on the error that was inherited from the ripple on DIL.

[0061] It should be noted that the step-down converter 100 could handle this unfiltered ripple. However, there are two disadvantages: 1. Subharmonic oscillations may occur, so caution is advised when generating the duty cycle. 2. We use DIERRF at a specific time to decide / set the duty cycle. This is equivalent to sampling. Here, DIERRF can be 1A away from the average DIERFF, which is zero, due to this ripple. Therefore, the inner loop can set the inductor current IL on average 1A away from DITARGET. This leads to the same problem as in the case of the PID 124 with a gain of 1, and we encounter an additional problem in the case of multiphase circuits with asymmetrical inductors.

[0062] Therefore, in average current mode control devices, the PID 124 acts as an integrator to avoid these two problems.

[0063] However, the PID 124, which acts as an integrator, reacts slowly, leading to the previously described problems in response to a load transition. In summary, the integrating effect of the PID 124 has a detrimental consequence: DIERRF changes take longer, and the decision to adjust the duty cycle is delayed. This worsens the response time of the buck converter 100.

[0064] Fig. Figure 2(a) is a schematic representation of a digital control device 200 for a switching converter 202 according to a first embodiment of the present disclosure. The switching converter is configured to receive an input voltage Vin and to generate an output voltage Vout. The switching converter 200 comprises one or more power switches 204 (represented in the present example by a single switch) and an energy storage element 206.

[0065] The digital control device 200 is configured to receive a digital current signal DI. The digital current signal DI is a digital representation of a current flowing through the energy storage element 206. The energy storage element 206 can, for example, be an inductor, so that the current flowing through the energy storage element 206 can correspond to the inductor current IL, and the digital current signal DI can correspond to the digital inductor current DIL, as previously described in relation to Fig. 1(b) discussed.

[0066] The digital control device 200 is further configured to generate a filtered digital current fault signal DIERRF using the digital current signal DI and a ripple cancellation signal (RIPC). The ripple cancellation signal RIPC is intended to reduce ripple in the digital current signal DI when generating the filtered digital current fault signal DIERRF.

[0067] It is evident that in one specific embodiment, the control device 200 can partially reduce the ripple, so that some ripple still remains on the DIERRF. In an alternative embodiment, the control device 200 can completely reduce the ripple, so that the ripple is removed during the generation of DIERRF.

[0068] The ripple results from the periodic charging and discharging of the energy storage element 206 during the switching operation of the switching converter 202. For example, for a buck converter, the ripple can be as previously described with respect to the operation of the inductor 114 and as shown in curves 138 and 140. The “ripple” in the Fig. The example shown in 1(c) refers to the periodic variation with a triangular profile resulting from the switching operation of the step-down converter 100.

[0069] The digital control device 200 is further configured to control the switching converter 202, the control of the switching converter 202 depending on the filtered digital current fault signal DIERFF.

[0070] In a specific embodiment, the switching converter 202 can, for example, be a buck converter, a boost converter or a buck-boost converter; and the energy storage element 206 can be an inductor.

[0071] The use of the ripple correction signal RIPC means that the ripple can be removed when generating the filtered digital current error signal DIERRF without the need for integration (as in Fig. 1(b) provided by the PID 124). Therefore, the present disclosure provides a control device that overcomes the disadvantages of known systems that respond slowly due to the PID 124, while retaining the advantages of an average current control mode.

[0072] Fig. 2(b) is a schematic representation of a specific embodiment of the in Fig. 2(a) system shown. In the present embodiment, the digital control device 200 is configured to receive a digitized output voltage DVout. The digitized output voltage signal DVout is a digital representation of the output voltage Vout of the switching converter 202. The digitized output voltage signal DVout is generated using an analog-to-digital converter (ADC) 208, which receives the output voltage Vout and digitizes it to provide the digitized output voltage signal DVout. The digitized output voltage signal DVout can be used to generate a digital target current signal DITARGET (not shown).

[0073] Fig. 2(c) is a schematic representation of a further specific embodiment of the in Fig. 2(a) of the system shown. In the present embodiment, the digital current signal DI is received by a digital current generation circuit 210. The digital current generation circuit 210 can, for example, include an analog-to-digital converter configured to detect the current flow through the energy storage element 206 and to digitize the detected current flow to generate the digital current signal DI. In another embodiment, the digital current generation circuit 210 can include a current synthesizer.

[0074] Fig. 2(d) is a schematic representation of a further specific embodiment of the in Fig. 2(a) system shown, comprising features previously described in relation to the Fig. 2(b) and Fig. 2(c) were described.

[0075] Fig. 3(a) is a schematic representation of a specific embodiment of the control device 200, as it can be used in each of the embodiments described herein, according to the understanding of those skilled in the art and according to a second embodiment of the disclosure.

[0076] The control device 200 includes a voltage fault generation circuit 300 which is configured to use the digitized output voltage signal DVout and a digitized voltage reference signal DREF to generate a digital fault signal DVERR.

[0077] The voltage fault generation circuit 300 can be configured to generate the digital fault signal DVERR by subtracting the digitized output voltage signal DVout from the digitized voltage reference signal DREF, which can be represented as follows: DVERR=DREF−DVout

[0078] The control device 200 further includes a proportional integral differential (PID) circuit 302, which is configured to convert the digitized voltage error signal DVERR into the digital set current signal DITARGET.

[0079] The control device 200 can further include a current fault generation circuit 304 configured to use the digital set current signal DITARGET and the digitized current signal DI to generate an unfiltered digital current fault signal DIERR.

[0080] The current fault generation circuit 304 can be configured to generate the unfiltered digital current fault signal DIERR by subtracting the digital set current signal DITARGET from the digital current signal DI as follows: DIERR=DI−DITARGET

[0081] The control device 200 can further include a ripple suppression circuit 306 configured to receive the unfiltered digital current fault signal DIERR and the ripple suppression signal RIPC and to generate the filtered digital current fault signal DIERRF using the ripple suppression signal RIPC to reduce the ripple of the unfiltered digital current fault signal DIERR.

[0082] The ripple suppression circuit 306 can be configured to generate the filtered digital current fault signal DIERRF by adding the unfiltered digital current fault signal DIERR to the ripple suppression signal RIPC, as follows: DIERRF=DIERR+RIPC

[0083] Fig. 3(b) is a schematic representation of a specific embodiment of the control device 200, as it can be used in each of the embodiments described herein, according to the understanding of those skilled in the art and according to a third embodiment of the disclosure.

[0084] In the present example, the control device 200 comprises a pulse width modulation (PWM) circuit 308 configured to generate a PWM signal (referred to as "PWM" in the figures) using the filtered digital current error signal DIERRF. The digital current error signal DIERRF can be received by the components as shown in the Fig. 3(a) The specific embodiment shown is described in accordance with the understanding of those skilled in the art.

[0085] The control device 200 further comprises a logic and gate driver circuit 310, which is configured to receive the PWM signal and to generate a gate driver signal GN for each of the one or more power switches 204 using the PWM signal.

[0086] It is obvious that the single gate driver signal GN is for illustrative purposes. In practice, and when applied to a switching converter with a high-side and a low-side FET, particularly when applied to a buck converter for the present example, when PWM = 0, the low-side FET is turned on by a gate driver signal; and when PWM = 1, the high-side FET is turned on by a gate driver signal.

[0087] Furthermore, the logic and gate driver circuit can include a driver component for generating the driver signals; and a logic component for providing a break-before-make operation to handle the switch between high-side and low-side.

[0088] The PWM circuit 308 can further include a circuit 314 for generating a duty cycle signal, which is configured to generate a digital signal DCA using the filtered digital current fault signal DIERRF and an offset signal PDSS.

[0089] In one specific embodiment, the digital signal DCA can be as follows: DCA = DIERRF + PDSS

[0090] The PWM circuit 308 can further include a comparator 316 which is configured to receive the digital signal DCA and a ramp signal RAMP and to output the PWM signal based on a comparison between the digital signal DCA and the ramp signal RAMP.

[0091] The comparator 316 can be configured to generate the PWM signal so that the PWM signal has rising and falling edges that depend on the digital signal DCA crossing the ramp signal RAMP.

[0092] It is obvious that the comparator 316 is functionally a comparator, but its time-domain resolution is increased by the use of one or more DLLs.

[0093] For example, if the clock frequency FS of a direct comparator were 100 MHz, the time resolution for PWM would be 10 ns, since the comparator in digital mode would update the PWM every 10 ns. In reality, the 316 comparator follows the scheme in Fig. 5(e): Comparison of the digital edges of DCA and RAMP and generation of an accurate time for the PWM duration (much finer than 10 ns) using DLL. In further embodiments, the functionality of comparator 316 can be provided by more than one comparator.

[0094] The offset signal PDSS can depend on the duty cycle D of the switching converter 202 and the maximum value of the ramp signal RMAX. For example, if the ramp signal RAMP varies from 0 to RMAX, PDSS can be calculated graphically, given the desired duty cycle D, as follows: PDSS=(1−D).RMAX

[0095] It is obvious that equation (6) in the case of Fig. 5(c) is valid where RAMP is a triangular signal. In other embodiments where RAMP has a different profile, it will be different, but easily derivable graphically by those skilled in the art.

[0096] For an embodiment in which the switching converter 202 is a buck converter, equation (6) can be rewritten as follows: PDSS=(1−Vout / Vin).RMAX

[0097] Fig. Figure 4 is a schematic representation of a specific embodiment of the system of the present disclosure, wherein the switching converter 202 comprises a buck converter, and according to a fourth embodiment of the present disclosure. The buck converter comprises an inductor 400, two power switches 402, 404, and an output capacitor 406 and employs current-mode control. The logic and gate driver circuit 310 outputs two gate driver signals GP, GN, each signal being directed to one of the power switches 402, 404. The logic and gate driver circuit 310 may also include a non-overlap system (“break before make,” as described above) provided by the logic circuit. The components 300, 304, 306 may be adders and / or subtractors, according to the understanding of those skilled in the art.

[0098] Fig. 5(a) is a time diagram showing simulation results of a practical implementation of the in Fig. Figure 4 shows the system. Shown is a curve 500 of the digital target current signal DITARGET; a curve 502 of the digital inductor current DIL; and a curve 504 of the unfiltered digital current error DIER-ROR.

[0099] The Fig. 5(a), Fig. 5(b) and Fig. 5(c) use a continuous time and data range for the time diagrams for clarity.

[0100] In the present example, the energy storage element 206 is an inductor and therefore the digital current signal DI is the digitized inductor current DIL.

[0101] It is desirable that the average digital set current corresponds to the average digital inductor current, as described by equation (1). As in Fig. As can be seen in Figure 5(a), the system is currently in this desired stable state over a period of time (denoted by TSW) as shown by curve 506, which shows that the average digital current error DIERR over this period is 0A.

[0102] It can be seen that the unfiltered digital current error DIERR takes over the entire ripple of the digital inductor current DIL, provided that the digital current setpoint DITARGET is constant.

[0103] S1 and S2 are the edges of this ripple and come directly from the DIL. S1 and S2 can either be constant, typically (Vin-Vout) / L and -Vout / L for a buck converter, where "L" denotes the inductance of inductor 206. However, the edges S1 and S2 can also be non-constant. Furthermore, the edges S1 and S2 can be exponential, for example, due to the series resistances in the power stage and / or the power reduction (derating) of the inductor. In this disclosure, we assume that S1 and S2 are always known and can be compensated. S1 can follow IMAX(1-expt(-t / T)), where T=L / R and IMAX=(VIN-VOUT) / Rswitch.

[0104] Fig. 5(b) is another time diagram showing simulation results from a practical implementation of the in Fig. Figure 4 shows the system. A curve 507 of the ripple suppression signal RIPC is shown; and a curve 508 of the filtered digital current error DIERRF is shown.

[0105] The ripple suppression signal RIPC has opposite edges to the digital current error DIERR and is centered around zero.

[0106] Since the digital current error DIERR is a digital edge and assuming that its values ​​are completely known over time, the ripple suppression signal RPIC can be generated with opposite polarity and with the same digital numbers in absolute value.

[0107] In this way, the sum of DIERR and RIPC (as provided by equation (4)) leads to the mathematical removal of the ripple. Therefore, due to digital processing, we can achieve ripple elimination without requiring PID 124.

[0108] Fig. 5(c) is another time diagram showing simulation results from a practical implementation of the in Fig. Figure 4 shows the system. Curve 510 of the offset signal PDSS is shown; curve 512 of the ramp signal RAMP; curve 514 of the digital signal DCA; and curve 516 of the PWM signal. PDSS denotes a predictive offset to obtain a steady-state duty cycle (DSS). The relationship between the in Fig. The parameters shown in 5(c) are given by equation (5).

[0109] It should be noted that (DIL-DITARGET) is generated instead of (DITARGET-DIL) to satisfy the final modulation scheme (see Fig. 5(c)). Further embodiments can generate DITARGET-DIL according to the understanding of those skilled in the art.

[0110] As previously mentioned in relation to Fig. As explained in 1(a), the average current mode provides a gain (infinite at 0Hz, since the PID 124 is an integrator) to keep the average DITARGET and the average DIL essentially equal.

[0111] The generation of DIERRF using the ripple suppression signal RIPC, as provided by equation (4), is an operation with a gain of 1.

[0112] The duty cycle D (represented by the PWM signal) is generated by the crossing of the digital signal DCA with a triangular ramp RAMP. In this example, this is achieved through dual leading / falling edge modulation: the rising edge of the PWM signal (MAGNETIZE) is not clock-synchronized ("falling-edge modulation"), nor is the falling edge ("leading-edge modulation"). Instead, both rising and falling edges of the PWM are determined by crossing the DCA RAMP.

[0113] The digitized versions of Vin and Vout can be used to generate the offset signal PDSS according to equation (7). An analog-to-digital converter can be used to acquire the input voltage Vin, digitize Vin, and generate a digital signal representing Vin. DVout can be generated as previously described and according to the understanding of experts.

[0114] The duty cycle control method using the offset signal PDSS means that the required duty cycle D can be achieved within acceptable tolerances for practical application, while the average of the filtered digital current error DIERRF remains zero, so that the average DITARGET is equal to the average DIL.

[0115] This method can be referred to as DSS (Steady-State Duty-Cycle), as mentioned in the literature “An Estimative Current Mode Controller for DC-DC Converters Operating in Continuous Conduction Mode, IEEE paper by Mehdi Ferdowsi”, which uses a different method than the present disclosure and does not use front / back edge operations.

[0116] The advantages of both rising / falling flanks being determined by an intersection of DCA and RAMP are: • If Vout varies, this is passed to DITARGET, which changes the DCA level (after removing the ripple). This can continue until the DCA / RAMP intersection, so that the sampling effect no longer occurs at the beginning of a period, as with a DPWM, as in Fig. 1(a), (b) and (c) described. Any sudden change in Vout can modify the PWM rise time up to just before TS prior to this transition. • The falling PWM edge is re-evaluated until it intersects DCA RAMP. This results in two evaluations / samples within a single TSW period. This leads to improvements in bandwidth compared to a system using only leading-edge modulation.

[0117] Fig. Figure 5(d) is a diagram showing simulation results of a phase response and a gain response for a practical implementation of the circuit of Fig. Figure 4 shows a circuit that uses only a leading-edge modulation. Curve 518 is a phase response of the circuit. Fig. 4; a 520 curve is a phase response of the circuit that uses only a leading-edge modulation; a 522 curve is a gain response of the circuit. Fig. 4; and curve 524 is a gain response of the circuit that uses only a leading-edge modulation. The circuit of Fig. Figure 4 shows, as already explained, an improvement in bandwidth compared to the circuit that uses only front-edge modulation.

[0118] The following discussion concerns discrete-time considerations. To meet the requirements of mobile communications, the duty cycle resolution is typically -200p. To achieve this resolution, a 5 GHz clock would normally be required, which would result in excessive power consumption by the digital control system. Two solutions are known: • Dithering: Dithering is applicable to DPWM, as described in Fig. 1(b), and would force a rough duty cycle sampling only once per TSW. We would therefore lose the advantage of re-evaluating the DCA / RAMP intersection at every TS. • Local high-clock domain for fine resolution. Although used in US9419627B2 and US9667260B2, the requirements for mobile communications are 30 times finer, and the required 5 GHz would still result in excessive power consumption.

[0119] Embodiments of the present disclosure use a local DLL (delay locked loop) for fine resolution. This can be used for both leading and trailing edges. DLLs can enable slope-based intersection calculations for leading / falling edges. More than one DLL can be used, for example, to reset and lock one DLL while another is in use. In a specific embodiment where more modulators are required (multiphase), there is preferably one or more dedicated DLLs for each phase.

[0120] Fig. 5(e) is a diagram 526 showing an intersection point for the digital signal DCA and the ramp signal RAMP, where DCA is constant (“flat”); and a diagram 528 showing the digital signal DCA and the ramp signal RAMP, where DCA is sloped.

[0121] In Fig. Figure 5(e) represents DCA and RAMP in the digital discrete time domain: they vary with the rate TS, which is, for example, 10 ns. The following two cases are shown: • Diagram 526. “Flat” constant DCA: the DIL-induced ripple was perfectly canceled out and the average digital current setpoint was itself constant. • Diagram 528. Inclined DCA: although the DIL-induced ripple has been removed, the residual ripple on the average digital current setpoint is still present on the DCA.

[0122] In both cases, at each rising step of RAMP (or falling edge if RAMP decreases), the equivalent edge is calculated as in continuous time (dotted lines). Then, the time intersection of the two edges is calculated (labeled 530a in Diagram 526 and 530b in Diagram 528). At a time point labeled "IRQ", the calculation shows that the continuous-time edges intersect in the shaded interval [TS / 2, 3TS / 2], and the intersection time is known.

[0123] In this example, the DLL divides the TS=10ns interval into 64 segments and is programmed to the required value. For example, the edges cross at "IRQ" 8.3ns later: based on the time interval from TS / 2 to 3TS / 2. This corresponds to 3.3ns if started from TS / 2. The DLL code is calculated as (3.3ns / 10ns) multiplied by 64, which equals 21.

[0124] Fig. Figure 5(f) is a schematic representation of an example of a DLL 540 as it can be implemented in each of the embodiments described here, according to the understanding of those skilled in the art.

[0125] The DLL 540 adds the 100 MHz clock signal to a series of, for example, 64 delays (TD). A control block 542 LCKCTRL compares the output of the series "t64" with the next edge of the 100 MHz clock signal, which occurs 10 ns later. If t64 occurs after this next edge, it means that 64×TD exceeds 10 ns.

[0126] Block 542 LCKCTRL adjusts a control signal (either analog or digital) to speed up the delays TD. If t64 occurs before the next 100 MHz edge, this means that 64×TD is shorter than 10 ns. In this case, block 542 LCKCTRL increases the delays using DELREG. Finally, after several 100 MHz cycles, control device 542 LCKCTRL ensures that 64×TD = 10 ns. DLL 540 is then "locked out," and TD ~ 160 ps = 10 ns / 64.

[0127] We see that by selecting a tap using the MUX and the selection code sel<5:0>, the signal transmission is obtained as a fraction N / 64 of the 10ns clock cycle. DELREG, and more generally the system, can be analog or digital.

[0128] Fig. Figure 5(g) is a diagram 544 showing a crossing point for the digital signal DCA 546 and the ramp signal RAMP 548. We use sel<5:0> and IRQ for the DCA versus RAMP crossing point.

[0129] Some of the examples shown here include DCA and RAMP, with their counterparts SCA and SRAMP respectively in the continuous time domain.

[0130] In the digital domain, we check DCA and RAMP in each clock cycle (e.g., 100 MHz): we calculate their continuous-time equivalents SCA and SRAMP and check whether they intersect in the next cycle. If this is the case, the digital control device (equivalent to block 316 in Fig. 4, which can offer additional functionality beyond that of a typical comparator) the intersection point in the continuous time domain and digitizes it as the code sel<5:0 >. In Fig. 5(g) is the intersection at ¼ of TS=10ns, so the code is 16 (64 / 4) and is sent to DLL 540.

[0131] Additionally, an interrupt IRQ is sent to instruct the DLL 540 to output the signal crossing. This fine-tuning creates a crossing 2.5 ns after the IRQ, which corresponds to 1 / 4 of the total Ts=10 ns period. In this case, the "crossing" signal starts the PWM via an RS latch, for example.

[0132] In a specific embodiment, the intersection can even be predicted further in advance: we do not check whether the intersection is within the next period, but within the next period plus half or a full clock cycle, as in Fig. 5(e) shown. In Fig. 5(e) is marked IRQ when the crossing occurs in the shaded area, which is not immediately afterward, but delayed by half a cycle. The reason for the delay is that we allocate this time for the digital computation of code_sel<5:0> (propagation through gates).

[0133] Fig. Figure 6 is a diagram showing simulation results for a practical implementation of the system of Fig. Figure 4 shows the curves are labelled according to the previously used labelling. A curve 600 of the inductor current IL is shown.

[0134] The digital target current DITARGET and the digitized inductor current DIL are differentiated, and the ripple is canceled. Then a fixed offset PDSS is added to obtain DCA.

[0135] Each time DCA is about to cross RAMP in the interval from TS / 2 to 3TS / 2 after evaluation, we see that the DLL code is adjusted (designated with the number 602). It is sent to DLL, and the signal PWM edges are triggered according to the DLL code. It can be seen that they are not aligned with rising / falling edges, but are at an intermediate point due to fine-tuning.

[0136] The use of simultaneous front / back edge modulation and management of discrete-time quantization using local DLLs, as provided in embodiments of the disclosure, can be used to further improve performance and adapt to the requirements of mobile communications.

[0137] Fig. Figure 7(a) is a diagram showing a curve 700 of the digitized inductor current DIL, which varies with time, with the edges formed by straight lines; and a curve 702 of the digitized inductor current DIL, which varies with time, with the edges being nonlinear.

[0138] Curve 700 shows an idealized form of the digitized inductor current DIL, as used in US9419627B2 and US9667260B2. In reality, however, the digitized inductor current DIL does not exhibit this idealized form but instead has rising and falling edges for each period with a nonlinear profile. Specifically, the falling edge shows an exponential decay, and the rising edge shows inverse exponential growth. It should be noted that the time graphs depict continuous time and continuous data for clarity.

[0139] The curvature of the flanks results from the resistance contributions of the switching converter 202. For example, and with reference to the example of the buck converter, as in Fig. As shown in Figure 4, the resistance value of the inductor 400 and the on-resistances of the switches 402, 404 contribute to the non-linear profiles.

[0140] It is evident that other switching converters can also exhibit nonlinear edge profiles of the digital inductor current DIL (or the digital current DI if a different energy storage element is used).

[0141] In the discrete time domain (clocked at TS, which corresponds to the processing time of the control device 200), the digitized inductor current DIL during the magnetization phase, when the inductor is coupled to the input voltage Vin via the switch 402, can be represented as follows: isynth[n]=isynth[n−1]−A(RHS).isynth[n−1]+B.(Vin−Vout) / L

[0142] The digital inductor current DIL during the demagnetization phase, when the inductor is coupled to ground PGND via switch 404, can be represented as follows: isynth[n]=isynth[n−1]−A(RLS).isynth[n−1]−B.(VOUT) / L

[0143] The variable A-term is thus the nonlinear correction of ideal flanks contributed by the B-term. A=TS×RL where R is the sum of the DC resistance (DCR) of inductor 400 and RHS (in the magnetized state); and R is the sum of DCR and RLS (in the demagnetized state); and applies to the case of a buck converter. RHS is the on-resistance of switch 402 and RHL is the on-resistance of switch 404. B = TS, where TS is the processing time of control device 200.

[0144] It is preferable to generate the ripple suppression signal RIPC in such a way that a filtered digital current error DIERRF can be produced without ripple. It should be noted that the subscript (t), as for RIPC(t), can be used to denote continuous time, while subscripts [n] are for discrete time.

[0145] Fig. Figure 7(b) is a diagram showing curve 706 of the unfiltered digital current error DIERR; curve 708 of the ripple suppression signal RIPC; and curve 710 of the filtered digital current error DIERRF, as can be obtained by applying equation (4). In the present example, the ripple suppression signal RIPC uses straight edges.

[0146] As shown by equation (3), the digital current error signal DIERR is equal to the digital current signal DI minus the digital current setpoint DITARGET, so that DIERR = DIL - DITARGET if the energy storage element 206 is the inductor.

[0147] As can be seen from curve 706, DIERR takes over the nonlinear ripple of DIL. The linear suppression scheme using the ripple suppression signal RIPC allows the filtered digital current error DIERRF to be centered at 0A. Therefore, the ripple suppression signal RIPC with a linear profile can be used with embodiments of the present disclosure to provide an improvement over known systems, for example, the one in Fig. to provide the system shown in 1(b).

[0148] The difficulty of ΔIS and ΔIP (as in Fig. 7(b) denoted and unequal) and to adjust the remaining DIERRF ripple as shown in curve 710, however, can produce slow subharmonic oscillations that have been observed in simulations.

[0149] Therefore, further improvements can be achieved by using a different ripple suppression signal, RIPC. Fig. Figure 7(c) is a diagram of a negatively idealized ripple suppression signal RIPC(t) using nonlinear edges. RIPC(t) is the inverse of the ripple of the inductor current IL, and its negative value, -RIPC, is represented by a curve 712, as shown in Figure 7. Fig. 7(c) shown.

[0150] The preferred properties of RIPC(t) are: • It is centered at 0A. This is advantageous because it is desirable to cancel out the ripple content while leaving the average digital inductor current (DIL) unchanged. • It cancels a recursive equation DIERR(t).

[0151] It is obvious that Fig. 7(c) shows an idealized representation and an improvement can be achieved in a practical system compared to a ripple suppression signal RIPC that has straight edges, without exactly matching curve 712 or the preferred properties.

[0152] Fig. Figure 8(a) is a schematic representation of a specific embodiment of the digital control device 200, comprising a ripple suppression signal generator 800, and according to a fifth embodiment of the present disclosure. It is obvious that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and according to the understanding of those skilled in the art.

[0153] The ripple suppression signal RIPC includes, within each signal period, a rising edge that includes a first nonlinear section and a falling edge that includes a second nonlinear section.

[0154] For example, in a specific embodiment, the ripple suppression signal RIPC can have the profile shown by curve 712 in Fig. (7c).

[0155] In a specific embodiment and with regard to the cancellation of the recursive equation DIERR(t), we can perform a calculation “back in time” to calculate the digitized inductor current DIL in a previous time step and from the start iteration, as given by the equation: l(STR)=isynth[n−1]−A(RHS).isynth[n−1]+B.(Vin−Vout) / L

[0156] This can then be used to generate the RIPC ripple suppression signal.

[0157] However, generating the RIPC(t) curve before STR can be difficult because the starting point of the magnetization of inductor 400 may be hard to identify due to the calculation, which requires an evaluation of the digital inductor current DIL at an earlier time step.

[0158] Feasibility studies show that it is fundamentally possible to generate the RIPC ripple suppression signal in this way, but it would require a processing clock speed above 5GHz, which would result in a consumption of >100 mA and a 30% decrease in efficiency.

[0159] Fig. Figure 8(b) is a schematic representation of a specific embodiment of the digital control device 200 of Fig. 8(a) according to a sixth embodiment of the present disclosure. In the present disclosure, the digital control device further comprises a sampling circuit 802 configured to sample the digital current signal DI. The ripple suppression signal generator 800 is configured to generate the ripple suppression signal RIPC using the sampled digital current signal DI. It should be noted that the following description assumes that the energy storage element 206 is the inductor 400, such that the digital current signal DI is the digitized inductor current DIL. It is obvious that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and according to the understanding of those skilled in the art.

[0160] Fig. Figure 9(a) is a diagram showing a curve 900 of the digitized inductor current DIL for sampling using the sampling circuit 802. To generate the ripple suppression signal RIPC(t), DILPEAK and DILVALLEY can be measured at each switching cycle of the switching converter (as shown in Figure 9(a)). Fig. 9(a) can be extracted, and the ripple suppression signal RIPC can be generated using the following equation: RIPC(t)=(DILPEAK+DILVALLEY) / 2−DIL(t)

[0161] Fig. 9(b) is a diagram 902 of the gain and phase relationships using the sampling method of the present embodiment (curves 904, 906) compared to an idealized ripple suppression signal RIPC (curves 908, 910) and a schematic representation 912 of the simulated circuit of the present embodiment with respect to a practical implementation of the system.

[0162] The sampling technique means that there are local loops (for sampling / extraction) that create resonance effects and lead to subharmonic oscillations. Simplis POP simulations showed these resonances, as in Fig. 9(b) is shown.

[0163] Fig. Figure 10 is a schematic representation of a specific embodiment of the digital control device 200 according to a seventh embodiment of the present disclosure. It is obvious that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and according to the understanding of those skilled in the art.

[0164] The ripple suppression signal generator 800 is configured to receive a clock signal. The clock signal FSW is a periodic digital signal with a switching frequency equal to the switching frequency FSW of the switching converter 202. The clock signal is in Fig. 10 labeled “FSW”.

[0165] The 800 ripple suppression signal generator produces the RIPC ripple suppression signal using the FSW clock signal. The 800 ripple suppression signal generator can generate the RIPC ripple suppression signal using both the FSW clock signal and a PWM signal. The signal period of the RIPC ripple suppression signal is equal to the period of the FSW clock signal.

[0166] The switching frequency of the switching converter 202 can also be controlled by the clock signal FSW. The clock signal FSW can be provided by a clock circuit (not shown).

[0167] Fig. 11 is a diagram showing waveforms in relation to the operation of the system of Fig. Figure 10 shows a curve 1100 of the clock signal FSW; a curve 1102 of the digitized current error signal DIERR; a curve 1104 of the PWM signal; and a curve 1106 of a negative of the ripple correction signal RIPC.

[0168] In the present diagram, curve 1106 is discontinuous and shows a portion of the total ripple suppression signal RIPC. Curve 1106 includes nonlinear sections 1108 (also labeled S2P) of the rising edge and nonlinear sections 1110 (also labeled S1P) of the falling edge of the ripple suppression signal RIPC. It should be noted that in the diagram, the falling edge rises and the rising edge falls, as -RIPC is indicated.

[0169] The 800 ripple suppression signal generator can be configured to generate the RIPC ripple suppression signal by setting the RIPC ripple suppression signal to zero at each transition of the FSW clock signal, as shown in Fig. 11 shown.

[0170] As previously stated, the control device 200 of Fig. 8(b) The sampling technique described above avoids resonant local loops. The resonant local loops can be eliminated by avoiding the sampling effects. This is achieved by setting the ripple suppression signal RIPC to values ​​of 0 at each transition of the clock signal FSW, which do not depend on the unfiltered digital current error DIERR.

[0171] The clock edges of the clock signal FSW are used to trigger the nonlinear edges S1P and S2P at values ​​of 0. S1P and S2P can be recalculated in the same way as the recursive equation DIL (which yielded DIERR). Subtracting S1P and S2P from DIERR in the segments shown mathematically cancels the ripple in the result DIERRF. The start / stop point of these segments is chosen because this is where the decision to start / stop the signal PWM is made.

[0172] In a specific embodiment and within each signal period, the rising edge of the ripple suppression signal RIPC can include a first linear section and the falling edge of the ripple suppression signal RIPC can include a second linear section.

[0173] In a specific embodiment, the rising edge comprises the first linear section, which rises linearly to zero, and the first nonlinear section, which rises nonlinearly from zero. Furthermore, the falling edge comprises the second linear section, which falls linearly to zero, and the second nonlinear section, which falls nonlinearly from zero.

[0174] Fig. Figure 12 is a schematic representation of a specific embodiment of the digital control device 200 according to an eighth embodiment of the present disclosure. It is obvious that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and according to the understanding of those skilled in the art.

[0175] Compared to the digital control device 200 from Fig. 10 The digital control device 200 of the present embodiment further comprises the PWM circuit 308 and the gate driver circuit 310, which function as previously described. In the present embodiment, the ripple suppression signal generator is configured to generate the ripple suppression signal RIPC using the PWM signal.

[0176] Fig. 13 is a diagram showing waveforms relating to the operation of the system of Fig. 12. Shown is a curve 1300 of the PWM signal; a curve 1302 of the negative of the ripple suppression signal RIPC; a curve 1304 of the clock signal FSW; a curve 1306 of the unfiltered digital current error DIERR; and a curve 1308 of the filtered digital current error DIERRF.

[0177] The rising edge of the ripple suppression signal RIPC includes a nonlinear section 1310 (also designated S2P) and a linear section 1312 (also designated S2S) within each period. The falling edge of the ripple suppression signal RIPC includes a nonlinear section 1314 (also designated S1P) and a linear section 1316 (also designated S1S) within each period.

[0178] In the present embodiment, the nonlinear section S1P has an exponential decay profile, and the nonlinear section S2P has an inverse exponential growth profile. It is obvious that these profiles in Fig. 13 are inverted because -RIPC is shown, whereas a diagram of RIPC would show the profiles as described.

[0179] In a specific embodiment, the ripple suppression signal generator 800 can be configured to generate the ripple suppression signal RIPC using the PWM signal by alternating between the rising and falling edges of the ripple suppression signal RIPC at each transition of the PWM signal. This is indicated by the occurrence of PWM signal edges in Fig. 13 shown, which are labelled with the numbers 1318 and 1320.

[0180] The PWM signal comprises a magnetization state and a demagnetization state. The ripple suppression signal generator 800 can be configured to generate the RIPC ripple suppression signal by producing the falling edge when the PWM signal is in the magnetization state and the rising edge when the PWM signal is in the demagnetization state.

[0181] In an embodiment where the energy storage element 206 is the inductor 400, the first linear section of the rising edge S2S is equal to the output voltage Vout divided by the inductance L, and the second linear section S1S of the falling edge is equal to the output voltage Vout minus the input voltage Vin divided by the inductance L.

[0182] With reference to Fig. 13. It can be observed that in Fig. In the embodiment shown in Figure 12, the ripple suppression signal RIPC is generated by combining both linear and nonlinear edges, which offers the following advantages: • True mathematical ripple suppression is preferred when the resulting filtered digital current error DIERRF crosses the ramp signal RAMP. In this case, it is preferable to use S1P / S2P, which closely follow the edges of the digital inductor current DIL. • Once the crossing of DIERRF and RAMP is complete, which is indicated by the PWM signal, it is preferable to avoid a large discontinuity in DIERRF (and DCA) properties: therefore, S1S / S2S is used, as it guarantees 0 for the next transition to S1P / S2P without large computational requirements.

[0183] The selection of S1P, S2P, S1S, S2S is in Fig. 13 shown, as well as the filtered digital current error DIERRF, as provided for by equation (4).

[0184] It should be noted that the use of a leading / lagging modulation scheme offers advantages. In particular, considering the delays of the power stage, the rising / falling clock edges of the clock signal FSW occur midway through the magnetization / demagnetization phase, allowing the transition between edges to happen at a time when no decision is being made.

[0185] Fig. 13 can be further summarized over an entire TSW period using the timestamps shown: 1. On the falling edge of the FSW clock, RIPC uses S2P to compensate for the ripple on DIERR. Since DIERR itself has the same S2P edge, we have a mathematical cancellation: DIERRR is flat. 2. Crossover has been detected and PWM is now "1". We no longer need perfect cancellation, but preferably we suppress all sampling effects and any dependence on DIERR itself. We therefore use the straight edge S1S. This introduces a moderate jump and residual curvature. 3. On the rising edge of the FSW clock, the leading / falling edge characteristics are such that the crossing of DCA (which is just a shifted version of DIERRF) with RAMP occurs later, after this marker. Furthermore, S1S has reached 0, so RIPC is set to S1P, and it starts at 0. From this point on, mathematical cancellation is ensured. 4. A DIERRF / DCA crossover occurs and PWM returns to zero. Perfect cancellation is no longer necessary, therefore we use S2S, which guarantees a value of 0 on the next switch. 5. The front / back edge modulator ensures that the crossing occurs after this marker. Switch to S2P, as in marker 1.

[0186] Fig. Figure 14 is a diagram showing the generation of the straight edges, which are used, for example, for the straight edge sections of the ripple suppression signal RIPC with respect to the Fig. 12 and Fig. The embodiment described in section 13 can be used. A curve 1400 for generating a first straight edge is shown; and a curve 1402 for generating a second straight edge.

[0187] The DIERRF result from the correction (DIERR(t)+RIPC(t)) preferably shows minimal discontinuities. This is the edge of the DIERRF signal used to generate PWM (e.g., as in relation to Fig. 5(c) described). Sudden transitions of DIERRF can lead to faulty edge calculations, where the use of straight edge sections of the ripple suppression signal RIPC solves this problem.

[0188] For the negative of the ripple suppression signal RIPC, the straight edge S1S during MAGNETIZATION is equal to (Vin-Vout) / L; and the straight edge of S2S during DEMAGNETIZATION is equal to -Vout / L.

[0189] It is obvious that the edges for the ripple suppression signal RIPC are provided by the equations for the negative signal multiplied by minus 1.

[0190] These edges are started and reset in such a way that they cross zero on the edges of the DCDC clock FSW. Therefore, they are independent of DIERR. It is simple to calculate the starting point of these edges at the moment they are reset (on an FSW edge) to guarantee the zero crossing on the other FSW edge.

[0191] Fig. Figure 15 is a schematic representation of a specific embodiment of the digital control device 200 and the step-down converter 202, wherein the digital control device 200 comprises the ripple suppression signal generator 800, which may correspond to one of the embodiments described herein, and according to a ninth embodiment of the present disclosure. In this specific example, the ripple suppression generator 800 functions as described in Fig. 12 illustrated embodiments are described.

[0192] In summary, the control device 200 operates to eliminate the nonlinear ripple of the digital inductor current signal DIL by using a ripple suppression signal RIPC with straight edges, which allows the avoidance of a parasitic sampling effect, and nonlinear edges, which allow mathematical cancellation at critical decision points.

[0193] Fig. Figure 16 is a diagram showing simulation results for a practical implementation of the in Fig. The system shown in 15 is illustrated. Fig. 16 is a discrete-time simulation. It should be noted that DCA is the shifted version of DIERRF, but has the same ripple.

[0194] A curve 1600 of the digital current setpoint DITARGET is shown; a curve 1602 of the digital inductor current DIL; a curve 1604 of the unfiltered digital current error DIERR; a curve 1606 of the clock signal FSW; a curve 1608 of the straight edge S1S; a curve 1610 of the straight edge S2S; a curve 1612 of the PWM signal; a curve 1614 of the ramp signal RAMP; and a curve 1616 of the digital signal DCA.

[0195] Fig. Figure 17(a) is a schematic representation of a specific example of PID 302, as it can be used with any of the embodiments described herein, according to the understanding of those skilled in the art. D, P, I are gains used for matching.

[0196] Fig. Figure 17(b) is a schematic representation of a specific example of the ripple suppression signal generator 800, as it can be used with any of the embodiments described herein, according to the understanding of those skilled in the art. The signal generator 800 in the present example comprises synthesizers 1700, 1702; stage extraction and accumulation units 1704, 1706; and a selection circuit 1708. • S1S and S2S are straight edges, which according to Fig. 14 were created by synthesizers 802, 804 with knowledge of the digitized VIN, VOUT, L, so that the edges S1S=(VIN-VOUT) / L and S2S=(-VOUT)) / L are in the digital domain. • S1P and S2P are cumulative edges: they are reset to 0 until they are selected (as in Fig. 11). Then they are created by accumulating the steps coming from DIERR. For example, S1P is in Fig. 13 from 0 to time 3, then it is created using the same digital steps as DIERR.

[0197] Various improvements and modifications can be made to the above without altering the scope of the disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 9419627B2 [0118, 0138] US 9667260B2 [0118, 0138]< / x> < / dil> < / ditarget>

Claims

[1] A digital control device for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device configured to: Receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element; Generating a filtered digital current error signal using the digitized current signal and a ripple suppression signal, wherein the ripple suppression signal is provided to reduce the ripple of the digital current signal in generating the filtered digital current error signal; and Controlling the switching converter, whereby the control of the switching converter depends on the filtered digital current error signal. [2] The digital control device according to claim 1, wherein the digital current signal is received by a digitized current generation circuit. [3] The digital control device of claim 1 or 2, configured to receive a digitized output voltage signal, wherein the digitized output voltage signal is a digital representation of the output voltage of the switching converter. [4] The digital control device according to claim 3, configured to generate a digital command current signal using the digitized output voltage signal. [5] The digital control device according to claim 4, comprising: a first voltage error generation circuit configured to use the digitized output voltage signal and a digital voltage reference signal to generate a digital error signal; and a proportional-integral-derivative circuit configured to convert the digital error signal into the digital command current signal. [6] The digital control device according to claim 4 or 5, comprising: a first current error generation circuit configured to use the digital desired current signal and the digital current signal to generate an unfiltered digital current error signal; and a ripple suppression circuit configured to: Receiving the unfiltered digital current error signal and the ripple suppression signal; and Generating the filtered digital current error signal by using the ripple suppression signal to reduce the ripple of the unfiltered digital current error signal. [7] The digital control device according to claim 6, wherein the ripple suppression circuit is configured to generate the filtered digital current error signal by adding the unfiltered digital current error signal to the ripple suppression signal. [8] The digital control device according to any preceding claim, comprising: a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current error signal; and a logic and gate driver circuit configured to receive the PWM signal and generate a gate driver signal for each of the one or more power switches using the PWM signal. [9] The digital control device according to claim 8, wherein the pulse modulation circuit comprises: a duty cycle signal generation circuit configured to generate a digital signal using the filtered digital current error signal and an offset signal; and a comparator configured to receive the digital signal and a ramp signal and to output the PWM signal based on a comparison between the digital signal and the ramp signal. [10] The digital control device according to claim 9, wherein the comparator is configured to generate the PWM signal comprising rising and falling edges dependent upon the digital signal crossing the ramp signal. [11] The digital control device according to claim 9 or 10, wherein the offset signal depends on a duty cycle of the switching converter and a maximum value of the ramp signal. [12] A method of controlling, using a digital control device, a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the method comprising: Receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element; Generating a filtered digital current error signal using the digitized current signal and a ripple suppression signal, wherein the ripple suppression signal is provided to reduce a ripple of the digital current signal when generating the filtered digital current error signal; and Controlling the switching converter, whereby the control of the switching converter depends on the filtered digital current error signal.

Images