DIGITAL CONTROL DEVICE

Abstract

A digital control device for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising a ripple suppression signal generator configured to generate a ripple suppression signal, the digital control device being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, generating a filtered digital current fault signal using the digitized current signal and the ripple suppression signal, the ripple suppression signal being provided to reduce ripple in the digitized current signal when generating the filtered digital current fault signal.and controlling the switching converter, wherein the control of the switching converter depends on the filtered digital current error signal, wherein the ripple suppression signal in each signal period includes a rising edge comprising a first nonlinear section and / or a falling edge comprising a second nonlinear section.

Description

[0001] The present disclosure relates to a digital control device. In particular, the present disclosure relates to a digital control device for a switching converter. BACKGROUND

[0002] Fig. 1(a) is a schematic diagram of a digital buck converter 100 including analog-to-digital converters (ADCs) 102, 104, 106 and a controller 108. The buck converter 100 includes switches 110, 112, an inductor 114, and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0003] While the power stage and passive components (inductor 114 and capacitor 116) remain the same as in an analog buck converter, ADC 102 converts the output voltage VOUT into a digital number. This conversion is performed at a specific rate in the time domain: for example, the digital number VOUT is updated every 1µs.

[0004] Optionally, the inductor current IL of the inductor 114 and the input voltage VIN can also be converted from analog to digital depending on the digital control method.

[0005] We distinguish: • For example, the switching frequency (FSW) of the buck converter 100 is 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the power stage frequency. • The processing frequency of the digital controller 108 (FS), for example, approximately 100 MHz. FS is equal to 1 / TS, where TS is the processing time of the controller 108. FS can optionally also be the sampling frequency of the ADC 102.

[0006] Fig. Figure 1(b) is a schematic diagram of an average current mode digital buck converter 118 with a control circuit 120.

[0007] The operation of the circuit of Fig. 1(b) is as follows: • The output voltage VOUT is digitized by the ADC 102 to provide a digitized output voltage signal DOUT. The digitized output voltage signal DOUT is compared to a digital reference voltage DREF, which corresponds to the target voltage for the output voltage VOUT. Both numbers DOUT and DREF can be, for example, 8-bit bus, where the digital code [0; 255] corresponds to the analog range [0.50V; 1.50V]. • A digital error voltage signal DVERR is equal to DREF-DOUT, which is provided to a digital control loop proportional-integral-derivative (PID) circuit 122 to convert this digitized error voltage DVERR into a digital command current DITARGET, which is a digital number that is the command for setting the analog inductor current IL. When the output voltage VOUT decreases, the digitized output voltage signal DOUT also decreases, the digital error voltage signal DVERR increases, and the digital command current DITARGET increases: the digital control PID 122 requests more inductor current IL to restore the output voltage VOUT. • The digital target current DITARGET can be encoded on multiple bits, e.g., 16 bits, as well as the following signals. The inductor target current DITARGET enters an "inner loop" consisting of (a digital current generation circuit 123; a PIDI circuit 124; a PWM circuit 126; and the power stage 100). This inner loop adjusts the MAG / DEMAG duty cycle so that the analog inductor current IL averages out to its digital counterpart, the inductor current target DITARGET. • The digital current generation circuit 123 may be the ADC 104 as shown in Fig. 1(a), or may be a “synthesizer” so that it can digitally reproduce the behavior of the inductor current IL depending on the input voltage VIN, the output voltage VOUT, the duty cycle, and possibly other parameters. • The inner loop operates as follows: when the digital target current DITARGET is higher than the digital inductor current DIL, the digital current error DIERR increases. The digital current error DIERR passes through an integrator (PID 124) to produce a filtered and amplified version, where the filtered digital current error DIERRF increases and enters a digital-to-duty converter (the PWM circuit 126) to increase the duty cycle. This results in an increase in the inductor current IL.

[0008] The control circuit 120 also includes addition / subtraction circuits 128, 130 and the logic and gate driver circuit 132.

[0009] Once the inner loop has reached a steady state, the average digital set current is equal to the average digital inductor current, which can be denoted as follows: <ditarget> = <dil>

[0010] A variable enclosed in "<>" is used to denote an average of the variables. For example, <x>the average of the variable x.

[0011] Fig. Figure 1(c) is a graph illustrating the transient response of the digital buck converter 100. Curve 134 shows the output voltage VOUT; curve 136 shows the digital target current DITARGET; curve 138 shows the digital inductor current DIL; curve 140 shows the digital current error DIERR; curve 142 shows the filtered digital current error; and curve 144 shows a duty cycle DUTY. The digital inductor current DIL is the inductor current IL after digitization.

[0012] To simplify the explanation, Fig. 1(c) in the continuous time and data domain (as if it were analog and not digital).

[0013] We imagine a load that lowers the output voltage VOUT at the end of the period T0. • The control then increases the digital set current DITARGET to raise the output voltage VOUT again. This spontaneously increases the digital current error DIERR (which has the residual ripple inherited from DIL (since DIERR = DITARGET-DIL). • The filtered digital current error DIERRF increases slowly after the transition. At some point, the duty cycle is readjusted for the following period (sampling effect) and allows the inductor current IL (and thus the digital inductor current DIL) to increase, reducing the digital current error DIERR until the average of the digital inductor current DIL equals the desired digital inductor current DITARGET = 2A (at the end of T2).

[0014] It can be seen that the change in the filtered digital current error DIERRF takes a long time, so the decision to adjust the duty cycle is delayed. This degrades the response time of the buck converter 100. In particular, the time period T1 during which VOUT could continue to decrease was not utilized. SUMMARY

[0015] It is desirable to provide a digital control device that improves the response time of a switching converter, such as a digital buck converter, in response to a load transient.

[0016] According to a first aspect of the disclosure, a digital controller is provided for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, generate a filtered digital current error signal using the digitized current signal and a ripple orto generate a ripple suppression signal, wherein the ripple suppression signal is provided to reduce a ripple of the digital current signal when generating the filtered digital current error signal, and to control the switching converter, wherein the control of the switching converter is dependent on the filtered digital current error signal.

[0017] Optionally, the switching converter is a buck converter, a boost converter, or a buck-boost converter.

[0018] Optionally, the energy storage element is an inductor.

[0019] Optionally, the one or more circuit breakers comprise a first circuit breaker and a second circuit breaker.

[0020] Optionally, the digital current signal is received by a digitized current generation circuit.

[0021] Optionally, the digital current generation circuit comprises a first analog-to-digital converter configured to detect the current flow through the energy storage element and digitize the detected current flow to generate the digital current signal.

[0022] Optionally, the digital power generation circuit includes a power synthesizer.

[0023] Optionally, the digital control device is configured to receive a digitized output voltage signal, wherein the digitized output voltage signal is a digital representation of the output voltage of the switching converter.

[0024] Optionally, the digitized output voltage signal is received by a second analog-to-digital converter configured to receive the output voltage and digitize the output voltage to generate the digitized output voltage signal.

[0025] Optionally, the digital control device is configured to generate a digital target current signal using the digitized output voltage signal.

[0026] Optionally, the digital control device comprises a first voltage error generation circuit configured to use the digitized output voltage signal and a digital voltage reference signal to generate a digital error signal, and a proportional-integral-derivative circuit configured to convert the digital error signal into the digital desired current signal.

[0027] Optionally, the first voltage error generation circuit is configured to generate the digital error signal by subtracting the digitized output voltage signal from the digital voltage reference signal.

[0028] Optionally, the digital control device comprises a first current error generation circuit configured to use the digital command current signal and the digital current signal to generate an unfiltered digital current error signal, and a ripple suppression circuit configured to receive the unfiltered digital current error signal and the ripple suppression signal and generate the filtered digital current error signal by using the ripple suppression signal to reduce the ripple of the unfiltered digital current error signal.

[0029] Optionally, the first current error generation circuit is configured to generate the unfiltered digital current error signal by subtracting the digital target current signal from the digital current signal.

[0030] Optionally, the ripple suppression circuit is configured to generate the filtered digital current error signal by adding the unfiltered digital current error signal to the ripple suppression signal.

[0031] Optionally, the digital controller includes a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current error signal, and a logic and gate driver circuit configured to receive the PWM signal and generate a gate driver signal for each of the one or more power switches using the PWM signal.

[0032] Optionally, the pulse modulation circuit includes a duty cycle signal generation circuit configured to generate a digital signal using the filtered digital current error signal and an offset signal, and a comparator configured to receive the digital signal and a ramp signal and output the PWM signal based on a comparison between the digital signal and the ramp signal.

[0033] Optionally, the comparator is configured to generate the PWM signal, which includes rising and falling edges that depend on the digital signal crossing the ramp signal.

[0034] Optionally, the offset signal depends on a duty cycle of the switching converter and a maximum value of the ramp signal.

[0035] According to a second aspect of the disclosure, a method is provided for controlling, using a digital control device, a switching converter configured to receive an input voltage and generate an output voltage, wherein the switching converter comprises one or more power switches and an energy storage element, the method comprising receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element, generating a filtered digital current error signal using the digitized current signal and a ripple suppression signal, wherein the ripple suppression signal is provided to reduce a ripple of the digital current signal during generation of the filtered digital current error signal, and controlling the switching converter,where the control of the switching converter depends on the filtered digital current error signal.,

[0036] It will be appreciated that the method of the second aspect may comprise the features set out in the first aspect and may incorporate other features described therein.

[0037] According to a third aspect of the disclosure, a digital control device is provided for a switching converter configured to receive an input voltage and generate an output voltage, wherein the switching converter comprises one or more power switches and an energy storage element, wherein the digital control device comprises a ripple suppression signal generator configured to generate a ripple suppression signal, wherein the digital control device is configured to receive a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element, generate a filtered digital current error signal using the digitized current signal and the ripple suppression signal, wherein the ripple suppression signal is provided,to reduce a ripple of the digitized current signal when generating the filtered digital current error signal, and to control the switching converter, wherein the control of the switching converter is dependent on the filtered digital current error signal, wherein the ripple suppression signal comprises a rising edge comprising a first non-linear section and / or a falling edge comprising a second non-linear section within each signal period.

[0038] Optionally, the digital control device comprises a sampling circuit configured to sample the digital current signal, wherein the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the sampled digital current signal.

[0039] Optionally, the ripple suppression signal generator is configured to receive a clock signal, wherein the clock signal is a periodic digital signal having a switching frequency derived from the switching frequency of the switching converter, and to generate the ripple suppression signal using the clock signal, wherein the signal period of the ripple suppression signal is equal to the period of the clock signal.

[0040] Optionally, the switching frequency of the switching converter is controlled by the clock signal.

[0041] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal by setting the ripple suppression signal to zero at each transition of the clock signal.

[0042] Optionally, the ripple suppression signal within each signal period comprises the rising edge comprising a first linear portion and / or the falling edge comprising a second linear portion.

[0043] Optionally, the rising edge comprises the first linear portion increasing linearly to zero and the first non-linear portion increasing non-linearly from zero, and the falling edge comprises the second linear portion decreasing linearly to zero and the second non-linear portion decreasing non-linearly from zero.

[0044] Optionally, the digital controller comprises a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current error signal, and a logic and gate driver circuit configured to receive the PWM signal and generate a gate driver signal for each of the one or more power switches using the PWM signal, wherein the ripple suppression signal generator is configured to generate the ripple suppression signal using the PWM signal.

[0045] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal using the PWM signal by alternating between the rising edge and the falling edge at each transition of the PWM signal.

[0046] Optionally, the PWM signal includes a magnetization state and a demagnetization state, and the ripple suppression signal generator is configured to generate the ripple suppression signal by generating the falling edge when the PWM signal is in the magnetization state and generating the rising edge when the PWM signal is in the demagnetization state.

[0047] Optionally, the energy storage element is an inductor with an inductance.

[0048] Optionally, the first linear portion of the rising edge is equal to the output voltage divided by the inductance and the second linear portion of the falling edge is equal to the output voltage minus the input voltage divided by the inductance.

[0049] Optionally, the first nonlinear section has an inverse exponential growth profile and the second nonlinear section has an exponential decay profile.

[0050] Optionally, the ripple suppression signal generator is configured to generate the ripple suppression signal based on an operating state of the switching converter.

[0051] Optionally, the operating state of the switching converter is derived from the control state of the switching converter and / or the actual state of the switching converter.

[0052] Optionally, the control state depends on one or more PWM signals and / or the actual state depends on the switching state of the one or more power switches.

[0053] Optionally, the switching converter is a buck-boost converter and the control state depends on two PWM signals.

[0054] Optionally, the digital controller comprises a pulse width modulation circuit configured to generate the one or more PWM signals using the filtered digital current error signal, and a logic and gate drive circuit configured to receive the one or more PWM signals and generate a gate drive signal for each of the one or more power switches using the one or more PWM signals, wherein the ripple suppression signal generator is configured to generate the ripple suppression signal using the one or more PWM signals.

[0055] Optionally, the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the one or more PWM signals by alternating between the rising edge and the falling edge at each transition of at least one of the one or more PWM signals.

[0056] Optionally, each of the one or more PWM signals includes a magnetization state and a demagnetization state, and the ripple suppression signal generator is configured to generate the ripple suppression signal by generating the falling edge when at least one of the one or more PWM signals is in the magnetization state and generating the rising edge when at least one of the one or more PWM signals is in the demagnetization state.

[0057] According to a fourth aspect of the disclosure, a method for controlling a switching converter using a digital control device is provided, wherein the switching converter is configured to receive an input voltage and generate an output voltage, wherein the switching converter comprises one or more power switches and an energy storage element, wherein the digital control device comprises a ripple suppression signal generator configured to generate a ripple suppression signal, the method comprising receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element, generating a filtered digital current error signal using the digitized current signal and the ripple suppression signal, wherein the ripple suppression signal is provided,to reduce a ripple of the digitized current signal when generating the filtered digital current error signal, and controlling the switching converter, wherein the control of the switching converter is dependent on the filtered digital current error signal, wherein the ripple suppression signal comprises a rising edge comprising a first non-linear portion and / or a falling edge comprising a second non-linear portion within each signal period.

[0058] It will be appreciated that the method of the fourth aspect may include features set out in the third aspect and may incorporate other features described therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The disclosure will now be described in more detail by way of example only and with reference to the accompanying drawings, in which: Fig. 1(a) is a schematic diagram of a digital downconverter, Fig. 1(b) is a schematic diagram of an average current mode digital buck converter with control circuit, Fig. Figure 1(c) is a diagram showing the transient response of the digital buck converter; Fig. 2(a) is a schematic diagram of a digital control device for a switching converter according to a first embodiment of the present disclosure, Fig. 2(b) is a schematic representation of a specific embodiment of the Fig. 2(a) shown system, Fig. 2(c) is a schematic representation of another specific embodiment of the Fig. 2(a) shown system, Fig. 2(d) is a schematic representation of another specific embodiment of the Fig. 2(a) shown system; Fig. 3(a) is a schematic diagram of a specific embodiment of the control device according to a second embodiment of the present disclosure, Fig. 3(b) is a schematic diagram of a specific embodiment of the control device according to a third embodiment of the present disclosure; Fig. 4 is a schematic representation of a specific embodiment of the system of the present disclosure according to a fourth embodiment of the present disclosure; Fig. 5(a) is a timing diagram showing simulation results of a practical implementation of the Fig. 4 system shown, Fig. 5(b) is another timing diagram showing simulation results of a practical implementation of the Fig. 4 system shown, Fig. 5(c) is another timing diagram showing simulation results of a practical implementation of the Fig. 4 system shown, Fig. 5(d) is a diagram showing simulation results of a phase response and a gain response for a practical implementation of the circuit of Fig. 4 shows, Fig. 5(e) is a diagram showing a crossover point for the digital signal and the ramp signal, Fig. 5(f) is a schematic representation of an example of a local DLL (delay locked loop) as may be implemented in each of the described embodiments, Fig. 5(g) is a diagram showing a crossover point for the digital signal and the ramp signal; Fig. 6 is a diagram showing simulation results for a practical implementation of the system of Fig. 4 shows; Fig. 7(a) is a graph showing the time-varying digitized inductor current, Fig. 7(b) is a diagram showing the unfiltered digital current error, the ripple suppression signal and the filtered digital current error, Fig. Figure 7(c) is a diagram of a negatively idealized ripple cancellation signal using nonlinear slopes; Fig. 8(a) is a schematic diagram of a specific embodiment of the digital control device according to a fifth embodiment of the present disclosure, Fig. 8(b) is a schematic diagram of a specific embodiment of the digital control device according to a sixth embodiment of the present disclosure; Fig. 9(a) is a diagram showing the digitized inductor current for sampling, Fig. Figure 9(b) is a diagram of the gain and phase relationships using the sampling method compared to an idealized ripple cancellation signal and a schematic representation of a simulated circuit; Fig. 10 is a schematic diagram of a specific embodiment of the digital control device according to a seventh embodiment of the present disclosure; Fig. 11 is a diagram showing waveforms related to the operation of the system of Fig. 10 refer; Fig. 12 is a schematic diagram of a specific embodiment of the digital control device according to an eighth embodiment of the present disclosure; Fig. 13 is a diagram showing waveforms related to the operation of the system of Fig. 12 refer; Fig. Figure 14 is a diagram showing the generation of the straight edges that can be used for the straight edge portions of the ripple cancellation signal; Fig. 15 is a schematic diagram of a specific embodiment of the digital controller and the buck converter according to a ninth embodiment of the present disclosure; Fig. 16 is a diagram showing simulation results for a practical implementation of the Fig. 15 system shown; and Fig. 17(a) is a schematic diagram of a specific example of a digital control loop proportional-integral-derivative circuit, Fig. 17(b) is a schematic diagram of a specific example of the ripple suppression signal generator. DETAILED DESCRIPTION

[0060] In Fig. 1(b) the PID 124 acts as a low-pass filter and is used for the following reasons: • It is preferable for the PID 124 to apply a gain. For example, we have a 50% duty cycle, we want an inductor current IL = 1A, and the block PWM circuit 126 requires an input-filtered digital current error DIERRF between 0 and 15 to generate / control a duty cycle in [0; 1]. If the PID 124 had a gain of 1, (DITARGET-DIL) would have to be 7 to achieve the 50% duty cycle. Therefore, the digital command current DITARGET would have to be 8, for the digital inductor current DIL = 1A. We can see that the two values ​​DITARGET and DIL would be very different. This does not pose a fundamental problem for the operation of the buck converter 100, but we lose the advantage of DITARGET-DIL (which could be useful, among other things, for a current limiter applied to DITARGET). Applying the same calculation with a much larger PID 124 gain results in DITARGET being approximately equal to DIL, which is preferable. • The PID 124 must also filter the difference (DITARGET-DIL): in fact, this allows to remove the ripple on the error inherited by the ripple on DIL.

[0061] It should be noted that the buck converter 100 could cope with this unfiltered ripple. However, there are two drawbacks: 1. Subharmonic oscillations may occur, so caution must be taken when generating the duty cycle. 2. We use DIERRF at a specific time to decide / set the duty cycle. This is equivalent to sampling. Here, DIERRF may be 1 A away from the average DIERFF, which is zero, due to this ripple. Therefore, the inner loop may set the inductor current IL on average 1 A away from DITARGET. This leads to the same problem as in the case of the 124-bit PID with a gain of 1, and we encounter an additional problem in the case of multiphase with asymmetric inductors.

[0062] Therefore, in average current mode controllers, the PID 124 acts as an integrator to avoid these two problems.

[0063] However, the PID 124, which acts as an integrator, reacts slowly, leading to the previously described problems in response to a load transition. In summary, the integrating effect of the PID 124 has an adverse consequence: the DIERRF change takes longer, and the decision to adjust the duty cycle is delayed. This degrades the response time of the buck converter 100.

[0064] Fig. Figure 2(a) is a schematic diagram of a digital controller 200 for a switching converter 202 according to a first embodiment of the present disclosure. The switching converter is configured to receive an input voltage Vin and generate an output voltage Vout. The switching converter 200 includes one or more power switches 204 (represented by a single switch in the present example) and an energy storage element 206.

[0065] The digital control device 200 is configured to receive a digital current signal DI. The digital current signal DI is a digital representation of a current flowing through the energy storage element 206. The energy storage element 206 may, for example, be an inductor, such that the current flowing through the energy storage element 206 may correspond to the inductor current IL, and the digital current signal DI may correspond to the digital inductor current DIL, as previously described with respect to Fig. 1(b) discussed.

[0066] The digital controller 200 is further configured to generate a filtered digital current error signal DIERRF using the digital current signal DI and a ripple cancellation signal (RIPC). The ripple cancellation signal RIPC is provided to reduce ripple in the digital current signal DI during the generation of the filtered digital current error signal DIERRF.

[0067] It will be appreciated that in a specific embodiment, controller 200 may partially reduce the ripple, so that some ripple is still present on DIERRF. In an alternative embodiment, controller 200 may completely reduce the ripple, so that the ripple is removed during the generation of DIERRF.

[0068] The ripple results from the periodic charging and discharging of the energy storage element 206 during the switching operation of the switching converter 202. For example, for a buck converter, the ripple may be as previously described with respect to the operation of the inductor 114 and as illustrated in curves 138, 140. The "ripple" in the Fig. The example shown in Figure 1(c) refers to the periodic variation with a triangular profile resulting from the switching operation of the buck converter 100.

[0069] The digital controller 200 is further configured to control the switching converter 202, wherein the control of the switching converter 202 is dependent on the filtered digital current error signal DIERFF.

[0070] In a specific embodiment, the switching converter 202 may be, for example, a buck converter, a boost converter, or a buck-boost converter; and the energy storage element 206 may be an inductor.

[0071] The use of the ripple correction signal RIPC means that the ripple can be removed when generating the filtered digital current error signal DIERRF without the need for integration (as in Fig. 1(b) by the PID 124). Therefore, the present disclosure provides a control device that overcomes the disadvantages of known systems that respond slowly due to the PID 124, while retaining the advantages of an average current control mode.

[0072] Fig. 2(b) is a schematic representation of a specific embodiment of the Fig. 2(a). In the present embodiment, the digital controller 200 is configured to receive a digitized output voltage DVout. The digitized output voltage signal DVout is a digital representation of the output voltage Vout of the switching converter 202. The digitized output voltage signal DVout is generated using an analog-to-digital converter (ADC) 208, which receives the output voltage Vout and digitizes the output voltage Vout to provide the digitized output voltage signal DVout. The digitized output voltage signal DVout can be used to generate a digital target current signal DITARGET (not shown).

[0073] Fig. 2(c) is a schematic representation of another specific embodiment of the Fig. 2(a). In the present embodiment, the digital current signal DI is received by a digital current generation circuit 210. The digital current generation circuit 210 may, for example, include an analog-to-digital converter configured to detect the current flow through the energy storage element 206 and to digitize the detected current flow to generate the digital current signal DI. In another embodiment, the digital current generation circuit 210 may include a current synthesizer.

[0074] Fig. Figure 2(d) is a schematic representation of another specific embodiment of the Fig. 2(a), which includes features previously described with respect to the Fig. 2(b) and Fig. 2(c).

[0075] Fig. 3(a) is a schematic representation of a specific embodiment of the control device 200, as may be used in any of the embodiments described herein, as understood by those skilled in the art and according to a second embodiment of the disclosure.

[0076] The control device 200 includes a voltage error generation circuit 300 configured to use the digitized output voltage signal DVout and a digitized voltage reference signal DREF to generate a digital error signal DVERR.

[0077] The voltage error generation circuit 300 may be configured to generate the digital error signal DVERR by subtracting the digitized output voltage signal DVout from the digitized voltage reference signal DREF, which may be represented as follows: DVERR=DREF−DVout

[0078] The control device 200 further includes a proportional-integral-derivative (PID) circuit 302 configured to convert the digitized voltage error signal DVERR into the digital target current signal DITARGET.

[0079] The control device 200 may further include a current error generation circuit 304 configured to use the digital target current signal DITARGET and the digitized current signal DI to generate an unfiltered digital current error signal DIERR.

[0080] The current error generation circuit 304 may be configured to generate the unfiltered digital current error signal DIERR by subtracting the digital target current signal DITARGET from the digital current signal DI as follows: DIERR=DI−DITARGET

[0081] The control device 200 may further include a ripple suppression circuit 306 configured to receive the unfiltered digital current error signal DIERR and the ripple suppression signal RIPC and to generate the filtered digital current error signal DIERRF using the ripple suppression signal RIPC to reduce the ripple of the unfiltered digital current error signal DIERR.

[0082] The ripple suppression circuit 306 may be configured to generate the filtered digital current error signal DIERRF by adding the unfiltered digital current error signal DIERR to the ripple suppression signal RIPC, as follows: DIERRF=DIERR+RIPC Fig. 3(b) is a schematic representation of a specific embodiment of the control device 200 as may be used in any of the embodiments described herein, as understood by those skilled in the art and according to a third embodiment of the disclosure.

[0083] In the present example, the control device 200 includes a pulse width modulation (PWM) circuit 308 configured to generate a PWM signal (referred to as "PWM" in the figures) using the filtered digital current error signal DIERRF. The digital current error signal DIERRF may be received by the components as described with respect to the Fig. 3(a) will be described, as understood by those skilled in the art.

[0084] The control device 200 further includes a logic and gate driver circuit 310 configured to receive the PWM signal and generate a gate driver signal GN for each of the one or more power switches 204 using the PWM signal.

[0085] It is obvious that the single gate drive signal GN is for illustrative purposes. In practice, and when applied to a switching converter with a high-side FET and a low-side FET, particularly when applied to a buck converter for the present example, when PWM = 0, the low-side FET is turned on by a gate drive signal; and when PWM = 1, the high-side FET is turned on by a gate drive signal.

[0086] Further, the logic and gate driver circuit may include a driver component for generating the driver signals; and a logic component for providing a break-before-make operation to handle the transition between high-side and low-side.

[0087] The PWM circuit 308 may further include a duty cycle signal generation circuit 314 configured to generate a digital signal DCA using the filtered digital current error signal DIERRF and an offset signal PDSS.

[0088] In a specific embodiment, the digital signal DCA may be as follows: DCA=DIERRF+PDSS

[0089] The PWM circuit 308 may further include a comparator 316 configured to receive the digital signal DCA and a ramp signal RAMP and output the PWM signal based on a comparison between the digital signal DCA and the ramp signal RAMP.

[0090] The comparator 316 may be configured to generate the PWM signal such that the PWM signal has rising and falling edges that depend on the digital signal DCA crossing the ramp signal RAMP.

[0091] It is obvious that the comparator 316 is functionally a comparator, but its resolution in the time domain is increased by the use of one or more DLLs.

[0092] For example, if the clock frequency FS for a direct comparator were 100MHz, the time resolution for PWM would be 10ns, since the comparator in digital mode would update the PWM every 10ns. In reality, the comparator 316 follows the scheme in Fig. 5(e): Comparing the digital edges of DCA and RAMP and generating a precise time for the PWM duration (much finer than 10 ns) using DLL. In further embodiments, the functionality of comparator 316 may be provided by more than one comparator.

[0093] The offset signal PDSS can depend on a duty cycle D of the switching converter 202 and a maximum value of the ramp signal RMAX. For example, if the ramp signal RAMP varies from 0 to RMAX, PDSS can be calculated graphically if we want the duty cycle D, as follows: PDSS=(1−D).RMAX

[0094] It is obvious that equation (6) in the case of Fig. 5(c) is valid where RAMP is a triangular signal. In further embodiments where RAMP has a different profile, it will be different, but easily deducible graphically for those skilled in the art.

[0095] For an embodiment in which the switching converter 202 is a buck converter, equation (6) can be rewritten as follows: PDSS=(1−Vout / Vin).RMAX

[0096] Fig. 4 is a schematic representation of a specific embodiment of the system of the present disclosure, wherein the switching converter 202 comprises a buck converter, and according to a fourth embodiment of the present disclosure. The buck converter includes an inductor 400, two power switches 402, 404, and an output capacitor 406, and uses current mode control. The logic and gate driver circuit 310 outputs two gate drive signals GP, GN, with each signal provided to one of the power switches 402, 404. The logic and gate driver circuit 310 may also include a break-before-make system (as noted above) provided by the logic circuit. The components 300, 304, 306 may be adders and / or subtractors, as understood by those skilled in the art.

[0097] Fig. Figure 5(a) is a timing diagram showing simulation results of a practical implementation of the Fig. 4. Shown are a curve 500 of the digital target current signal DITARGET; a curve 502 of the digital inductor current DIL; and a curve 504 of the unfiltered digital current error DIER-ROR.

[0098] The Fig. 5(a), Fig. 5(b) and Fig. 5(c) use a continuous time and a continuous data range for the timing diagrams for clarity.

[0099] In the present example, the energy storage element 206 is an inductor and therefore the digital current signal DI is the digitized inductor current DIL.

[0100] It is desirable that the average digital set current equals the average digital inductor current, as described by equation (1). As in Fig. As can be seen in Figure 5(a), the system is currently in this desired steady state over a period of time (denoted by TSW), as a curve 506 shows that the average of the digital current error DIERR over this period is 0A.

[0101] It can be seen that the unfiltered digital current error DIERR takes over the entire ripple of the digital inductor current DIL, provided that the digital current setpoint DITARGET is constant.

[0102] S1 and S2 are the edges of this ripple and come directly from the DIL. S1 and S2 can be either constant, typically (Vin-Vout) / L and -Vout / L for a buck converter, where "L" denotes the inductance of inductor 206. However, the edges S1 and S2 can be non-constant. Furthermore, the edges S1 and S2 can be exponential, for example, due to the series resistances in the power stage and / or the derating of the inductor. In the present disclosure, we assume that S1 and S2 are always known and can be compensated. S1 can follow IMAX(1-expt(-t / T)), where T=L / R and IMAX=(VIN-VOUT) / Rswitch.

[0103] Fig. Figure 5(b) is another timing diagram showing simulation results of a practical implementation of the Fig. 4. Shown is a curve 507 of the ripple suppression signal RIPC; and a curve 508 of the filtered digital current error DIERRF.

[0104] The ripple suppression signal RIPC has opposite edges to the digital current error DIERR and is centered around zero.

[0105] Since the digital current error DIERR is a digital edge and provided that its values ​​over time are perfectly known, the ripple suppression signal RPIC can be generated with opposite polarity and with the same digital numbers in absolute value.

[0106] In this way, the sum of DIERR and RIPC (as provided by equation (4)) results in mathematical ripple removal. Due to digital processing, we can therefore achieve ripple removal without the need for PID 124.

[0107] Fig. Figure 5(c) is another timing diagram showing simulation results of a practical implementation of the Fig. 4. Shown are a curve 510 of the offset signal PDSS; a curve 512 of the ramp signal RAMP; a curve 514 of the digital signal DCA; and a curve 516 of the PWM signal. PDSS denotes a predictive offset to obtain a steady state duty cycle (DSS). The relationship between the Fig. 5(c) is given by equation (5).

[0108] It should be noted that (DIL-DITARGET) is generated instead of (DITARGET-DIL) to satisfy the final modulation scheme (see Fig. 5(c)). Other embodiments may generate DITARGET-DIL, as understood by those skilled in the art.

[0109] As previously stated with regard to Fig. As explained in Figure 1(a), the average current mode provides a gain (infinite at 0 Hz because the PID 124 is an integrator) to keep the average DITARGET and the average DIL essentially equal.

[0110] The generation of DIERRF using the ripple cancellation signal RIPC, as provided by equation (4), is a unity gain operation.

[0111] The duty cycle D (represented by the PWM signal) is generated by the crossings of the digital signal DCA against a triangular ramp RAMP. In the present example, this is achieved by a dual leading / trailing edge: the rising edge of the PWM signal (MAGNETIZE) is not synchronized by a clock ("trailing edge modulation"), or the falling edge is not synchronized by a clock ("leading edge modulation"). Instead, both rising / falling edges of PWM are determined by crossing DCA RAMP.

[0112] The digitized version of Vin and Vout can be used to generate the offset signal PDSS according to equation (7). An analog-to-digital converter can be used to capture the input voltage Vin, digitize Vin, and generate a digital signal representing Vin. DVout can be generated as previously described and within the understanding of those skilled in the art.

[0113] The method of duty cycle control using the offset signal PDSS means that the required duty cycle D can be achieved within acceptable tolerances for practical applicability while the average of the filtered digital current error DIERRF remains equal to zero, so that the average DITARGET is equal to the average DIL.

[0114] This method may be referred to as DSS (Steady-State Duty-Cycle), as mentioned in the literature "An Estimative Current Mode Controller for DC-DC Converters Operating in Continuous Conduction Mode, IEEE paper by Mehdi Ferdowsi", which uses a different method than the present disclosure and does not use leading / trailing edge operations.

[0115] The advantages of having both rising / falling edges determined by a crossing of DCA and RAMP are: • If Vout varies, this is passed to DITARGET, which changes the DCA level (after removing the ripple). This can be done up to the DCA / RAMP intersection, so that the sampling effect no longer occurs at the beginning of a period, as with a DPWM, as in Fig. 1(a), (b), and (c). Any sudden change in Vout can modify the PWM rise time until just before TS before this transition. • The falling PWM edge is re-evaluated until DCA crosses RAMP. This results in two evaluations / samples in one TSW period. This results in bandwidth improvements compared to the system that uses only leading-edge modulation.

[0116] Fig. Figure 5(d) is a diagram showing simulation results of a phase response and a gain response for a practical implementation of the circuit of Fig. 4 and a circuit that uses only leading edge modulation. A curve 518 is a phase response of the circuit of Fig. 4; a curve 520 is a phase response of the circuit using only leading edge modulation; a curve 522 is a gain response of the circuit of Fig. 4; and a curve 524 is a gain response of the circuit using only leading edge modulation. The circuit of Fig. 4 shows, as already explained, an improvement in bandwidth compared to the circuit that uses only leading edge modulation.

[0117] The following discussion refers to discrete-time considerations. To meet the requirements of mobile communications, the duty cycle resolution is typically -200ps. Achieving this resolution would typically require a 5 GHz clock, which would result in excessive power consumption by the digital controller. Two known solutions are: • Dithering: Dithering is applicable to DPWM as described in Fig. 1(b), and would force sampling of the coarse duty cycle only once per TSW. We would therefore lose the benefit of re-evaluating the DCA / RAMP intersection at each TS. • Local high-clock domain for fine resolution. Although used in US9419627B2 and US9667260B2, the requirements for mobile communications are 30 times finer, and the required 5GHz would still cause excessive power consumption.

[0118] Embodiments of the present disclosure use a local DLL (delay locked loop) for fine resolution. This can be used for both leading and trailing edges. DLLs can enable slope-based intersection calculations for leading / trailing edges. More than one DLL can be used, for example, to reset and lock one DLL while the other is in use. In a specific embodiment where more modulators are needed (multi-phase), there are preferably one or more dedicated DLLs for each phase.

[0119] Fig. 5(e) is a diagram 526 showing a crossover point for the digital signal DCA and the ramp signal RAMP, where DCA is constant ("flat"); and a diagram 528 for the digital signal DCA and the ramp signal RAMP, where DCA is sloped.

[0120] In Fig. Figure 5(e) shows DCA and RAMP in the digital discrete time domain: they vary with the rate TS, which is, for example, 10 ns. The following two cases are shown: • Diagram 526. "Flat" constant DCA: the DIL-induced ripple was perfectly canceled and the average digital current setpoint was itself constant. • Diagram 528. Tilted DCA: although the DIL-induced ripple has been removed, the residual ripple on the average digital current setpoint itself is still present on the DCA.

[0121] In both cases, at each rising step of RAMP (or falling edge if RAMP is decreasing), the equivalent edge is calculated as in continuous time (dotted lines). Then, the time intersection of the two edges is calculated (labeled 530a in diagram 526 and 530b in diagram 528). At a time point labeled "IRQ," the calculation shows that in the shaded interval [TS / 2, 3TS / 2], the continuous time edges cross, and the crossing time is known.

[0122] In this example, the DLL divides the TS=10ns into 64 sections and is programmed to the required value. For example, the edges at "IRQ" cross 8.3ns later: relative to the time interval from TS / 2 to 3TS / 2. This corresponds to 3.3ns when started from TS / 2. The DLL code is calculated as (3.3ns / 10ns) multiplied by 64, which is equal to 21.

[0123] Fig. 5(f) is a schematic diagram of an example of a DLL 540 as may be implemented in any of the embodiments described herein, as understood by those skilled in the art.

[0124] The DLL 540 adds the 100 MHz clock to a series of, say, 64 delays TD. A control block 542, LCKCTRL, compares the output of the series "t64" with the next edge of the 100 MHz clock, which comes 10 ns later. If t64 comes after this next edge, it means that 64×TD exceeds 10 ns.

[0125] The LCKCTRL block 542 adjusts a control signal (either analog or digital) to make the TD delays faster. If t64 arrives before the next 100 MHz edge, this means that 64×TD is shorter than 10 ns. In this case, the LCKCTRL block 542 extends the delays using DELREG. Finally, after several 100 MHz cycles, the control device 542 ensures that 64×TD=10 ns. The DLL 540 is "locked," and TD~160ps=10 ns / 64.

[0126] We see that by selecting a tap using the MUX and the selection code sel<5:0>, the signal passage is obtained as a fraction N / 64 of the 10ns clock. DELREG, and more generally the system, can be analog or digital.

[0127] Fig. Figure 5(g) is a diagram 544 showing a crossover point for the digital signal DCA 546 and the ramp signal RAMP 548. We use sel<5:0> and IRQ for the DCA versus RAMP crossover point.

[0128] Some examples shown here involve DCA and RAMP, with their counterparts in the continuous time domain being SCA and SRAMP, respectively.

[0129] In the digital domain, we check DCA and RAMP in each clock period (e.g., 100 MHz): we calculate their continuous-time equivalents SCA and SRAMP and check if they cross in the next period. If this is the case, the digital controller (equivalent to block 316 in Fig. 4, which can provide additional functionality beyond a typical comparator) detects the crossing point in the continuous time domain and digitizes it as a code sel<5:0 >. In Fig. 5(g) is the intersection at 1 / 4 of TS=10ns, so the code is 16 (64 / 4) and is sent to the DLL 540.

[0130] Additionally, an interrupt IRQ is sent to instruct the DLL 540 to issue the signal crossover. This fine-tuning creates a crossover 2.5 ns after the IRQ, which corresponds to 1 / 4 of the total Ts=10 ns period. The "crossover" signal, in this case, starts the PWM via an RS latch, for example.

[0131] In a specific embodiment, the crossing can be predicted even further in advance: we do not check whether the crossing is within the next period, but within the next period plus half or a whole clock cycle, as in Fig. 5(e). In Fig. In Figure 5(e), IRQ is marked when the crossing occurs in the shaded area, which is not immediately afterward, but is delayed by half a cycle. The reason for the delay is that we allocate this time for the digital calculation of code_sel<5:0> (propagation through gates).

[0132] Fig. Figure 6 is a diagram showing simulation results for a practical implementation of the system of Fig. 4. The labeling of the curves corresponds to the labeling used previously. Shown is a curve 600 of the inductor current IL.

[0133] The digital target current DITARGET and the digitized inductor current DIL are differentiated, and the ripple is removed. A fixed offset PDSS is then added to obtain DCA.

[0134] Every time DCA is about to cross RAMP in the interval from TS / 2 to 3TS / 2 after evaluation, we see that the DLL code is adjusted (denoted by the number 602). This is sent to the DLL, and the signal PWM edges are triggered according to the DLL code. It can be seen that they are not aligned with rising / falling edges, but are at an intermediate point due to the fine-tuning.

[0135] The use of simultaneous leading / trailing edge modulation and management of discrete-time quantization using local DLLs, as present in embodiments of the disclosure, can be used to further improve performance and adapt to the requirements of mobile communications.

[0136] Fig. Figure 7(a) is a diagram showing a curve 700 of the digitized inductor current DIL varying with time, with the edges formed by straight lines; and a curve 702 of the digitized inductor current DIL varying with time, with the edges being nonlinear.

[0137] Curve 700 shows an idealized form of the digitized inductor current DIL, as used in US9419627B2 and US9667260B2. In reality, however, the digitized inductor current DIL does not exhibit the idealized form, but instead has rising and falling edges for each period with a nonlinear profile. In particular, the falling edge shows an exponential decay, and the rising edge shows a reverse exponential growth. Note that the timing diagrams show continuous time and continuous data to make the explanation clearer.

[0138] The curvature of the edges results from the resistance contributions of the switching converter 202. For example, and with reference to the example of the buck converter, as in Fig. As shown in Figure 4, the resistance of the inductor 400 and the on-resistances of the switches 402, 404 contribute to the nonlinear profiles.

[0139] It is obvious that other switching converters may also exhibit nonlinear edge profiles of the digital inductor current DIL (or the digital current DI if a different energy storage element is used).

[0140] In the discrete time domain (clocked at TS, which corresponds to the processing time of the controller 200), the digitized inductor current DIL during the magnetization phase, when the inductor is coupled to the input voltage Vin via the switch 402, can be represented as follows: isynth[n]=isynth[n−1]−A(RHS).isynth[n−1]+B.(Vin−Vout) / L

[0141] The digital inductor current DIL during the demagnetization phase, when the inductor is coupled to ground PGND via switch 404, can be represented as follows: isynth[n]=isynth[n−1]−A(RLS).isynth[n−1]−B.(VOUT) / L

[0142] The variable A term is thus the nonlinear correction of ideal edges, which is contributed by the B term. A=TS×RL where R is the sum of the direct current resistance (DCR) of inductor 400 and RHS (in the magnetized state); and R is the sum of DCR and RLS (in the demagnetized state); and applies to the case of a buck converter. RHS is the on-resistance of switch 402 and RHL is the on-resistance of switch 404. B = TS, where TS is the processing time of controller 200.

[0143] It is preferable to generate the ripple suppression signal RIPC such that a filtered digital current error DIERRF can be generated without ripple. Note that the subscript (t), as for RIPC(t), can be used to denote continuous time, while subscripts [n] are for discrete time.

[0144] Fig. Figure 7(b) is a diagram showing a curve 706 of the unfiltered digital current error DIERR; a curve 708 of the ripple suppression signal RIPC; and a curve 710 of the filtered digital current error DIERRF, as obtained by applying equation (4). In the present example, the ripple suppression signal RIPC uses straight edges.

[0145] As shown by equation (3), the digital current error signal DIERR is equal to the digital current signal DI minus the digital current command DITARGET, so that DIERR = DIL - DITARGET when the energy storage element 206 is the inductor.

[0146] As can be seen by curve 706, DIERR inherits the nonlinear ripple from DIL. The straight-line cancellation scheme using the ripple cancellation signal RIPC allows the filtered digital current error DIERRF to be centered at 0 A. Therefore, the ripple cancellation signal RIPC with a straight-line profile can be used with embodiments of the present disclosure to provide an improvement over known systems, for example, the ripple cancellation signal described in Fig. 1(b) system.

[0147] The difficulty of determining ΔIS and ΔIP (as in Fig. 7(b) and unequal) and adjusting the remaining DIERRF ripple as shown in curve 710 can, however, produce slow subharmonic oscillations that have been observed in simulations.

[0148] Therefore, further improvements can be achieved by using a different ripple cancellation signal RIPC. Fig. Figure 7(c) is a diagram of a negatively idealized ripple cancellation signal RIPC(t) using nonlinear edges. RIPC(t) is the inverse of the ripple of the inductor current IL, and its negative value, -RIPC, is represented by a curve 712, as shown in Fig. 7(c).

[0149] The preferred properties of RIPC(t) are: • It is centered at 0A. This is advantageous because it is desirable to cancel the ripple content while keeping the average of the digital inductor current DIL unchanged. • It cancels a recursive equation DIERR(t).

[0150] It is obvious that Fig. 7(c) shows an idealized representation and an improvement can be achieved in a practical system over a ripple cancellation signal RIPC that has straight edges without exactly matching the curve 712 or the preferred characteristics.

[0151] Fig. Figure 8(a) is a schematic diagram of a specific embodiment of the digital controller 200 including a ripple suppression signal generator 800, according to a fifth embodiment of the present disclosure. It is apparent that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and as understood by those skilled in the art.

[0152] The ripple suppression signal RIPC comprises, within each signal period, a rising edge comprising a first non-linear portion and a falling edge comprising a second non-linear portion.

[0153] For example, in a specific embodiment, the ripple suppression signal RIPC may have the profile shown by curve 712 in Fig. (7c).

[0154] In a specific embodiment, and with regard to the cancellation of the recursive equation DIERR(t), we can perform a calculation "back in time" to calculate the digitized inductor current DIL in a previous time step and from the starting iteration, as given by the equation: |(STR)=isynth[n−1]−A(RHS).isynth[n−1]+B.(Vin−Vout) / L

[0155] This can then be used to generate the ripple cancellation signal RIPC.

[0156] However, it may be difficult to generate the RIPC(t) curve before STR because the starting point of magnetization of the inductor 400 may be difficult to detect due to the calculation, which requires an evaluation of the digital inductor current DIL in an earlier time step.

[0157] Feasibility studies show that it is fundamentally possible to generate the ripple cancellation signal RIPC in this way, but it would require a processing clock above 5GHz, which would result in a consumption of >100 mA and a 30% degradation in efficiency.

[0158] Fig. Figure 8(b) is a schematic diagram of a specific embodiment of the digital control device 200 of Fig. 8(a) according to a sixth embodiment of the present disclosure. In the present disclosure, the digital control device further includes a sampling circuit 802 configured to sample the digital current signal DI. The ripple suppression signal generator 800 is configured to generate the ripple suppression signal RIPC using the sampled digital current signal DI. It should be noted that the following description refers to the energy storage element 206 being the inductor 400, so that the digital current signal DI is the digitized inductor current DIL. It is apparent that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and as understood by those skilled in the art.

[0159] Fig. Figure 9(a) is a diagram showing a curve 900 of the digitized inductor current DIL for sampling using the sampling circuit 802. To generate the ripple suppression signal RIPC(t), at each switching cycle of the switching converter DILPEAK and DILVALLEY (as shown in Fig. 9(a)) can be extracted, and the ripple suppression signal RIPC can be generated using the following equation: RIPC(t)=(DILPEAK+DILVALLEY) / 2−DIL(t)

[0160] Fig. 9(b) is a diagram 902 of the gain and phase relationships using the sampling method of the present embodiment (curves 904, 906) compared to an idealized ripple cancellation signal RIPC (curves 908, 910) and a schematic representation 912 of the simulated circuit of the present embodiment in relation to a practical implementation of the system.

[0161] The sampling technique means that there are local loops (for sampling / extraction) that create resonance effects and lead to subharmonic oscillations. Simplis POP simulations showed these resonances, as shown in Fig. 9(b).

[0162] Fig. 10 is a schematic diagram of a specific embodiment of the digital control device 200 according to a seventh embodiment of the present disclosure. It is apparent that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and as understood by those skilled in the art.

[0163] The ripple suppression signal generator 800 is configured to receive a clock signal. The clock signal FSW is a periodic digital signal with a switching frequency equal to the switching frequency FSW of the switching converter 202. The clock signal is Fig. 10 is labeled "FSW".

[0164] The ripple suppression signal generator 800 generates the ripple suppression signal RIPC using the clock signal FSW. The ripple suppression signal generator 800 can generate the ripple suppression signal RIPC using the clock signal FSW and the PWM signal. The signal period of the ripple suppression signal RIPC is equal to the period of the clock signal FSW.

[0165] The switching frequency of the switching converter 202 can also be controlled by the clock signal FSW. The clock signal FSW can be provided by a clock circuit (not shown).

[0166] Fig. 11 is a diagram showing waveforms related to the operation of the system of Fig. 10 shows. Shown are a curve 1100 of the clock signal FSW; a curve 1102 of the digitized current error signal DIERR; a curve 1104 of the PWM signal; and a curve 1106 of a negative of the ripple correction signal RIPC.

[0167] In the present diagram, curve 1106 is discontinuous and shows a portion of the total ripple suppression signal RIPC. Curve 1106 includes nonlinear portions 1108 (also denoted by S2P) of the rising edge and nonlinear portions 1110 (also denoted by S1P) of the falling edge of the ripple suppression signal RIPC. Note that in the diagram, the falling edge is rising and the rising edge is falling, since -RIPC is indicated.

[0168] The ripple suppression signal generator 800 may be configured to generate the ripple suppression signal RIPC by setting the ripple suppression signal RIPC to zero at each transition of the clock signal FSW, as shown in Fig. 11 shown.

[0169] As previously stated, the control device 200 of Fig. 8(b) leads to resonant local loops. The resonant local loops can be eliminated by avoiding the sampling effects. This is achieved by setting the ripple suppression signal RIPC to values ​​of 0 at each transition of the clock signal FSW, which values ​​are independent of the unfiltered digital current error DIERR.

[0170] The clock edges of the clock signal FSW are used to start the nonlinear edges S1P and S2P at values ​​of 0. S1P and S2P can be recalculated in the same way as the recursive equation DIL (which yielded DIERR). Subtracting S1P and S2P from DIERR in the segments shown results in mathematical cancellation of the ripple in the result DIERRF. The start / stop of these segments is chosen because this is where the decision regarding the start / stop of the signal PWM is made.

[0171] In a specific embodiment and within each signal period, the rising edge of the ripple suppression signal RIPC may include a first linear portion and the falling edge of the ripple suppression signal RIPC may include a second linear portion.

[0172] In a specific embodiment, the rising edge includes the first linear portion, which increases linearly to zero, and the first nonlinear portion, which increases nonlinearly from zero. Furthermore, the falling edge includes the second linear portion, which decreases linearly to zero, and the second nonlinear portion, which decreases nonlinearly from zero.

[0173] Fig. 12 is a schematic diagram of a specific embodiment of the digital control device 200 according to an eighth embodiment of the present disclosure. It is apparent that the ripple suppression signal generator 800 of the present embodiment can be used to generate the ripple suppression signal RIPC in any of the embodiments described herein and as understood by those skilled in the art.

[0174] Compared to the digital control device 200 of Fig. 10, the digital control device 200 of the present embodiment further includes the PWM circuit 308 and the gate driver circuit 310, which function as described above. In the present embodiment, the ripple suppression signal generator is configured to generate the ripple suppression signal RIPC using the PWM signal.

[0175] Fig. Figure 13 is a diagram showing waveforms related to the operation of the system of Fig. 12. Shown are a curve 1300 of the PWM signal; a curve 1302 of the negative of the ripple suppression signal RIPC; a curve 1304 of the clock signal FSW; a curve 1306 of the unfiltered digital current error DIERR; and a curve 1308 of the filtered digital current error DIERRF.

[0176] The rising edge of the ripple suppression signal RIPC includes a nonlinear portion 1310 (also denoted S2P) and a linear portion 1312 (also denoted S2S) within each period. The falling edge of the ripple suppression signal RIPC includes a nonlinear portion 1314 (also denoted S1P) and a linear portion 1316 (also denoted S1S) within each period.

[0177] In the present embodiment, the non-linear section S1P has an exponential decay profile and the non-linear section S2P has an inverse exponential growth profile. It is obvious that these profiles in Fig. 13 are inverted since -RIPC is shown, while a diagram of RIPC would show the profiles as described.

[0178] In a specific embodiment, the ripple suppression signal generator 800 may be configured to generate the ripple suppression signal RIPC using the PWM signal by alternating between the rising edge and the falling edge of the ripple suppression signal RIPC at each transition of the PWM signal. This is indicated by the occurrence of PWM signal edges in Fig. 13, which are designated by the numbers 1318 and 1320.

[0179] The PWM signal includes a magnetization state and a demagnetization state. The ripple suppression signal generator 800 may be configured to generate the ripple suppression signal RIPC by generating the falling edge when the PWM signal is in the magnetization state and generating the rising edge when the PWM signal is in the demagnetization state.

[0180] In an embodiment where the energy storage element 206 is the inductor 400, the first linear portion of the rising edge S2S is equal to the output voltage Vout divided by the inductance L and the second linear portion S1S of the falling edge is equal to the output voltage Vout minus the input voltage Vin divided by the inductance L.

[0181] With reference to Fig. 13 it can be observed that the Fig. 12, the ripple suppression signal RIPC is generated by combining both linear and non-linear edges, which offers the following advantages: • True mathematical ripple suppression is preferred when the resulting filtered digital current error DIERRF crosses the ramp signal RAMP. In this case, it is preferable to use S1P / S2P, which closely follow the edges of the digital inductor current DIL. • Once the crossing of DIERRF and RAMP is completed, which is indicated by the PWM signal, it is preferable to avoid a large discontinuity in DIERRF (and DCA) characteristics: therefore S1S / S2S are used, since they guarantee 0 for the next transition to S1P / S2P without large computational requirements.

[0182] The selection of S1P, S2P, S1S, S2S is in Fig. 13, as well as the filtered digital current error DIERRF, as provided by equation (4).

[0183] It should be noted that using a leading / lagging modulation scheme offers advantages. In particular, considering the power stage delays, the rising / falling edges of the DCDC clock of the clock signal FSW are in the middle of the magnetization / demagnetization phase, allowing the transition between the edges to occur at a time when no decision is being made.

[0184] Fig. 13 can be further summarized using the timestamps shown over an entire TSW period: 1. On the falling edge of the FSW clock, RIPC uses S2P to compensate for the ripple on DIERR. Since DIERR itself has the same S2P edge, we thus have a mathematical cancellation: DIERRF is flat. 2. Crossing has been detected and PWM is now "1". We no longer need perfect cancellation, but preferably we suppress all sampling effects and any dependence on DIERR itself. We thus use the straight edge S1S. This introduces a moderate jump and residual curvature. 3. On the rising edge of the FSW clock, the leading / trailing edge characteristics are such that the intersection of DCA (which is just a shifted version of DIERRF) with RAMP occurs later after this mark. Furthermore, S1S has reached 0, so RIPC is set to S1P, and it starts at 0. From this point on, mathematical cancellation is ensured. 4. A DIERRF / DCA crossover occurs, and PWM decreases. Perfect cancellation is no longer required, so we use S2S, which guarantees 0 at the next transition. 5. The leading / trailing edge modulator ensures that the crossing occurs after this marker. Switch to S2P, like marker 1.

[0185] Fig. Figure 14 is a diagram showing the generation of the straight edges used, for example, for the straight edge portions of the ripple suppression signal RIPC of the Fig. 12 and Fig. 13. Shown is a curve 1400 for generating a first straight edge; and a curve 1402 for generating a second straight edge.

[0186] The result DIERRF from the correction (DIERR(t)+RIPC(t)) preferably shows minimal discontinuities. This is the edge of the signal DIERRF, which is used to generate PWM (e.g., as described in relation to Fig. 5(c)). Sudden transitions of DIERRF can lead to erroneous edge calculations, but the use of straight edge portions of the ripple suppression signal RIPC solves this problem.

[0187] For the negative of the ripple suppression signal RIPC, the even edge of S1S during magnetization is equal to (Vin-Vout) / L; and the even edge of S2S during demagnetization is equal to -Vout / L.

[0188] It is obvious that the edges for the ripple suppression signal RIPC are provided by the equations for the negative signal multiplied by minus 1.

[0189] These edges are started and reset so that they cross 0 on the edges of the DCDC clock FSW. Thus, they are independent of DIERR. It is easy to calculate the starting point of these edges at the moment they are reset (on one FSW edge) to guarantee the 0 crossing on the other FSW edge.

[0190] Fig. 15 is a schematic representation of a specific embodiment of the digital controller 200 and the buck converter 202, wherein the digital controller 200 includes the ripple suppression signal generator 800, which may correspond to any of the embodiments described herein, and according to a ninth embodiment of the present disclosure. In this specific example, the ripple suppression generator 800 functions as described for the Fig. The embodiment shown in Figure 12 is described.

[0191] In summary, the controller 200 operates to eliminate the nonlinear ripple of the digital inductor current signal DIL using a ripple cancellation signal RIPC with straight edges that allow the avoidance of a parasitic sampling effect and nonlinear edges that allow mathematical cancellation at critical decision times.

[0192] Fig. 16 is a diagram showing simulation results for a practical implementation of the Fig. 15 shows the system shown. Fig. Figure 16 is a discrete-time simulation. Note that DCA is the shifted version of DIERRF, but has the same ripple.

[0193] Shown are a curve 1600 of the digital current command DITARGET; a curve 1602 of the digital inductor current DIL; a curve 1604 of the unfiltered digital current error DIERR; a curve 1606 of the clock signal FSW; a curve 1608 of the even edge S1S; a curve 1610 of the even edge S2S; a curve 1612 of the PWM signal; a curve 1614 of the ramp signal RAMP; and a curve 1616 of the digital signal DCA.

[0194] Fig. Figure 17(a) is a schematic representation of a specific example of PID 302, as may be used with any of the embodiments described herein, as understood by those skilled in the art. D, P, I are gains used for adjustment.

[0195] Fig. Figure 17(b) is a schematic diagram of a specific example of ripple cancellation signal generator 800, as may be used with any of the embodiments described herein, as understood by those skilled in the art. Signal generator 800 in the present example includes synthesizers 1700, 1702; step extraction and accumulation units 1704, 1706; and a selection circuit 1708. • S1S and S2S are straight flanks, which according to Fig. 14 were created by synthesizers 802, 804 with knowledge of the digitized VIN, VOUT, L, so that the edges S1S=(VIN-VOUT) / L and S2S=(-VOUT)) / L are in the digital domain. • S1P and S2P are cumulative edges: they are reset to 0 until they are selected (as in Fig. 11). They are then created by accumulating the steps coming from DIERR. For example, S1P is in Fig. 13 from 0 to time 3, then it is created with the same digital steps as DIERR.

[0196] Various improvements and modifications may be made to the above without departing from the scope of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 9419627B2 [0117, 0137] US 9667260B2 [0117, 0137]< / x> < / dil> < / ditarget>

Claims

[1] A digital control device for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising a ripple suppression signal generator configured to generate a ripple suppression signal, the digital control device being configured to: Receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element; Generating a filtered digital current error signal using the digitized current signal and the ripple suppression signal, wherein the ripple suppression signal is provided to reduce a ripple of the digitized current signal in generating the filtered digital current error signal; and Controlling the switching converter, wherein the control of the switching converter is dependent on the filtered digital current error signal; wherein: the ripple suppression signal in each signal period includes: a rising edge comprising a first non-linear section; and / or a falling edge comprising a second nonlinear section. [2] The digital control device according to claim 1, comprising a sampling circuit configured to sample the digital current signal, wherein the ripple suppression signal generator is configured to generate the ripple suppression signal using the sampled digital current signal. [3] The digital control device according to claim 1 or 2, wherein the ripple suppression signal generator is configured to: Receiving a clock signal, wherein the clock signal is a periodic digital signal having a switching frequency derived from the switching frequency of the switching converter; and Generating the ripple suppression signal using the clock signal; wherein: the signal period of the ripple suppression signal is equal to the period of the clock signal. [4] The digital control device according to claim 3, wherein the switching frequency of the switching converter is controlled by the clock signal. [5] The digital control device according to claim 3 or 4, wherein the ripple suppression signal generator is configured to generate the ripple suppression signal by setting the ripple suppression signal to zero at each transition of the clock signal. [6] The digital control device according to any preceding claim, wherein the ripple suppression signal in each signal period comprises: the rising edge comprising a first linear portion; and / or the falling edge comprising a second linear portion. [7] The digital control device according to claim 6, wherein: the rising edge includes: the first linear section, which increases linearly to zero; and the first nonlinear section, which increases nonlinearly from zero; and the falling edge includes: the second linear section, which decreases linearly to zero; and the second nonlinear section, which decreases nonlinearly from zero. [8] The digital control device according to claim 7, comprising: a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current error signal; and a logic and gate driver circuit configured to receive the PWM signal and generate a gate driver signal for each of the one or more power switches using the PWM signal; wherein: the ripple suppression signal generator is configured to generate the ripple suppression signal using the PWM signal. [9] The digital control device according to claim 8, wherein the ripple suppression signal generator is configured to generate the ripple suppression signal using the PWM signal by alternately transitioning between the rising edge and the falling edge at each transition of the PWM signal. [10] The digital control device according to claim 9, wherein: the PWM signal comprises a magnetization state and a demagnetization state; and the ripple suppression signal generator is configured to generate the ripple suppression signal by generating the falling edge, when the PWM signal is in the magnetization state, and generating the rising edge when the PWM signal is in the demagnetization state. [11] A method of controlling, using a digital control device, a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising a ripple suppression signal generator configured to generate a ripple suppression signal, the method comprising: Receiving a digitized current signal, wherein the digitized current signal is a digital representation of a current flow through the energy storage element; Generating a filtered digital current error signal using the digitized current signal and the ripple suppression signal, wherein the ripple suppression signal is provided to reduce a ripple of the digitized current signal in generating the filtered digital current error signal; and Controlling the switching converter, wherein the control of the switching converter is dependent on the filtered digital current error signal; wherein: the ripple suppression signal in each signal period includes: a rising edge comprising a first non-linear section; and / or a falling edge comprising a second nonlinear section.

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