Circuit arrangement for a binarized neural network using silicon gate diodes

Abstract

The present disclosure relates to a circuit arrangement of a binarized neural network using silicon gate diodes. The circuit arrangement of a binarized neural network according to one embodiment of the present disclosure comprises a plurality of silicon gate diodes in which a diode structure is arranged as a channel region between an anode terminal and a cathode terminal, a gate terminal is arranged on the diode structure to perform unidirectional switching by means of a potential barrier control in the channel region based on different voltages applied to each of the anode terminal and the gate terminal, and storage properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop.Furthermore, in the circuit arrangement of a binarized neural network, the silicon gate diodes operate as synaptic elements in a memory arrangement connected in parallel, and the results of a multiply-accumulate (MAC) operation are output based on an input signal applied by an input line processor connected to the memory arrangement and a weight update signal applied by a synapse line processor connected to the memory arrangement.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Korean Patent Application No. 10-2023-0114457, filed on August 30, 2023, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. BACKGROUND OF REVELATIONArea of ​​Revelation

[0002] The present disclosure relates to a circuit arrangement for a binarized neural network using silicon gate diodes, and more particularly to a technology for implementing a self-activating circuit arrangement for a binarized neural network that performs a self-activating function using a silicon gate diode that performs storage and switching functions in a single element based on a positive feedback loop. Description of the state of the art

[0003] In a conventional von Neumann-based computer system, a processor and memory are separate, and data signals are transmitted through a bus.

[0004] As computing power improves, a bottleneck phenomenon occurs due to a difference in data processing speed between a processor and a memory, and there are limits to processing large amounts of data.

[0005] That is, the von Neumann-based system, which is a product of revolutionary development in the semiconductor industry, has improved the integration density and performance of modern computers, but has the disadvantage of consuming a lot of power and having long data transmission and standby times due to the physical separation between a processor and a memory hierarchy.

[0006] Given the rise of data-intensive applications such as 5G communication standards, Internet of Things (IoT), and artificial intelligence (AI) following the fourth industrial revolution, a new computing paradigm is an essential requirement for large-scale data processing.

[0007] To solve the above problems, active research is being carried out on logic-in-memory (LIM) memory technology, which combines computation and storage functions.

[0008] According to internal logic memory technology, since the computing function of a processor and the storage function of a memory are executed in the same space, the time and power required during data transmission can be reduced, and the integration of the system can be greatly improved.

[0009] Conventional memory technology with internal logic has been actively researched based on static random-access memory (SRAM) and dynamic RAM (DRAM), which are volatile memory elements, and resistive RAM (ReRAM), magnetoresistive RAM (MRAM), and phase-change RAM (PCRAM), which are non-volatile memory elements.

[0010] To overcome limitations in processing large amounts of data, package-on-package (PoP) and through-silicon-via (TSV) technologies are being explored, which integrate logic memory into a single chip. However, since logic and memory functions are not executed simultaneously in a single transistor, problems remain regarding bottleneck phenomena, power consumption, computational efficiency, and integration.

[0011] In addition, memory technology with internal logic based on a non-volatile memory element requires a complex manufacturing process due to the use of non-silicon materials. Furthermore, this technology exhibits low element uniformity and stability, making practical use difficult.

[0012] Furthermore, previously explored memory technologies with internal logic cannot implement all basic complementary metal oxide semiconductor (CMOS) logic operations in one cell and have low integration because individual circuits and wiring are required for each logic operation.

[0013] Accordingly, the development of a binarized neural network technology using silicon gate diodes that can be applied to the CMOS process and can perform both switching and storage functions simultaneously, and a self-activated neural network technology that performs the activation function of a neuron circuit in a neural network is required. [Prior art documents][Patent documents] (Patent Document 1) Korean Patent Application Publication No. 10-2023-0053195, "State-dependent memory with internal logic using silicon diodes" (Patent Document 2) Korean Patent Application Publication No. 10-2022-0110774, "Power and Area Efficient Structure of Synaptic Memory Cell" (Patent Document 3) Korean Patent Application Publication No. 10-2023-0020840, "VARIABLE MEMORY ELEMENT WITH INTERNAL LOGIC USING SILICON TRANSISTORS" (Patent Document 4) Korean Patent Application Publication No. 10-2022-0107808, "Circuit Device of a Mixed-Signal Binary Neural Network" SUMMARY OF REVELATION

[0014] Therefore, the present disclosure has been made in view of the above problems, and it is an object of the present disclosure to implement a self-activating circuit arrangement for a binarized neural network that performs a self-activating function using a silicon gate diode that performs storage and switching functions in a single element based on a positive feedback loop.

[0015] It is a further object of the present disclosure to implement a self-activating circuit arrangement for a binarized neural network, which has unidirectional switching characteristics by controlling a potential barrier; and which is capable of increasing the area and computational efficiency of an artificial neural network by having excellent storage characteristics of a silicon gate diode, which also has storage characteristics as holes or electrons accumulated in a potential well due to a positive feedback loop and a self-activating function by the linearity of an output signal according to an input signal.

[0016] It is yet another object of the present disclosure to increase the computational accuracy of an artificial neural network by enabling the use of the CMOS process, enabling the fabrication of large-scale devices, and virtually eliminating the deviation between the characteristics of a silicon gate diode and the characteristics of a synaptic device.

[0017] It is yet another object of the present disclosure to implement a circuit arrangement for a binarized neural network comprising a memory arrangement consisting of silicon gate diodes based on a positive feedback loop and performing the activation function of a neuron circuit; and having excellent uniformity and stability.

[0018] It is yet another object of the present disclosure to implement a circuit arrangement for a binarized neural network that is capable of reducing standby power by utilizing the excellent memory characteristics of silicon gate diodes; and that can be used in next-generation artificial intelligence computing technology by increasing computing efficiency with low power consumption through excellent switching characteristics.

[0019] According to one aspect of the present disclosure, a circuit arrangement for a binarized neural network is provided, comprising a plurality of silicon gate diodes in which a diode structure is arranged as a channel region between an anode terminal and a cathode terminal, a gate terminal is arranged on the diode structure to perform unidirectional switching by potential barrier control in the channel region based on different voltages applied to each of the anode terminal and the gate terminal, and storage properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop, wherein the silicon gate diodes operate as synaptic elements in a memory arrangement connected in parallel, and results of a multiply-accumulate (MAC) operation based on an input signal,applied by an input line processor connected to the memory array and a weight update signal applied by a synapse line processor connected to the memory array.

[0020] The silicon gate diode can receive an anode voltage of the anode terminal as the input signal, generate a latch-up phenomenon due to the positive feedback loop when the applied input signal increases in a positive direction, have any of two storage states for the channel region, receive a gate voltage of the gate terminal as the weight update signal to control the input signal causing the latch-up phenomenon, update a synaptic state associated with the storage state according to the application of the input signal and the weight update signal, and perform the MAC calculation function according to the synaptic weight.

[0021] The silicon gate diode can output a current signal corresponding to one of "0" to "1" as an operation result by performing a multiplication operation between a continuous input of "0" to "1" when the applied input signal increases in a positive direction and a synaptic weight of any one of a "0" state and a "1" state corresponding to the two memory states.

[0022] In the silicon gate diode, in a case of potentiation operation in which the synaptic weight is updated to the "1" state, an operation result can be output as a current signal proportional to the applied input signal, and in a case of depression operation in which the synaptic weight is updated to the "0" state, a current signal at 0 mA can be output regardless of the applied input signal.

[0023] When the synaptic weight is in a "1" state, the silicon gate diode can output a cathode current of the cathode terminal in a form similar to a rectified linear unit (ReLU) function diagram form, regardless of the gate voltage.

[0024] The memory device may connect the anode terminal, the gate terminal, and the cathode terminal in parallel in the silicon gate diodes to form an input line, a weight line, and an output line, respectively. The input line may be arranged perpendicular to the weight line and the output line, and the weight line and the output line may be arranged in parallel.

[0025] The input line can receive the input signal, the weight line can receive the weight update signal, and the output line can output the MAC operation result based on the input signal and the weight update signal to a next artificial neural network.

[0026] In the memory device, the silicon gate diodes may be connected in a form of N x M, and by a multiplication operation of a synaptic weight updated based on an input signal applied to the input line and a weight update signal applied to the weight line, each current through the output line may be added and a sum operation performed to output the MAC operation results as a synaptic weight matrix.

[0027] In the memory array, when N and M are "2", the input signal may consist of a first input signal and a second input signal, the synaptic weight may consist of a first synaptic weight to a fourth synaptic weight, a first current and a second current may be output to the output line, and the synaptic weight matrix consisting of the first current and the second current may be calculated as a result of a vector matrix multiplication operation of the synaptic weight and the input signal.

[0028] In the memory device, when both the first and second input signals are applied while the weight update signal is fixed to 1 V, a value of the first current may be twice a value of the second current, and thereafter, when only the first input signal is applied, a value of the first current may be equal to a value of the second current.

[0029] In the memory device, when only the second input signal is applied, only the first current can have a value proportional to the second input signal, and when the first input signal and the second input signal are not applied, the first current and the second current can be measured close to 0 mA.

[0030] The silicon gate diode may comprise a single silicon gate diode, a double silicon gate diode, or a triple silicon gate diode. BRIEF DESCRIPTION OF THE CHARACTERS

[0031] The above and other objects, features and other advantages of the present disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1A to Fig. 2B are diagrams illustrating the structures and circuit symbols of a silicon gate diode constituting a circuit arrangement for a binarized neural network according to an embodiment of the present disclosure; Fig. 3A to Fig. 3C are diagrams illustrating the electrical characteristics of a silicon gate diode forming a circuit arrangement for a binarized neural network according to an embodiment of the present disclosure; Fig. 4 is a diagram illustrating circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure; Fig. 5A to Fig. 6B are diagrams illustrating a multiplication operation in a method of operating a binarized neural network circuitry using silicon gate diodes according to an embodiment of the present disclosure; Fig. 7A to Fig. 9F are diagrams illustrating a multiply-accumulate (MAC) operation in a method of operating a binarized neural network circuitry using silicon gate diodes according to an embodiment of the present disclosure; Fig. 10 includes the optical images of a silicon gate diode according to an embodiment of the present disclosure; and Fig. 11A to Fig. 11C are diagrams illustrating the arithmetic operations of a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF REVELATION

[0032] In the following, the embodiments of the present disclosure will be described in detail with reference to the figures.

[0033] It should be understood, however, that the present disclosure is not limited to the embodiments according to the concept of the present disclosure, but includes modifications, equivalents, or alternatives that fall within the spirit and scope of the present disclosure.

[0034] In the following description of the present disclosure, a detailed description of the known functions and configurations incorporated herein is omitted if it may obscure the subject matter of the present disclosure.

[0035] Furthermore, the terms used in the specification are defined in consideration of the functions used in the present disclosure and may be modified according to the intention or conventionally used methods of clients, operators, and users. Accordingly, definitions of the terms should be understood based on the entire description of this specification.

[0036] In the description of the figures, the same reference numerals may be used for similar elements.

[0037] The singular terms in this specification may include plural terms unless the context clearly indicates otherwise.

[0038] In this description, terms such as “A or B” and “at least one of A and / or B” may include all possible combinations of the elements listed together.

[0039] Expressions such as "first" and "second" can be used to qualify the elements regardless of order or importance, and are used to distinguish one element from another and not to limit the elements.

[0040] It is understood that when one element (e.g., first) is referred to as being “connected” or “coupled” to another element (e.g., second), the first element may be connected directly to the second element or may be connected to the second element via an intermediate element (e.g., third).

[0041] As used herein, “adapted to” may be used interchangeably, for example, with “suitable for,” “capable of,” “modified to,” “made for,” “able to,” or “designed for” with respect to hardware or software.

[0042] In some situations, the phrase “device adapted to” may mean that the device “can do” with other devices or components.

[0043] For example, in the sentence “processor configured to perform A, B, and C,” the processor may refer to a general-purpose processor (e.g., CPU or application processor) capable of performing a corresponding operation by executing an associated processor (e.g., embedded processor) for performing the corresponding operation or one or more software programs stored in a storage device.

[0044] In addition, the term “or” means “inclusive or” rather than “exclusive or”.

[0045] That is, unless otherwise stated or clear from the context, the phrase “x uses a or b” means any of natural inclusive permutations.

[0046] Terms such as “unit” or “module”, etc., should be understood as a unit that performs at least one function or operation and that may be implemented in a hardware manner, a software manner, or a combination of the hardware and software manners.

[0047] Fig. 1A to Fig. 2B are diagrams illustrating the structures and circuit symbols of a silicon gate diode constituting a circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0048] Fig. 1A and Fig. 1B illustrate the structures and circuit symbols of the silicon gate diode constituting the circuitry for a binarized neural network according to an embodiment of the present disclosure.

[0049] With reference to Fig. 1A, in a silicon gate diode 100 constituting the circuitry for a binarized neural network according to an embodiment of the present disclosure, a channel region between an anode terminal 101 and a cathode terminal 104 consists of a first channel region 102 and a second channel region 103.

[0050] A gate insulating film 105 is located on the second channel region 103 and a gate terminal 106 is located on the gate insulating film 105.

[0051] In a circuit symbol 110 of the silicon gate diode constituting the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a channel region 112 is located between an anode terminal 111 and a cathode terminal 113, and a gate terminal 114 is connected thereto.

[0052] With reference to Fig. 1B, in a silicon gate diode 120 constituting the circuitry for a binarized neural network according to an embodiment of the present disclosure, a channel region between an anode terminal 121 and a cathode terminal 124 consists of a first channel region 122 and a second channel region 123.

[0053] A gate insulating film 125 is located on the first channel region 122 and a gate terminal 126 is located on the gate insulating film 125.

[0054] In a circuit symbol 130 of the silicon gate diode constituting the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a channel region 132 is located between an anode terminal 131 and a cathode terminal 133, and a gate terminal 134 is connected thereto.

[0055] According to an embodiment of the present disclosure, an input line is connected to the anode terminal 111 or the anode terminal 131, an output line is connected to the cathode terminal 113 or the cathode terminal 133, and the memory state of the channel region is determined according to the update of a synaptic weight.

[0056] Fig. 2A illustrates the structure and circuit symbol of a dual silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure.

[0057] With reference to Fig. 2A, in a silicon gate diode 200 constituting the circuitry for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 202 is located between an anode terminal 201 and a cathode terminal 203, a gate insulating film 204 is located on the intrinsic region 202, and a first gate terminal 205 and a second gate terminal 206 are located on the gate insulating film 204.

[0058] The intrinsic region 202 operates as a channel region based on a gate voltage input from the first gate terminal 205 or the second gate terminal 206.

[0059] In a circuit symbol 210 of the silicon gate diode constituting the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 212 is located between an anode terminal 211 and a cathode terminal 213, and a first gate terminal 214 and a second gate terminal 215 are connected thereto.

[0060] Fig. 2B illustrates the structure and circuit symbol of a triple silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure.

[0061] With reference to Fig. 2B, in a silicon gate diode 220 constituting the circuitry for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 222 is located between an anode terminal 221 and a cathode terminal 223, a gate insulating film 224 is located on the intrinsic region 222, and a programming gate terminal 225 and a control gate terminal 226 are located on the gate insulating film 224.

[0062] The intrinsic region 222 operates as a channel region based on a gate voltage input from the programming gate terminal 225.

[0063] More specifically, when the magnitude of a programming voltage (VPG) input from the intrinsic region 222 to the programming gate terminal 225 is high, the intrinsic region 222 operates as an n-channel, corresponding to a first channel operation. When the magnitude of the programming voltage (VPG) is low, the intrinsic region 222 operates as a p-channel, corresponding to a second channel operation.

[0064] When the first channel operation is performed, if the magnitude of a control voltage (VCG) input through the control gate terminal 226 is large, it is determined that the silicon gate diode 220 is in the on state. If the magnitude of a control voltage (VCG) input through the control gate terminal 226 is low, it is determined that the silicon gate diode 220 is in the off state.

[0065] In a circuit symbol 230 of the silicon gate diode constituting the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 232 is located between an anode terminal 231 and a cathode terminal 233, and a programming gate terminal 234 and a control gate terminal 235 are connected thereto.

[0066] For example, the anode terminal, the gate terminal, and the cathode terminal may be referred to as an anode electrode, a gate electrode, and a cathode electrode, respectively.

[0067] That is, the silicon gate diode constituting the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure may have a structure in which a single gate electrode terminal is deposited on an n- or p-doped channel region on a silicon channel, or multiple gate electrode terminals are deposited on an intrinsically doped region.

[0068] In addition, the silicon gate diode operates by inducing a positive feedback loop through a potential barrier and exhibits switching and memory properties, so that the silicon gate diode can be designed as a synaptic element of the binarized neural network.

[0069] That is, the silicon gate diode has switching and storage properties that make it possible to implement a circuit arrangement for a self-activating binarized neural network in which the activation function of a neuron circuit is performed by a neural network.

[0070] Accordingly, the present disclosure can implement a circuit arrangement for a self-activating binarized neural network that performs a self-activating function using a silicon gate diode that performs storage and switching functions in a single element based on a positive feedback loop.

[0071] Fig. 3A to Fig. 3C are diagrams illustrating the electrical characteristics of a silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure.

[0072] Fig. 3A to Fig. 3C show the electrical characteristics of the silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure.

[0073] With reference to Fig. 3A shows a diagram 300 relating to the electrical properties of the silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure, a change in the cathode current (I Diode ) output to a cathode terminal according to an anode voltage (V IN ) which is applied to an anode terminal.

[0074] Diagram 300 shows that when the silicon gate diode forming the circuitry for a binarized neural network has an anode voltage (V IN) increases in the positive direction, a latch-up phenomenon occurs due to a positive feedback loop, and two states are shown.

[0075] In addition, the anode voltage at which latch-up occurs varies depending on the gate voltage (V W ) of the silicon gate diode.

[0076] The circuitry for a binarized neural network can perform synaptic weight update and multiply-accumulate (MAC) calculation functions by applying an anode voltage and a gate voltage based on the properties of the single element.

[0077] Regardless of the gate voltage, the cathode current (I Diode ) of an element in the “1” state should be similar to the diagram form of the function of a rectified linear unit (ReLU).

[0078] The ReLU function can be the activation function of a neuron circuit used in most artificial neural network architectures.

[0079] That is, in the silicon gate diode constituting the binarized neural network of the present disclosure, the output current has the shape of the ReLU function in the synaptic weight state of "1" regardless of the gate voltage, so that a circuit arrangement for a self-activating binarized neural network that self-activates a neuron circuit can be implemented.

[0080] Due to the unidirectional switching or self-rectification properties and the high linearity of a single silicon gate diode, a self-activating binarized neural network can be implemented that performs a self-activating function.

[0081] With reference to Fig. Figure 3B shows a diagram 310 relating to the electrical properties of the silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure, the case where the gate voltage (V W ) of the silicon gate diode is 0 V, with respect to a change in the cathode current (I Diode ) output to a cathode terminal according to an anode voltage (V IN ) which is applied to an anode terminal.

[0082] With reference to Fig. Figure 3C shows a diagram 320 relating to the electrical properties of the silicon gate diode forming the circuitry for a binarized neural network according to an embodiment of the present disclosure, the case where the gate voltage (V W ) of the silicon gate diode is 1 V, with respect to a change in the cathode current (I Diode) output to a cathode terminal according to an anode voltage (V IN ) which is applied to an anode terminal.

[0083] When the anode voltage (VIN) is 0 V, it may be in a standby state.

[0084] A diagram 320 shows the operating conditions of the Bayesian neural network (BNN), where the cathode current (I Diode ) at a gate voltage (V W ) of 1 V increases rapidly, at about 2.5 V, when the anode voltage (V IN ) increases.

[0085] Diagram 320 shows that a positive feedback loop is eliminated at about 1 V when the anode voltage (V IN ) decreases.

[0086] The bistable nature is called cathode current (I Diode ) to anode voltage (V IN ), and the high ratio of the current magnitudes of states 1 and 0 can be about 10 8 be.

[0087] When a gate voltage (V W ) 1 V for an anode voltage (V IN ) of 2 V, the electrical properties of a pn diode with unipolar switching properties are adopted.

[0088] Regardless of the gate voltage (V W ) is the shape of the curve for the cathode current (I Diode ) compared to the anode voltage (V IN ) in state 1 is similar to the form of the function of a rectified linear unit used in the activation function of a neural network.

[0089] The difference in cathode current (I Diode ) depending on the change between state 1 and state 0 can be used in MAC operation.

[0090] Fig. 4 is a diagram illustrating circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0091] Fig. 4 illustrates the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0092] With reference to Fig. 4, in a circuit arrangement 400 for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure, a diode structure is located as a channel region between an anode terminal and a cathode terminal, and a gate terminal is located on the diode structure. With this configuration, unidirectional switching is implemented by potential barrier control in the channel region based on different voltages applied to the anode terminal and the gate terminal, respectively. Furthermore, multiple silicon gate diodes may be included to implement storage properties as holes or electrons that accumulate in the potential well due to a positive feedback loop.

[0093] For example, the silicon gate diode binarized neural network circuitry 400 may be an artificial neural network that reduces computation time and power consumption by binarizing synaptic weights.

[0094] Accordingly, the present disclosure can implement a self-activating circuit arrangement for a binarized neural network that has unidirectional switching characteristics by controlling a potential barrier, and is capable of increasing the area and computational efficiency of an artificial neural network by having excellent storage characteristics of a silicon gate diode that also has storage characteristics as holes or electrons accumulated in a potential well due to a positive feedback loop and a self-activating function by the linearity of an output signal according to an input signal.

[0095] A plurality of silicon gate diodes may operate as synaptic elements 401 in a memory array connected in parallel and may output multiply-accumulate (MAC) operation results based on an input signal applied by an input line processor 402 connected to the memory array and a weight update signal applied by a synapse line processor 403 connected to the memory array.

[0096] In the memory arrangement as circuit arrangement 400 for a binarized neural network, an anode terminal, a gate terminal, and a cathode terminal of a plurality of silicon gate diodes can be connected in parallel to form an input line (IL), a weight line (WL), and an output line (OL), respectively. The input line (IL) can be arranged perpendicular to the weight line (WL) and the output line (OL), and the weight line (WL) and the output line (OL) can be arranged parallel to each other.

[0097] The anode terminal is connected to the input line (IL), the gate terminal is connected to the weight line (WL) and the cathode terminal is connected to the output line (OL).

[0098] The gate terminal and the cathode terminal can form the weight line (WL) and the output line (OL) respectively.

[0099] For example, in the memory array, depending on M, which is the number of rows formed by a plurality of silicon gate diodes, the first weight line (WL0) to the M-th weight line (WL m ) and the first output line (OL0) to the M-th output line (OL m ) can be trained.

[0100] The number of input lines (IL) corresponding to the columns and the number of output lines (OL) corresponding to the rows can be the same or different.

[0101] However, the weight line (WL) and the output line (OL) must have the same number (M).

[0102] For example, since the number of elements forming rows and columns can be as much as the number of inputs and outputs, N and M can be the same number or different numbers.

[0103] For example, in the memory device, depending on N, which is the number of columns formed by a plurality of silicon gate diodes, the first input line (IL0) to the N-th input line (IL n ) must be trained.

[0104] The silicon gate diode receives the anode voltage of the anode terminal as an input signal and generates a latch-up phenomenon due to a positive feedback loop when the applied input signal increases in the positive direction.

[0105] The silicon gate diode has one of two storage states for the channel region. The silicon gate diode receives the gate voltage of the gate terminal as a weight update signal, allowing the input signal at which the latch-up phenomenon occurs to be controlled.

[0106] Furthermore, the silicon gate diode can update a synaptic state with respect to any memory state according to the application of an input signal and a weight update signal, and can perform a MAC calculation function according to a synaptic weight.

[0107] For example, the silicon gate diode can output as an operation result a current signal corresponding to one of "0" to "1" by performing a multiplication operation between a continuous input of "0" to "1" when the applied input signal increases in the positive direction and a synaptic weight of one of two memory states "0" and "1".

[0108] Fig. 5A to Fig. 6B are diagrams illustrating a multiplication operation in a method of operating a binarized neural network circuitry using silicon gate diodes according to an embodiment of the present disclosure.

[0109] Fig. 5A illustrates a multiplication operation in the method of operating the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0110] With reference to Fig. 5A, in the method of operating the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure, cases are divided into a first case 500 and a second case 501, and a MAC operation is performed between an input signal and a synaptic weight.

[0111] Accordingly, the circuitry for a binarized neural network can implement artificial intelligence functions such as image recognition through a continuous multi-layer neural network.

[0112] The synaptic weight can be updated by the input voltage of an input line and a weight line.

[0113] The input signal applied through the input line (V IN ) can have continuous values, which can mean a continuous input A from 0 to 1 in the binarized neural network.

[0114] The current signal (I OUT ) corresponding to an output can be read by OL, and at this time, due to the self-activation properties of the silicon gate diode, the input A can take the form of a ReLU function for the input signal (V IN ).

[0115] The operations corresponding to the first case 500 and the second case 501 are summarized in Table 1 below. [Table 1] Anodenspannung (A) synaptisches Gewicht (W) Ausgang (OUT) erster Fall 0~1 0 0 zweiter Fall 1 0~1

[0116] The silicon gate diode has two storage states, a "1" state and a "0" state, which can represent a binarized synaptic weight W (0) and a binarized synaptic weight W (1), respectively.

[0117] In the first case 500, when the synaptic weight is W0, since the case means that the silicon gate diode is off (“0” state), the output current (I OUT ) regardless of the applied input signal (V IN ) at a very low value.

[0118] Regarding the anode voltage (A) of 0 ~ 1, a voltage below the reference voltage corresponds to 0, and a voltage greater than the reference voltage corresponds to 1.

[0119] For example, if the reference voltage is 1 V, a voltage greater than 1 V can correspond to 1.

[0120] In addition, in the output, a current greater than the reference current from 0 to 1 is output as 1, and a current less than the reference current is output as 0.

[0121] This may mean that the multiplication operation result of an anode voltage and a synaptic weight in the MAC operation of the binarized neural network is always 0 regardless of an input signal.

[0122] In the second case 501, when the synaptic weight W is 1, since this case means that the silicon gate diode is switched on (“1” state), the output current (I OUT ) linearly proportional to the applied input signal (V IN ) change.

[0123] This means that in the MAC operation of the binarized neural network, the multiplication operation result of an anode voltage and a synaptic weight can be proportional to an input.

[0124] According to an embodiment of the present disclosure, the silicon gate diode may output a current signal corresponding to one of "0" to "1" as an operation result by performing a multiplication operation between a continuous input of "0" to "1" when an applied input signal increases in the positive direction and the synaptic weight of one of two memory states of "0" and "1".

[0125] Here, with respect to inputs from “0” to “1”, when the input signals increase or decrease in the positive direction, a voltage below the reference voltage corresponds to “0”, and a voltage greater than the reference voltage corresponds to “1”.

[0126] For example, if the reference voltage is 1 V, a voltage greater than 1 V can correspond to “1”.

[0127] Fig. 5B shows energy band diagrams according to a state change of a silicon gate diode in the method of operating the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0128] With reference to Fig. 5B, a first energy band diagram 510 may indicate that the state of the silicon gate diode is “0,” and a second energy band diagram 511 may indicate that the state of the silicon gate diode is “1.”

[0129] In the “0” state according to the first energy band diagram 510, excess charge carriers are missing in the potential wells of the n- and p-doping regions of the energy band diagram, which prevents diode current (I Diode ) flows into a diode.

[0130] In contrast, in state “1” according to the second energy band diagram 511, excess charge carriers accumulate in the potential wells of the n- and p-doping regions of the energy band diagram, causing diode current to flow into a diode.

[0131] Modulating a potential barrier allows the diode to exhibit bistable properties.

[0132] A weight voltage of 0 V is applied when exponentiation and depression operations are performed, and a weight voltage of 1 V is applied when standby and multiplication operations are performed.

[0133] The conductivity of state “0” and state “1” can be the conductivity of an element, which varies depending on the presence or absence of charge in a potential well in response to a rise or depression operation.

[0134] Fig. 6A shows the timing diagram of a multiplication operation in the method of operating the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0135] With reference to Fig. 6A, a timing diagram 600 may include a corresponding increase portion 601 after the update of the weight “1”, may include a corresponding decrease portion 602 after the update of the weight “0”, while an output current (I OUT ) proportional to a continuous input signal (V IN ) pulse is measured, and is independent of an input signal (V IN ) a low output current (I OUT ) of 0 mA can be measured.

[0136] According to one embodiment of the present disclosure, in the silicon gate diode, in the case of an exponentiation operation in which a synaptic weight is updated to the state "1," an operation result is output as a current signal proportional to an applied input signal. In the case of a depression operation in which a synaptic weight is updated to the state "0," a current signal can be output as 0 mA regardless of an applied input signal.

[0137] When a synaptic weight is in the "1" state, the silicon gate diode can output the cathode current of a cathode terminal in a form similar to the graph form of a rectified linear unit (ReLU) function, regardless of a gate voltage.

[0138] To update the synaptic weight W to 1 according to the operation method in the timing diagram 600, the voltage pulses of an input voltage (V IN ) of 2 V and a voltage of the synaptic weight applied to a gate terminal (V W ) of 0 V.

[0139] Afterwards, a continuous I OUT from 0 mA to 7.4 mA proportional to a continuous V IN from 1.1 to 2.0 V can be measured.

[0140] To update the synaptic weight (W) to 0, the voltage pulses of V IN of 2 V and V W of 0 V.

[0141] Regardless of the same input voltage (V A ) a very low output current close to 0 mA can be measured.

[0142] This shows that a single synaptic element performs a multiplication operation based on excellent linearity.

[0143] With reference to Fig. 6B, the silicon gate diode in a diagram 610 shows an excellent linear relationship between input and output and can perform multiplication operations.

[0144] The diagram 610 shows a test result 611 and a straight fit 612.

[0145] Accordingly, the present disclosure can increase the computational accuracy of an artificial neural network by enabling the use of the CMOS process, enabling the fabrication of large-size devices, and nearly eliminating the deviation between the characteristics of a silicon gate diode and the characteristics of a synaptic device.

[0146] Technologies using conventional next-generation memories, such as ReRAM and MRAM, have the disadvantages of being unable to use the CMOS process, having poor element uniformity and stability, and being difficult to put into practical use due to complex processing.

[0147] In conventional artificial neural network technology, multiple neural network layers are connected by an activation function, but to implement this, a complex additional neuron circuit is required, which can degrade the area and energy efficiency of an artificial neural network.

[0148] However, the present disclosure can implement a circuit arrangement for a binarized neural network capable of reducing standby power by utilizing the excellent memory characteristics of silicon gate diodes and can be used in next-generation artificial intelligence computing technology by increasing computing efficiency with low power consumption through excellent switching characteristics.

[0149] Fig. 7A to Fig. 8B are diagrams illustrating a multiply-accumulate (MAC) operation in the method of operating the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0150] Fig. 7A and Fig. 7B illustrate a case where a memory array consisting of silicon gate diodes connected in a 4×1 pattern is used with respect to a MAC operation in the method of operating the circuit array for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0151] With reference to Fig. 7A, in a memory arrangement 700 corresponding to the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, an output current is converted to an output current (I OUT ) are added through a common output line (OL) and a summation operation is performed.

[0152] With reference to Fig. 7B, in a timing diagram 710 corresponding to the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, the input voltage (V IN1 to V IN4 ) of the input line from 1.1 V to 2 V by 0.1 V per step.

[0153] Timing diagram 710 shows the results of a summing operation in which an output current from each diode is added to the output current (I OUT ) is added through the common output line (OL).

[0154] Fig. 8A and Fig. 8B illustrate a matrix MAC operation with respect to a MAC operation in the method of operating the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0155] Fig. 8A shows a circuit arrangement 800 for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure and a synaptic weight matrix 801 according to the operation of the circuit arrangement for a binarized neural network.

[0156] Fig. 8B shows the circuitry 800 for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure and a timing diagram 810 related to the operation of the circuitry for a binarized neural network.

[0157] The MAC operation of the binarized neural network uses a silicon gate diode array connected in a 2×2 form as the binarized neural network circuitry 800.

[0158] In the memory array relating to the binary neural network circuitry 800, a plurality of silicon gate diodes are connected in an N×N configuration. Through the multiplication operation of a synaptic weight updated based on an input signal applied to an input line and a weight update signal applied to a weight line, each current through the output line is added, a sum operation is performed, and the MAC operation result can be output to a synaptic weight matrix.

[0159] Furthermore, in the memory device, when N is "2", the input signal consists of a first input signal and a second input signal, the synaptic weight consists of a first synaptic weight to a fourth synaptic weight and a first current and a second current output to the output line, and the synaptic weight matrix consisting of the first current and the second current can be calculated as the result of a vector matrix multiplication operation of the synaptic weight and the input signal.

[0160] The silicon gate diode can perform multiplication operations of each input signal (V IN1 , V IN2 ) and synaptic weights (W 11 , W 12 , W 21 , W 22 ) and can perform a summation operation where each output current (I OUT1 , I OUT2 ) through the common first output line (O L1) and the second output line (O L2 ) is added.

[0161] This means, mathematically, the 2×2 array can perform a vector matrix multiplication operation ([W11W12W21W22][IN1IN2]=[OUT1OUT2]), and the synaptic weight matrix 801 is exemplary

[1110] .

[0162] In the circuit arrangement 800 for a binarized neural network, after updating the synaptic weight of each element, if both V IN1 as well as V IN2 be created, while V W is set to 1 V, I OUT1 exactly twice the value of I OUT2 Then, if only V IN1 is created, I OUT1 and I OUT2 the same value.

[0163] Conversely, if only V IN2 is created, only I OUT1 have a value proportional to the input signal.

[0164] Finally, if not all input signals are applied, both I OUT1 as well as I OUT2 measured at low levels.

[0165] These results are consistent with the multiplication operation between the input vector and the synaptic weight matrix.

[0166] A silicon gate diode array connected in a 2×2 form by the binarized neural network circuitry 800 can implement the MAC operation of a self-activating binarized neural network.

[0167] The circuit arrangement 800 for a binarized neural network is described in a 2×2 form, but can be extended to an N×M form.

[0168] The timing diagram 810 shows that in a first area 811, when both V IN1 as well as V IN2 with V W , which is set to 1 V, I OUT1 exactly twice the value of IOUT2 has.

[0169] A second area 812 shows that I OUT1 and I OUT2 can have the same value if only V IN1 is created.

[0170] A third area 813 shows that if only V IN2 is created, only I OUT1 can have a value proportional to the input signal.

[0171] A fourth area 814 shows that both I OUT1 as well as I OUT2 can be measured at low levels when no input signal is applied.

[0172] That is, in the memory arrangement relating to the binary neural network circuit arrangement 800, when both the first and second input signals are applied while the weight update signal is fixed at 1 V, the value of the first current is twice the value of the second current. Subsequently, when only the first input signal is applied, the first current and the second current may have the same value.

[0173] Furthermore, in the memory device, when only the second input signal is applied, only the first current has a value proportional to the second input signal. When the first input signal and the second input signal are not applied, the first current and the second current can be measured at approximately 0 mA.

[0174] Accordingly, the present disclosure can implement a circuit arrangement for a binarized neural network that includes a memory array composed of silicon gate diodes based on a positive feedback loop and performs the activation function of a neuron circuit; and that has excellent uniformity and stability.

[0175] Fig. 9A to Fig. 9F are timing diagrams showing the MAC matrix operation results according to the weight update of the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0176] The matrix operation of the Fig. 9A to Fig. 9F refers to the matrix equation on each timing diagram.

[0177] During all matrix operations, the weight voltage is fixed at 1 V and the input voltage can be 0 V or a value between 1 V and 2 V.

[0178] All matrix equations usually contain [IN1IN2]=

[11] , which shows that the V IN Pulse in Fig. 7B for V IN1 and V IN2 is applied.

[0179] That is, if the weights of the 2×2 array elements change while both inputs “1” and “2” are fixed to “1”, the operation result satisfies the matrix equation.

[0180] Fig. Fig. 9A shows a timing diagram 900 corresponding to a case where the first output current (I OUT1 ) is measured as “0” under MAC matrix operations and the second output current (I OUT2 ) is measured as “0”.

[0181] The matrix operation according to the timing diagram 900 may be the same as the matrix operation on the timing diagram 900.

[0182] During the matrix operation, the weight voltage is 1 V and the input voltage can be 0 V or a value between 1 V and 2 V.

[0183] Fig. Figure 11C illustrates a case of performing a matrix operation.

[0184] Fig. Fig. 9B shows a timing diagram 910 corresponding to a case where the value according to the first output current (I OUT1 ) is measured as “1” under MAC matrix operations and the value is determined according to the second output current (I OUT2 ) is measured as “0”.

[0185] The matrix operation according to the timing diagram 910 may be the same as the matrix operation on the timing diagram 910.

[0186] Fig. Fig. 9C shows a timing diagram 920 corresponding to a case where the value according to the first output current (I OUT1 ) is measured as “1” under MAC matrix operations and the value is determined according to the second output current (I OUT2) is measured as “1”.

[0187] The matrix operation according to the timing diagram 920 may be the same as the matrix operation on the timing diagram 920.

[0188] Fig. Fig. 9D shows a timing diagram 930 corresponding to a case where the value according to the first output current (I OUT1 ) is measured as “2” under MAC matrix operations and the value is calculated according to the second output current (I OUT2 ) is measured as “0”.

[0189] The matrix operation according to the timing diagram 930 may be the same as the matrix operation on the timing diagram 930.

[0190] Fig. 9E shows a timing diagram 940 corresponding to a case where the value according to the first output current (I OUT1 ) is measured as “2” under MAC matrix operations and the value is calculated according to the second output current (I OUT2 ) is measured as “1”.

[0191] The matrix operation according to the timing diagram 940 may be the same as the matrix operation on the timing diagram 940.

[0192] Fig. Fig. 9F shows a timing diagram 950 corresponding to a case where the value according to the first output current (I OUT1 ) is measured as “2” under MAC matrix operations and the value is calculated according to the second output current (I OUT2 ) is measured as “2”.

[0193] The matrix operation according to the timing diagram 950 may be the same as the matrix operation on the timing diagram 950.

[0194] The matrix operations described above can be summarized as shown in Equation 1 below. [W11W12W21W22][IN1IN2]=[OUT1OUT2]

[0195] In equation 1, W can represent a binarized weight (conductivity), IN can represent an input signal (voltage), and OUT can represent an output signal (current) according to a matrix operation.

[0196] According to the timing diagrams 900 to 950, it is “1” when the output current is equal to the first output current (I OUT1 ) and the second output current (I OUT2 ) is 7.5 mA. If the output current is 15 mA, it is "2." If the output current is less than 7.5 mA, it is "0."

[0197] However, according to the example above, 7.5 mA is not limited to output "1." Regardless of the input voltage, if the output current is 0 mA, the output will be "0." In contrast, if the output current is measured at a specific value according to the input voltage, it may mean "1."

[0198] This proportional relationship can be Fig. 6B. Output "1" corresponds to an element. In the timing diagram 950, the output current is twice the current of an element compared to the input voltage, so it can represent output "2."

[0199] The circuitry for a binarized neural network using silicon gate diodes can perform a matrix operation for each weight, in this case the output of the matrix MAC operation has a high consistency with a simplified vector matrix multiplication (VMM) equation due to the high uniformity of the silicon gate diode.

[0200] Fig. 10 includes the optical images of a silicon gate diode according to an embodiment of the present disclosure.

[0201] Fig. 10 shows the optical images of the silicon gate diode according to an embodiment of the present disclosure.

[0202] In Fig. 10 shows an image 1010 an enlarged portion of an image 1000.

[0203] For example, image 1000 and image 1010 may be optical images of a silicon gate diode for performing a matrix MAC operation between the binarized weight of the BNN and an analog input.

[0204] Fig. 11A to Fig. 11C are diagrams illustrating the arithmetic operations of a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0205] Fig. 11A shows a weight update in the arithmetic operation of the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0206] With reference to Fig. 11A, in a weight update operation 1100, the binarized weight (W) matrix V IN(2.0 or -2.0 V) and the silicon gate diode, which consists of the arrangement with V W = 0.0 V is selected, increases (or decreases) at V IN of 2.0 V (-2.0 V).

[0207] Fig. 11B shows a standby state in the arithmetic operation of the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0208] With reference to Fig. 11B, during a standby operation 1110, 1 V is applied to all weight lines and 0 V occurs in all input lines.

[0209] The silicon gate diode maintains a memory state with a very low output current (I Diode ) upright.

[0210] Fig. 11C shows a multiplication operation in the arithmetic operation of the circuitry for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0211] With reference to Fig. 11C, in a multiplication operation 1120, the diode selected from the array may V W = 1.0 V and V IN = 0.0 V or V IN = 1.1-2.0 V.

[0212] I OUT1 the product of an input voltage and a binarized weight, can be calculated from the sum of the output current (I Diode ) can be obtained.

[0213] The present disclosure may implement a self-activating circuit arrangement for a binarized neural network that performs a self-activating function using a silicon gate diode that performs storage and switching functions in a single element based on a positive feedback loop.

[0214] The present disclosure can implement a self-activating circuit arrangement for a binarized neural network that has unidirectional switching characteristics by controlling a potential barrier, and is capable of increasing the area and computational efficiency of an artificial neural network by having excellent storage characteristics of a silicon gate diode that also has storage characteristics as holes or electrons accumulated in a potential well due to a positive feedback loop and a self-activating function by the linearity of an output signal according to an input signal.

[0215] The present disclosure can increase the computational accuracy of an artificial neural network by enabling the use of the CMOS process, enabling the fabrication of large-size devices, and nearly eliminating the deviation between the characteristics of a silicon gate diode and the characteristics of a synaptic device.

[0216] The present disclosure can implement a circuit arrangement for a binarized neural network that includes a memory array composed of silicon gate diodes based on a positive feedback loop and performs the activation function of a neuron circuit; and that has excellent uniformity and stability.

[0217] The present disclosure can implement a circuit arrangement for a binarized neural network capable of reducing standby power by utilizing the excellent memory characteristics of silicon gate diodes; and can be used in next-generation artificial intelligence computing technology by increasing computing efficiency with low power consumption through excellent switching characteristics.

[0218] In the specific embodiments described above, elements included in the disclosure are expressed in the singular or plural according to the specific embodiments shown.

[0219] It should be understood, however, that the singular or plural representations should be chosen as appropriate for the situation presented for the purpose of description, and that the embodiments described above are not limited to the singular or plural components. Components expressed in the plural may consist of a single number, and components expressed in the singular form may consist of a plurality of elements.

[0220] Moreover, the present disclosure has been described with reference to exemplary embodiments, but it should be understood that various modifications may be made without departing from the scope of the present disclosure.

[0221] Therefore, the scope of the present disclosure should not be limited by the embodiments, but should be determined by the following claims and equivalents to the following claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0114457

[0001] KR 10-2023-0053195

[0013] KR 10-2022-0110774

[0013] KR 10-2023-0020840

[0013] KR 10-2022-0107808

[0013]

Claims

[1] Circuit arrangement for a binarized neural network, comprising: a plurality of silicon gate diodes in which a diode structure is arranged as a channel region between an anode terminal and a cathode terminal, a gate terminal is arranged on the diode structure to perform unidirectional switching by potential barrier control in the channel region based on different voltages applied to each of the anode terminal and the gate terminal, and storage properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop, wherein the silicon gate diodes operate as synaptic elements in a memory array connected in parallel, and results of a multiply-accumulate (MAC) operation are output based on an input signal applied by an input line processor connected to the memory array and a weight update signal applied by a synapse line processor connected to the memory array. [2] A circuit arrangement for a binarized neural network according to claim 1, wherein the silicon gate diode receives an anode voltage of the anode terminal as the input signal, generates a latch-up phenomenon due to the positive feedback loop when the applied input signal increases in a positive direction, has any one of two storage states for the channel region, receives a gate voltage of the gate terminal as the weight update signal to control the input signal causing the latch-up phenomenon, updates a synaptic state associated with the storage state according to the application of the input signal and the weight update signal, and performs the MAC calculation function according to the synaptic weight. [3] A circuit device for a binarized neural network according to claim 2, wherein the silicon gate diode outputs a current signal corresponding to one of "0" to "1" as an operation result by performing a multiplication operation between a continuous input of "0" to "1" when the applied input signal increases in a positive direction and a synaptic weight of any one of a "0" state and a "1" state corresponding to the two memory states. [4] A circuit arrangement for a binarized neural network according to claim 3, wherein in the silicon gate diode, in a case of an exponentiation operation in which the synaptic weight is updated to the "1" state, an operation result is output as a current signal proportional to the applied input signal, and in a case of a depression operation in which the synaptic weight is updated to the "0" state, a current signal at 0 mA is output regardless of the applied input signal. [5] A circuit arrangement for a binarized neural network according to claim 2, wherein, when the synaptic weight is in a "1" state, the silicon gate diode outputs a cathode current of the cathode terminal in a form similar to a graph form of a rectified linear unit (ReLU) function regardless of the gate voltage. [6] A circuit arrangement for a binarized neural network according to claim 1, wherein the memory arrangement connects the anode terminal, the gate terminal and the cathode terminal in parallel in the silicon gate diodes to form an input line, a weight line and an output line, respectively, wherein the input line is arranged perpendicular to the weight line and the output line and the weight line and the output line are arranged in parallel. [7] A circuit arrangement for a binarized neural network according to claim 6, wherein the input line receives the input signal, the weight line receives the weight update signal, and the output line outputs the MAC operation result based on the input signal and the weight update signal to a next artificial neural network. [8] A circuit arrangement for a binarized neural network according to claim 7, wherein in the memory device, the silicon gate diodes are connected in a form of N × M and by a multiplication operation of a synaptic weight updated based on an input signal applied to the input line and a weight update signal applied to the weight line, each current through the output line is added and a sum operation is performed to output the MAC operation results as a synaptic weight matrix. [9] A circuit arrangement for a binarized neural network according to claim 8, wherein in the memory arrangement, when N and M are "2", the input signal consists of a first input signal and a second input signal, the synaptic weight consists of a first synaptic weight to a fourth synaptic weight, a first current and a second current are output to the output line, and the synaptic weight matrix consisting of the first current and the second current is calculated as a result of a vector matrix multiplication operation of the synaptic weight and the input signal. [10] A circuit arrangement for a binarized neural network according to claim 9, wherein in the memory arrangement, when both the first and second input signals are applied while the weight update signal is fixed to 1 V, a value of the first current is twice a value of the second current and thereafter, when only the first input signal is applied, a value of the first current is equal to a value of the second current. [11] A circuit arrangement for a binarized neural network according to claim 10, wherein in the memory arrangement, when only the second input signal is applied, only the first current has a value proportional to the second input signal, and when the first input signal and the second input signal are not applied, the first current and the second current are measured close to 0 mA. [12] A circuit arrangement for a binarized neural network according to claim 1, wherein the silicon gate diode comprises a single silicon gate diode, a double silicon gate diode or a triple silicon gate diode.

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